Low-on-resistance split-gate power MOSFET structure and manufacturing method

Abstract

The invention discloses a low-on-resistance split-gate power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure and a manufacturing method thereof. The MOSFET structure comprises a doped semiconductor layer of a first conductive type, a first metal oxide semiconductor layer and a second metal oxide semiconductor layer, wherein the doped semiconductor layer is arranged on a substrate; the two split gate trenches are arranged in the semiconductor layer in parallel, and trench corners are arranged between the bottoms and the side surfaces of the split gate trenches; the two doped transition regions are located in the semiconductor layer in a spaced mode and at least surround the groove corners of the two split gate grooves respectively; wherein the doping concentration of the first conductive type shown in the doped transition region is smaller than the doping concentration of the first conductive type of the semiconductor layer outside the doped transition region, so that the reverse withstand voltage is enhanced, and meanwhile, the on-resistance of the SGT device is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a low on-resistance split-gate power MOSFET structure and a manufacturing method. Background Art

[0002] Split-gate MOS (SGT) has a lower on-resistance than ordinary trench gate power MOSFET due to its unique charge balance mechanism, and has replaced traditional ordinary trench MOSFET in most medium and low voltage applications.

[0003] The main structural feature of the traditional split-gate power MOSFET is that each functional unit includes two split-gate trenches in the epitaxial layer. Among them, a gate structure composed of polysilicon and oxide is provided in the upper part of the split-gate trench, and a conductive channel is formed at the sidewall of the trench at this position under appropriate bias. A field plate-like structure composed of zero-potential polysilicon and oxide is provided in the lower part of the split-gate trench, which forms a space charge region under reverse bias to bear the potential drop, that is, the reverse withstand voltage utilizes the charge balance principle. Therefore, an epitaxial layer with a higher doping concentration than ordinary trench MOSFET can be used, and under the condition of obtaining the same withstand voltage, it has a lower on-resistance or a higher current density, which is conducive to high-power applications.

[0004] Due to the special morphology of the bottom of the split-gate trench, the electric field is concentrated, and the actual avalanche breakdown position is usually located at the corner of the bottom of the split-gate trench, which may cause damage to the device. By reducing the doping concentration of the epitaxial layer material, although the avalanche breakdown withstand voltage can be increased to a certain extent, it also creates a problem that is not conducive to the expansion of the electric field, and is therefore not conducive to further reducing the on-resistance of the epitaxial layer. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a low on-resistance split-gate power MOSFET structure and a manufacturing method.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a low on-resistance split-gate power MOSFET structure, comprising:

[0008] A doped semiconductor layer of a first conductivity type disposed on the substrate;

[0009] Two split gate trenches are arranged in parallel in the semiconductor layer, and a trench corner is formed between the bottom and the side of the split gate trench;

[0010] Two doped transition regions are located in the semiconductor layer at intervals and surround at least the trench corners of two split-gate trenches respectively;

[0011] The doping concentration of the first conductivity type exhibited in the doped transition region is lower than the doping concentration of the first conductivity type in the semiconductor layer outside the doped transition region.

[0012] Furthermore, the doped transition zone contains doping impurities of the second conductivity type, which are used to reversely compensate for the doping impurities of the first conductivity type originally in the semiconductor layer in the doped transition zone, so that the doping concentration of the first conductivity type exhibited by the doped transition zone is lower than the doping concentration of the first conductivity type in the semiconductor layer outside the doped transition zone.

[0013] Furthermore, it also includes: a first doping region of the first conductivity type and a second doping region of the second conductivity type which are sequentially arranged in the semiconductor layer from the surface of the semiconductor layer between the two split gate trenches.

[0014] Furthermore, the doped transition region also extends along the wall of the split gate trench to at least connect with the second doped region.

[0015] Furthermore, a first gate and a second gate are sequentially provided in the split gate trench from the bottom, and a dielectric layer is provided between the first gate, the second gate and the inner wall of the split gate trench, and between the first gate and the second gate; and / or, a conductive contact hole is also provided on the surface of the semiconductor layer between the split gate trenches, and the bottom of the conductive contact hole passes through the first doped region and is connected to the second doped region.

[0016] The present invention also provides a method for manufacturing a low on-resistance split-gate power MOSFET structure, comprising:

[0017] providing a substrate, and forming a doped semiconductor layer of a first conductivity type on the substrate;

[0018] forming two parallel split-gate trenches from the surface of the semiconductor layer into the semiconductor layer;

[0019] A doped transition region is formed in the semiconductor layer outside the wall of each split gate trench, so that each doped transition region at least surrounds a corresponding trench corner, and the doping concentration of the first conductivity type exhibited by the doped transition region is less than the doping concentration of the first conductivity type of the semiconductor layer outside the doped transition region.

[0020] Furthermore, forming a doped transition region in the semiconductor layer outside the wall of each split gate trench specifically includes:

[0021] Filling a doped dielectric layer of a second conductivity type in the split gate trench;

[0022] Allowing the doping impurities of the second conductivity type contained in the doping medium layer to diffuse outside the walls of the split gate trenches, and forming a doping transition region in the semiconductor layer outside the walls of each split gate trench; then, removing the doping medium layer;

[0023] In which, the second conductive type of doping impurities diffused from the doped medium layer to the semiconductor layer are used to reversely compensate for the first conductive type of doping impurities originally in the semiconductor layer in the doped transition zone, so that the doping concentration of the first conductive type shown in the doped transition zone is lower than the doping concentration of the first conductive type in the semiconductor layer outside the doped transition zone.

[0024] Furthermore, a thermal diffusion process is used to diffuse the doped impurities in the doped dielectric layer filled in the split gate trench into a certain area outside the trench wall of the split gate trench, thereby forming the doped transition region; and / or, after the doped transition region is formed, a wet etching process is used to completely remove the doped dielectric layer in the split gate trench.

[0025] Furthermore, after removing the doped medium layer, the method further comprises:

[0026] Forming a first dielectric layer on the inner wall of the split gate trench, and filling the split gate trench within the first dielectric layer to form a first gate material layer;

[0027] removing a portion of the first gate material layer to form a first gate at the bottom of the split gate trench, and removing a portion of the first dielectric layer to form a first gate dielectric layer located outside the first gate at the bottom of the split gate trench;

[0028] A second dielectric layer is formed on top of the first gate and the first gate dielectric layer, and on the upper sidewall of the split gate trench, and a second gate material layer is filled in the upper portion of the split gate trench within the second dielectric layer to form a second gate in the upper portion of the split gate trench, a second gate dielectric layer located outside the second gate, and an isolation layer located below the second gate.

[0029] Furthermore, it also includes:

[0030] forming a first doping region of a first conductivity type and a second doping region of a second conductivity type sequentially disposed between the two split gate trenches from the surface of the semiconductor layer into the semiconductor layer, and at least connecting the second doping region to the doping transition regions on both sides;

[0031] forming an interlayer dielectric layer on the surface of the semiconductor layer to cover the split gate trench and the first doped region;

[0032] Forming a contact hole trench on the surface of the interlayer dielectric layer between the split gate trenches, the contact hole trench penetrating the surface of the semiconductor layer and having a bottom in contact with the second doping region;

[0033] Filling the contact hole trench to form a conductive contact hole;

[0034] forming a metal layer connected to the conductive contact hole on the surface of the interlayer dielectric layer;

[0035] A passivation layer is formed on the surface of the metal layer.

[0036] It can be seen from the above technical scheme that the present invention forms doped transition regions with mixed doped impurities of different conductive types in the doped semiconductor layer of the first conductive type within a certain range outside the walls of the two split gate trenches of the SGT functional unit, and uses the second conductive impurities contained in the doped transition region to reversely compensate for the first conductive impurities in the original semiconductor layer in the doped transition region, so that the doping concentration of the first conductive type in the doped transition region is less than the doping concentration of the first conductive type in the semiconductor layer outside the doped transition region, thereby reducing the doping concentration of the first conductive type in the semiconductor layer in the corner region of the split gate trench, and thus increasing the avalanche breakdown withstand voltage to a certain extent. Therefore, a higher doping concentration can be used in other regions of the semiconductor layer between the doped transition regions to facilitate the expansion of the electric field, thereby reducing the electric field concentration in the corner region at the bottom of the trench and reducing the resistance of the semiconductor layer in the forward conduction state, thereby further reducing the on-resistance of the SGT device while enhancing the reverse withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a low on-resistance split-gate power MOSFET structure according to a preferred embodiment of the present invention.

[0038] Figure 2-Figure 10 The present invention is a process flow chart of a method for manufacturing a low on-resistance split-gate power MOSFET structure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0040] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate material may be formed of various materials that can conduct electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni3Si, Pt, Ru, W, and combinations of the above-mentioned various conductive materials. The gate oxide layer (gate dielectric layer) material may be made of SiO2 or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Moreover, the gate oxide layer may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for the gate oxide layer.

[0041] The first doping type may be one of N-type and P-type, and the second doping type may be the other of N-type and P-type. N-type may be formed by injecting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by injecting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.

[0042] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0043] refer to Figure 1 A low on-resistance split-gate power MOSFET structure of the present invention comprises a semiconductor layer 10 disposed on a substrate (not shown), two split-gate trenches 30 disposed in the semiconductor layer 10 , and two doped transition regions 50 disposed on a certain range outside the trench wall of the split-gate trench 30 .

[0044] Two split gate trenches 30 extend downward from the surface (the upper surface in the figure) of the semiconductor layer 10 into the semiconductor layer 10 to form two parallel deep trench structures. The two deep trenches and the area therebetween define a functional unit of the SGT device.

[0045] A first gate 611 and a second gate 801 are sequentially arranged in each split gate trench 30 from the bottom. A dielectric layer 82 is arranged between the first gate 611, the second gate 801 and the inner wall of the split gate trench 30, and between the first gate 611 and the second gate 801. The dielectric layer 82 between the first gate 611 and the inner wall of the split gate trench 30 can form a first gate dielectric layer 601; the dielectric layer 82 between the second gate 801 and the sidewall of the split gate trench 30 can form a second gate dielectric layer 811; and the dielectric layer 82 between the first gate 611 and the second gate 801 can form an isolation layer 812. The first gate 611 acts as a shielding gate and forms a field plate structure similar to the first gate dielectric layer 601, forming a space charge region under reverse bias to bear the potential drop, and the first gate dielectric layer 601 acts as a field plate oxide layer. The second gate 801 serves as a control gate. By combining the control gate with the second gate dielectric layer 811 at the upper sidewall of the split gate trench 30 , a conductive channel is formed at the upper sidewall of the split gate trench 30 corresponding to the control gate under appropriate bias.

[0046] Each split gate trench 30 has a trench corner 31 between the bottom and the side. It should be noted that in conventional SGT devices, the special morphology of the bottom corner of the split gate trench 30 causes electric field concentration, so that the actual avalanche breakdown position is usually located at this corner.

[0047] refer to Figure 1 The semiconductor layer 10 may be a first conductivity type doped epitaxial semiconductor layer 10 disposed on a substrate. Taking the first doping type as N type and the second doping type as P type as an example, the semiconductor layer 10 may be a first conductivity type N type doped epitaxial semiconductor layer 10.

[0048] Two doped transition regions 50 are formed in the semiconductor layer 10 and are respectively disposed along the walls of the two split gate trenches 30 and respectively surround at least the trench corners 31 of the two split gate trenches 30. The two doped transition regions 50 are isolated from each other by the semiconductor layer 10 material.

[0049] In some embodiments, the doped transition region 50, on the basis of surrounding the trench corner 31 of the split gate trench 30, continues to extend along the trench wall of the split gate trench 30, and can completely surround the side wall of the split gate trench 30 (the portion of the doped transition region 50 located at the relatively outer side of the two split gate trenches 30 shown in the figure is not shown, and only the local structure of the doped transition region 50 located at the relatively inner side and bottom position of the two split gate trenches 30 is shown, which can be understood as a simplified form of the accompanying drawing. Alternatively, it can also be understood that the doped transition region 50 is only continuously formed at the relatively inner side and bottom position of the two split gate trenches 30).

[0050] Below the surface of the semiconductor layer 10 between the two split gate trenches 30, a first doping region 92 and a second doping region 93 are further provided. The first doping region 92 and the second doping region 93 are sequentially provided between the two split gate trenches 30 from the surface of the semiconductor layer 10 to the inside of the semiconductor layer 10. The first doping region 92 may be a source region of N+ type doping of the first conductivity type; the second doping region 93 may be a body region (P-body) of P-type doping of the second conductivity type.

[0051] Furthermore, the doped transition region 50 also extends along the wall of the split gate trench 30 to be connected to the second doped region 93 serving as the body region.

[0052] Furthermore, the doped transition region 50 also extends along the wall of the split gate trench 30 to connect with the first doped region 92 serving as the source region.

[0053] The doped transition region 50 contains both N-type doped impurities of the first conductivity type and P-type doped impurities of the second conductivity type. The N-type doped impurities and the P-type doped impurities are mixed in the doped transition region 50 to form a doped transition region 50 having mixed doped impurities of different conductivity types. The doped transition region 50 having mixed doping generally presents an N-type conductivity type. Moreover, the N-type doping concentration exhibited by the doped transition region 50 is less than the N-type doping concentration of the semiconductor layer 10 outside the doped transition region 50.

[0054] The N-type conductivity type generally presented by the doped transition region 50 is achieved by the interaction between the N-type doping impurities and the P-type doping impurities contained in the doped transition region 50. The N-type doping concentration of the semiconductor layer 10 originally corresponds to the N-type doping impurity concentration contained in the doped transition region 50. However, due to the certain concentration of P-type doping impurities contained in the doped transition region 50, a reverse compensation effect is produced on the certain concentration of N-type doping impurities contained in the doped transition region 50, that is, part of the N-type doping concentration in the doped transition region 50 is offset. As a result, the N-type doping concentration shown in the doped transition region 50 is less than the N-type doping concentration of the semiconductor layer 10 outside the doped transition region 50.

[0055] In some embodiments, the doped transition region 50 may be formed on the semiconductor layer 10 and take the semiconductor layer 10 material as the matrix. At the same time, a certain concentration of P-type doping impurities may be infiltrated into the predetermined doped transition region 50 region by, for example, thermal diffusion, to reversely compensate for the N-type doping impurities in the original semiconductor layer 10 in the doped transition region 50 region, so that the N-type doping concentration of the doped transition region 50 is less than the N-type doping concentration of the semiconductor layer 10 outside the doped transition region 50, and a doped transition region 50 having mixed doping impurities of different conductive types is formed.

[0056] The present invention utilizes the structure of the special doped transition region 50 formed as described above, and can realize the epitaxial material (epitaxial semiconductor layer 10 material) with a lower doping concentration within a certain range outside the two trench sidewalls of the traditional SGT, and appropriately reduce the N-type doping concentration of the semiconductor layer 10 material in the corner region of the split-gate trench 30 of the present invention, so as to increase the avalanche breakdown withstand voltage to a certain extent. Therefore, the epitaxial semiconductor layer 10 material with a higher doping concentration can be used in other regions of the semiconductor layer 10 between the two doped transition regions 50 to facilitate the expansion of the electric field, thereby reducing the electric field concentration in the bottom trench corner 31 region while reducing the resistance of the semiconductor layer 10 in the forward conduction state, thereby further reducing the on-resistance of the SGT device while enhancing the reverse withstand voltage.

[0057] In some embodiments, an interlayer dielectric layer 90 (ILD) is further disposed on the surface of the semiconductor layer 10 .

[0058] Furthermore, a conductive contact hole 94 whose bottom is connected to the second doped region 93 (body region) is also provided on the surface of the interlayer dielectric layer 90. For example, a tungsten plug may be provided in the conductive contact hole 94. The conductive contact hole 94 may be centrally disposed between the two split gate trenches 30 and extend downward from the surface of the interlayer dielectric layer 90 into the semiconductor layer 10, and the bottom of the conductive contact hole 94 passes through the first doped region 92 (source region) and is connected to the second doped region 93 (body region), so that the conductive contact hole 94 forms an ohmic connection with the source region and the body region in sequence.

[0059] In some embodiments, a metal layer 91 is further provided on the surface of the interlayer dielectric layer 90. The metal layer 91 is connected to the top of the conductive contact hole 94. The metal layer 91 can be made of conventional materials, such as AlSiCu metal layer 91.

[0060] Furthermore, a dielectric passivation layer (not shown) is provided on the surface of the metal layer 91 to protect the device.

[0061] In some embodiments, the substrate may be a semiconductor substrate, such as a silicon-based, silicon carbide-based, gallium nitride-based, or other compound semiconductor material substrates.

[0062] In some embodiments, the semiconductor layer 10 may be formed of a material homogeneous with the substrate. For example, the substrate may be a silicon substrate, and the semiconductor layer 10 may be an N-type epitaxial layer of homogeneous silicon material formed on the silicon substrate.

[0063] In some embodiments, the first gate 611 and the second gate 801 may be made of N+ type saturated doped polysilicon. The first gate dielectric layer 601, the second gate dielectric layer 811 and the isolation layer 812 may be made of SiO2, but the present invention is not limited thereto.

[0064] In some embodiments, the material of the interlayer dielectric layer 90 may be, for example, at least one of NSG (non-doped silicate glass) and BPSG (boron phospho-silicate glass).

[0065] The following further describes in detail a method for manufacturing a low on-resistance split-gate power MOSFET structure of the present invention through specific implementation modes and in combination with the accompanying drawings.

[0066] refer to Figure 2-Figure 10 The present invention provides a method for manufacturing a low on-resistance split-gate power MOSFET structure, which can be used to manufacture, for example, Figure 1 A low on-resistance split-gate power MOSFET structure is shown, and may include the following steps:

[0067] Step S1: providing a substrate, and forming a doped semiconductor layer 10 of a first conductivity type on the substrate.

[0068] like Figure 2 As shown, a silicon substrate (not shown) can be used, for example, and an epitaxial process can be used to form a semiconductor layer 10 of the same material as the silicon substrate on the silicon substrate. For example, an N-type semiconductor layer 10 of a first conductivity type with a certain doping concentration and thickness can be epitaxially grown on the surface of an N-type silicon substrate with a certain resistivity.

[0069] Step S2 : forming two parallel split-gate trenches 30 from the surface of the semiconductor layer 10 into the semiconductor layer 10 .

[0070] like Figure 3 As shown, a first photoresist layer is formed on the surface of the semiconductor layer 10 , and the split gate trench 30 region is photolithographically formed to form a first photoresist pattern 20 , and the split gate trench 30 region is defined by the first photoresist pattern 20 .

[0071] like Figure 4 As shown, dry etching is then performed to etch downward two parallel deep trenches that meet the morphology and size requirements on the surface of the semiconductor layer 10 to form a split gate trench 30. Afterwards, the remaining first photoresist pattern 20 is removed.

[0072] Step S3: forming a doped transition region 50 in the semiconductor layer 10 outside the wall of each split gate trench 30, so that each doped transition region 50 surrounds at least one corresponding trench corner 31, and the doping concentration of the first conductivity type exhibited by the doped transition region 50 is less than the doping concentration of the first conductivity type of the semiconductor layer 10 outside the doped transition region 50.

[0073] like Figure 5 As shown, then, a doped dielectric layer 40 of the second conductivity type is deposited on the surface of the semiconductor layer 10 . The doped dielectric layer 40 may be, for example, a highly doped P-type oxide (such as silicon dioxide) layer of the second conductivity type, and fills the split gate trench 30 .

[0074] Then, a high-temperature thermal diffusion process is used to diffuse the P-type doping impurities contained in the doping dielectric layer 40 filled in the split gate trench 30 into a certain area outside the wall of the split gate trench 30, and reversely compensate the N-type doping impurities in the original semiconductor layer 10 in the diffusion area, so that the N-type doping concentration shown in the diffusion area (i.e., the formed doping transition area 50) is less than the N-type doping concentration of the semiconductor layer 10 outside the diffusion area, so that the above-mentioned diffusion area in the semiconductor layer 10 outside the wall of each split gate trench 30 respectively forms a doping transition area 50 surrounding a corresponding trench corner 31, that is, two independent doping transition areas 50 are formed. Figure 6 In one example, the process temperature during high temperature thermal diffusion is generally between 1000°C and 1150°C.

[0075] After the diffusion region reaches a predetermined doping concentration distribution, the high-temperature diffusion is stopped. Then, the highly doped P-type oxide layer (doped dielectric layer 40) in the split gate trench 30 and on the surface of the semiconductor layer 10 is removed by a wet etching process to form Figure 6 The structure shown.

[0076] like Figure 7 As shown, a first dielectric layer 60 of a certain thickness is then formed on the inner wall of the split gate trench 30 by combining thermal oxidation with deposition. Then, a first gate material layer 61 is deposited in the split gate trench 30 within the first dielectric layer 60. The material of the first dielectric layer 60 can be SiO2; the material of the first gate material layer 61 can be saturated doped N+ type polysilicon. After completion, chemical mechanical polishing (CMP) is performed to remove the excess first gate material layer 61 and the first dielectric layer 60 on the surface of the semiconductor layer 10.

[0077] like Figure 8As shown, then, by etching, a portion of the first gate material layer 61 in the split gate trench 30 is removed to a certain depth in the deep trench, so as to form a first gate 611 as a shielding gate at the lower portion of the split gate trench 30. Then, a portion of the first dielectric layer 60 is etched away to a height corresponding to the top height of the first gate 611, so as to form a first gate dielectric layer 601 (shielding gate dielectric layer) located between the first gate 611 and the inner wall of the split gate trench 30 at the lower portion of the split gate trench 30.

[0078] like Fig. 9 As shown, after that, a second dielectric layer 81 is formed on the top of the first gate 611 and the first gate dielectric layer 601, and on the upper sidewall of the split gate trench 30 by using gate oxide oxidation and polysilicon deposition processes, and a second gate material layer 80 is filled in the upper part of the split gate trench 30 within the second dielectric layer 81. The material of the second dielectric layer 81 can be SiO2; the material of the second gate material layer 80 can be saturated doped N+ type polysilicon.

[0079] After completion, the redundant second gate material layer 80 and the second dielectric layer 81 on the surface of the semiconductor layer 10 are removed by CMP. Thus, a second gate 801 as a control gate, a second gate dielectric layer 811 (control gate dielectric layer) located outside the second gate 801, and an isolation layer 812 (formed by the second dielectric layer 81 located below the second gate 801) located below the second gate 801 and used to isolate the second gate 801 from the first gate 611 are formed in the upper portion of the split gate trench 30.

[0080] The first dielectric layer 60 and the second dielectric layer 81 together form Figure 1 The dielectric layer 82 in.

[0081] After that, it also includes:

[0082] Step S4: forming a first doping region 92 of the first conductivity type and a second doping region 93 of the second conductivity type sequentially disposed between the two split gate trenches 30 from the surface of the semiconductor layer 10 into the semiconductor layer 10 , and at least connecting the second doping region 93 to the doping transition regions 50 on both sides.

[0083] like Fig.10 As shown, by adopting ion implantation and annealing process, a second P-type doped region 93 of a second conductivity type is formed downwardly from the surface of the semiconductor layer 10 between the two split gate trenches 30 and located at a certain depth in the semiconductor layer 10 as a body region.

[0084] Next, by using ion implantation and annealing processes, a first N+ type doped region 92 of the first conductivity type is formed below the surface of the semiconductor layer 10 above the second doped region 93 and is also located between the two split gate trenches 30 as a source region.

[0085] Through ion implantation and annealing processes, both sides of the second doping region 93 and the first doping region 92 can be connected to a doping transition region 50 on the corresponding side.

[0086] Step S5: forming an interlayer dielectric layer 90 on the surface of the semiconductor layer 10 to cover the split gate trenches 30 and the first doped region 92; forming a contact hole trench on the surface of the interlayer dielectric layer 90 between the split gate trenches 30, which passes through the surface of the semiconductor layer 10 and has a bottom in contact with the second doped region 93; and filling the contact hole trench to form a conductive contact hole 94.

[0087] like Fig.10 As shown, an interlayer dielectric layer 90 (ILD) may be formed on the surface of the semiconductor layer 10 by depositing, for example, NSG and / or BPSG on the surface of the semiconductor layer 10 and then reflowing the layer to cover the two split-gate trenches 30 and the first doped region 92 .

[0088] Then, a contact hole trench can be formed downward on the surface of the interlayer dielectric layer 90 between the two split gate trenches 30 by using photolithography and etching processes, and the bottom of the contact hole trench is in contact with the top surface of the second doped region 93. Preferably, the contact hole trench can be located at the midline position between the two split gate trenches 30.

[0089] Next, Ti and TiN layers, for example, can be formed on the inner wall of the contact hole trench in sequence, and metal tungsten, for example, can be filled in the contact hole trench within the TiN layer. Then, by chemical mechanical polishing, the excess Ti, TiN and tungsten materials on the surface of the interlayer dielectric layer 90 outside the contact hole trench are removed, and a tungsten plug is formed in the contact hole trench. Thus, a conductive contact hole 94 is formed, the bottom of which is connected to the second doping region 93 (body region), and is also connected to the first doping region 92 (source region).

[0090] Step S6 : forming a metal layer 91 connected to the conductive contact hole 94 on the surface of the interlayer dielectric layer 90 ; and forming a passivation layer on the surface of the metal layer 91 .

[0091] like Fig.10 As shown, a sputtering process is used to form, for example, an AlSiCu metal layer 91 on the surface of the interlayer dielectric layer 90, and the AlSiCu metal layer 91 is in contact with the top of the tungsten plug of the conductive contact hole 94. Finally, the result is as shown in FIG. Figure 1 The complete structure shown.

[0092] Subsequently, the AlSiCu metal layer 91 can be patterned by photolithography and etching processes, and a dielectric passivation layer (not shown) can be formed on the surface of the interlayer dielectric layer 90 (metal layer 91). Covering the metal layer 91 with the passivation layer can effectively protect the device.

[0093] In summary, the present invention forms doped transition regions 50 with mixed doped impurities of different conductive types in the doped semiconductor layer 10 of the first conductive type within a certain range outside the groove walls of the two split gate grooves 30 of the SGT functional unit, and uses the second conductive type doped impurities contained in the doped transition region 50 to reversely compensate for the first conductive type doped impurities in the original semiconductor layer 10 in the doped transition region 50, so that the doping concentration of the first conductive type shown in the doped transition region 50 is less than the doping concentration of the first conductive type of the semiconductor layer 10 outside the doped transition region 50, thereby reducing the doping concentration of the first conductive type of the semiconductor layer 10 material in the corner region of the split gate groove 30, and thus increasing the avalanche breakdown withstand voltage to a certain extent. Therefore, a higher doping concentration can be used in other regions of the semiconductor layer 10 between the doped transition regions 50 to facilitate the expansion of the electric field, thereby reducing the electric field concentration in the trench corner 31 region at the bottom of the groove, and reducing the resistance of the semiconductor layer 10 in the forward conduction state, thereby enhancing the reverse withstand voltage and further reducing the on-resistance of the SGT device.

[0094] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A low on-resistance split-gate power MOSFET structure, characterized in that: include: A doped semiconductor layer of a first conductivity type disposed on the substrate; Two split gate trenches are arranged in parallel in the semiconductor layer, and a trench corner is formed between the bottom and the side of the split gate trench; Two doped transition regions are located in the semiconductor layer at intervals and surround at least the trench corners of two split-gate trenches respectively; The doping concentration of the first conductivity type exhibited in the doped transition region is lower than the doping concentration of the first conductivity type in the semiconductor layer outside the doped transition region.

2. The low on-resistance split-gate power MOSFET structure according to claim 1, characterized in that: The doped transition zone contains doping impurities of the second conductivity type, which are used to reversely compensate for the doping impurities of the first conductivity type originally in the semiconductor layer in the doped transition zone, so that the doping concentration of the first conductivity type exhibited by the doped transition zone is lower than the doping concentration of the first conductivity type of the semiconductor layer outside the doped transition zone.

3. The low on-resistance split-gate power MOSFET structure according to claim 1, characterized in that: Also includes: A first doping region of a first conductivity type and a second doping region of a second conductivity type are sequentially arranged in the semiconductor layer from the surface of the semiconductor layer between the two split gate trenches.

4. The low on-resistance split-gate power MOSFET structure according to claim 3, characterized in that: The doped transition region further extends along the wall of the split gate trench to at least connect with the second doped region.

5. The low on-resistance split-gate power MOSFET structure according to claim 1, characterized in that: A first gate and a second gate are sequentially arranged in the split gate trench from the bottom, and a dielectric layer is arranged between the first gate, the second gate and the inner wall of the split gate trench, and between the first gate and the second gate; and / or a conductive contact hole is also arranged on the surface of the semiconductor layer between the split gate trenches, and the bottom of the conductive contact hole passes through the first doped region and is connected to the second doped region.

6. A method for manufacturing a low on-resistance split-gate power MOSFET structure, characterized in that: include: providing a substrate, and forming a doped semiconductor layer of a first conductivity type on the substrate; forming two parallel split-gate trenches from the surface of the semiconductor layer into the semiconductor layer; A doped transition region is formed in the semiconductor layer outside the wall of each split gate trench, so that each doped transition region at least surrounds a corresponding trench corner, and the doping concentration of the first conductivity type exhibited by the doped transition region is less than the doping concentration of the first conductivity type of the semiconductor layer outside the doped transition region.

7. The method for manufacturing a low on-resistance split-gate power MOSFET structure according to claim 6, characterized in that: The forming of a doped transition region in the semiconductor layer outside the wall of each split gate trench specifically includes: Filling a doped dielectric layer of a second conductivity type in the split gate trench; Allowing the doping impurities of the second conductivity type contained in the doping medium layer to diffuse outside the walls of the split gate trenches, and forming a doping transition region in the semiconductor layer outside the walls of each split gate trench; then, removing the doping medium layer; In which, the second conductive type of doping impurities diffused from the doped medium layer to the semiconductor layer are used to reversely compensate for the first conductive type of doping impurities originally in the semiconductor layer in the doped transition zone, so that the doping concentration of the first conductive type shown in the doped transition zone is lower than the doping concentration of the first conductive type in the semiconductor layer outside the doped transition zone.

8. The method for manufacturing a low on-resistance split-gate power MOSFET structure according to claim 7, characterized in that: Using a thermal diffusion process, the doping impurities in the doping medium layer filled in the split gate trench are diffused into a certain area outside the trench wall of the split gate trench, thereby forming the doping transition region; And / or, after forming the doped transition region, a wet etching process is used to completely remove the doped dielectric layer in the split gate trench.

9. The method for manufacturing a low on-resistance split-gate power MOSFET structure according to claim 7, characterized in that: After removing the doped medium layer, the method further comprises: Forming a first dielectric layer on the inner wall of the split gate trench, and filling the split gate trench within the first dielectric layer to form a first gate material layer; removing a portion of the first gate material layer to form a first gate at the bottom of the split gate trench, and removing a portion of the first dielectric layer to form a first gate dielectric layer located outside the first gate at the bottom of the split gate trench; A second dielectric layer is formed on top of the first gate and the first gate dielectric layer, and on the upper sidewall of the split gate trench, and a second gate material layer is filled in the upper portion of the split gate trench within the second dielectric layer to form a second gate in the upper portion of the split gate trench, a second gate dielectric layer located outside the second gate, and an isolation layer located below the second gate.

10. The method for manufacturing a low on-resistance split-gate power MOSFET structure according to claim 9, characterized in that: Also includes: forming a first doping region of a first conductivity type and a second doping region of a second conductivity type sequentially disposed between the two split gate trenches from the surface of the semiconductor layer into the semiconductor layer, and at least connecting the second doping region to the doping transition regions on both sides; forming an interlayer dielectric layer on the surface of the semiconductor layer to cover the split gate trench and the first doped region; Forming a contact hole trench on the surface of the interlayer dielectric layer between the split gate trenches, the contact hole trench penetrating the surface of the semiconductor layer and having a bottom in contact with the second doping region; Filling the contact hole trench to form a conductive contact hole; forming a metal layer connected to the conductive contact hole on the surface of the interlayer dielectric layer; A passivation layer is formed on the surface of the metal layer.

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