Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a processing method thereof, and the semiconductor device comprises a semiconductor substrate; the gate metal structure is arranged on the semiconductor substrate; the gate dielectric layer is arranged between the gate metal structure and the semiconductor substrate; the covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer comprises a first covering layer and a second covering layer, the first covering layer is located in a central area opposite to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, and the material of the second covering layer is different from that of the first covering layer; and the work function of the second covering layer is different from that of the first covering layer. Therefore, work functions on two sides of the transistor can be changed, especially the work function of one side, close to the drain, of the gate metal structure, thereby improving the electric field intensity of an overlapping region of the gate and the drain, weakening the leakage current of the transistor, and improving the performance of a semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the current semiconductor chip manufacturing, field effect transistors will leak electricity when they are turned off or in standby mode, generating leakage current and causing static power consumption. The leakage currents that cause static power consumption in field effect transistors mainly include: subthreshold leakage current from source to drain, gate leakage current, and gate-induced drain leakage GIDL (gate-induced drain leakage) current occurring in the gate-drain overlap region. Among them, GIDL current is the dominant current in leakage current.

[0003] In the process of field effect transistor manufacturing, it is difficult to avoid the overlap between the gate and the drain. This overlap leads to the generation of GIDL current. When the gate-drain voltage at the gate-drain overlap area is very large, the electrons in the silicon near the interface of the overlap area undergo band-to-band tunneling between the valence band and the conduction band to form a current. We call this current GIDL tunneling current. As the gate oxide layer becomes thinner and thinner, the GIDL tunneling current will also increase sharply, weakening the ability of the field effect transistor gate, thereby affecting the performance of the field effect transistor. Summary of the invention

[0004] The present application provides a semiconductor device and a manufacturing method thereof, which can reduce the electric field strength in the overlapping region of the gate and the drain, thereby weakening the leakage current of the transistor.

[0005] To solve the above technical problems, the first aspect of the present application provides a semiconductor device, comprising: a semiconductor substrate; a gate metal structure, arranged on the semiconductor substrate; a gate dielectric layer, arranged between the gate metal structure and the semiconductor substrate; a covering layer, arranged between the gate dielectric layer and the gate metal structure, the covering layer comprising a first covering layer and a second covering layer, the first covering layer being located in a central area relative to the gate metal structure, the second covering layer being located on at least one side of the first covering layer, the material of the second covering layer being different from the material of the first covering layer, and the work function of the second covering layer being different from the work function of the first covering layer.

[0006] In some embodiments, the first covering layer and the second covering layer are located on the same layer.

[0007] In some embodiments, the gate metal structure is a gate metal structure of a P-type transistor, and a work function of the second covering layer is lower than a work function of the first covering layer.

[0008] In some embodiments, the first capping layer includes a TiN layer, and the second capping layer includes a doped polysilicon layer or a silicon-doped TiN layer.

[0009] In some embodiments, the gate metal structure is a gate-last structure, and the dielectric constant of the gate dielectric layer is in the range of 16 to 25.

[0010] In some embodiments, the gate metal structure includes: a metal gate filling layer; and a work function metal layer, which is disposed between the capping layer and the metal gate filling layer and covers the sidewalls of the metal gate filling layer.

[0011] In some embodiments, the work function metal layer includes a first work function metal layer, a work function adjustment layer and a second work function metal layer, and the work function adjustment layer is located between the first work function metal layer and the second work function metal layer; the metal gate filling layer includes an Al metal gate filling layer.

[0012] In some embodiments, the second capping layer is disposed at the same layer as any one of the work function metal layers.

[0013] To solve the above technical problems, the second aspect of the present application also provides a process method for a semiconductor device, comprising: providing a semiconductor substrate; forming a gate dielectric layer, a covering layer and a gate metal structure on the semiconductor substrate, wherein the gate dielectric layer is located between the semiconductor substrate and the gate metal structure, the covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer comprises a first covering layer and a second covering layer, the first covering layer is located in a central area relative to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, the material of the second covering layer is different from the material of the first covering layer, and the work function of the second covering layer is different from the work function of the first covering layer.

[0014] In some embodiments, the gate dielectric layer, the capping layer and the gate metal structure are formed on the semiconductor substrate, comprising: forming a dielectric layer and a patterned first capping material layer on the semiconductor substrate, wherein the patterned first capping material layer is located above the dielectric layer; forming a second capping material layer, wherein the second capping material layer covers the dielectric layer and the patterned first capping material layer; removing a portion of the second capping material layer, retaining the second capping material layer on at least one side of the patterned first capping material layer, wherein the patterned first capping material layer serves as the first capping layer, and the remaining second capping material layer serves as the second capping layer.

[0015] In some embodiments, the second covering layer is disposed at one end of the drain of the semiconductor device.

[0016] In some embodiments, the gate metal structure is a post-gate structure, and the dielectric constant of the gate dielectric layer is between 16 and 25; the removal of part of the second covering material layer and retaining the second covering material layer on at least one side of the patterned first covering material layer include: forming a virtual gate layer and a hard mask layer on the second covering material layer; patterning the hard mask layer, the virtual gate layer, the second covering material layer and the dielectric layer to form a gate island structure, wherein the remaining dielectric layer in the gate island structure serves as the gate dielectric layer, and the remaining virtual gate layer serves as a virtual gate, and the gate island structure includes a patterned The patterned first covering material layer and the remaining second covering material layer on at least one side of the patterned first covering material layer; forming gate sidewalls on both sides of the gate island structure, and removing the virtual gate and part of the second covering material layer to expose the patterned first covering material layer and the remaining second covering material layer on at least one side of the patterned first covering material layer, and forming a virtual gate groove, wherein the patterned first covering material layer serves as the first covering layer, and the remaining second covering material layer serves as the second covering layer; filling the gate metal structure in the virtual gate groove.

[0017] In some embodiments, filling the gate metal structure in the virtual gate groove includes: forming a work function metal layer and a metal gate filling layer in the virtual gate groove, the work function metal layer covers the first covering layer and the second covering layer, and covers the sidewalls of the gate spacer.

[0018] In some embodiments, the work function metal layer includes a first work function metal layer, a work function adjustment layer and a second work function metal layer, and the work function adjustment layer is located between the first work function metal layer and the second work function metal layer; the metal gate filling layer includes an Al metal gate filling layer.

[0019] In some embodiments, the gate metal structure is a gate metal structure of a P-type transistor, the work function of the second covering layer is lower than the work function of the first covering layer; the first covering layer includes a TiN layer, and the second covering layer includes a doped polysilicon layer or a silicon-doped TiN layer.

[0020] The semiconductor device provided by some embodiments of the present application includes: a semiconductor substrate; a gate metal structure, arranged on the semiconductor substrate; a gate dielectric layer, arranged between the gate metal structure and the semiconductor substrate; a covering layer, arranged between the gate dielectric layer and the gate metal structure, the covering layer includes a first covering layer and a second covering layer, the first covering layer is located in a central area relative to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, the material of the second covering layer is different from the material of the first covering layer, and the work function of the second covering layer is different from the work function of the first covering layer. In this way, the work function on both sides of the transistor can be changed, especially the work function on the side of the gate metal structure close to the drain, thereby improving the electric field strength in the overlapping area between the gate and the drain, weakening the leakage current of the transistor, and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0022] Figure 1 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application;

[0023] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0024] Figure 3 For this application Figure 5 A schematic diagram of the structure before the first covering material layer is patterned;

[0025] Figure 4 For this application Figure 3 A schematic diagram of a structure in which a first photoresist is provided in a semiconductor device;

[0026] Figure 5 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application after step S21;

[0027] Figure 6 For this application Figure 5 A schematic structural diagram of a semiconductor device after forming a second covering material layer, a virtual gate layer and a hard mask layer;

[0028] Figure 7 For this application Figure 6 A schematic diagram of a structure in which a second photoresist is provided in a semiconductor device;

[0029] Figure 8 For this application Figure 7 A schematic diagram of a structure formed by patterning a hard mask layer, a virtual gate layer, a second covering material layer and a dielectric layer in a semiconductor device;

[0030] Fig. 9 For this application Figure 8 Schematic diagram of the structure of the semiconductor device formed after step S233. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first" and "second" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0033] All directional indications in the embodiments of the present application (such as up, down, left, right, front, back, top, bottom...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0034] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0035] Unless otherwise defined, the term “substantially” mentioned in this application, with respect to numerical quantities or quantitative relationships, can be understood as a range of approximately ±15% of a certain numerical value.

[0036] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0037] In current semiconductor devices, transistors leak electricity when they are in the off state or in the standby state, generating GIDL (gate-induced drain leakage) current, which weakens the ability of the transistor gate and thus affects the performance of the transistor.

[0038] In order to solve the above technical problems and weaken the GIDL current, the present application provides a semiconductor device. Figure 1 , Figure 1 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application.

[0039] The semiconductor device 100 includes: a semiconductor substrate 110, a gate metal structure 120, a gate dielectric layer 130 and a capping layer 140. The gate metal structure 120 is disposed on the semiconductor substrate 110, and the gate dielectric layer 130 is disposed between the gate metal structure 120 and the semiconductor substrate 110. Further, the semiconductor device 100 also includes a source 1501 and a drain 1502, whereby the gate metal structure 120, the source 1501 and the drain 1502 together form a transistor device structure. In some embodiments, the transistor device structure is a field effect transistor. The capping layer 140 is disposed between the gate dielectric layer 130 and the gate metal structure 120. Further, the covering layer 140 includes a first covering layer 141 and a second covering layer 142, wherein the first covering layer 141 is located in the central region relative to the gate metal structure 120, and the second covering layer 142 is located on at least one side of the first covering layer 141, for example, the second covering layer 142 is located on the side of the first covering layer 141 close to the drain 1502, or the second covering layer 142 is located on both sides of the first covering layer 141 close to the drain 1502 and the source 1501. It should be noted that the first covering layer 141 and the second covering layer 142 are two different and independent layers. At the same time, the material of the second covering layer 142 is different from the material of the first covering layer 141, and the work function of the second covering layer 142 is also different from the work function of the first covering layer 141. Specifically, when the gate metal structure 120 is a gate metal structure of a P-type transistor, the work function of the second covering layer 142 is lower than the work function of the first covering layer 141, thereby reducing the electric field strength in the overlapping area between the gate metal structure 120 of the P-type transistor and the drain 1502, or reducing the electric field strength in the overlapping area between the gate metal structure 120 of the P-type transistor and the drain 1502 and the source 1501, thereby weakening the GIDL current; when the gate metal structure 120 is a gate metal structure of an N-type transistor, the work function of the second covering layer 142 is higher than the work function of the first covering layer 141, thereby increasing the electric field strength in the overlapping area between the gate metal structure 120 of the N-type transistor and the drain 1502, or increasing the electric field strength in the overlapping area between the gate metal structure 120 of the N-type transistor and the drain 1502 and the source 1501, thereby weakening the GIDL current. Therefore, the semiconductor device 100 provided in the present application improves the electric field strength in the overlapping area between the gate metal structure 120 and the drain 1502 by changing the work function on both sides of the gate metal structure 120, especially the work function on the side of the gate metal structure 120 close to the drain 1502, thereby weakening the leakage current of the transistor and improving the performance of the semiconductor device 100.

[0040] Since the interface coupling between the gate dielectric layer 130 and the semiconductor substrate 110 is not good and has defects, in some embodiments, the semiconductor device 100 further includes a spacer layer 160, which is disposed between the semiconductor substrate 110 and the gate dielectric layer 130 to improve the interface coupling between the semiconductor substrate 110 and the gate dielectric layer 130, and at the same time plays the role of isolation, insulation and buffering, thereby ensuring the working stability and reliability of the transistor. In some embodiments, the semiconductor substrate 110 may be made of Si, SiC, etc., and the spacer layer 160 may be made of SiO2, SiN, etc., which are not limited here.

[0041] In some embodiments, the first capping layer 141 includes a TiN layer, and the second capping layer 142 includes a doped polysilicon layer or a silicon-doped TiN layer. When the second capping layer 142 is a doped polysilicon layer, and the transistor to which the second capping layer 142 belongs is a P-type transistor, the ions doped in the polysilicon layer are low work function ions, such as ions based on Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac or Th elements; when the transistor to which the second capping layer 142 belongs is an N-type transistor, the ions doped in the polysilicon layer are high work function ions, such as ions based on B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg or Po elements. In other embodiments, the first cover layer 141 and the second cover layer 142 may also be made of other different materials, as long as the work functions of the first cover layer 141 and the second cover layer 142 are different and the electric field strength in the overlapping area between the gate metal structure 120 and the drain 1502 can be improved. Thus, the first cover layer 141 and the second cover layer 142 can be made of different materials according to different requirements and different process conditions, so that the process of the semiconductor device 100 is more flexible, the restrictions on material selection are reduced, and more possibilities are provided for the process technology of the semiconductor device 100. In addition, in some embodiments, the width of the second cover layer 142 relative to the first cover layer 141 can also be set and adjusted according to different requirements and different process conditions, which is not limited here.

[0042] In some embodiments, the gate metal structure 120 is a post-gate structure, that is, the gate metal structure 120 is made using a post-gate process, that is, an RMG (Replacement Metal Gate) process. The dielectric constant of the gate dielectric layer 130 is between 16 and 25, that is, the gate dielectric layer 130 is a HK (High-K) dielectric layer, which refers to a dielectric material layer with a higher dielectric constant than silicon dioxide. In some embodiments, the HK dielectric material used in the gate dielectric layer 130 is hafnium dioxide (HfO2). In other embodiments, the gate dielectric layer 130 can also select a suitable HK dielectric layer according to the material of the gate metal structure 120 and specific process parameters. As the size of the semiconductor device 100 continues to decrease, the post-gate process is adopted to replace silicon dioxide or silicon oxynitride with a HK dielectric layer as a gate oxide layer, which can effectively improve the gate leakage current.

[0043] In some embodiments, the semiconductor device 100 further includes a gate spacer 123 , and the gate spacer 123 is disposed on both sides of the gate dielectric layer 130 , the capping layer 140 , and the gate metal structure 120 .

[0044] In some embodiments, the gate metal structure 120 includes a metal gate filling layer 121 and a work function metal layer 122. The work function metal layer 122 is arranged between the covering layer 140 and the metal gate filling layer 121, and covers the side wall of the metal gate filling layer 121, that is, the work function metal layer 122 is also arranged between the side wall of the metal gate filling layer 121 and the gate sidewall 123.

[0045] In some embodiments, the work function metal layer 122 includes a first work function metal layer 1221, a work function adjustment layer 1222, and a second work function metal layer 1223. Specifically, the work function adjustment layer 1222 is located between the first work function metal layer 1221 and the second work function metal layer 1223. In some embodiments, the material of the first work function metal layer 1221 and the second work function metal layer 1223 is TaN, and the material of the work function adjustment layer 1222 is TiN. In other embodiments, the work function metal layer 122 may also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN. In some embodiments, the metal gate filling layer 121 includes an Al metal gate filling layer. In other embodiments, the metal gate filling layer 121 may also be set to other low-resistance metal materials.

[0046] like Figure 1As shown, in some embodiments, the second covering layer 142 and the first covering layer 141 are disposed in the same layer. In other embodiments, the second covering layer 142 may also be disposed in any layer between the gate dielectric layer 130 and the metal gate filling layer 121. For example, the second covering layer 142 may be disposed in the same layer as a certain layer in the work function metal layer 122, as long as the second covering layer 142 is disposed on both sides of the gate metal structure 120, especially on the side of the gate metal structure 120 close to the drain 1502, so that the work function of the overlapped portion of the gate metal structure 120 and the drain 1502 changes.

[0047] To further solve the above technical problems, the present application also provides a process method for manufacturing a semiconductor device. Figure 2 , Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application.

[0048] Specifically, the process method of the semiconductor device 100 includes:

[0049] Step S1: providing a semiconductor substrate.

[0050] See also Figure 1 First, a semiconductor substrate 110 is provided. In some embodiments, the material of the semiconductor substrate 110 may be Si, SiC, etc., which is not limited here.

[0051] Step S2: forming a gate dielectric layer, a covering layer and a gate metal structure on the semiconductor substrate, wherein the gate dielectric layer is located between the semiconductor substrate and the gate metal structure, the covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer comprises a first covering layer and a second covering layer, the first covering layer is located in a central area relative to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, the material of the second covering layer is different from the material of the first covering layer, and the work function of the second covering layer is different from the work function of the first covering layer.

[0052] Continue to see Figure 1, a gate dielectric layer 130, a capping layer 140 and a gate metal structure 120 are further formed on the semiconductor substrate 110, wherein the gate dielectric layer 130 is located between the semiconductor substrate 110 and the gate metal structure 120. The capping layer 140 is disposed between the gate dielectric layer 130 and the gate metal structure 120. Further, the capping layer 140 includes a first capping layer 141 and a second capping layer 142, wherein the first capping layer 141 is located in a central region relative to the gate metal structure 120, and the second capping layer 142 is located on at least one side of the first capping layer 141, for example, the second capping layer 142 is located on a side of the first capping layer 141 close to the drain 1502, or the second capping layer 142 is located on both sides of the first capping layer 141 close to the drain 1502 and the source 1501. Moreover, the material of the second capping layer 142 is different from the material of the first capping layer 141, and the work function of the second capping layer 142 is different from the work function of the first capping layer 141. Specifically, when the gate metal structure 120 is a gate metal structure of a P-type transistor, the work function of the second covering layer 142 is lower than the work function of the first covering layer 141 ; when the gate metal structure 120 is a gate metal structure of an N-type transistor, the work function of the second covering layer 142 is higher than the work function of the first covering layer 141 .

[0053] In some embodiments, the gate metal structure 120 is a gate-last structure. For details, please refer to the above description of the structure of the semiconductor device 100 , which will not be described here.

[0054] Specifically, step S2: forming a gate dielectric layer, a capping layer and a gate metal structure on the semiconductor substrate further comprises:

[0055] Step S21: forming a dielectric layer and a patterned first covering material layer on the semiconductor substrate, wherein the patterned first covering material layer is located on the dielectric layer.

[0056] See also Figure 5 , Figure 5 A schematic diagram of the structure of the semiconductor device provided in some embodiments of the present application after step S21.

[0057] A dielectric layer 130a and a patterned first covering material layer 141a are formed on the semiconductor substrate 110, and the patterned first covering material layer 141a is located on the dielectric layer 130a. Figure 3 and Figure 4 , Figure 3 For this application Figure 5 A schematic diagram of the structure before the first covering material layer is patterned; Figure 4 For this application Figure 3After the dielectric layer 130a and the first covering material layer 141a are sequentially formed on the semiconductor substrate 110, the first photoresist 10 is disposed relative to the first covering material layer 141a, and then the first covering material layer 141a is etched using the first photoresist 10 as a mask to form a semiconductor device as shown in FIG. Figure 5 The patterned first covering material layer 141a is shown. In some embodiments, before forming the dielectric layer 130a, a spacer layer 160 is formed on the semiconductor substrate 110 to improve the interface coupling between the semiconductor substrate 110 and the dielectric layer 130a, and to play the role of isolation, insulation and buffering, thereby ensuring the working stability and reliability of the transistor. In some embodiments, the semiconductor substrate 110 may be made of Si, SiC, etc., and the spacer layer 160 may be made of SiO2, SiN, etc., which are not limited here.

[0058] Step S22: forming a second covering material layer, wherein the second covering material layer covers the dielectric layer and the patterned first covering material layer.

[0059] See also Figure 6 , Figure 6 For this application Figure 5 Schematic diagram of the structure of the semiconductor device after forming the second covering material layer, the virtual gate layer and the hard mask layer. After the first covering material layer 141a is patterned, a second covering material layer 142a is formed on the first covering material layer 141a and the dielectric layer 130a, as shown in FIG. Figure 6 As shown, the second covering material layer 142a covers the dielectric layer 130a and the first covering material layer 141a, that is, part of the second covering material layer 142a is formed on both sides of the first covering material layer 141a.

[0060] In some embodiments, the first capping material layer 141 a and the second capping material layer 142 a may be formed by an atomic deposition process.

[0061] Step S23: removing part of the second covering material layer, and retaining the second covering material layer on at least one side of the patterned first covering material layer, wherein the patterned first covering material layer serves as the first covering layer, and the remaining second covering material layer serves as the second covering layer.

[0062] After forming the second covering material layer 142a, part of the second covering material layer 142a is removed, and the second covering material layer 142a on at least one side of the patterned first covering material layer 141a is retained, wherein the patterned first covering material layer 141a serves as the first covering layer 141, and the remaining second covering material layer 142a, i.e., the second covering material layer 142a located on at least one side of the first covering layer 141, serves as the second covering layer 142. The materials of the first covering layer 141 and the second covering layer 142 can refer to the above description of the structure of the semiconductor device 100, which will not be described here.

[0063] Specifically, step S23: removing a portion of the second covering material layer, and retaining the second covering material layer on at least one side of the patterned first covering material layer, further comprises:

[0064] Step S231: forming a dummy gate layer and a hard mask layer on the second covering material layer.

[0065] Continue to see Figure 6 A dummy gate layer 170a and a hard mask layer 180 are further formed on the second covering material layer 142a. In some embodiments, the material of the dummy gate layer 170a is polysilicon, and the material of the hard mask layer 180 is SiO2, SiN, etc., which are not limited here.

[0066] Step S232: Patterning the hard mask layer, the virtual gate layer, the second covering material layer and the dielectric layer to form a gate island structure, wherein the remaining dielectric layer in the gate island structure serves as the gate dielectric layer, the remaining virtual gate layer serves as a virtual gate, and the gate island structure includes the patterned first covering material layer, and the portion of the second covering material layer remaining on at least one side of the patterned first covering material layer.

[0067] See also Figure 7 and Figure 8 , Figure 7 For this application Figure 6 A schematic diagram of a structure in which a second photoresist is provided in a semiconductor device; Figure 8 For this application Figure 7Schematic diagram of the structure formed after the semiconductor device in the embodiment of the present invention patterns the hard mask layer, the virtual gate layer, the second covering material layer and the dielectric layer. After forming the virtual gate layer 170a and the hard mask layer 180, a second photoresist 20 is provided. In some embodiments, the width exposed by the second photoresist 20 is greater than the width exposed by the first photoresist 10 to retain the second covering material layer 142a on at least one side of the first covering material layer 141a. Then, the hard mask layer 180, the virtual gate layer 170a, the second covering material layer 142a and the dielectric layer 130a are patterned using the second photoresist 20 as a mask to form a gate island structure 190. Among them, the remaining dielectric layer 130a in the gate island structure 190 serves as the gate dielectric layer 130, and the remaining virtual gate layer 170a serves as the virtual gate 170. In some embodiments, the dielectric constant of the gate dielectric layer 130 is in the range of 16 to 25. For details, please refer to the above description of the structure of the semiconductor device 100, which will not be described here. Further, such as Figure 8 As shown, the gate island structure 190 further includes a patterned first covering material layer 141 a and a portion of a second covering material layer 142 a remaining on at least one side of the patterned first covering material layer 141 a .

[0068] Step S233: forming gate sidewalls on both sides of the gate island structure, and removing portions of the virtual gate and the second covering material layer to expose the patterned first covering material layer and a portion of the second covering material layer remaining on at least one side of the patterned first covering material layer, and forming a virtual gate groove, wherein the patterned first covering material layer serves as the first covering layer, and the remaining second covering material layer serves as the second covering layer.

[0069] See also Fig. 9 , Fig. 9 For this application Figure 8Schematic diagram of the structure of the semiconductor device after step S233. First, a gate sidewall 123 is formed on both sides of the gate island structure 190. In some embodiments, after the gate sidewall 123 is formed, the source 1501 and the drain 1502 are further formed. The specific process technology can refer to the existing technologies related to the sidewall formation and the source and drain injection, which will not be described here. Further, after the gate sidewall 123 is formed, the hard mask layer 180, the virtual gate 170 and the second covering material layer 142a are removed to expose the patterned first covering material layer 141a and the second covering material layer 142a remaining on at least one side of the patterned first covering material layer 141a, that is, the remaining second covering material layer 142a is arranged on the same layer as the first covering material layer 141a, and is only located on at least one side of the patterned first covering material layer 141a, especially on the side of the gate metal structure 120 close to the drain 1502, thereby forming a virtual gate groove 171. Finally, the patterned first covering material layer 141a serves as the first covering layer 141, and the remaining second covering material layer 142a serves as the second covering layer 142. In some embodiments, the dummy gate 170 and part of the second covering material layer 142a may be removed by photolithography, dry etching, wet etching or the like.

[0070] Step S234: filling a gate metal structure in the dummy gate groove.

[0071] See also Figure 1 , the gate metal structure 120 is further filled in the dummy gate groove 171 .

[0072] Specifically, step S234: filling the gate metal structure in the virtual gate groove further includes: forming a work function metal layer 122 and a metal gate filling layer 121 in the virtual gate groove 171, and the work function metal layer 122 covers the first cover layer 141 and the second cover layer 142, and covers the sidewalls of the gate spacer 123. In some embodiments, the work function metal layer 122 and the metal gate filling layer 121 can be formed by an atomic deposition process, and then a CMP (Chemical Mechanical Polishing) process is used for planarization.

[0073] In some embodiments, forming the work function metal layer 122 includes sequentially forming a first work function metal layer 1221, a work function adjustment layer 1222, and a second work function metal layer 1223 in the virtual gate groove 171. In some embodiments, the material of the first work function metal layer 1221 and the second work function metal layer 1223 is TaN, and the material of the work function adjustment layer 1222 is TiN. In other embodiments, the work function metal layer 122 may also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN. In some embodiments, the material of the metal gate filling layer 121 is Al, and in other embodiments, the metal gate filling layer 121 may also be set to other low-resistance metal materials.

[0074] As described above, in some embodiments, the second capping layer 142 is finally formed on the same layer as the first capping layer 141. In other embodiments, the second capping layer 142 may also be formed on any layer between the gate dielectric layer 130 and the metal gate filling layer 121 through other process steps, for example, on the same layer as a certain layer in the work function metal layer 122, as long as the second capping layer 142 is provided on both sides of the gate metal structure 120, especially on the side close to the drain 1502, so that the work function of the overlapped portion of the gate metal structure 120 and the drain 1502 changes.

[0075] The semiconductor device 100 provided in the present application includes: a semiconductor substrate 110; a gate metal structure 120, which is arranged on the semiconductor substrate 110; a gate dielectric layer 130, which is arranged between the gate metal structure 120 and the semiconductor substrate 110; a covering layer 140 is arranged between the gate dielectric layer 130 and the gate metal structure 120, and the covering layer 140 includes a first covering layer 141 and a second covering layer 142, the first covering layer 141 is located in a central area relative to the gate metal structure 120, and the second covering layer 142 is located on at least one side of the first covering layer 141, for example, the second covering layer 142 is located on both sides of the first covering layer 141, or the second covering layer 142 is located on a side of the first covering layer 141 close to the drain 1502, and at the same time, the material of the second covering layer 142 is different from the material of the first covering layer 141, and the work function of the second covering layer 142 is different from the work function of the first covering layer 141. Therefore, the semiconductor device 100 provided in the present application improves the electric field strength in the overlapping region between the gate metal structure 120 and the drain 1502 by changing the work function on both sides of the gate metal structure 120, especially the work function of the gate metal structure 120 close to the drain 1502, thereby weakening the leakage current of the transistor and improving the performance of the semiconductor device 100. Furthermore, the first cover layer 141 and the second cover layer 142 can be made of different materials according to different requirements and different process conditions, so that the process of the semiconductor device 100 is more flexible, the restrictions on material selection are reduced, and more possibilities are provided for the process technology of the semiconductor device 100.

[0076] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: Semiconductor substrate; A gate metal structure is disposed on the semiconductor substrate; A gate dielectric layer, disposed between the gate metal structure and the semiconductor substrate; A covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer includes a first covering layer and a second covering layer, the first covering layer is located in a central area relative to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, the material of the second covering layer is different from the material of the first covering layer, and the work function of the second covering layer is different from the work function of the first covering layer.

2. The semiconductor device according to claim 1, wherein: The first covering layer and the second covering layer are located in the same layer.

3. The semiconductor device according to claim 1, wherein: include: The gate metal structure is a gate metal structure of a P-type transistor, and a work function of the second covering layer is lower than a work function of the first covering layer.

4. The semiconductor device according to claim 3, characterized in that The first covering layer includes a TiN layer, and the second covering layer includes a doped polysilicon layer or a silicon-doped TiN layer.

5. The semiconductor device according to claim 1, wherein: The gate metal structure is a gate-last structure, and the dielectric constant of the gate dielectric layer is in the range of 16 to 25.

6. The semiconductor device according to claim 1, wherein: The gate metal structure comprises: Metal gate filling layer; The work function metal layer is disposed between the cover layer and the metal gate filling layer and covers the side wall of the metal gate filling layer.

7. The semiconductor device according to claim 6, characterized in that The work function metal layer includes a first work function metal layer, a work function adjustment layer and a second work function metal layer, and the work function adjustment layer is located between the first work function metal layer and the second work function metal layer; the metal gate filling layer includes an Al metal gate filling layer.

8. The semiconductor device according to claim 7, characterized in that The second covering layer is disposed on the same layer as any one of the work function metal layers.

9. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; A gate dielectric layer, a covering layer and a gate metal structure are formed on the semiconductor substrate, wherein the gate dielectric layer is located between the semiconductor substrate and the gate metal structure, the covering layer is arranged between the gate dielectric layer and the gate metal structure, the covering layer comprises a first covering layer and a second covering layer, the first covering layer is located in a central area relative to the gate metal structure, the second covering layer is located on at least one side of the first covering layer, the material of the second covering layer is different from the material of the first covering layer, and the work function of the second covering layer is different from the work function of the first covering layer.

10. The process method according to claim 9, characterized in that: The step of forming a gate dielectric layer, a capping layer and a gate metal structure on the semiconductor substrate comprises: forming a dielectric layer and a patterned first covering material layer on the semiconductor substrate, wherein the patterned first covering material layer is located on the dielectric layer; forming a second covering material layer, wherein the second covering material layer covers the dielectric layer and the patterned first covering material layer; A portion of the second covering material layer is removed, and the second covering material layer on at least one side of the patterned first covering material layer is retained, wherein the patterned first covering material layer serves as the first covering layer, and the remaining second covering material layer serves as the second covering layer.

11. The process method according to claim 10, characterized in that: The second covering layer is arranged at one end of the drain of the semiconductor device.

12. The process method according to claim 10, characterized in that: The gate metal structure is a back gate structure, and the dielectric constant of the gate dielectric layer is in the range of 16 to 25; The step of removing a portion of the second covering material layer and retaining the second covering material layer on at least one side of the patterned first covering material layer comprises: forming a dummy gate layer and a hard mask layer on the second covering material layer; Patterning the hard mask layer, the virtual gate layer, the second covering material layer and the dielectric layer to form a gate island structure, wherein the remaining dielectric layer in the gate island structure serves as the gate dielectric layer, the remaining virtual gate layer serves as a virtual gate, and the gate island structure comprises the patterned first covering material layer and a portion of the second covering material layer remaining on at least one side of the patterned first covering material layer; Forming gate sidewalls on both sides of the gate island structure, and removing the dummy gate and part of the second covering material layer to expose the patterned first covering material layer and a portion of the second covering material layer remaining on at least one side of the patterned first covering material layer, and forming a dummy gate groove, wherein the patterned first covering material layer serves as the first covering layer, and the remaining second covering material layer serves as the second covering layer; A gate metal structure is filled in the dummy gate groove.

13. The process method according to claim 12, characterized in that: The step of filling a gate metal structure in the dummy gate groove comprises: A work function metal layer and a metal gate filling layer are formed in the virtual gate groove, and the work function metal layer covers the first covering layer and the second covering layer, and covers the sidewall of the gate spacer.

14. The process method according to claim 13, characterized in that: The work function metal layer includes a first work function metal layer, a work function adjustment layer and a second work function metal layer, and the work function adjustment layer is located between the first work function metal layer and the second work function metal layer; the metal gate filling layer includes an Al metal gate filling layer.

15. The process method according to claim 9, characterized in that: The gate metal structure is a gate metal structure of a P-type transistor, and the work function of the second covering layer is lower than the work function of the first covering layer; The first covering layer includes a TiN layer, and the second covering layer includes a doped polysilicon layer or a silicon-doped TiN layer.

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