Power device and manufacturing method thereof

Abstract

The invention discloses a power device and a manufacturing method of the power device. The power device comprises a semiconductor substrate and a plurality of gate structures, wherein a well region and a drift region are formed in the semiconductor substrate; the gate structures are formed on the semiconductor substrate, each gate structure is in bridge connection with the well region and the drift region, each gate structure comprises a first gate and a second gate, the work functions of the first gate and the second gate are different, the first gate is located on the well region, the second gate is located on the drift region, and the first gate is in contact with the second gate; the gate structure composed of the first gate and the second gate which are different in work function is arranged on the semiconductor substrate, so that the gate structure is in bridge connection with the well region and the drift region, the overall work function difference between the gate structure and the semiconductor substrate is reduced, the voltage endurance capability of the power device is effectively improved, and the hot carrier injection life of the power device is effectively prolonged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a method for manufacturing the power device. Background Art

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the structure between the layers of materials, especially power devices, because the different structures between the layers of materials affect the electrical performance of the devices.

[0003] Current power devices, especially LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices, use a metal gate, and the same type of metal gate is used for the channel region and the drain region. Generally, the voltage withstand or hot carrier injection reliability of the LDMOS device is improved by ion implantation or gate oxide thickness adjustment of the LDMOS device; however, adjusting the ion implantation or gate oxide thickness will reduce the voltage withstand capability of the LDMOS device, thereby affecting the electrical performance of the LDMOS device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a power device and a method for manufacturing the power device, which can effectively improve the voltage resistance of the power device and thus improve the electrical performance of the power device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a power device, comprising: a semiconductor substrate and a plurality of gate structures, wherein a well region and a drift region are formed in the semiconductor substrate; a plurality of gate structures are formed on the semiconductor substrate, and each of the gate structures bridges the well region and the drift region, wherein each of the gate structures comprises a first gate and a second gate, the first gate and the second gate have different work functions, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact with each other.

[0006] In an embodiment of the present application, the gate structure further includes an oxide layer; the oxide layer is disposed on the semiconductor substrate, and the first gate and the second gate are disposed on the oxide layer.

[0007] In an embodiment of the present application, the first gate is a first type metal gate, the second gate structure is a second type metal gate, and the first type metal gate is different from the second type metal gate.

[0008] In one embodiment of the present application, it also includes: an interlayer dielectric layer, in which connecting pillars are formed, and the connecting pillars include a first gate connecting pillar and a second gate connecting pillar; wherein the first gate connecting pillar corresponds to the first gate, and the second gate connecting pillar corresponds to the second gate.

[0009] In one embodiment of the present application, it further includes: a metal layer, which is disposed on the interlayer dielectric layer; wherein the first gate connecting column is connected to the second gate connecting column through the metal layer.

[0010] In one embodiment of the present application, a first doped region is formed in the well region, and a second doped region is formed in the drift region; the connecting column also includes a first source / drain connecting column and a second source / drain connecting column, wherein the first source / drain connecting column corresponds to connecting the first doped region, and the second source / drain connecting column corresponds to connecting the second doped region.

[0011] In one embodiment of the present application, it also includes: an isolation structure, which includes a first isolation structure and a second isolation structure; wherein the first isolation structure is arranged in the drift region, and the gate structure is isolated from the second doped region in the drift region by the first isolation structure; the second isolation structure is arranged in the well region, and different power devices are isolated by the second isolation structure.

[0012] To solve the above technical problems, another technical solution adopted in the present application is: providing a method for manufacturing a power device, comprising: providing a semiconductor substrate and forming a dummy gate structure on the semiconductor substrate, wherein a well region and a drift region are formed in the semiconductor substrate; removing the dummy gate structure and forming a gate structure so that the gate structure bridges the well region and the drift region, wherein the gate structure comprises a first gate and a second gate, the work functions of the first gate and the second gate are different, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact with each other.

[0013] In one embodiment of the present application, the removing of the dummy gate structure and the forming of the gate structure so that the gate structure bridges the well region and the drift region include: removing the dummy gate structure on the well region and forming the first gate on the well region, and removing the dummy gate structure on the drift region and forming the second gate on the drift region.

[0014] In an embodiment of the present application, before forming the first gate and the second gate, the method further includes: forming an oxide layer to cover the exposed well region and the drift region.

[0015] In one embodiment of the present application, after forming the gate structure, it also includes: forming a first interlayer dielectric layer, and forming connecting columns in the first interlayer dielectric layer, the connecting columns including a first gate connecting column and a second gate connecting column; wherein the first gate connecting column corresponds to connecting the first gate, and the second gate connecting column corresponds to connecting the second gate.

[0016] In one embodiment of the present application, the method further includes: forming a metal layer, wherein the metal layer is formed on the first interlayer dielectric layer; wherein the first gate connecting column is connected to the second gate connecting column via the metal layer.

[0017] In one embodiment of the present application, it also includes: forming a first source / drain connection column and a second source / drain connection column in the first interlayer dielectric layer, wherein the first source / drain connection column corresponds to connecting the first doped region in the well region, and the second source / drain connection column corresponds to connecting the second doped region in the drift region.

[0018] In one embodiment of the present application, providing a semiconductor substrate and forming a dummy gate structure on the semiconductor substrate includes: providing a semiconductor substrate and forming a dielectric layer on the semiconductor substrate; forming a first groove in the dielectric layer and forming a dummy gate structure in the first groove; removing the dielectric layer and forming a second interlayer dielectric layer to cover the dummy gate structure.

[0019] In one embodiment of the present application, before forming the pseudo gate structure, it also includes: performing ion implantation in the semiconductor substrate to form a well region and a drift region, wherein the doping types of the well region and the drift region are opposite; after forming the pseudo gate structure, it also includes: performing ion implantation in the well region to form a first doping region, and performing ion implantation in the drift region to form a second doping region, wherein the doping types of the first doping region and the second doping region are opposite.

[0020] In one embodiment of the present application, it also includes: an isolation structure is formed in the semiconductor substrate, the isolation structure includes a first isolation structure and a second isolation structure; wherein the first isolation structure is arranged in the drift region, and the gate structure is isolated from the second heavily doped region in the drift region by the first isolation structure; the second isolation structure is arranged in the well region, and different power devices are isolated by the second isolation structure.

[0021] Different from the prior art, the power device provided by the present application includes: a semiconductor substrate and multiple gate structures; wherein a well region and a drift region are formed in the semiconductor substrate; multiple gate structures are formed on the semiconductor substrate, and each gate structure straddles the well region and the drift region, wherein each gate structure includes a first gate and a second gate, the first gate and the second gate have different work functions, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact; that is, in the present application, a gate structure consisting of a first gate and a second gate with different work functions is formed on the substrate, and the gate structure straddles the well region and the drift region, which can effectively reduce the overall work function difference between the gate and the substrate, reduce the electric field between the gate and the substrate, thereby reducing the carrier concentration, reducing the substrate current, and then providing the voltage resistance and hot carrier injection lifetime of the LDMOS device to improve the electrical performance of the LDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0023] Figure 1 It is a schematic structural diagram of an embodiment of a power device in the present application;

[0024] Figure 2 is a schematic diagram of a top view of a power device according to an embodiment of the present application;

[0025] Figure 3 It is a schematic flow chart of an embodiment of a method for manufacturing a power device in the present application;

[0026] Figure 4 It is a structural schematic diagram of an embodiment of forming a dummy gate structure on a semiconductor substrate in the present application;

[0027] Figure 5 is a structural schematic diagram of an embodiment of forming a first gate in the present application;

[0028] Figure 6 is a schematic structural diagram of an embodiment of forming a second gate in the present application;

[0029] Figure 7 It is a structural schematic diagram of an embodiment of forming a first interlayer dielectric layer and a metal layer in the present application.

[0030] In the accompanying drawings, there are a semiconductor substrate 100, a first isolation structure 1011, a second isolation structure 1012, a well region 110, a first doped region 111, a drift region 120, a second doped region 121, a gate structure 200, a first gate 210, a second gate 220, an oxide layer 230, a first interlayer dielectric layer 300, a first gate connecting column 310, a second gate connecting column 320, a first source / drain connecting column 330, a second source / drain connecting column 340, a metal layer 400, a dummy gate structure 500, and a second interlayer dielectric layer 600. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0033] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0035] Existing LDMOS devices have the characteristics of high withstand voltage, low on-resistance, high voltage and high current drive, and are mainly used in high voltage power analog circuits and drivers, such as power management, display driver, mobile phone amplifier, automotive electronics, etc. They are widely used. At present, the gate of LDMOS devices under silicon-based advanced nodes adopts the form of metal gate, and the same type of metal gate is used for the channel area and the drain area. The withstand voltage capability of LDMOS devices or the reliability of hot carrier injection is improved by adjusting the ion implantation or gate oxide thickness of LDMOS devices. However, adjusting the ion implantation or gate oxide thickness will reduce the withstand voltage capability of LDMOS devices, thereby affecting the electrical performance of LDMOS devices.

[0036] Therefore, a power device is provided, which can effectively improve the voltage resistance of the power device and further improve the electrical performance of the power device.

[0037] See also Figure 1 , Figure 1 It is a schematic structural diagram of the first embodiment of the power device in this application.

[0038] like Figure 1 As shown, the power device of the present application includes: a semiconductor substrate 100 and a plurality of gate structures 200 .

[0039] A well region 110 and a drift region 120 are formed in a semiconductor substrate 100; a plurality of gate structures 200 are formed on the semiconductor substrate 100, and each gate structure 200 bridges the well region 110 and the drift region 120, wherein each gate structure 200 includes a first gate 210 and a second gate 220, the first gate 210 is located on the well region 110, and the second gate 220 is located on the drift region 120; the gate structure 200 also includes an oxide layer 230, the oxide layer 230 is disposed on the semiconductor substrate 100, and the first gate 210 and the second gate 220 are disposed on the oxide layer 230.

[0040] Among them, the semiconductor substrate 100 can be any suitable base material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S□SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0041] The well region 110 refers to a well region formed by ion implantation into a semiconductor substrate. The drift region 120 is also a drift region formed by ion implantation into a semiconductor substrate. A storage gap is provided between the well region and the drift region, and the doping types of the well region and the drift region are opposite.

[0042] In some embodiments, the first gate 210 and the second gate 220 are in contact, and the work functions of the first gate 210 and the second gate 220 are different; that is, in the same power device, different types of gate structures are used, which can effectively improve the voltage resistance of the power device; and the first gate 210 is set on the well region 110, and the second gate 220 is set on the drift region 120, so that the gate structure 200 can bridge the well region 110 and the drift region 120, thereby reducing the overall work function difference between the gate structure 200 and the semiconductor substrate 100.

[0043] In some embodiments, a gate dielectric layer may be further included, and the gate dielectric layer is disposed between the gate structure 200 and the semiconductor substrate 100 ; further, an oxide layer 230 is disposed between the gate dielectric layer and the semiconductor substrate 100 .

[0044] In some embodiments, the first gate 210 may include a first metal covering layer and a first gate metal structure, and the first metal covering layer is disposed between the gate dielectric layer and the first gate metal structure. Further, the first metal covering layer may include a first sub-metal covering layer and a second sub-metal covering layer, the first sub-metal covering layer being located in the central region of the first gate, and the second sub-metal covering layer being located on at least one side of the first sub-metal covering layer, for example, the second sub-metal covering layer being located on the side of the first sub-metal covering layer close to the drain, or the second sub-metal covering layer being located on both sides of the first sub-metal covering layer close to the drain and the source. The material of the second sub-metal covering layer is different from that of the first sub-metal covering layer, and the work function of the second sub-metal covering layer is different from the work function of the first sub-metal covering layer. Specifically, when the first gate is a gate structure of a P-type transistor, the work function of the second sub-metal covering layer is lower than the work function of the first sub-metal covering layer; when the first gate is a gate structure of an N-type transistor, the work function of the second sub-metal covering layer is higher than the work function of the first sub-metal covering layer.

[0045] In other embodiments, the first sub-metal cover layer and the second sub-metal cover layer may be made of the same material, that is, the first sub-metal cover layer and the second sub-metal cover layer have the same work function, for example, the first sub-metal cover layer and the second sub-metal cover layer are both made of TiN.

[0046] Furthermore, the first gate metal structure includes a first work function adjustment layer and a first metal gate filling layer, the first work function adjustment layer covers the first sub-metal covering layer and the second sub-metal covering layer. In some embodiments, the first work function adjustment layer and the first metal gate filling layer can be formed by an atomic deposition process, and then a CMP (Chemical Mechanical Polishing) process is used for planarization. The material of the first work function adjustment layer corresponding to the gate structure of a P-type transistor when the first gate is different from the material of the first work function adjustment layer corresponding to the gate structure of an N-type transistor when the first gate is.

[0047] Further, the first work function adjustment layer may include a first sub-work function adjustment layer, a second sub-work function adjustment layer and a third sub-work function adjustment layer; that is, the first sub-work function adjustment layer, the second sub-work function adjustment layer and the third sub-work function adjustment layer are sequentially formed on the first metal cover layer; taking the gate structure of the first gate being a P-type transistor as an example, the material of the first sub-work function adjustment layer may be TaN, the material of the second sub-work function adjustment layer may be TiN, and the material of the third sub-work function adjustment layer may be TaN. In other embodiments, the first work function adjustment layer may also be set to other structures, or to other materials according to different requirements and process parameters, such as TaAlN, etc. In some embodiments, the material of the first metal gate filling layer is Al. In other embodiments, the first metal gate filling layer may also be set to other low-resistance metal materials.

[0048] If the first gate is a gate structure of an N-type transistor as an example, the material of the first sub-work function adjustment layer can be TaN, the material of the second sub-work function adjustment layer can be TiAl, and the material of the third sub-work function adjustment layer can be TiN / Ti. In other embodiments, the first work function adjustment layer can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlC.

[0049] As described above, in some embodiments, the second sub-metal covering layer is finally formed on the same layer as the first sub-metal covering layer. In other embodiments, the second sub-metal covering layer may also be formed on any layer between the gate dielectric layer and the first metal gate filling layer through other process steps, for example, on the same layer as a layer in the first work function adjustment layer, as long as the second sub-metal covering layer is arranged on both sides of the first gate, especially close to the drain side, so that the work function of the first gate and the drain overlap changes.

[0050] In some embodiments, the second gate may include a second metal covering layer and a second gate metal structure, and the second metal covering layer is disposed between the gate dielectric layer and the second gate metal structure. Further, the second metal covering layer may include a third sub-metal covering layer and a fourth sub-metal covering layer, the third sub-metal covering layer is located in the central region of the second gate, and the fourth sub-metal covering layer is located on at least one side of the third sub-metal covering layer, for example, the fourth sub-metal covering layer is located on the side of the third sub-metal covering layer close to the drain, or the fourth sub-metal covering layer is located on both sides of the third sub-metal covering layer close to the drain and the source. The material of the fourth sub-metal covering layer is different from that of the third sub-metal covering layer, and the work function of the fourth sub-metal covering layer is different from that of the third sub-metal covering layer. Specifically, when the second gate is a gate structure of a P-type transistor, the work function of the fourth sub-metal covering layer is lower than the work function of the third sub-metal covering layer; when the second gate is a gate structure of an N-type transistor, the work function of the fourth sub-metal covering layer is higher than the work function of the third sub-metal covering layer.

[0051] In other embodiments, the third sub-metal cover layer and the fourth sub-metal cover layer may be made of the same material, that is, the third sub-metal cover layer and the fourth sub-metal cover layer have the same work function, for example, the third sub-metal cover layer and the fourth sub-metal cover layer are both made of TiN.

[0052] Furthermore, the second gate metal structure includes a second work function adjustment layer and a second metal gate filling layer, and the second work function adjustment layer covers the third sub-metal covering layer and the fourth sub-metal covering layer. In some embodiments, the second work function adjustment layer and the second metal gate filling layer can be formed by an atomic deposition process, and then a CMP (Chemical Mechanical Polishing) process is used for planarization, wherein the material of the second work function adjustment layer corresponding to the gate structure of the second gate being an N-type transistor is different from the material of the second work function adjustment layer corresponding to the gate structure of the second gate being a P-type transistor.

[0053] Further, the second work function adjustment layer may include a fourth sub-work function adjustment layer, a fifth sub-work function adjustment layer and a sixth sub-work function adjustment layer; that is, the fourth sub-work function adjustment layer, the fifth sub-work function adjustment layer and the sixth sub-work function adjustment layer are sequentially formed on the second metal cover layer; taking the second gate as a gate structure of an N-type transistor as an example, the material of the fourth sub-work function adjustment layer may be TaN, the material of the fifth sub-work function adjustment layer may be TiAl, and the material of the sixth sub-work function adjustment layer may be TiN / Ti. In other embodiments, the second work function adjustment layer may also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlC. In some embodiments, the material of the second metal gate filling layer is Al. In other embodiments, the second metal gate filling layer may also be set to other low-resistance metal materials.

[0054] If the second gate is a gate structure of a P-type transistor as an example, the material of the fourth sub-work function adjustment layer can be TaN, the material of the fifth sub-work function adjustment layer can be TiN, and the material of the sixth sub-work function adjustment layer can be TaN. In other embodiments, the second work function adjustment layer 4102 can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN.

[0055] As described above, in some embodiments, the fourth sub-metal covering layer is finally formed on the same layer as the third sub-metal covering layer. In other embodiments, the fourth sub-metal covering layer may also be formed on any layer between the gate dielectric layer and the second metal gate filling layer through other process steps, for example, on the same layer as a layer in the second work function adjustment layer, as long as the fourth sub-metal covering layer is arranged on both sides of the second gate, especially close to the drain side, so that the work function of the second gate and the drain overlap changes.

[0056] Further, the first gate is a first type metal gate, the second gate is a second type metal gate, and the first type metal gate is different from the second type metal gate.

[0057] The first type metal gate may be a P-type metal gate, and the second type metal gate may be an N-type metal gate; or the first type metal gate may be an N-type metal gate, and the second type metal gate may be a P-type metal gate.

[0058] For example, when the power device is an N-type LDMOS device, the well region is P-type, the drift region is N-type, the first type metal gate is N-type, and the second type metal gate is P-type. When the power device is a P-type LDMOS device, the well region is N-type, the drift region is P-type, the first type metal gate is P-type, and the second type metal gate is N-type.

[0059] Continue reading Figure 1The power device also includes a first interlayer dielectric layer 300, in which connecting pillars are arranged, and the connecting pillars include a first gate connecting pillar 310 and a second gate connecting pillar 320; wherein the first gate connecting pillar 310 corresponds to connecting the first gate 210, and the second gate connecting pillar 320 corresponds to connecting the second gate 220.

[0060] Specifically, the first gate 210 and the second gate 220 form a gate structure, which is arranged on the oxide layer 230. The first gate connecting column 310 corresponds to the first gate 210 on the oxide layer 230 and leads the first gate out; the second gate connecting column 320 corresponds to the second gate 220 on the oxide layer 230 and leads the second gate out.

[0061] Further, see Figure 1 The power device further includes a metal layer 400, which is disposed on the first interlayer dielectric layer 300, and the first gate connection pillar 310 is connected to the second gate connection pillar 320 via the metal layer 400, so that the first gate 210 and the second gate 220 form a gate structure of the same LDMOS device. Because the work functions of the first gate 210 and the second gate 220 are different, the overall work function difference between the gate structure and the semiconductor substrate is reduced.

[0062] Further, see Figure 1 A first doping region 111 is formed in the well region 110 of the power device, and a second doping region 121 is formed in the drift region 120 of the power device.

[0063] Correspondingly, the connection pillars may also include a first source / drain connection pillar 330 and a second source / drain connection pillar 340; wherein the first source / drain connection pillar 330 is connected to the first doping region 111, and the second source / drain connection pillar 340 is connected to the second doping region 121. The first doping region 111 may be a source region, and the second doping region 121 may be a drain region, that is, the well region 110 has a source region, and the drift region 120 has a drain region; the drift region 120 may be a low-concentration ion-doped region, and also a high-resistance region, capable of withstanding a relatively high voltage, the drain region may be a high-concentration ion-doped region, and the source region may be a medium-concentration ion-doped region.

[0064] In some embodiments, the first doping region 111 and the second doping region 121 may be source and drain regions, that is, the first doping region 111 may be a source region and the second doping region 121 may be a drain region, or the first doping region 111 is a drain region and the second doping region 121 is a source region.

[0065] Further, see Figure 1An isolation structure is also provided in the semiconductor substrate 100 of the power device, and the isolation structure includes a first isolation structure 1011 and a second isolation structure 1012; wherein the first isolation structure 1011 is provided in the drift region 120, and the gate structure 200 is isolated from the second doped region 121 in the drift region 120 by the first isolation structure 1011; the second isolation structure 1012 is provided in the well region 110, and different power devices are isolated by the second isolation structure.

[0066] In some embodiments, a plurality of first isolation structures 1011 may be provided in the drift region 120, and a second doped region 121 may be provided between two first isolation structures 1011, so that the second doped region 121 is isolated from the gate structures 200 adjacent to both sides; wherein the isolation structure may be a shallow trench isolation (STI) structure.

[0067] In some embodiments, a lightly doped region (not shown in the figure) may also be formed in the semiconductor substrate, that is, a lightly doped region implanted by LDD (Lightly Doped Drain) ions. For example, the first lightly doped region and the second lightly doped region are in contact with the first doping region 111 and the second doping region 121, respectively, that is, the first lightly doped region may be in contact with the source region and the second lightly doped region may be in contact with the drain region, or the first lightly doped region may be in contact with the drain region and the second lightly doped region may be in contact with the source region.

[0068] by Figure 1 Taking LDMOS as an example, an N-type LDMOS device and a P-type LDMOS device are used for description below.

[0069] When the power device is an N-type LDMOS device, the X direction is taken as the first direction, that is, the direction from the drift region 120 to the right well region 110 is taken as the first direction; an N-type drift region 120 is provided in the semiconductor substrate 100 of the N-type LDMOS device, and P-type well regions 110 are provided on both sides of the N-type drift region 120, and an N-type second doping region 121 is provided in the N-type drift region as a drain terminal, and an N-type first doping region 111 is provided in the P-type well region as a source terminal; and an oxide layer 230 is formed on the semiconductor substrate at the junction of the N-type drift region and the P-type well region, that is, the oxide layer 230 covers the portion The present invention is divided into an N-type drift region and a P-type well region, and a P-type metal gate is formed on the oxide layer 230 corresponding to the N-type drift region, and an N-type metal gate is formed on the oxide layer 230 corresponding to the P-type well region; and then covered with an interlayer dielectric layer 300, and a first gate connecting column 310 and a second gate connecting column 320 are formed in the interlayer dielectric layer, the first gate connecting column corresponds to the N-type metal gate, and the second gate connecting column corresponds to the P-type metal gate; and a metal layer 400 is covered on the interlayer dielectric layer, so that the first gate connecting column 310 and the second gate connecting column 320 are connected together through the metal layer 400.

[0070] When the power device is a P-type LDMOS device, the X direction is taken as the first direction, and the direction of the drift region 120 toward the well region 110 on the right is the first direction; a P-type drift region 120 is provided in the semiconductor substrate 100 of the P-type LDMOS device, and N-type well regions 110 are provided on both sides of the P-type drift region 120, and a P-type second doping region 121 is provided in the P-type drift region as a drain terminal, and a P-type first doping region 111 is provided in the N-type well region as a source terminal; and an oxide layer 230 is formed on the semiconductor substrate at the junction of the P-type drift region and the N-type well region, that is, the oxide layer 230 covers part A P-type drift region is formed, and a part of the N-type well region is covered, and then an N-type metal gate is formed on the oxide layer 230 corresponding to the P-type drift region, and a P-type metal gate is formed on the oxide layer 230 corresponding to the N-type well region; and then an interlayer dielectric layer 300 is covered, and a first gate connecting column 310 and a second gate connecting column 320 are formed in the interlayer dielectric layer, the first gate connecting column corresponds to the P-type metal gate, and the second gate connecting column corresponds to the N-type metal gate; and a metal layer 400 is covered on the interlayer dielectric layer, so that the first gate connecting column 310 and the second gate connecting column 320 are connected together through the metal layer 400.

[0071] In order to make the structure of the power device clearer, a top view is used below to illustrate it.

[0072] See also Figure 2 , Figure 2 It is a schematic diagram of a top view of the structure of an embodiment of a power device in the present application.

[0073] Taking the X direction as the first direction and the Y direction as the second direction, the direction of the drift region 120 toward the well region 110 on the right is the first direction, and the first gate 210 and the second gate 220 extend along the second direction.

[0074] like Figure 2 As shown, when the power device is an N-type LDMOS device, the first gate is an N-type metal gate, the second gate is a P-type metal gate, the first gate 210 and the second gate 220 are arranged on the semiconductor substrate and extend along the second direction, and corresponding first gate connection pillars 310 and second gate connection pillars 320 are arranged in the interlayer dielectric layer, the first gate connection pillars 310 are correspondingly connected to the N-type metal gate, the second gate connection pillars 320 are correspondingly connected to the P-type metal gate, and the first gate connection pillars 310 and the second gate connection pillars 320 are connected together through the metal layer 400. In addition, a first source / drain connection pillar 330 and a second source / drain connection pillar 340 are also arranged in the interlayer dielectric layer, the first source / drain connection pillar 330 is correspondingly connected to the first doped region, and the second source / drain connection pillar 340 is correspondingly connected to the second doped region.

[0075] like Figure 2 As shown, when the power device is a P-type LDMOS device, the first gate is a P-type metal gate, the second gate is an N-type metal gate, the first gate 210 and the second gate 220 are arranged on the semiconductor substrate and extend along the second direction, and corresponding first gate connection pillars 310 and second gate connection pillars 320 are arranged in the interlayer dielectric layer, the first gate connection pillar 310 is correspondingly connected to the P-type metal gate, the second gate connection pillar 320 is correspondingly connected to the N-type metal gate, and the first gate connection pillar 310 and the second gate connection pillar 320 are connected together through the metal layer 400. In addition, a first source / drain connection pillar 330 and a second source / drain connection pillar 340 are also arranged in the interlayer dielectric layer, the first source / drain connection pillar 330 is correspondingly connected to the first doped region, and the second source / drain connection pillar 340 is correspondingly connected to the second doped region.

[0076] In this embodiment, a gate structure consisting of a first gate and a second gate having different work functions is formed on the substrate, and the gate structure bridges the well region and the drift region, which can effectively reduce the overall work function difference between the gate and the substrate, reduce the electric field between the gate and the substrate, thereby reducing the carrier concentration, reducing the substrate current, and further improving the voltage resistance and hot carrier injection life of the LDMOS device, so as to improve the electrical performance of the LDMOS device.

[0077] The present application also provides a method for manufacturing a power device.

[0078] See also Figure 3 , Figure 3 It is a schematic flow chart of an embodiment of a method for manufacturing a power device in the present application.

[0079] like Figure 3 As shown, the manufacturing method of the power device of the present application includes the following steps.

[0080] S10, providing a semiconductor substrate, and forming a dummy gate structure on the semiconductor substrate, wherein a well region and a drift region are formed in the semiconductor substrate.

[0081] Specifically, a semiconductor substrate 100 is provided. In some embodiments, the material of the semiconductor substrate may be Si, SiC, etc., which is not limited herein.

[0082] The overall process of the front-end process is: providing a semiconductor substrate, forming an active area (AA), performing ion implantation and annealing in the semiconductor substrate to form a well region and a drift region in the semiconductor substrate, and then forming a high dielectric constant oxide layer and a corresponding dummy gate structure.

[0083] In some embodiments, a corresponding isolation sidewall of a pseudo gate structure may be formed, and LDD ion implantation and annealing may be performed, i.e., lightly doped drain extension (LDD) may be performed to form a main isolation sidewall (MainSpacer), and then source / drain region implantation may be performed to form source / drain region, and metal silicide (Silicide) and metal silicide blocking layer (Salicide Block, SAB) and source / drain region may be annealed, and the interlayer dielectric layer may be covered.

[0084] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a dummy gate structure on a semiconductor substrate in the present application.

[0085] like Figure 4 As shown, the semiconductor substrate 100 includes a well region 110 and a drift region 120, and a first doped region 111 is formed in the well region 110, a second doped region 121 is formed in the drift region 120, and a second isolation structure 1012 is also formed in the well region 110, and a first isolation structure 1011 is also formed in the drift region 120, wherein the second isolation structure 1012 is used to isolate from another power device, and the first doped region 111 can be arranged between two first isolation structures 1011.

[0086] First, a semiconductor substrate 100 is provided, and a dielectric layer is formed on the semiconductor substrate.

[0087] In some embodiments, before forming the dummy gate structure, the method further includes:

[0088] Ion implantation is performed in the semiconductor substrate 100 to form a well region 110 and a drift region 120 , wherein the well region 110 and the drift region 120 have opposite doping types.

[0089] In some embodiments, an isolation structure can also be formed in the semiconductor substrate 100, and the isolation structure includes a first isolation structure 1011 and a second isolation structure 1012, wherein the first isolation structure 1011 is arranged in the drift region 120, and the gate structure is isolated from the second doped region 121 in the drift region 120 by the first isolation structure 1011; the second isolation structure 1012 is arranged in the well region 110, and different power devices are isolated by the second isolation structure.

[0090] Next, a first groove is formed in the dielectric layer, and a dummy gate structure 500 is formed in the first groove.

[0091] In some embodiments, after forming the dummy gate structure, the method further includes:

[0092] Ion implantation is performed in the well region to form a first doping region 111 , and ion implantation is performed in the drift region to form a second doping region 121 , wherein the first doping region 111 and the second doping region 121 have opposite doping types, namely, source / drain regions are formed.

[0093] The first doping region 111 may be an N+ doping region, and the second doping region 121 may be a P+ doping region.

[0094] Then, the dielectric layer is removed to form a second interlayer dielectric layer 600 to cover the dummy gate structure 500 , so as to complete the manufacturing process of forming the dummy gate structure on the semiconductor substrate 100 .

[0095] In some embodiments, a first lightly doped region (not marked in the figure) and a second lightly doped region (not marked in the figure) may also be formed in the semiconductor substrate, wherein the first lightly doped region and the second lightly doped region are in contact with the first doping region 111 and the second doping region 121, respectively, that is, the first lightly doped region may be in contact with the source region and the second lightly doped region may be in contact with the drain region, or the first lightly doped region may be in contact with the drain region and the second lightly doped region may be in contact with the source region.

[0096] S20, removing the dummy gate structure and forming a gate structure so that the gate structure bridges the well region and the drift region, wherein the gate structure includes a first gate and a second gate, the first gate and the second gate have different work functions, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact.

[0097] The gate structure is a gate-last structure, that is, the gate structure is made by a gate-last process (Replacement Metal Gate, RMG, metal replacement gate), that is, the dummy gate structure is removed, and a gate structure is formed in the removed area, and the gate structure is a metal gate structure.

[0098] Because the gate structure includes the first gate 210 and the second gate 220 , the first gate 210 and the second gate 220 may be formed in any order, that is, the first gate 210 may be formed first, or the second gate 220 may be formed first. The following description will take forming the first gate 210 first as an example.

[0099] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming a first gate in the present application.

[0100] like Figure 5 As shown, in Figure 4 On this basis, the dummy gate structure corresponding to the well region is removed.

[0101] Specifically, a second groove is opened from the second interlayer dielectric layer 600 toward the semiconductor substrate 100 to expose the dummy gate structure corresponding to the well region 110 , and then a portion of the dummy gate structure corresponding to the well region 110 is removed, and then a metal gate material is filled in the removed area to form the first gate 210 .

[0102] In some embodiments, the first gate 210 includes a first metal covering layer and a first gate metal structure, wherein the first metal covering layer may include a first sub-metal covering layer and a second sub-metal covering layer, the first sub-metal covering layer is located in the central area of ​​the first gate, and the second sub-metal covering layer is located on at least one side of the first sub-metal covering layer; the first gate metal structure includes a first work function adjustment layer and a first metal gate filling layer, the first work function adjustment layer covers the first sub-metal covering layer and the second sub-metal covering layer; the first work function adjustment layer may include a first sub-work function adjustment layer, a second sub-work function adjustment layer and a third sub-work function adjustment layer, which are sequentially formed in the second groove, and then the first metal gate filling layer is filled in the second groove, and the first metal covering layer and the first gate metal structure form the first gate 210.

[0103] In some embodiments, before forming the first gate, an oxide layer 230 needs to be formed to cover the exposed well region 110 .

[0104] Then, a second gate electrode is formed.

[0105] See also Figure 6 , Figure 6 It is a structural schematic diagram of an embodiment of forming a second gate in the present application.

[0106] like Figure 6 As shown, in Figure 5 On this basis, the dummy gate structure corresponding to the drift region 120 is removed.

[0107] Specifically, a third groove is opened from the second interlayer dielectric layer 600 toward the semiconductor substrate to expose the dummy gate structure corresponding to the drift region 120 , and then a portion of the dummy gate structure corresponding to the drift region 120 is removed, and then a metal gate material is filled in the removed area to form the second gate 220 .

[0108] In some embodiments, the second gate 220 includes a second metal covering layer and a second gate metal structure, wherein the second metal covering layer may include a third sub-metal covering layer and a fourth sub-metal covering layer, the third sub-metal covering layer is located in the central area of ​​the second gate, and the fourth sub-metal covering layer is located on at least one side of the third sub-metal covering layer; the second gate metal structure includes a second work function adjustment layer and a second metal gate filling layer, the second work function adjustment layer covers the third sub-metal covering layer and the fourth sub-metal covering layer; the second work function adjustment layer may include a fourth sub-work function adjustment layer, a fifth sub-work function adjustment layer and a sixth sub-work function adjustment layer, which are sequentially formed in the second groove, and then the second metal gate filling layer is filled in the second groove, and the second gate 220 is composed of the second metal covering layer and the second gate metal structure.

[0109] In some embodiments, before forming the second gate, an oxide layer 230 needs to be formed to cover the exposed drift region 220 .

[0110] At this time, the oxide layer corresponding to the first gate 210 and the oxide layer corresponding to the second gate 220 are integrated as a whole, so that the oxide layer, the first gate and the second gate form a gate structure 200 . Therefore, the gate structure 200 bridges the well region 110 and the drift region 120 .

[0111] In some embodiments, a gate dielectric layer may be further formed, and the gate dielectric layer is disposed on the oxide layer 230 , that is, the gate dielectric layer is disposed between the oxide layer 230 and the gate structure 200 .

[0112] Furthermore, after the gate structure is formed, a first interlayer dielectric layer and a metal layer need to be formed.

[0113] See also Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of forming a first interlayer dielectric layer and a metal layer in the present application.

[0114] like Figure 7 As shown, in Figure 6On the basis of the present invention, a first interlayer dielectric layer 300 is formed, and connecting pillars are formed in the first interlayer dielectric layer 300, the connecting pillars including a first gate connecting pillar 310 and a second gate connecting pillar 320; wherein the first gate connecting pillar 310 is correspondingly connected to the first gate 210 to lead out the first gate 210; the second gate connecting pillar 320 is correspondingly connected to the second gate 220 to lead out the second gate 220; and a metal layer 400 is formed on the first interlayer dielectric layer 300 to connect the first gate connecting pillar 310 and the second gate connecting pillar 320 together.

[0115] In some embodiments, the second interlayer dielectric layer 600 may be removed and then covered with the first interlayer dielectric layer 300; or the first interlayer dielectric layer 300 may be directly covered on the second interlayer dielectric layer 600. Figure 7 An example is given for explanation including only the first interlayer dielectric layer.

[0116] In some embodiments, a first source / drain connection column 330 and a second source / drain connection column 340 are further formed in the first interlayer dielectric layer 300, and correspondingly, a corresponding metal layer 400 may also be formed on the first source / drain connection column 330 and the second source / drain connection column 340; Figure 7 As shown, the first source / drain connection column 330 corresponds to the first doped region 111 in the well region 110 to lead out the first doped region 111, and the second source / drain connection column 340 corresponds to the second doped region 121 in the drift region 120 to lead out the second doped region 121; for example, the first source / drain connection column 330 corresponds to the source region to lead out the source region, and the second source / drain connection column 340 corresponds to the drain region to lead out the drain region.

[0117] In some embodiments, the first gate connecting pillar 310, the second gate connecting pillar 320, the first source / drain connecting pillar 330 and the second source / drain connecting pillar 340 can be prepared by the same process, that is, they can be formed simultaneously; the metal layer 400 on each connecting pillar can also be prepared by the same process, that is, they can also be formed simultaneously.

[0118] In the present embodiment, a base structure of a semiconductor substrate forming a pseudo gate structure is provided, and a well region and a drift region are formed in the semiconductor substrate, and then a gate structure of a metal gate is formed after removing the pseudo gate structure of polysilicon, and the gate structure bridges the well region and the drift region, and the gate structure is composed of a first gate and a second gate with different work functions, which can effectively reduce the overall work function difference between the gate and the substrate, reduce the electric field between the gate and the substrate, thereby reducing the carrier concentration, reducing the substrate current, and then providing the voltage resistance and hot carrier injection life of the LDMOS device to improve the electrical performance of the LDMOS device.

[0119] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A semiconductor substrate, wherein a well region and a drift region are formed in the semiconductor substrate; A plurality of gate structures are formed on the semiconductor substrate, and each of the gate structures bridges the well region and the drift region, wherein each of the gate structures includes a first gate and a second gate, the first gate and the second gate have different work functions, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact with each other.

2. The power device according to claim 1, characterized in that: The gate structure also includes an oxide layer; The oxide layer is disposed on the semiconductor substrate, and the first gate and the second gate are disposed on the oxide layer.

3. The power device according to claim 1, characterized in that: The first gate is a first type metal gate, and the second gate is a second type metal gate, and the first type metal gate is different from the second type metal gate.

4. The power device according to claim 1, characterized in that: Also includes: An interlayer dielectric layer, wherein connection pillars are formed in the interlayer dielectric layer, and the connection pillars include a first gate connection pillar and a second gate connection pillar; The first gate connection column is connected to the first gate, and the second gate connection column is connected to the second gate.

5. The power device according to claim 4, characterized in that: Also includes: A metal layer, the metal layer being disposed on the interlayer dielectric layer; The first gate connecting column is connected to the second gate connecting column through the metal layer.

6. The power device according to claim 4, characterized in that: A first doping region is formed in the well region, and a second doping region is formed in the drift region; The connection pillar further includes a first source / drain connection pillar and a second source / drain connection pillar, wherein the first source / drain connection pillar is correspondingly connected to the first doped region, and the second source / drain connection pillar is correspondingly connected to the second doped region.

7. The power device according to claim 1, characterized in that: Also includes: An isolation structure, the isolation structure comprising a first isolation structure and a second isolation structure; Wherein, the first isolation structure is disposed in the drift region, and the gate structure is isolated from the second doping region in the drift region by the first isolation structure; The second isolation structure is disposed in the well region, and different power devices are isolated by the second isolation structure.

8. A method for manufacturing a power device, characterized in that: include: Providing a semiconductor substrate, and forming a dummy gate structure on the semiconductor substrate, wherein a well region and a drift region are formed in the semiconductor substrate; The dummy gate structure is removed, and a gate structure is formed so that the gate structure bridges the well region and the drift region, wherein the gate structure includes a first gate and a second gate, the first gate and the second gate have different work functions, the first gate is located on the well region, the second gate is located on the drift region, and the first gate and the second gate are in contact.

9. The manufacturing method according to claim 8, characterized in that: The removing of the dummy gate structure and forming a gate structure so that the gate structure straddles the well region and the drift region comprises: The dummy gate structure on the well region is removed, and the first gate is formed on the well region, and the dummy gate structure on the drift region is removed, and the second gate is formed on the drift region.

10. The manufacturing method according to claim 9, characterized in that: Before forming the first gate and the second gate, the method further includes: An oxide layer is formed to cover the exposed well region and the drift region.

11. The manufacturing method according to claim 8, characterized in that: After forming the gate structure, it also includes: Forming a first interlayer dielectric layer, and forming connecting pillars in the first interlayer dielectric layer, wherein the connecting pillars include a first gate connecting pillar and a second gate connecting pillar; The first gate connection column is connected to the first gate, and the second gate connection column is connected to the second gate.

12. The manufacturing method according to claim 11, characterized in that: Also includes: forming a metal layer, wherein the metal layer is formed on the first interlayer dielectric layer; The first gate connecting column is connected to the second gate connecting column through the metal layer.

13. The manufacturing method according to claim 11, characterized in that: Also includes: A first source / drain connection column and a second source / drain connection column are formed in the first interlayer dielectric layer, wherein the first source / drain connection column is correspondingly connected to the first doped region in the well region, and the second source / drain connection column is correspondingly connected to the second doped region in the drift region.

14. The manufacturing method according to claim 8, characterized in that: The step of providing a semiconductor substrate and forming a dummy gate structure on the semiconductor substrate comprises: Providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate; forming a first groove in the dielectric layer, and forming a dummy gate structure in the first groove; The dielectric layer is removed, and a second interlayer dielectric layer is formed to cover the dummy gate structure.

15. The manufacturing method according to claim 14, characterized in that: Before forming the dummy gate structure, the method further includes: Performing ion implantation in the semiconductor substrate to form a well region and a drift region, wherein the well region and the drift region have opposite doping types; After forming the dummy gate structure, the method further includes: Ion implantation is performed in the well region to form a first doped region, and ion implantation is performed in the drift region to form a second doped region, wherein the first doped region and the second doped region have opposite doping types.

16. The manufacturing method according to claim 15, characterized in that: Also includes: forming an isolation structure in the semiconductor substrate, the isolation structure comprising a first isolation structure and a second isolation structure; Wherein, the first isolation structure is disposed in the drift region, and the gate structure is isolated from the second doping region in the drift region by the first isolation structure; The second isolation structure is disposed in the well region, and different power devices are isolated by the second isolation structure.

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