Array substrate and preparation method thereof, display panel and display device

Abstract

The invention provides an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises a substrate and an oxide thin film transistor arranged on the substrate, the oxide thin film transistor comprises an oxide channel layer, a first gate insulating layer and a first gate layer; wherein the first gate insulating layer is arranged on the side, away from the substrate, of the oxide channel layer, the first gate layer is arranged on the side, away from the substrate, of the first gate insulating layer, and a gap is formed between the first gate layer and the first gate insulating layer; and the orthographic projection of the gap on the oxide channel layer is located in the orthographic projection area of the first gate layer on the oxide channel layer. The array substrate has a large subthreshold swing of a transfer characteristic curve, the uniformity of a display panel is improved, the display panel has a good display effect, and the yield and product competitiveness of the display panel are improved.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] Oxide thin film transistor (Oxide TFT) technology has strong process stability and uniformity of key channel process parameters, and has significant advantages in the application of large-size display screens (flat panels, computers, and TV screens). However, the current subthreshold swing (SS) of OxideTFT is around 0.2, which is difficult to make larger and lower than the low-temperature polysilicon thin film transistor (full name: Low Temperature Poly-Silicon Thin Film Transistor, referred to as: LTPS TFT). The current subthreshold (SS) of low-temperature polysilicon thin film transistors is greater than 0.4, resulting in poor uniformity of OLED display quality. Therefore, improving the subthreshold of oxide thin film transistors is the key to improving the display effect of OLEDs. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide an array substrate and a preparation method thereof, a display panel and a display device, which can help reduce the average dielectric constant between the gate layer and the oxide channel layer and reduce the capacitance between the gate layer and the oxide channel layer by setting a gap between the gate layer and the gate insulating layer, thereby helping to increase the subthreshold swing of the transfer characteristic curve and improve the uniformity of the display panel, so that the display panel has a good display effect, thereby improving the yield rate and product competitiveness of the display panel.

[0004] In a first aspect, the present invention provides an array substrate, comprising: a substrate and an oxide thin film transistor disposed on the substrate;

[0005] The oxide thin film transistor comprises an oxide channel layer, a first gate insulating layer and a first gate layer;

[0006] Among them, the first gate insulation layer is arranged on the side of the oxide channel layer facing away from the substrate, the first gate layer is arranged on the side of the first gate insulation layer facing away from the substrate, and a gap is formed between the first gate layer and the first gate insulation layer, and the orthographic projection of the gap on the oxide channel layer is located inside the orthographic projection area of ​​the first gate layer on the oxide channel layer.

[0007] As an optional scheme, an oxide conductive layer is arranged between the first gate layer and the first gate insulating layer, and the edge of the oxide conductive layer on the oxide channel layer in the first direction protrudes beyond the edge of the first gate layer on the oxide channel layer in the first direction, and the gap is formed by etching the oxide conductive layer; wherein the first direction refers to the radial direction of the oxide channel layer.

[0008] As an optional solution, the gap extends along the second direction, a size of the gap in the second direction is less than or equal to a size of the oxide channel layer in the second direction, and the first direction is perpendicular to the second direction.

[0009] As an optional solution, there are two gaps, the two gaps are spaced apart in the first direction, and the orthographic projections of the two gaps on the oxide channel layer are respectively located in a region where the orthographic projection of the first gate layer on the oxide channel layer is close to an edge.

[0010] As an optional solution, the gap extends along the first direction, and a size of the gap in the first direction is less than or equal to a size of the first gate layer in the first direction.

[0011] As an optional solution, the gaps include at least two, and the at least two gaps are arranged at intervals along the second direction.

[0012] As an optional solution, the size of the gap in the second direction is greater than 0 and less than or equal to 1 μm.

[0013] As an optional solution, the oxide thin film transistor also includes a second gate layer and a second gate insulating layer. The second gate layer is arranged on the substrate, the second gate insulating layer is arranged on the side of the second gate layer away from the substrate, and the second gate layer is located on the side of the oxide channel layer close to the substrate.

[0014] As an optional solution, the oxide thin film transistor further includes an interlayer dielectric layer and a source-drain electrode layer, wherein the interlayer dielectric layer covers a side of the first gate layer facing away from the substrate, and the source-drain electrode layer is arranged on a side of the interlayer dielectric layer facing away from the substrate.

[0015] In a second aspect, the present invention provides a method for preparing an array substrate, comprising the following steps:

[0016] providing a substrate;

[0017] forming an oxide channel layer and a first gate insulating layer in sequence on the substrate;

[0018] An oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, and an edge of an orthogonal projection of the oxide conductive layer on the oxide channel layer in the first direction protrudes from an edge of an orthogonal projection of the first gate layer on the oxide channel layer in the first direction;

[0019] The oxide conductive layer is etched to form a gap between the first gate layer and the first gate insulating layer, and the orthogonal projection of the gap on the oxide channel layer is located inside the orthogonal projection region of the first gate layer on the oxide channel layer.

[0020] As an optional solution, an oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising:

[0021] forming an oxide conductive layer on a side of the first gate insulating layer facing away from the substrate;

[0022] A first gate layer is stacked on the oxide conductive layer, and an edge of the first gate layer in a first direction is retracted or flush with an edge of the oxide conductive layer in the first direction.

[0023] As an optional solution, etching the oxide conductive layer to form a gap between the first gate layer and the first gate insulating layer includes:

[0024] A portion of the oxide conductive layer is etched so that the remaining oxide conductive layer supports the first gate layer, and the gaps are located at two sides of the remaining oxide conductive layer in the first direction.

[0025] As an optional solution, an oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising:

[0026] An oxide conductive layer is formed on a side of the first gate insulating layer facing away from the substrate, the oxide conductive layer includes a first region and a second region spaced apart along a first direction, the first region and the second region extend along a second direction respectively, and the size of each of the first region and the second region in the second direction is less than or equal to the size of the oxide channel layer in the second direction, and the first direction is perpendicular to the second direction;

[0027] The first gate layer is formed so that the first gate layer is stacked in the first region and the second region and fills a gap between the first region and the second region, and an edge of the first gate layer is retracted or flush with an edge of the first region and an edge of the second region in a first direction.

[0028] As an optional solution, an oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising:

[0029] forming an oxide conductive layer on a side of the first gate insulating layer facing away from the substrate, wherein the oxide conductive layer includes at least one sub-region spaced apart in the second direction, and the sub-region extends along the first direction;

[0030] The first gate layer is formed so that it covers the oxide conductive layer and the gap between two adjacent sub-regions in the second direction, and the edge of the first gate layer in the first direction is retracted or flush with the edge of each sub-region.

[0031] As an optional solution, before sequentially forming an oxide channel layer and a first gate insulating layer on the substrate, the method further includes:

[0032] A second gate layer and a second gate insulating layer are sequentially formed on the substrate, wherein the second gate layer is located on a side of the oxide channel layer close to the substrate.

[0033] As an optional solution, the method further includes:

[0034] An interlayer dielectric layer and a source-drain electrode layer are sequentially formed on a side of the first gate layer facing away from the substrate.

[0035] In a third aspect, the present invention provides a display panel, comprising the array substrate of the first aspect or the array substrate prepared according to the method of the second aspect.

[0036] In a fourth aspect, the present invention provides a display device, comprising the display panel of the third aspect.

[0037] The array substrate of the present invention has an oxide thin film transistor disposed on the substrate, the oxide thin film transistor including an oxide channel layer, a first gate insulating layer and a first gate layer, the first gate insulating layer being disposed on the side of the oxide channel layer away from the substrate, the first gate layer being disposed on the side of the first gate insulating layer away from the substrate, and a gap being formed between the first gate layer and the first gate insulating layer, and the positive projection of the gap on the oxide channel layer being located inside the positive projection region of the first gate layer on the oxide channel layer. In this way, the gap cannot be filled by the interlayer dielectric layer on the side of the first gate layer away from the substrate, which is conducive to reliably reducing the average dielectric constant between the first gate layer and the oxide channel layer, thereby reducing the capacitance between the first gate layer and the oxide channel layer, and further facilitating the subthreshold swing of the transfer characteristic curve of the oxide thin film transistor, improving the uniformity of the display panel, so that the display panel has a good display effect, and further improving the yield rate and product competitiveness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0039] Figure 1 It is a structural schematic diagram of a display panel in the prior art;

[0040] Figure 2 A schematic structural diagram of an array substrate according to an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a display panel according to an embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the front structure of an array substrate according to an embodiment of the present application (provided with an oxide conductive layer);

[0043] Figure 5 for Figure 3 AA ′ A schematic diagram of the cross-sectional structure of;

[0044] Figure 6 This is a schematic diagram of the front structure of an array substrate according to an embodiment of the present application (the oxide conductive layer is etched away);

[0045] Figure 7 for Figure 6 AA ′ A schematic diagram of the cross-sectional structure of;

[0046] Figure 8 A schematic diagram of the structure of another display panel according to an embodiment of the present application;

[0047] Fig. 9 This is a schematic diagram of the front structure of another array substrate of an embodiment of the present application (provided with an oxide conductive layer);

[0048] Fig.10 for Fig. 9 AA ′ A schematic diagram of the cross-sectional structure of;

[0049] Fig.11 This is a schematic diagram of the front structure of another array substrate according to an embodiment of the present application (the oxide conductive layer is etched away);

[0050] Fig.12 for Fig.11 AA ′ A schematic diagram of the cross-sectional structure of;

[0051] Fig.13 A schematic diagram of the structure of another display panel according to an embodiment of the present application;

[0052] Fig.14 This is a schematic diagram of the front structure of another array substrate of an embodiment of the present application (provided with an oxide conductive layer);

[0053] Fig.15 for Fig.14 AA ′ A schematic diagram of the cross-sectional structure of;

[0054] Fig.16 This is a schematic diagram of the front structure of another array substrate according to an embodiment of the present application (the oxide conductive layer is etched away);

[0055] Fig.17 for Fig.16 AA ′ Schematic diagram of the cross-sectional structure.

[0056] In the figure,

[0057] 100. Array substrate;

[0058] 10. substrate, 11. barrier layer;

[0059] 20. oxide thin film transistor, 21. oxide channel layer, 22. first gate insulating layer, 23. first gate layer, 24. gap, 25. second gate layer, 26. second gate insulating layer, 27. interlayer dielectric layer, 28. source and drain electrode layer, 29. oxide conductive layer;

[0060] 200. Display panel;

[0061] 30. planarization layer, 40. anode layer, 50. pixel definition layer, 51. light-emitting layer. DETAILED DESCRIPTION

[0062] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0063] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0064] like Figure 1 As shown, the display panel in the related art includes a substrate 10 and a barrier layer 11, a second gate layer 25, a second gate insulating layer 26, an oxide channel layer 21, a first gate insulating layer 22, a first gate layer 23, an interlayer dielectric layer 27, a source and drain layer 28, and a planar layer 30 (PLN) covering the side of the source and drain layer 28 away from the substrate 10, an anode layer 40 (AND) is arranged on the side of the planar layer 30 away from the substrate 10, a pixel definition layer 50 (PDL) is arranged on the side of the anode layer 40 away from the substrate 10, a pixel opening area is arranged on the pixel definition layer 50, a light-emitting layer 51 (EL) is arranged in the pixel opening area, and the light-emitting layer 51 is in contact with the anode layer 40. The subthreshold swing (ss) of the oxide thin film transistor in the display panel is about 0.2, while the subthreshold of the existing low temperature polysilicon thin film transistor (LTPS TFT) is greater than 0.4, which results in poor uniformity of display quality of the OLED display panel.

[0065] Based on the above problems, an embodiment of the present application provides an array substrate 100, such as Figure 2 As shown, it includes: a substrate 10 and an oxide thin film transistor 20 disposed on the substrate 10;

[0066] The oxide thin film transistor 20 includes an oxide channel layer 21, a first gate insulating layer 22 and a first gate layer 23;

[0067] Among them, the first gate insulation layer 22 is arranged on the side of the oxide channel layer 21 away from the substrate 10, the first gate layer 23 is arranged on the side of the first gate insulation layer 22 away from the substrate 10, and a gap 24 is formed between the first gate layer 23 and the first gate insulation layer 22, and the orthographic projection of the gap 24 on the oxide channel layer 21 is located inside the orthographic projection area of ​​the first gate layer 23 on the oxide channel layer 21.

[0068] It is understandable that the substrate 10 may include a flexible material or a rigid material. For example, when the display panel has a foldable or bendable requirement, the substrate 10 may be made of a flexible material, such as but not limited to PET (Polyethyleneterephthalate), PEN (Polyethylenenaphthalatetwoformic acid glycol ester) or PI (Polyimide); when the display panel has a rigid requirement, the substrate 10 may be made of a rigid material, such as but not limited to glass or PMMA (Polymethyl methacrylate).

[0069] The oxide thin film transistor 20 refers to a thin film transistor using a conductive oxide as a channel layer material; the oxide film thin film transistor of the embodiment of the present application may be a top gate structure, for example, the oxide thin film transistor may include an oxide channel layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source electrode and a drain electrode, etc. stacked in sequence. Of course, the oxide thin film transistor may also be a dual gate structure, for example, the oxide thin film transistor may include a bottom gate layer, a bottom gate insulating layer, an oxide channel layer, a top gate insulating layer, a top gate layer, an interlayer dielectric layer, a source electrode and a drain electrode, etc. stacked in sequence.

[0070] It should be noted that the gap 24 is provided between the first gate layer 23 and the first gate insulating layer 22 in the array substrate of the embodiment of the present application, which is only applicable to the top gate portion of the thin film transistor with the top gate structure and the thin film transistor with the double gate structure. The size and shape of the gap 24 between the first gate layer 23 and the first gate insulating layer 22 are not limited. For example, the gap 24 can be rectangular, elliptical, etc., as long as the hollowing process between the first gate layer 23 and the first gate insulating layer 22 can be achieved, so that the insulating dielectric between the first gate layer 23 and the oxide channel layer 21 is reduced, and the average dielectric constant between the first gate layer 23 and the oxide channel layer 21 is reduced, thereby reducing the capacitance between the first gate layer 23 and the oxide channel layer 21. Furthermore, the orthographic projection of the void 24 in the oxide channel layer 21 is located within the orthographic projection area of ​​the first gate layer 23 in the oxide channel layer 21, which means that the orthographic projection of the void 24 in the oxide channel layer 21 coincides with the orthographic projection of the first gate layer 23 in the oxide channel layer 21, that is, along the direction away from the substrate 10, the void 24 is located directly below the first gate layer 23. This is beneficial in that when an interlayer dielectric layer 27 or a gate insulating layer material is formed on the first gate layer 23, the interlayer dielectric layer 27 or the gate insulating layer material will not be filled in the void 24, thereby reliably ensuring that the void 24 is formed between the first gate layer 23 and the first gate insulating layer, thereby reducing the average dielectric constant between the first gate layer 23 and the oxide channel layer 21.

[0071] It can also be understood that the gap 24 can be formed by setting a support layer between the first gate layer 23 and the first gate insulating layer 22, and after the first gate layer 23 is formed, removing the support layer to form the gap 24; the gap 24 can also be formed by graphically setting the first gate insulating layer 22, etching away part of the first gate insulating layer 22 while ensuring that the first gate insulating layer 22 can reliably insulate and isolate the first gate layer 23 and the oxide channel layer 21, and after the gap 24 is formed in the first gate insulating layer 22, the first gate layer 23 is formed on the first gate insulating layer 22, so that the gap 24 is formed between the first gate layer 23 and the first gate insulating layer 22.

[0072] The array substrate of the embodiment of the present application is provided with an oxide thin film transistor 20 on a substrate 10, wherein the oxide thin film transistor 20 includes an oxide channel layer 21, a first gate insulating layer 22 and a first gate layer 23, wherein the first gate insulating layer 22 is provided on a side of the oxide channel layer 21 facing away from the substrate 10, and the first gate layer 23 is provided on a side of the first gate insulating layer 22 facing away from the substrate 10, and a gap 24 is formed between the first gate layer 23 and the first gate insulating layer 22, and the orthographic projection of the gap 24 on the oxide channel layer 21 is located inside the orthographic projection area of ​​the first gate layer 23 on the oxide channel layer 21. In this way, the gap 24 cannot be filled by the interlayer dielectric layer 27 on the side of the first gate layer 23 facing away from the substrate 10, which is conducive to reliably reducing the average dielectric constant between the first gate layer 23 and the oxide channel layer 21, thereby reducing the capacitance of the first gate layer 23 and the oxide channel layer 21, which is conducive to increasing the subthreshold swing of the transfer characteristic curve of the oxide thin film transistor, improving the uniformity of the display panel, and making the display panel have a good display effect, thereby improving the yield rate and product competitiveness of the display panel.

[0073] As an achievable method, Figure 3-17 As shown, an oxide conductive layer 29 is disposed between the first gate layer 23 and the first gate insulating layer 22, and the edge of the oxide conductive layer 29 in the first direction of the orthogonal projection of the oxide channel layer 21 protrudes from the edge of the orthogonal projection of the first gate layer 23 in the first direction of the oxide channel layer 21, and the gap 24 is formed by etching the oxide conductive layer 29; wherein the first direction refers to the radial direction of the oxide channel layer 21 (such as Figure 4 X direction).

[0074] The oxide conductive layer 29 may be, but is not limited to, an oxide such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO); the oxide conductive layer 29 is disposed on the side of the first gate insulating layer 22 away from the substrate 10, and the edge of the orthogonal projection of the oxide conductive layer 29 on the oxide channel layer 21 in the first direction protrudes from the edge of the orthogonal projection of the first gate layer 23 on the oxide channel layer 21 in the first direction. It can be understood that the edge of the oxide conductive layer 29 in the first direction (such as Figure 5 B1 and / or B2 shown in FIG. 2 should protrude from the edge of the first gate layer 23 in the first direction (eg Figure 5B3 and / or B4 shown in the figure), so that it is beneficial to reliably support the first gate layer 23 and at the same time, it can ensure that the oxide conductive layer 29 exceeding the first gate layer 23 is etched away, and by controlling and extending the etching time, the oxide conductive layer 29 located directly below the first gate layer 23 is etched away to form a gap 24 of the Undercut structure; wherein, the gap 24 located below the first gate layer 23 ensures reliable support for the first gate layer 23 to avoid the collapse of the first gate layer 23, and the size of the gap 24 in the first direction should be as large as possible; for example, the size of the gap 24 in the first direction is greater than 0 and less than or equal to 1μm.

[0075] It is also understandable that the oxide conductive layer 29 can be etched by a wet etching process, wherein the etching solution can be, but is not limited to, an IGZO etching solution.

[0076] In this embodiment, the oxide conductive layer 29 is provided to help reliably form the gap 24 , reduce the dielectric constant between the first gate layer 23 and the oxide channel layer 21 , and ensure the structural stability of the first gate layer 23 .

[0077] In some embodiments, Figure 6 and Fig.11 As shown, the gap 24 extends along the second direction (Y direction), the dimension of the gap 24 in the second direction is less than or equal to the dimension of the oxide channel layer 21 in the second direction, and the first direction is perpendicular to the second direction.

[0078] The second direction corresponds to the X direction and the Y direction as shown in the figure respectively with the first direction;

[0079] The gap 24 of this embodiment is convenient for processing, which is beneficial to reducing processing requirements. At the same time, it can reduce the dielectric constant between the first gate layer 23 and the oxide channel layer 21, thereby reducing the capacitance between the first gate layer 23 and the oxide channel layer 21, and further improving the subthreshold of the oxide thin film transistor 20.

[0080] In a preferred embodiment, Figure 7 and 12 As shown, there are two gaps 24 , which are spaced apart in the first direction, and the orthographic projections of the two gaps 24 on the oxide channel layer 21 are respectively located in a region close to the edge of the orthographic projection of the first gate layer 23 on the oxide channel layer 21 .

[0081] Among them, the orthographic projection of the gap 24 on the oxide channel layer 21 is located in the area close to the edge of the orthographic projection of the first gate layer 23 on the oxide channel layer 21, that is, the gap 24 is located on the opposite sides of the first gate layer 23 in the first direction, which is conducive to facilitating the processing of the gap 24 while ensuring the structural stability of the first gate layer 23.

[0082] As an achievable method, Fig.16 and 17 As shown, the gap 24 is along the first direction ( Fig.16 The size of the gap 24 in the first direction is less than or equal to the size of the first gate layer 23 in the first direction.

[0083] The gap 24 extends along the first direction, that is, the gap 24 extends along the radial direction of the channel. In this way, the setting method of the gap 24 is flexible, and the number and size of the gap 24 can be adjusted according to actual needs, thereby ensuring that the dielectric constant between the first gate layer 23 and the oxide channel layer 21 is reduced, and the capacitance between the first gate layer 23 and the oxide channel layer 21 is reduced. At the same time, it can ensure that the first gate layer 23 is reliably formed and the structure is stable and will not collapse.

[0084] The number of gaps 24 may be one, two, or more than two, depending on the processing technology and actual product requirements.

[0085] In actual processing, the size of the gap 24 in the first direction is equal to the size of the first gate layer 23 in the first direction, which is beneficial to minimize the dielectric constant between the first gate layer 23 and the oxide channel layer 21, reduce the capacitance between the first gate layer 23 and the oxide channel layer 21, and thus improve the subthreshold of the oxide thin film transistor 20.

[0086] In a preferred embodiment, Fig.17 As shown, the gaps 24 include at least two gaps 24, and the at least two gaps 24 are arranged at intervals along the second direction.

[0087] In this embodiment, at least two gaps 24 are arranged at intervals, which is conducive to reliably reducing the dielectric constant between the first gate layer 23 and the oxide channel layer 21, and is also conducive to ensuring that the structure of the first gate layer 23 is stable and will not collapse.

[0088] In some embodiments, the size of the gap 24 in the second direction is greater than 0 and less than or equal to 1 μm.

[0089] In this embodiment, the gap 24 is in the second direction (eg Fig.16 The size of the product (in the X direction) is convenient for processing and has low requirements on processing technology.

[0090] As an achievable method, Figure 2 As shown, the oxide thin film transistor 20 further includes a second gate layer 25 and a second gate insulating layer 26. The second gate layer 25 is disposed on the substrate 10. The second gate insulating layer 26 is disposed on a side of the second gate layer 25 facing away from the substrate 10. The second gate layer 25 is located on a side of the oxide channel layer 21 close to the substrate 10.

[0091] In this embodiment, the second gate layer 25 and the first gate layer 23 constitute a dual-gate oxide thin film transistor 20, wherein the first gate layer 23 is a top gate and the second gate layer 25 is a bottom gate. Compared with the ordinary oxide thin film transistor 20, the control ability of the gate over the channel current in the dual-gate oxide thin film transistor 20 is enhanced, which can effectively increase the carrier concentration in the channel, thereby increasing the current density.

[0092] As an achievable method, Figure 2 As shown, the oxide thin film transistor 20 further includes an interlayer dielectric layer 27 and a source-drain electrode layer 28 . The interlayer dielectric layer 27 covers the side of the first gate layer 23 facing away from the substrate 10 , and the source-drain electrode layer 28 is arranged on the side of the interlayer dielectric layer 27 facing away from the substrate 10 .

[0093] The interlayer dielectric layer 27 is used to isolate and insulate the first gate layer 23 and the source-drain layer 28 . The interlayer dielectric layer 27 may be, but is not limited to, silicon nitride, silicon oxynitride, or the like.

[0094] It can be understood that since a gap 24 is formed between the first gate layer 23 and the first gate insulating layer 22, and the gap 24 is located directly below the first gate layer 23 along the direction away from the substrate 10, when the material of the interlayer dielectric layer 27 is formed on the first gate layer 23, the material of the interlayer dielectric layer 27 will not be filled in the gap 24, thereby reliably ensuring that the gap 24 is formed between the first gate layer 23 and the first gate insulating layer, reducing the average dielectric constant between the first gate layer 23 and the oxide channel layer 21, and thereby achieving improvement in the subthreshold of the oxide thin film transistor 20.

[0095] In this embodiment, the interlayer dielectric layer 27 is conducive to insulating and isolating the first gate layer 23 and the source and drain layer 28. The source and drain layer 28 is used for current transmission in the thin film transistor. When a certain voltage is applied to the first gate layer 23, a conductive channel is formed in the channel, allowing conduction between the source and the drain.

[0096] In summary, in the array substrate of the embodiment of the present application, the first gate insulating layer 22 is arranged on the side of the oxide channel layer 21 away from the substrate 10, and the first gate layer 23 is arranged on the side of the first gate insulating layer 22 away from the substrate 10, and a gap 24 is formed between the first gate layer 23 and the first gate insulating layer 22, and the orthographic projection of the gap 24 on the oxide channel layer 21 is located inside the orthographic projection area of ​​the first gate layer 23 on the oxide channel layer 21. In this way, the gap 24 cannot be filled by the interlayer dielectric layer 27 on the side of the first gate layer 23 away from the substrate 10, which is conducive to reliably reducing the average dielectric constant between the first gate layer 23 and the oxide channel layer 21, thereby reducing the capacitance between the first gate layer 23 and the oxide channel layer 21, and further facilitating the subthreshold swing of the transfer characteristic curve of the oxide thin film transistor, improving the uniformity of the display panel, so that the display panel has a good display effect, and further improving the yield rate and product competitiveness of the display panel;

[0097] Furthermore, by disposing an oxide conductive layer 29 between the first gate layer 23 and the first gate insulating layer 22 and etching the oxide conductive layer 29 to form the gap 24, the processing method is simple and easy to implement, and the first gate layer 23 is conveniently formed to ensure the stability of the structure of the first gate layer 23.

[0098] In a second aspect, the present invention provides a method for preparing an array substrate, comprising the following steps:

[0099] Step S10, providing a substrate 10;

[0100] Step S20, forming an oxide channel layer 21 and a first gate insulating layer 22 in sequence on the substrate 10;

[0101] The oxide channel layer 21 may be, but is not limited to, IGZO; the first gate insulating layer 22 may be, but is not limited to, inorganic materials such as silicon dioxide and silicon nitride or organic materials with a relatively low dielectric constant such as polyimide.

[0102] The oxide channel layer 21 and the first gate insulating layer 22 may be formed by conventional chemical vapor deposition or the like, which is not limited in the embodiments of the present application.

[0103] Step S30, forming an oxide conductive layer 29 and a first gate layer 23 in sequence on a side of the first gate insulating layer 22 facing away from the substrate 10, and an edge of the oxide conductive layer 29 on the orthogonal projection of the oxide channel layer 21 in the first direction protrudes beyond an edge of the orthogonal projection of the first gate layer 23 on the oxide channel layer 21 in the first direction;

[0104] The oxide conductive layer 29 may be, but is not limited to, an oxide such as ITO, and may be formed by chemical deposition or sputtering. For example, the thickness of the oxide conductive layer 29 may be less than 100 μm. The first gate layer 23 may be, but is not limited to, a single-layer metal structure or a stacked metal structure;

[0105] The edge of the orthogonal projection of the oxide conductive layer 29 on the oxide channel layer 21 in the first direction protrudes beyond the edge of the orthogonal projection of the first gate layer 23 on the oxide channel layer 21 in the first direction. Figure 5 B1 and / or B2 in the figure) protrude from the edge of the first gate layer 23 in the first direction (eg Figure 5 B3 and / or B4), so that it is convenient to etch the oxide conductive layer 29.

[0106] Step S40 , etching the oxide conductive layer 29 to form a gap 24 between the first gate layer 23 and the first gate insulating layer 22 , and the orthographic projection of the gap 24 on the oxide channel layer 21 is located inside the orthographic projection region of the first gate layer 23 on the oxide channel layer 21 .

[0107] The oxide conductive layer 29 may be etched using a wet etching process. In actual processing, an IGZO etching solution may be used for etching, and the size of the gap 24 may be controlled by controlling the etching time, which is beneficial to ensure that the structure of the first gate layer 23 is stable and does not collapse while reducing the dielectric constant between the first gate layer 23 and the oxide channel layer 21.

[0108] As an achievable manner, in step S30, an oxide conductive layer 29 and a first gate layer 23 are sequentially formed on a side of the first gate insulating layer facing away from the substrate 10, such as Figure 3-7 As shown, including:

[0109] Forming an oxide conductive layer 29 on a side of the first gate insulating layer facing away from the substrate 10;

[0110] The first gate layer 23 is stacked on the oxide conductive layer 29 , and the edge of the first gate layer 23 in the first direction is retracted or flush with the edge of the oxide conductive layer 29 in the first direction.

[0111] Among them, the first gate layer 23 is stacked and arranged on the side of the oxide conductive layer 29 away from the substrate 10. In this way, the first gate layer 23 uses the oxide conductive layer 29 as the substrate 10, which is convenient for forming the first gate layer 23, and the oxide conductive layer 29 can reliably support the first gate layer 23; the edge of the first gate layer 23 in the first direction is indented or flush with the edge of the oxide conductive layer 29 in the first direction, so that the oxide conductive layer 29 protrudes from the edge of the first gate layer 23, exposing the oxide conductive layer 29, which is convenient for etching the oxide conductive layer 29.

[0112] Furthermore, in the actual processing, in step S40, the oxide conductive layer 29 is etched to form a gap 24 between the first gate layer 23 and the first gate insulating layer 22. Figure 7 As shown, including:

[0113] A portion of the oxide conductive layer 29 is etched so that the remaining oxide conductive layer 29 supports the first gate layer 23 , and the gaps 24 are located at both sides of the remaining oxide conductive layer 29 in the first direction.

[0114] Specifically, the edge of the first gate layer 23 protruding from the oxide conductive layer 29 is etched inward, and the etching time is controlled so that a portion of the oxide conductive layer 29 directly below the first gate layer 23 is etched away, and a gap 24 of an Undercut structure is formed below the first gate layer 23 to reduce the average dielectric constant between the first gate layer 23 and the oxide channel layer 21, thereby reducing the capacitance.

[0115] As an achievable manner, in step S30, an oxide conductive layer 29 and a first gate layer 23 are sequentially formed on a side of the first gate insulating layer facing away from the substrate 10, such as Figure 8-11 As shown, including:

[0116] An oxide conductive layer 29 is formed on a side of the first gate insulating layer 22 facing away from the substrate 10, the oxide conductive layer 29 includes a first region and a second region spaced apart along a first direction, the first region and the second region extend along a second direction respectively, and the size of each of the first region and the second region in the second direction is less than or equal to the size of the oxide channel layer 21 in the second direction, and the first direction is perpendicular to the second direction;

[0117] The first gate layer 23 is formed to stack the first region and the second region and fill the gap between the first region and the second region. In the first direction, the edge of the first gate layer 23 is retracted or flush with the edge of the first region and the edge of the second region.

[0118] In the present embodiment, the oxide conductive layer 29 includes a first region and a second region which are spaced apart from each other, so that a portion of the first gate layer 23 is directly formed on the first gate insulating layer 22, and the first gate insulating layer 22 can reliably support the first gate insulating layer 22; and the first gate layer 23 is stacked on the first region and the second region at the same time, which is beneficial to reducing the etching process requirements, and the first region and the second region can be etched to reliably form the gap 24 without causing the first gate layer 23 to collapse.

[0119] It can be understood that the size of the first gate layer 23 stacked in the first area and the second area in the first direction is smaller than the size of the first gate layer 23 located in the gap between the first area and the second area in the first direction. This is conducive to ensuring that the first gate layer 23 has good structural stability.

[0120] As an achievable manner, in step S30, an oxide conductive layer 29 and a first gate layer 23 are sequentially formed on a side of the first gate insulating layer facing away from the substrate 10, such as Figure 13-17 As shown, including:

[0121] An oxide conductive layer 29 is formed on a side of the first gate insulating layer 22 facing away from the substrate 10, wherein the oxide conductive layer 29 includes at least one sub-region spaced apart in the second direction, and the sub-region extends along the first direction;

[0122] It can be understood that the number of sub-regions can be one, two or more than two, the number of sub-regions corresponds to the number of gaps 24, and the sub-regions extend along the first direction, which is conducive to increasing the size of the gaps 24 in the first direction.

[0123] The first gate layer 23 is formed to cover the oxide conductive layer 29 and the gap between two adjacent sub-regions in the second direction, and the edge of the first gate layer 23 in the first direction is retracted or flush with the edge of each sub-region.

[0124] It can be understood that controlling the etching time can facilitate the size of the gap 24 formed in the first direction to be smaller than or equal to the size of the first gate layer 23 in the first direction.

[0125] The configuration of the oxide conductive layer 29 in this embodiment is flexible and is conducive to forming the gap 24 between the first gate layer 23 and the first gate insulating layer 22 to the greatest extent, thereby minimizing the dielectric constant between the first gate layer 23 and the oxide channel layer 21 .

[0126] In some embodiments, before step 20, sequentially forming an oxide channel layer 21 and a first gate insulating layer 22 on the substrate 10, the preparation method further includes:

[0127] A second gate layer 25 and a second gate insulating layer 26 are sequentially formed on the substrate 10 . The second gate layer 25 is located on a side of the oxide channel layer 21 close to the substrate 10 .

[0128] In some embodiments, the method further comprises:

[0129] An interlayer dielectric layer 27 and a source-drain electrode layer 28 are sequentially formed on a side of the first gate layer 23 facing away from the substrate 10 .

[0130] In summary, the preparation method of the array substrate of the present application, by setting the oxide conductive layer 29 and changing the setting position of the oxide conductive layer 29, can flexibly adjust the position and size of the gap 24, thereby facilitating the reliable formation of the gap 24, reducing the dielectric constant between the first gate layer 23 and the oxide channel layer 21, improving the subthreshold of the oxide thin film transistor 20, and ensuring the structural stability of the first gate layer 23.

[0131] In a third aspect, an embodiment of the present application provides a display panel 200, comprising the array substrate 100 of the first aspect or the array substrate 100 prepared according to the method of the second aspect. It is understandable that the display panel has all the features and advantages of the above array substrate or the method for preparing the array substrate, which will not be described in detail here. In short, the display panel has a good display effect, a high yield rate and product competitiveness.

[0132] For example, Figure 2 , 8 As shown in 13 , the display panel 200 includes the above-mentioned array substrate 100, and a flat layer 30 covering the source and drain layer 28 of the array substrate on the side facing away from the substrate 10, an anode layer 40 is arranged on the side of the flat layer 30 facing away from the substrate 10, a pixel definition layer 50 is arranged on the side of the anode facing away from the substrate 10, a pixel opening area is arranged on the pixel definition layer 50, and a light-emitting layer 51 is arranged in the pixel opening area.

[0133] In a fourth aspect, the present invention provides a display device, comprising the display panel of the third aspect. It is understandable that the display device has all the features and advantages of the above display panel, which will not be elaborated here. In short, the display device has high quality and yield rate and good display effect.

[0134] The display device is a product with an image display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query equipment of e-government, banks, hospitals, power and other departments), a monitor, etc. The display device may also be a microdisplay or a product containing a microdisplay. The product containing a microdisplay may be a smart watch, a smart bracelet, a helmet display, a stereo display mirror, and any of AR devices (such as AR glasses), VR devices (such as VR glasses), etc. For example, a microdisplay may be a display with a display size ranging from about 0.2 inches to about 2.5 inches, but is not limited thereto. It can be understood that the microdisplay may also be a display with a smaller display size, such as a display size less than or equal to 0.2 inches.

[0135] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the panel or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0136] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. An array substrate, characterized in that: include: A substrate and an oxide thin film transistor disposed on the substrate; The oxide thin film transistor comprises an oxide channel layer, a first gate insulating layer and a first gate layer; Among them, the first gate insulation layer is arranged on the side of the oxide channel layer away from the substrate, the first gate layer is arranged on the side of the first gate insulation layer away from the substrate, and a gap is formed between the first gate layer and the first gate insulation layer, and the orthographic projection of the gap on the oxide channel layer is located inside the orthographic projection area of ​​the first gate layer on the oxide channel layer.

2. The array substrate according to claim 1, characterized in that: An oxide conductive layer is arranged between the first gate layer and the first gate insulating layer, and the edge of the oxide conductive layer at the orthogonal projection of the oxide channel layer in the first direction protrudes beyond the edge of the orthogonal projection of the first gate layer at the oxide channel layer in the first direction, and the gap is formed by etching the oxide conductive layer; wherein the first direction refers to the radial direction of the oxide channel layer.

3. The array substrate according to claim 2, characterized in that: The gap extends along a second direction, a size of the gap in the second direction is smaller than or equal to a size of the oxide channel layer in the second direction, and the first direction is perpendicular to the second direction.

4. The array substrate according to claim 3, characterized in that: There are two gaps, the two gaps are spaced apart in the first direction, and the orthogonal projections of the two gaps on the oxide channel layer are respectively located in a region where the orthogonal projection of the first gate layer on the oxide channel layer is close to an edge.

5. The array substrate according to claim 2, characterized in that: The gap extends along the first direction, and a size of the gap in the first direction is less than or equal to a size of the first gate layer in the first direction.

6. The array substrate according to claim 5, characterized in that: The gaps include at least two, and at least two of the gaps are arranged at intervals along the second direction.

7. The array substrate according to any one of claims 2 to 6, characterized in that: The size of the gap in the second direction is greater than 0 and less than or equal to 1 μm.

8. The array substrate according to any one of claims 2 to 6, characterized in that: The oxide thin film transistor also includes a second gate layer and a second gate insulating layer. The second gate layer is arranged on the substrate. The second gate insulating layer is arranged on a side of the second gate layer away from the substrate. The second gate layer is located on a side of the oxide channel layer close to the substrate.

9. The array substrate according to any one of claims 2 to 6, characterized in that: The oxide thin film transistor further comprises an interlayer dielectric layer and a source-drain electrode layer. The interlayer dielectric layer covers a side of the first gate layer away from the substrate, and the source-drain electrode layer is arranged on a side of the interlayer dielectric layer away from the substrate.

10. A method for preparing an array substrate, characterized in that: The steps include: providing a substrate; forming an oxide channel layer and a first gate insulating layer in sequence on the substrate; An oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, and an edge of the oxide conductive layer at an orthogonal projection of the oxide channel layer in the first direction protrudes from an edge of the orthogonal projection of the first gate layer at the oxide channel layer in the first direction; The oxide conductive layer is etched to form a gap between the first gate layer and the first gate insulating layer, and an orthogonal projection of the gap on the oxide channel layer is located inside an orthogonal projection region of the first gate layer on the oxide channel layer.

11. The preparation method according to claim 10, characterized in that: An oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising: forming the oxide conductive layer on a side of the first gate insulating layer facing away from the substrate; The first gate layer is stacked on the oxide conductive layer, and an edge of the first gate layer in the first direction is retracted or flush with an edge of the oxide conductive layer in the first direction.

12. The preparation method according to claim 11, characterized in that: Etching the oxide conductive layer to form a gap between the first gate layer and the first gate insulating layer, comprising: A portion of the oxide conductive layer is etched so that the remaining oxide conductive layer supports the first gate layer, and the gap is located at two sides of the remaining oxide conductive layer in the first direction.

13. The preparation method according to claim 10, characterized in that: An oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising: forming the oxide conductive layer on a side of the first gate insulating layer away from the substrate, the oxide conductive layer comprising a first region and a second region spaced apart along the first direction, the first region and the second region respectively extending along the second direction, and the size of each of the first region and the second region in the second direction is less than or equal to the size of the oxide channel layer in the second direction, and the first direction is perpendicular to the second direction; The first gate layer is formed so that the first gate layer is stacked on the first region and the second region and fills a gap between the first region and the second region, and in the first direction, an edge of the first gate layer is retracted or flush with an edge of the first region and an edge of the second region.

14. The preparation method according to claim 10, characterized in that: An oxide conductive layer and a first gate layer are sequentially formed on a side of the first gate insulating layer facing away from the substrate, comprising: forming the oxide conductive layer on a side of the first gate insulating layer away from the substrate, the oxide conductive layer comprising at least one sub-region spaced apart in the second direction, the sub-region extending along the first direction; The first gate layer is formed so that the first gate layer covers the oxide conductive layer and the gap between two adjacent sub-regions in the second direction, and the edge of the first gate layer in the first direction is retracted or flush with the edge of each sub-region.

15. The preparation method according to any one of claims 10 to 14, characterized in that: Before sequentially forming an oxide channel layer and a first gate insulating layer on the substrate, the method further includes: A second gate layer and a second gate insulating layer are sequentially formed on the substrate, wherein the second gate layer is located on a side of the oxide channel layer close to the substrate.

16. The preparation method according to any one of claims 10 to 14, characterized in that: Also includes: An interlayer dielectric layer and a source-drain layer are sequentially formed on a side of the first gate layer facing away from the substrate.

17. A display panel, characterized in that The invention comprises the array substrate according to any one of claims 1 to 9 or an array substrate prepared by the method according to any one of claims 10 to 16.

18. A display device, characterized in that Comprising the display panel as claimed in claim 17.

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