Silicon heterojunction solar cell structure and preparation method thereof

Abstract

The invention provides a silicon heterojunction solar cell structure and a preparation method thereof, and the structure comprises a substrate, a first doped layer formed on the first surface of the substrate, a second doped layer formed on the second surface of the substrate, a buffer layer formed on the first doped layer and / or the second doped layer, and a transparent conductive layer formed on the first doped layer and the second doped layer. The transparent conductive layer covers the buffer layer. According to the invention, the buffer layer is formed between the first doping layer and the transparent conductive layer and / or between the second doping layer and the transparent conductive layer, and the buffer layer is used for reducing or avoiding the physical damage of the transparent conductive layer to the surface of the first doping layer and / or the second doping layer in the sputtering film forming process. The surface defect density of the first doped layer and / or the second doped layer is reduced, and the cell conversion efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar photovoltaic cells, and in particular to a silicon heterojunction solar cell structure and a preparation method thereof. Background Art

[0002] Silicon heterojunction (HJT) solar cells are a high-efficiency solar cell technology that combines crystalline silicon and thin-film technology. The solar cell is based on crystalline silicon, and after cleaning and texturing, an intrinsic amorphous silicon layer and an N-type amorphous silicon layer are deposited on the front of the crystalline silicon, an intrinsic amorphous silicon layer and a P-type amorphous silicon layer are deposited on the back, and a transparent conductive oxide (Transparent Conductive Oxide: TCO) is deposited on the front and back at the same time. Finally, metal electrodes are prepared on the front and back to obtain silicon heterojunction solar cells. Silicon heterojunction solar cells are considered to be the preferred technology for the next generation of mass-produced ultra-high-efficiency solar cells due to their excellent conversion efficiency, double-sided power generation rate, low temperature coefficient, high cell open circuit voltage and many other advantages.

[0003] In silicon heterojunction solar cells, the surface of the silicon wafer is a pyramid velvet structure produced by velveting. The TCO material usually forms a good ohmic contact with the interface of amorphous silicon, which can reduce the contact resistance between the TCO material and amorphous silicon. However, the prior art grows TCO materials on the surface of doped amorphous silicon by sputtering, which will damage the doped amorphous silicon film and reduce the current density of the silicon junction solar cell. Therefore, how to provide a silicon heterojunction solar cell structure and its preparation method, which can reduce the surface defect rate between the doped amorphous silicon layer and the TCO material and improve the cell conversion efficiency, has become one of the technical problems that people in this field need to solve urgently. Summary of the invention

[0004] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0005] To this end, the first objective of the present application is to propose a silicon heterojunction solar cell structure and a preparation method thereof, which can reduce the surface defect rate between the doped amorphous silicon layer and the TCO material and improve the cell conversion efficiency.

[0006] To achieve the above-mentioned purpose, the first embodiment of the present application proposes a method for preparing a silicon heterojunction solar cell structure, comprising the following steps:

[0007] providing a substrate, the substrate comprising a first surface and a second surface opposite to each other;

[0008] forming an intrinsic amorphous silicon layer on the first surface and the second surface;

[0009] forming a second doping layer and a first doping layer in sequence on the intrinsic amorphous silicon layer on the second surface and the first surface;

[0010] forming a buffer layer with a preset thickness on the first doping layer and / or the second doping layer;

[0011] forming a transparent conductive layer on the first doping layer and the second doping layer in sequence, wherein the transparent conductive layer covers the buffer layer;

[0012] A gate line electrode is formed on the transparent conductive layer.

[0013] Optionally, a preset thickness range of the buffer layer on the first doping layer and / or the second doping layer is between 2 nm and 10 nm.

[0014] Optionally, the buffer layer includes a first buffer layer, which includes one or more layers of P-type doped silicon film formed on the first doping layer using a plasma enhanced chemical vapor deposition process, including one or more combinations of silicon nitride film, silicon oxide film, and silicon carbide film.

[0015] Optionally, the buffer layer includes a second buffer layer, which includes one or more layers of N-type doped silicon film formed on the second doping layer using a plasma enhanced chemical vapor deposition process, including one or more combinations of silicon nitride film, silicon oxide film, and silicon carbide film.

[0016] Optionally, the buffer layer includes a metal nitride or metal oxide or metal oxynitride film formed on the first doping layer and / or the second doping layer using an atomic layer deposition process or a physical vapor deposition process, including a titanium nitride film, a titanium oxide film or a titanium oxynitride film.

[0017] Optionally, the first doped layer includes a P-type doped silicon film, the second doped layer includes an N-type doped silicon film, and the silicon film includes one or a combination of amorphous silicon film, nanocrystalline silicon film, nanocrystalline silicon oxygen film, microcrystalline silicon film, and microcrystalline silicon oxygen film.

[0018] Optionally, the substrate is N-type or P-type single crystal silicon, and before the step of forming an intrinsic amorphous silicon layer on the first surface and the second surface, the first surface and / or the second surface is cleaned and textured to form a textured structure.

[0019] Optionally, the transparent conductive layer is prepared by a DC magnetron sputtering method, and the material of the transparent conductive layer includes one or a combination of indium oxide, zinc oxide, cadmium oxide, and tin oxide.

[0020] To achieve the above-mentioned purpose, a second aspect of the present application provides a silicon heterojunction solar cell structure, wherein the silicon heterojunction solar cell structure is prepared by any one of the above-mentioned methods for preparing a silicon heterojunction solar cell structure.

[0021] Optionally, the thickness of the substrate ranges from 80nm to 180nm, the thickness of the intrinsic amorphous silicon layer ranges from 3nm to 10nm, the thickness of the first doped layer and the second doped layer ranges from 5nm to 15nm, and the thickness of the transparent conductive layer ranges from 50nm to 120nm.

[0022] The silicon heterojunction solar cell structure and the preparation method thereof provided by the present application have at least the following beneficial effects:

[0023] The present application provides a silicon heterojunction solar cell structure and a preparation method thereof, comprising a substrate, a first doped layer formed on a first surface of the substrate and a second doped layer formed on a second surface, a buffer layer formed on the first doped layer and / or the second doped layer, and a transparent conductive layer formed on the first doped layer and the second doped layer, wherein the transparent conductive layer covers the buffer layer. The present application forms a buffer layer between the first doped layer and the transparent conductive layer and / or between the second doped layer and the transparent conductive layer to reduce or avoid physical damage to the surface of the first doped layer and / or the second doped layer caused by sputtering of the transparent conductive layer during the film formation process, reduce the surface defect density of the first doped layer and / or the second doped layer, and improve the cell conversion efficiency.

[0024] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0026] Figure 1 It is a schematic diagram of the cross-sectional structure of a silicon heterojunction solar cell structure according to an embodiment of the present application.

[0027] Figure 2 The present invention is a schematic diagram of a process for preparing a silicon heterojunction solar cell structure according to an embodiment of the present application.

[0028] 101 substrate; first surface 1011; second surface 1012; 102 intrinsic amorphous silicon layer; 103 first doped layer; 104 second doped layer; 105 first buffer layer; 106 second buffer layer; 107 transparent conductive layer; 108 gate line electrode. DETAILED DESCRIPTION

[0029] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0030] According to one aspect of the present application, a silicon heterojunction solar cell structure is provided, such as Figure 1 As shown, the battery structure includes a substrate 100, an intrinsic amorphous silicon layer 102 formed on the surface of the substrate 100, a first doping layer 103 and a second doping layer 104 formed on the intrinsic amorphous silicon layer 102, a buffer layer formed on the first doping layer 103 and / or the second doping layer 104, a transparent conductive layer 107 (Transparent Conductive Oxide, TCO) formed on the first doping layer 103 and the second doping layer 104 and covering the buffer layer, and a gate line electrode 108 formed on the transparent conductive layer 107.

[0031] In some embodiments, the substrate 100 may be single crystal silicon with a thickness ranging from 80 nm to 180 nm, and may specifically be N-type doped single crystal silicon or P-type doped single crystal silicon.

[0032] The substrate 100 preferably uses N-type doped single crystal silicon material. The performance difference between P-type doped and N-type doped single crystal silicon is mainly due to the fact that metal impurities such as Fe, Cu, Ni, etc. are generally positively charged and have a stronger ability to capture electrons. P-type doping mainly incorporates boron or gallium, and the minority carriers are electrons, while N-type doping mainly incorporates phosphorus, and the minority carriers are holes. Therefore, the anti-pollution property of P-type doped single crystal silicon is weaker than that of N-type doped single crystal silicon. Under the same impurity metal condition, the minority carrier lifetime of N-type doped single crystal silicon is significantly higher than that of P-type doped single crystal silicon (the minority carrier lifetime of N-type doped single crystal silicon with the same resistivity is 1-2 orders of magnitude higher than that of P-type doped single crystal silicon); the higher the minority carrier lifetime of the material, the higher the photoelectric conversion efficiency, so that N-type doped single crystal silicon has a higher conversion efficiency.

[0033] In addition, since the boron element in the single crystal silicon will form a boron-oxygen complex with no saturated chemical bonds with oxygen under light or current injection, the complex will capture the carriers generated by light, reduce the minority carrier lifetime, and cause light-induced decay (LID) phenomenon. Therefore, the main idea of ​​reducing the light decay effect of P-type doped single crystal silicon is to reduce the internal boron or oxygen content, but this method will increase the cost of silicon wafers or lead to a decrease in the conversion efficiency of heterojunction cells. The boron content of N-type doped single crystal silicon is extremely low, which can effectively reduce the occurrence of light decay effect, and also makes N-type doped single crystal silicon the preferred material for substrate 100.

[0034] The substrate 100 includes a first surface 1011 and a second surface 1012 opposite to each other, that is, an upper surface and a lower surface opposite to each other in the thickness direction. By providing a pyramid or inverted pyramid-shaped velvet structure on the first surface 1011 and the second surface 1012 of the substrate 100, the reflection of light on the surface of the substrate 100 can be greatly reduced, and the light trapping effect can be enhanced. The size of the pyramid or inverted pyramid on the first surface 1011 and the second surface 1012 is between 1 μm and 2 μm.

[0035] Furthermore, since there are a large number of dangling bonds on the substrate 100 after texturing, these dangling bonds will form recombination centers and seriously reduce the minority carrier lifetime and open circuit voltage of the battery. Therefore, a passivation film composed of a layer of silicon nitride material can be formed on the first surface 1011 and the surface of the human body respectively. The silicon nitride material can form a stable bonding structure with the dangling bonds on the surface of the substrate 100, thereby reducing the density of the dangling bonds on the surface of the substrate 100 and improving the open circuit voltage of the battery.

[0036] In some embodiments, the intrinsic amorphous silicon layer 102 is formed on the first surface 1011 and the second surface 1012 of the substrate 100 , respectively, and the thickness of the first surface 1011 and the second surface 1012 ranges from 3 nm to 10 nm.

[0037] The intrinsic amorphous silicon layer 102 is formed on the first surface 1011 and the second surface 1012 respectively, so that the intrinsic amorphous silicon layer 102 can directly contact the first surface 1011 and the second surface 1012 to play the role of a passivation film, and the first doped layer 103 and the first surface 1011, and the second doped layer 104 and the second surface 1012 formed subsequently are spaced apart, and the first doped layer 103 and the second doped layer 104 are passivated to contact the intrinsic amorphous silicon layer 102. The surface defects are passivated, thereby greatly avoiding the recombination of carriers, achieving a higher minority carrier lifetime and open circuit voltage, and improving the battery performance. As an example, the material of the intrinsic amorphous silicon layer 102 is preferably hydrogenated amorphous silicon.

[0038] In some embodiments, the first doping layer 103 and the second doping layer 104 are formed on the intrinsic amorphous silicon layer 102, and the thickness range is between 5nm and 20nm. The first doping layer 103 is formed on the intrinsic amorphous silicon layer 102 close to the first surface 1011, and the second doping layer 104 is formed on the intrinsic amorphous silicon layer 102 close to the second surface 1012.

[0039] The first doped layer 103 includes a P-doped silicon film, which can form a PN junction with the N-type doped single crystal silicon substrate 100, and the second doped layer 104 includes an N-type doped silicon film, which can form a high-low junction (N+ / N) structure with the N-type doped single crystal silicon substrate 100. The silicon film includes but is not limited to one or more combinations of amorphous silicon film, nanocrystalline silicon film, nanocrystalline silicon oxygen film, microcrystalline silicon film, and microcrystalline silicon oxygen film. As an example, the silicon film preferably uses a hydrogenated amorphous silicon film, which is consistent with the constituent material of the intrinsic amorphous silicon layer 102. By setting the main constituent materials of the intrinsic amorphous silicon layer 102, the first doped layer 103, and the second doped layer 104 to hydrogenated amorphous silicon materials with a passivation effect, the effectiveness of the battery passivation can be guaranteed, thereby effectively improving the conversion efficiency of the battery.

[0040] Furthermore, in order to reduce the carrier transmission loss caused by defects in the p-type doped amorphous silicon film and the contact loss with the subsequent transparent conductive layer 107 film, the microstructure of the p-type amorphous silicon film can be adjusted towards crystallization to increase the activation rate of the p-type doping element, so that the amorphous silicon film has high electrical conductivity and improves the contact characteristics with the transparent conductive layer 107 film, thereby achieving the purpose of improving the fill factor and conversion efficiency.

[0041] In some embodiments, the buffer layer is formed on the first doping layer 103 and / or the second doping layer 104, and the thickness of the buffer layer on the first doping layer 103 and / or the second doping layer 104 is in the range of 2 nm to 10 nm. By forming the buffer layer on the first doping layer 103 and / or the second doping layer 104, physical damage to the first doping layer 103 and / or the second doping layer 104 caused by the subsequent transparent conductive layer 107 during the magnetron sputtering film formation process can be avoided to a certain extent, the surface defect density of the first doping layer 103 and / or the second doping layer 104 is reduced, and the battery conversion efficiency is improved.

[0042] The buffer layer may include a first buffer layer 105 , which may be one or more layers of P-type doped silicon films formed on the first doping layer 103 , including but not limited to one or more combinations of silicon nitride films, silicon oxide films, and silicon carbide films.

[0043] The buffer layer may also include a second buffer layer 106 , which includes one or more layers of N-type doped silicon films formed on the second doping layer 104 , including but not limited to one or more combinations of silicon nitride films, silicon oxide films, and silicon carbide films.

[0044] Since silicon films such as silicon nitride films, silicon oxide films, and silicon carbide films all have a wide optical band gap, the buffer layer not only has the advantages of high electron mobility, small dielectric constant, and strong radiation resistance, but can also be combined with the amorphous silicon film that constitutes the first doping layer 103 and / or the second doping layer 104 to obtain the performance advantage of high light transmittance, making silicon films such as silicon nitride films, silicon oxide films, and silicon carbide films suitable as preferred materials for battery window layers.

[0045] In addition, the thin film stack structure composed of the buffer layer and the amorphous silicon thin film constituting the intrinsic amorphous silicon layer 102, the first doped layer 103, and the second doped layer 104 also has excellent passivation performance, which can improve the open circuit voltage of the battery; at the same time, the stack structure also ensures good carrier transmission characteristics, which is beneficial to improving the battery conversion efficiency.

[0046] It should be noted that the buffer layer may be formed on the first doping layer 103 alone, or on the second doping layer 104 alone, or on both the first doping layer 103 and the second doping layer 104 at the same time, which is not specifically limited in the present application.

[0047] In another embodiment, the buffer layer may also be a metal nitride, metal oxide or metal oxynitride film formed on the second doping layer 104, including but not limited to one or a combination of titanium nitride film, titanium oxide film or titanium oxynitride film.

[0048] Since the titanium nitride film, titanium oxide film or titanium oxynitride film is a wide optical bandgap N-type material with high conductivity and transmittance, it can form a good ohmic contact with the first doping layer 103 and / or the second doping layer 104, reducing the problems of strong parasitic absorption and low efficiency of photogenerated carrier collection caused by the narrower amorphous silicon material due to structural disorder, and at the same time, it also improves the contact characteristics between amorphous silicon and the transparent conductive layer 107 to a certain extent, ensuring the effective transport of carriers, thereby achieving the purpose of improving the fill factor and conversion efficiency.

[0049] In some embodiments, the transparent conductive layer 107 is formed on the first doping layer 103 and the second doping layer 104, respectively, with a thickness ranging from 50nm to 120nm. The material of the transparent conductive layer 107 includes, but is not limited to, one or a combination of materials with high transparency and conductivity such as indium oxide, zinc oxide, cadmium oxide, and tin oxide.

[0050] Since the thin film stack structure composed of amorphous silicon thin films such as the intrinsic amorphous silicon layer 102, the first doped layer 103 or the second doped layer 104, and the buffer layer has poor conductivity, it is necessary to deposit a transparent conductive layer 107 on the surface of the stack structure to conduct electricity, so as to collect the current generated by the battery and transmit it to the external circuit.

[0051] During the deposition process of the transparent conductive layer 107, especially during the process of growing the transparent conductive layer 107 material by sputtering, high-energy particles may damage the photoelectric performance of the doped amorphous silicon film (the first doped layer and / or the second doped layer 104) with a thickness of only a few nanometers. By forming a buffer layer film on one side on the first doped layer 103 and / or the second doped layer 104 before the step of depositing the transparent conductive layer 107, and covering the buffer layer when the transparent conductive layer 107 is formed, the buffer layer can improve the contact characteristics between the first doped layer 103 and / or the second doped layer 104 composed of amorphous silicon material and the transparent conductive layer 107 to a certain extent, and ensure the effective transport of carriers, so as to achieve the purpose of improving the filling factor and conversion efficiency.

[0052] The gate electrode 108 is arranged above the transparent conductive layer 107, and includes a first gate line and a second gate line. The first gate line is located on the transparent conductive layer 107 near the first surface 1011, and the second gate line is located on the transparent conductive layer near the second surface 1012. The number of the first gate lines and the second gate lines and the positions in the thickness direction of the battery stack structure can correspond to each other. The gate electrode 108 is an important component of the metal electrode of the solar cell, and its main function is to collect and transmit photogenerated carriers, thereby realizing the conversion of solar energy into electric energy.

[0053] According to a second aspect of the present application, a method for preparing a silicon heterojunction solar cell structure is provided to prepare a silicon heterojunction solar cell structure as described in any of the above embodiments, such as Figure 1 and Figure 2 As shown, the method comprises the following steps:

[0054] S1, providing a substrate 100, wherein the substrate 100 includes a first surface 1011 and a second surface 1012 opposite to each other;

[0055] S2, forming an intrinsic amorphous silicon layer 102 on the first surface 1011 and the second surface 1012;

[0056] S3, sequentially forming a first doping layer 103 and a second doping layer 104 on the intrinsic amorphous silicon layer 102 on the first surface 1011 and the second surface 1012;

[0057] S4, forming a buffer layer with a preset thickness on the first doping layer 103 and / or the second doping layer 104;

[0058] S5, forming a transparent conductive layer 107 on the first doping layer 103 and the second doping layer 104 in sequence, and the transparent conductive layer 107 covers the buffer layer;

[0059] S5 , forming a gate line electrode 108 on the transparent conductive layer 107 .

[0060] In some embodiments, the substrate 100 in step S1 is a single crystal silicon substrate, specifically an industrial grade N-type single crystal silicon with a crystal orientation of (100), a resistivity of about 1Ω.cm, and a thickness of 100μm is used as the battery substrate 100.

[0061] The first surface 1011 and / or the second surface 1012 of the substrate 100 are textured surfaces, and the textured surfaces adopt a pyramid or inverted pyramid structure, which is textured by a KOH solution. Specifically, the N-type single crystal silicon substrate 100 in step S1 can be textured on both sides by a KOH solution to obtain a pyramid structure with an average size of 1 μm. The KOH solution is generally prepared in a ratio of KOH: additive: deionized water = 20:3:160, and the temperature is preferably 75°C, and then a standard RCA cleaning is performed to obtain a pre-treated silicon wafer.

[0062] In some embodiments, step S2 is performed by placing the double-sided textured N-type single crystal silicon substrate 100 in S1 in a PECVD device and introducing SiH 4 Gas is used to deposit a 5 nm intrinsic amorphous silicon layer 102 on the first surface 1011 and the second surface 1012 of the N-type single crystal silicon substrate 100. That is, after the intrinsic amorphous silicon layer 102 is formed on the first surface 1011 or the second surface 1012 of the substrate 100, the substrate 100 needs to be turned over and the intrinsic amorphous silicon layer 102 is continued to be formed on the second surface 1012 or the first surface 1011, and the thickness of the intrinsic amorphous silicon layer 102 on the first surface 1011 and the second surface 1012 can be related or different.

[0063] In addition, after the intrinsic amorphous silicon layer 102 is formed, it is necessary to continue to introduce high-purity H into the equipment chamber on the basis of S2. 2 As a dilution gas, the gas is used for 10 to 15 minutes to clean the substrate 100 .

[0064] In some embodiments, the first doped layer 103 in step S3 is a boron-doped nc-Si:H film, and the second doped layer 103 is a phosphorus-doped nc-Si:H film.

[0065] During the preparation of boron-doped nc-Si:H films, the chamber process pressure was set to 65 Pa, the substrate 100 temperature was set to 300 °C, the RF power was set to 50 W, and the gas flow ratio was set to SiH 4 :H 2 =1:60, the growth rate of nc-Si:H was controlled to be 0.6nm / min, and BH was introduced at the same time 3 The thickness of the nc-Si:H film and the concentration of boron atoms were 10 nm and 8E+19 cm -3.

[0066] During the preparation of phosphorus-doped nc-Si:H film, the chamber process pressure was set to 65 Pa, the substrate temperature was set to 300 °C, the RF power was 35 W, and the flow rate ratio of SiH 4 :H 2 =1:65 reaction gas, control the growth rate of nc-Si:H to 1nm / min; at the same time, introduce PH 3 The thickness of the nc-Si:H film and the concentration of phosphorus atoms were 10 nm and 1E+20 cm -3 .

[0067] It should be noted that, when the intrinsic amorphous silicon layer 102 is formed on the first surface 1011 and the second surface 1012 of the substrate 100 in step S2, the second doped layer 104 and the first doped layer 103 can be formed on the intrinsic amorphous silicon layer 102 on the second surface 1012 and the first surface 1011 in step S3, and the second doped layer 104 is formed on the intrinsic amorphous silicon layer 102 close to the second surface 1012, and the first doped layer 103 is formed on the intrinsic amorphous silicon layer 102 close to the first surface 1011.

[0068] In some embodiments, the buffer layer in step S4 can be prepared into a film after the first doping layer 103 and the second doping layer 104 are formed in step S3, or it can be interspersed in step S3 to form the first buffer layer 105 directly after the first doping layer 103, or to form the second buffer layer 106 directly after the second doping layer 104.

[0069] The first buffer layer 105 includes one or more P-type doped silicon films formed on the first doping layer 103 by plasma enhanced chemical vapor deposition, and the second buffer layer 106 includes one or more N-type doped silicon films formed on the second doping layer 104 by plasma enhanced chemical vapor deposition.

[0070] Specifically, the first doping layer 103 is boron-doped a-SiC:H, and the second doping layer 104 is phosphorus-doped a-SiC:H. After the boron-doped nc-Si:H film is formed in the PECVD chamber, the reaction gas CH 4 and the reaction gas flow ratio is SiH 4 :CH 4 :H 2 =1:8:60, control the growth rate of a-SiC:H to 4nm / min, and introduce BH 3 The thickness and phosphorus atomic concentration of a-SiC:H were 5 nm and 2E+20 cm -3Then, the substrate 100 is turned over, and the process parameters and gas parameters are adjusted to grow a phosphorus-doped nc-Si:H film on the intrinsic amorphous silicon layer 102 on the side of the first surface 1011, and after the phosphorus-doped nc-Si:H film reaches a preset thickness, the reaction gas CH is increased. 4 and the reaction gas flow ratio is SiH 4 :CH 4 :H 2 =1:6:60, control the growth rate of a-SiC:H to 2nm / min, and introduce PH 3 The thickness and phosphorus concentration of a-SiC:H were 5 nm and 5E+20 cm -3 .

[0071] In some other embodiments, the second buffer layer 106 is TiO x N y The step S4 can also be after the first doping layer 103 and the second doping layer 104 are deposited in step S3, or after the first doping layer 103 is deposited, the substrate 100 can be transferred and placed in the chamber of the PVD equipment, and a 3 nm thick TiO2 film can be formed on the second doping layer 104. x N y Thin film, TiO x N y During the film deposition process, by adjusting the O 2 The partial pressure increases TiO x N y The oxygen content in the film increases the light transmittance of the film and obtains a higher current density.

[0072] In some embodiments, step S5 uses a DC magnetron sputtering method to deposit a transparent conductive layer 107 on one side of the first surface 1011 and the second surface 1012, respectively; wherein the chamber temperature of the magnetron sputtering apparatus is preferably 250°C, the chamber pressure is 80Pa, and the sputtering power is 150W; the thickness of the transparent conductive layer 107 on the first surface 1011 side is preferably 75nm, and the thickness of the transparent conductive layer 107 on the second surface 1012 side is preferably 95nm.

[0073] When the second buffer layer 106 on the second surface 1012 is TiO x N y In the case of a thin film, the thickness of the transparent conductive layer 107 on the second surface 1012 side is preferably 50 nm.

[0074] In some embodiments, in step S6 , Ag / Al gate line electrodes 108 are printed on the transparent conductive layer 107 on both sides of the substrate 100 by screen printing.

[0075] It should be noted that for details not disclosed in the method for preparing the silicon heterojunction solar cell structure provided in this embodiment, please refer to the details disclosed in the silicon heterojunction solar cell structure in the embodiment of the present application, and no further details will be given here.

[0076] In summary, the present application provides a silicon heterojunction solar cell structure and a preparation method thereof, comprising a substrate 100, a first doping layer 103 formed on a first surface 1011 of the substrate 100 and a second doping layer 104 formed on a second surface 1012, a buffer layer formed on the first doping layer 103 and / or the second doping layer 104, and a transparent conductive layer 107 formed on the first doping layer 103 and the second doping layer 104, wherein the transparent conductive layer 107 covers the buffer layer. The present application forms a buffer layer between the first doping layer 103 and the transparent conductive layer 107 and / or between the second doping layer 104 and the transparent conductive layer 107, so as to reduce or avoid physical damage to the surface of the first doping layer 103 and / or the second doping layer 104 caused by sputtering of the transparent conductive layer 107 during the film formation process, reduce the surface defect density of the first doping layer 103 and / or the second doping layer 104, and improve the cell conversion efficiency.

[0077] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A method for preparing a silicon heterojunction solar cell structure, characterized in that: Includes steps: providing a substrate, the substrate comprising a first surface and a second surface opposite to each other; forming an intrinsic amorphous silicon layer on the first surface and the second surface; forming a second doping layer and a first doping layer in sequence on the intrinsic amorphous silicon layer on the second surface and the first surface; forming a buffer layer with a preset thickness on the first doping layer and / or the second doping layer; forming a transparent conductive layer on the first doping layer and the second doping layer in sequence, wherein the transparent conductive layer covers the buffer layer; A gate line electrode is formed on the transparent conductive layer.

2. The preparation method according to claim 1, characterized in that: The preset thickness range of the buffer layer on the first doping layer and / or the second doping layer is between 2 nm and 10 nm.

3. The preparation method according to claim 2, characterized in that: The buffer layer includes a first buffer layer, which includes one or more layers of P-type doped silicon films formed on the first doping layer using a plasma enhanced chemical vapor deposition process, including one or more combinations of silicon nitride films, silicon oxide films, and silicon carbide films.

4. The preparation method according to claim 2, characterized in that: The buffer layer includes a second buffer layer, which includes one or more layers of N-type doped silicon films formed on the second doping layer using a plasma enhanced chemical vapor deposition process, including one or more combinations of silicon nitride films, silicon oxide films, and silicon carbide films.

5. The preparation method according to claim 2, characterized in that: The buffer layer includes a metal nitride or metal oxide or metal oxynitride film formed on the first doping layer and / or the second doping layer by an atomic layer deposition process or a physical vapor deposition process, including a titanium nitride film, a titanium oxide film or a titanium oxynitride film.

6. The preparation method according to claim 1, characterized in that: The first doped layer includes a P-type doped silicon film, the second doped layer includes an N-type doped silicon film, and the silicon film includes one or a combination of amorphous silicon film, nanocrystalline silicon film, nanocrystalline silicon oxygen film, microcrystalline silicon film, and microcrystalline silicon oxygen film.

7. The preparation method according to claim 1, characterized in that: The substrate is N-type or P-type single crystal silicon. Before the step of forming an intrinsic amorphous silicon layer on the first surface and the second surface, the first surface and / or the second surface is cleaned and textured to form a textured structure.

8. The preparation method according to claim 1, characterized in that: The transparent conductive layer is prepared by a direct current magnetron sputtering method, and the material of the transparent conductive layer includes one or a combination of indium oxide, zinc oxide, cadmium oxide, and tin oxide.

9. A silicon heterojunction solar cell structure, characterized in that: The method comprises adopting the method for preparing a silicon heterojunction solar cell structure according to any one of claims 1 to 8.

10. The structure according to claim 9, characterized in that The thickness of the substrate ranges from 80nm to 180nm, the thickness of the intrinsic amorphous silicon layer ranges from 3nm to 10nm, the thickness of the first doped layer and the second doped layer ranges from 5nm to 15nm, and the thickness of the transparent conductive layer ranges from 50nm to 120nm.

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