LED chip and preparation method thereof

Abstract

The invention discloses an LED chip and a preparation method thereof. The LED chip comprises a substrate and an epitaxial structure arranged on the surface of one side of the substrate. The epitaxial structure comprises a first type semiconductor layer, a multi-quantum well layer and a second type semiconductor layer which are sequentially arranged along a first direction, and the first direction is perpendicular to the substrate and points to the epitaxial structure from the substrate; the multi-quantum well layer comprises a periodic structure formed by first film groups, and each first film group comprises a quantum barrier layer and a quantum well layer which are sequentially arranged along a first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is of a periodic structure composed of a first sub-layer and a second sub-layer; the first sub-layer is an I nGaN layer with the I n content being n, the second sub-layer is an I nGaN layer with the I n content being m, and m is larger than n, so that the energy band of the quantum well layer is in a zigzag shape. The zigzag energy band can regulate and control the spatial distribution of the I < n > cluster in the quantum well layer, reduce the barrier height and increase hole injection, thereby increasing the probability of overlapping of electrons and hole wave functions, and further improving the luminous efficiency of the LED chip.

Description

Technical Field

[0001] The present invention relates to the field of light emitting diodes, and more specifically, to an LED chip and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor electronic component that can emit light. Epitaxial wafer is the primary finished product in the LED manufacturing process. Existing LED epitaxial wafers include substrate, N-type semiconductor layer, multi-quantum well layer and P-type semiconductor layer. The substrate is used to provide a growth surface for the epitaxial material, the N-type semiconductor layer is used to provide electrons for compound luminescence, the P-type semiconductor layer is used to provide holes for compound luminescence, and the active area is used for radiation compound luminescence of electrons and holes.

[0003] At present, InGaN-based luminescent materials are increasingly being used in the fields of display and lighting due to their physical and chemical properties such as large bandgap (0.6eV-3.4eV), high breakdown electric field, and high electron saturation mobility. As the active region of LED chips, multi-quantum well InGaN / GaN is particularly important for the optical properties of LED chips. However, in the long-wave band, such as green light, dark green light, yellow light, and red light, as the In component in the active region InGaN increases, its crystal quality deteriorates and defects increase, thereby reducing the luminous efficiency of the LED chip.

[0004] Therefore, when preparing LED chips with high In content, solving the problem of low luminous efficiency of LED chips caused by lattice mismatch caused by high In components, as well as solving the problem of unconcentrated luminescence and impure color caused by In clusters, has become an urgent problem to be solved in order to improve the luminous efficiency of LED chips. Summary of the invention

[0005] In view of this, the present invention provides an LED chip and a preparation method thereof, which can improve the luminous efficiency of a high-In component LED chip and can make the luminescence more concentrated and the color rendering purer.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] Solution 1: An LED chip, comprising a substrate and an epitaxial structure arranged on one surface of the substrate; the epitaxial structure comprises a first-type semiconductor layer, a multi-quantum well layer and a second-type semiconductor layer arranged in sequence along a first direction, the first direction is perpendicular to the substrate, and the substrate points to the epitaxial structure; the multi-quantum well layer comprises a periodic structure composed of a first film group, each of the first film groups comprises a quantum barrier layer and a quantum well layer arranged in sequence along the first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is a periodic structure composed of a first sublayer and a second sublayer; the first sublayer is an InGaN layer with an In content of n, and the second sublayer is an InGaN layer with an In content of m, m>n, so that the energy band of the quantum well layer is zigzag.

[0008] Solution 2: Based on Solution 1, the value range of the period number Y of the quantum well layer is Y≥3.

[0009] Solution 3: Based on Solution 1, the In content of the quantum well layer in each of the first film groups is X; X=(n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer, and L2 is the thickness of the second sublayer.

[0010] Option 4, based on Option 3, each of the first film groups further includes an InN pre-layer located between the quantum barrier layer and the quantum well layer, and the In content of the InN pre-layer is greater than the In content in the quantum well layer.

[0011] Plan 5: Based on Plan 1, the difference between m and n is in the range of 0.04≤mn≤0.3.

[0012] Scheme 6: Based on Scheme 1, by adjusting the growth temperature of the quantum well layer, the In content of the first sublayer is n, and the In content of the second sublayer is m, thereby realizing the regulation of the sawtooth energy band of the quantum well layer; the growth temperature of the first sublayer is T1, and the growth temperature of the second sublayer is T2, T1>T2; the value ranges of T1 and T2 are both 650℃-850℃, including the endpoint values:

[0013] Alternatively, by regulating the flow rate of I n per unit time, the I n content of the first sublayer is n, and the I n content of the second sublayer is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer; when growing the first sublayer, the I n flow rate per unit time is F1, and when growing the second sublayer, the I n flow rate per unit time is F2, F2>F1; the value ranges of F1 and F2 are both 100sccm-2000sccm;

[0014] Alternatively, by regulating the flow rate of Ga per unit time, the In content of the first sublayer is n, and the In content of the second sublayer is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer; wherein, the Ga flow rate per unit time when growing the first sublayer is S1, and the Ga flow rate when growing the second sublayer is S2, S2>S1; the value ranges of S1 and S2 are both 100sccm-800sccm.

[0015] Solution 7: Based on Solution 1, the period number N of the multi-quantum well layer ranges from 3 to 15, including endpoint values.

[0016] Solution 8: A method for preparing an LED chip, comprising:

[0017] providing a substrate;

[0018] An epitaxial structure is grown on a surface of one side of a substrate; the growth of the epitaxial structure includes sequentially growing a first-type semiconductor layer, a multi-quantum well layer, and a second-type semiconductor layer along a first direction, wherein the first direction is perpendicular to the substrate and points from the substrate to the epitaxial structure; the multi-quantum well layer includes a periodic structure composed of a first film group, wherein the first film group includes a quantum barrier layer and a quantum well layer sequentially arranged along the first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is a periodic structure composed of a first sublayer and a second sublayer; the first sublayer is an InGaN layer with an In content of n, and the second sublayer is an InGaN layer with an In content of m, where m>n, so that the energy band of the quantum well layer is zigzag.

[0019] Solution nine: Based on solution eight, the value range of the period number Y of the quantum well layer is Y≥3.

[0020] Solution 10: Based on Solution 8, the In content of the quantum well layer in each of the first modules is X, X=(n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer, and L2 is the thickness of the second sublayer.

[0021] Solution 11: Based on Solution 10, growing each of the first modules further includes growing an InN pre-layer between the quantum barrier layer and the quantum well layer, and the In content of the InN pre-layer is greater than the In content of the quantum well layer.

[0022] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0023] The LED chip of the present application comprises a substrate and an epitaxial structure arranged on one side surface of the substrate; the epitaxial structure comprises a first-type semiconductor layer, a multi-quantum well layer, and a second-type semiconductor layer arranged in sequence along a first direction, the first direction is perpendicular to the substrate, and the substrate points to the epitaxial structure; the multi-quantum well layer comprises a periodic structure composed of first film groups, each of the first film groups comprises a quantum barrier layer and a quantum well layer arranged in sequence along the first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is a periodic structure composed of a first sublayer and a second sublayer; the first sublayer is an InGaN layer with an In content of n, and the second sublayer is an InGaN layer with an In content of m, m>n, so that the energy band of the quantum well layer is zigzag. And because this zigzag quantum well layer can regulate the spatial distribution of In clusters in the quantum well layer, while reducing the barrier height and increasing hole injection, the probability of electron and hole wave function overlap is increased, thereby improving the luminous efficiency of the LED chip; and the zigzag quantum well layer is composed of many V-shaped sawtooths, which can weaken the built-in electric field in the active region, enhance the migration rate of holes, and make the recombination of electrons and holes in the entire quantum well layer more uniform.

[0024] Furthermore, the In content of the quantum well layer in each first film group is X; X = (n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer, and L2 is the thickness of the second sublayer. Therefore, the thickness of the first sublayer and the second sublayer are different, and the In content is also different, thereby regulating the spatial distribution of the In clusters in the quantum well layer, reducing the barrier height, increasing hole injection, and improving the recombination efficiency of electrons and holes in the quantum well layer, thereby affecting luminescence.

[0025] Furthermore, since the difficulty of In incorporation will lead to the problem of low luminous efficiency of long-wave LEDs, in order to solve the problem of the difficulty of In incorporating In into the InGaN quantum well layer in the multi-quantum well layer in the prior art, a method of growing the multi-quantum well layer at a low temperature (for example: 550-600°C) is usually adopted to achieve more In incorporation to achieve the effect of long-wave emission; however, this method is prone to double-peak emission due to the low temperature, and the low temperature causes the crystal quality to deteriorate, which will form more non-radiative recombination centers, thereby affecting the luminous efficiency of the LED. In the present application, the first film group also includes an InN pre-layer located between the quantum barrier layer and the quantum well layer. By arranging an InN pre-layer below the InGaN quantum well layer, the In incorporation in the high In component LED chip is increased, so that the same wavelength can be obtained using a higher growth temperature, and the luminous efficiency of the LED chip is improved without deteriorating the material crystal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0027] Figure 1 This is a schematic diagram of the structure of an implementation method of the LED chip of the present application;

[0028] Figure 2 A schematic diagram of the structure of a multi-quantum well layer in the LED chip of the present application;

[0029] Figure 3 This is a schematic diagram of the structure of the quantum well layer in the LED chip of this application;

[0030] Figure 4 This is another schematic diagram of the structure of the multi-quantum well layer in the LED chip of this application;

[0031] Figure 5 This is a schematic diagram of the energy band of the quantum well layer in the LED chip of this application;

[0032] Figure 6 This is a structural schematic diagram of another embodiment of the LED chip of the present application;

[0033] Figure 7 This is a structural schematic diagram of another embodiment of the LED chip of the present application;

[0034] Figure 8 This is a structural schematic diagram of another implementation method of the LED chip of the present application;

[0035] Fig. 9 This is a schematic structural diagram of another implementation method of the LED chip of the present application;

[0036] Fig.10 This is a schematic diagram of the source for growing a multi-quantum well layer on an LED chip of the present application.

[0037] Figure numerals: substrate 1; first-type semiconductor layer 2; multi-quantum well layer 3; first module 31; quantum barrier layer 311; quantum well layer 312; first sublayer 3121; second sublayer 3122; InN pre-layer 313; second-type semiconductor layer 4; first electrode 5; second electrode 6; low-temperature nucleation layer 7; undoped GaN layer 8; electron blocking layer 9; P-type contact layer 10; first direction D1. DETAILED DESCRIPTION

[0038] To make the content of the present invention clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0040] Secondly, the present application is described in detail with reference to the schematic diagram. When describing the embodiments of the present application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0041] The present application provides an LED chip, such as Figure 1 As shown, the LED chip includes a substrate 1 and an epitaxial structure arranged on one side surface of the substrate 1; the epitaxial structure includes a first-type semiconductor layer 2, a multi-quantum well layer 3 and a second-type semiconductor layer 4 arranged in sequence along a first direction D1, and the first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial structure; Figure 2 As shown, the multi-quantum well layer 3 includes a periodic structure composed of a first film group 31, each of which includes a quantum barrier layer 311 and a quantum well layer 312 arranged in sequence along a first direction D1; the quantum barrier layer 311 is a GaN layer, such as Figure 3 As shown, the quantum well layer 312 is a periodic structure composed of a first sublayer 3121 and a second sublayer 3122; the first sublayer 3121 is an InGaN layer with an In content of n, and the second sublayer 3122 is an InGaN layer with an In content of m, where m>n, so that the energy band of the quantum well layer 312 is zigzag (as shown in FIG. Figure 5 shown).

[0042] Since the sawtooth quantum well layer 312 can regulate the spatial distribution of the In clusters in the quantum well layer 312, reduce the barrier height, increase hole injection, and thus increase the probability of electron and hole wave function overlap, thereby improving the luminous efficiency of the LED chip. In addition, the sawtooth quantum well layer 312 is composed of many V-shaped sawtooths, which can weaken the built-in electric field of the active region, enhance the migration rate of holes, and make the recombination of electrons and holes in the entire quantum well layer 312 more uniform.

[0043] One of the first semiconductor layer 2 and the second semiconductor layer 4 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In this application, the first semiconductor layer 2 is an N-type semiconductor, and the second semiconductor layer 4 is a P-type semiconductor layer.

[0044] Furthermore, the LED chip further includes a first electrode 5 electrically connected to the first-type semiconductor layer 2 and a second electrode 6 electrically connected to the second-type semiconductor layer 4 .

[0045] The substrate 1 may be a sapphire substrate, a silicon substrate, a silicon nitride substrate, etc., and this application does not make any specific limitation.

[0046] The N-type semiconductor layer may be N-type GaN, and preferably the thickness of the N-type GaN is 1.0 μm-2.1 μm, including the end value; the doping element of the N-type GaN is Si, and the doping concentration ranges from 1*10 18 cm -3 -10*10 18 cm -3 , including the endpoint values.

[0047] The P-type semiconductor layer may be P-type GaN. Preferably, the thickness of the P-type semiconductor layer is in the range of 80 nm to 170 nm, including the end value. The doping element of the P-type GaN is Mg, and the doping concentration is in the range of 5*10 18 cm -3 -10*10 18 cm -3 , including the endpoint values.

[0048] In a preferred embodiment, if Figure 3 As shown, the value range of the period number Y of the quantum well layer 312 is Y≥3, for example, Y is 3, 4, 5, 6, etc., that is, the first sublayer 3121 and the second sublayer 3122 in the quantum well layer 312 have Y pairs.

[0049] In a preferred embodiment, the difference between m and n is in the range of 0.04≤mn≤0.3.

[0050] In a preferred embodiment, the In content of the quantum well layer 312 in each of the first film groups 31 is X; X = (n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer 3121, L2 is the thickness of the second sublayer 3122; L1 and L2 refer to the thickness of the first sublayer 3121 and the second sublayer 3122 in the first direction D1. Therefore, the thickness of the first sublayer 3121 and the second sublayer 3122 are different, and the In content is also different, thereby regulating the spatial distribution of the In clusters in the quantum well layer 312, reducing the barrier height, increasing hole injection, and improving the recombination efficiency of electrons and holes in the quantum well layer, thereby affecting luminescence.

[0051] In a preferred embodiment, if Figure 4 As shown, each of the first film groups 31 further includes an InN pre-layer 313 located between the quantum barrier layer 311 and the quantum well layer 312 , and the In content of the InN pre-layer 313 is greater than the In content in the quantum well layer 312 .

[0052] Since the difficulty of In incorporation leads to the problem of low luminous efficiency of long-wave LED, in the prior art, in order to realize the problem of In incorporation difficulty of InGaN quantum well layer 3 in multi-quantum well layer 3, a method of growing multi-quantum well layer 3 at low temperature (e.g., 550°C-600°C) is usually adopted to realize more In incorporation to achieve the effect of long-wave emission; however, this method is prone to double peak emission due to the low temperature, and the low temperature leads to poor crystal quality, which will form more non-radiative recombination centers, thereby affecting the luminous efficiency of LED. In the present application, the first film group 31 also includes an InN pre-layer 313 located between the quantum barrier layer 311 and the quantum well layer 312. By arranging the InN pre-layer 313 below the InGaN quantum well layer 312, the In incorporation in the high In component LED chip is increased, so that a long-wave LED is obtained by using a higher growth temperature, and the luminous efficiency of the LED chip is improved without deteriorating the material crystal quality.

[0053] In a preferred embodiment, if Figure 2 As shown, the period number N of the multi-quantum well layer 3 ranges from 3 to 15, including end values; for example, N is 3, 5, 8, 10, etc. That is, the quantum barrier layer and the quantum well layer in the multi-quantum well layer have N pairs or the quantum barrier layer, the I nN pre-layer and the quantum well layer in the multi-quantum well layer have N groups.

[0054] In a preferred embodiment, if Figure 3As shown, by regulating the growth temperature of the quantum well layer 312, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby realizing the regulation of the sawtooth energy band of the quantum well layer 312; the growth temperature of the first sublayer 3121 is T1, and the growth temperature of the second sublayer 3122 is T2, T1>T2. Preferably, the value range of T1 and T2 is 650℃-850℃, including the endpoint value. That is, T1 and T2 can be selected within 650℃-850℃ under the condition that T1>T2, for example: 650℃, 700℃, 800℃, 850℃, etc.

[0055] Alternatively, by regulating the flow rate of In per unit time, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer 312; wherein, when the first sublayer 3121 is grown, the In flow rate per unit time is F1, and when the second sublayer 3122 is grown, the In flow rate per unit time is F2, and F2>F1. The value ranges of F1 and F2 are both 100sccm-2000sccm, including the endpoint values. That is, under the condition that F2>F1, F1 and F2 can be selected within 100sccm-2000sccm, for example, they can be: 100sccm, 300sccm, 500sccm, 750sccm, 1000sccm, 1500sccm, 2000sccm, etc.

[0056] Alternatively, by regulating the flow rate of Ga per unit time, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer 312; wherein the Ga flow rate per unit time when growing the first sublayer 3121 is S1, and the Ga flow rate when growing the second sublayer 3122 is S2, S2>S1. The value range of S1 and S2 is 100sccm-800sccm, including the endpoint value. That is, S1 and S2 can be selected within 100sccm-800sccm under the condition that S2>S1, for example, they can be: 100sccm, 300sccm, 550sccm, 700sccm, 850sccm, etc.

[0057] In a preferred embodiment, if Figure 6 As shown, the epitaxial structure further includes an undoped low-temperature nucleation layer 7 disposed between the substrate 1 and the first-type semiconductor layer 2. Preferably, the low-temperature nucleation layer 7 is AlN, and its thickness is 5nm-25nm, including end values.

[0058] In a preferred embodiment, if Figure 7As shown, the epitaxial structure also includes an undoped GaN layer 8 disposed between the low-temperature nucleation layer 7 and the first-type semiconductor layer 2. The purpose of providing the undoped GaN layer is to reduce the lattice mismatch between the substrate 1 and the subsequent growth material by growing a high-quality GaN layer. Preferably, the thickness of the undoped GaN is 2.0 μm-4 μm, including the end value.

[0059] In a preferred embodiment, if Figure 8 As shown, the epitaxial structure further includes an electron blocking layer 9 (EBL) disposed between the multi-quantum well layer 3 and the second-type semiconductor layer 4, and the electron blocking layer 9 is a P-type Al GaN layer. Preferably, the thickness of the P-type Al GaN layer is 80nm-120nm, including the end value, the doping element is Mg, and the doping concentration range is 5*10 18 cm -3 -10*10 18 cm -3 , including the endpoint values.

[0060] In a preferred embodiment, if Fig. 9 As shown, the epitaxial structure further includes a P-type contact layer 10 disposed on the second-type semiconductor layer 4. Preferably, the P-type contact layer 10 is P-type GaN, and its thickness is 7nm-25nm, including end values, and the doping concentration range is 1*10 19 cm -3 -5*10 19 cm -3 , including the endpoint values.

[0061] The present application also provides a method for manufacturing an LED chip, which comprises the following steps:

[0062] Among them, optionally, the equipment used is MOCVD, with trimethyl / ethylgallium TMGa / TEGa, trimethylaluminum TMAl and ammonia NH3 as Ga source, Al source and nitrogen source respectively, N2 as carrier gas, and N-type and P-type doping sources respectively being silane SiH4 and bis(cyclopentadienyl)magnesium CP2Mg.

[0063] S01: Provide a substrate 1. Specifically, place the substrate 1 in a MOCVD reaction chamber, heat the temperature to 1000°C-1200°C (including the endpoint value), and introduce high-purity hydrogen for 3min-15min (including the endpoint value). The substrate 1 can be a sapphire substrate 1, a silicon substrate 1, a silicon nitride substrate 1, etc., which is not specifically limited in this application.

[0064] S02: growing an epitaxial structure on the surface of one side of the substrate 1. Figure 1As shown, growing the epitaxial structure includes sequentially growing a first-type semiconductor layer 2, a multi-quantum well layer 3, and a second-type semiconductor layer 4 along a first direction D1, wherein the first direction D1 is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial structure; Figure 2 As shown, the multi-quantum well layer 3 includes a periodic structure composed of a first film group 31, wherein the first film group 31 includes a quantum barrier layer 311 and a quantum well layer 312 sequentially arranged along a first direction D1; the quantum barrier layer 311 is a GaN layer, as shown in FIG. Figure 3 As shown, the quantum well layer 312 is a periodic structure composed of a first sublayer 3121 and a second sublayer 3122; the first sublayer 3121 is an InGaN layer with an In content of n, and the second sublayer 3122 is an InGaN layer with an In content of m, m>n, so that the energy band of the quantum well layer 312 is a sawtooth shape.

[0065] One of the first semiconductor layer 2 and the second semiconductor layer 4 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In this embodiment, the first semiconductor layer 2 is an N-type semiconductor, and the second semiconductor layer 4 is a P-type semiconductor layer.

[0066] The N-type semiconductor may be N-type GaN, and preferably the thickness of the N-type GaN is 1.0 μm-2.1 μm, including the end value. The doping element of the N-type GaN is Si, and the doping concentration ranges from 1*10 18 cm -3 -10*10 18 cm -3 Specifically, N source, Ga source and silane are introduced during growth to grow N-type GaN.

[0067] The P-type semiconductor layer may be P-type GaN. Preferably, the thickness of the P-type semiconductor layer is in the range of 80-170 nm, including the end value. The doping element of the P-type GaN is Mg, and the doping concentration is in the range of 5*10 18 cm -3 -10*10 18 cm -3 Specifically, during the growth, N source, Ga source and bismuth magnesium are introduced to grow P-type GaN.

[0068] S03: A first electrode 5 electrically connected to the first type semiconductor layer 2 and a second electrode 6 electrically connected to the second type semiconductor layer 4 are fabricated on the epitaxial structure. Specifically, a groove exposing the first type semiconductor layer 2 is processed on the epitaxial structure, and a table is formed; the first electrode 5 is fabricated at the bottom of the groove, and the second electrode 6 is fabricated on the table.

[0069] In a preferred embodiment, the period number Y of the quantum well layer 312 has a value range of Y≥3.

[0070] In a preferred embodiment, the difference between m and n is in the range of 0.04≤mn≤0.3.

[0071] In a preferred embodiment, the period number N of the multi-quantum well layer 3 ranges from 3 to 15, including the end values.

[0072] In a preferred embodiment, in step S02, by adjusting the growth temperature of the quantum well layer 312, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer 312; the growth temperature of the first sublayer 3121 is T1, and the growth temperature of the second sublayer 3122 is T2, T1>T2. The value range of T1 and T2 is 650℃-850℃, including the endpoint value. That is, T1 and T2 can be selected within 650℃-850℃ under the condition that T1>T2, for example, they can be: 650℃, 700℃, 800℃, 850℃, etc.

[0073] Alternatively, in step S02, by regulating the flow rate of In per unit time, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer 312; wherein, when the first sublayer 3121 is grown, the In flow rate per unit time is F1, and when the second sublayer 3122 is grown, the In flow rate per unit time is F2, and F2>F1. The value ranges of F1 and F2 are both 100sccm-2000sccm, including the endpoint values. That is, F1 and F2 can be selected within 100sccm-2000sccm under the condition that F2>F1, for example, they can be: 100sccm, 300sccm, 500sccm, 750sccm, 1000sccm, 1500sccm, 2000sccm, etc.

[0074] Alternatively, in step S02, by regulating the flow rate of Ga per unit time, the In content of the first sublayer 3121 is n, and the In content of the second sublayer 3122 is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer 312; wherein the Ga flow rate per unit time when growing the first sublayer 3121 is S1, and the Ga flow rate when growing the second sublayer 3122 is S2, S2>S1. That is, S1 and S2 can be selected within 100sccm-800sccm under the condition that S2>S1, for example, can be: 100sccm, 300sccm, 550sccm, 700sccm, 850sccm, etc.

[0075] In a preferred embodiment, the In content of the quantum well layer 312 in each of the first modules 31 is X, X=(n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer 3121, and L2 is the thickness of the second sublayer 3122.

[0076] In a preferred embodiment, in step S02 , growing each of the first modules 31 further includes growing an InN pre-layer 313 between the quantum barrier layer 311 and the quantum well layer 312 , and the In content of the InN pre-layer 313 is greater than the In content of the quantum well layer 312 .

[0077] In order to facilitate understanding, a detailed description of the process of growing a multi-quantum well layer 3 in a growth cycle is given, taking the method of regulating the growth temperature of the quantum well layer 312 as an example:

[0078] Fig.10 The schematic diagram of the source for growing a multi-quantum well layer is shown below. The Ga source and N source are introduced, and the growth time is t0 to grow a GaN quantum barrier layer 311 with a thickness of 5nm-20nm (including the end value); then the Ga source is turned off, and the In source is introduced for growth, and the time is t1 (0s-60s, including the end value). As a pretreatment method, before growing the quantum well layer 312, its growth conditions are consistent with the subsequent quantum well layer 312 conditions, wherein the In source flow rate is 70sccm-350sccm (including the end value), and the InN pre-layer is grown. In theory, after the Ga source is turned off, a layer of InN should be grown, but in fact, there is still a Ga source in the reaction chamber, which is actually an InGaN layer with a very low Ga content. Its In content is much greater than the quantum well layer 312 grown later, and the In content in the entire quantum well layer 312 is increased, so that the same wavelength can be obtained with a higher growth temperature, and the luminous efficiency of the LED chip is improved without deteriorating the material crystal quality. Then, a Ga source is introduced to grow a quantum well layer 312 of 1nm-10nm (including the end value), and a zigzag quantum well layer 312 is formed by temperature control. In this process, the In content X of the quantum well layer 312 remains unchanged, that is, X=(n*L1+m*L2) / (L1+L2). The temperature is raised to T1, and the In source and Ga source are introduced for t2 time to obtain an InGaN layer with an In content of n, and then the temperature is lowered to T2, and the In source and Ga source are introduced for t2 time to obtain an InGaN layer with an In content of m. Repeat the above cycle Y (for example, 3, 4, 5, 6, etc.) to obtain a zigzag quantum well layer 312 with a constant In content. Finally, the above quantum barrier layer 311, InN pre-layer, and zigzag quantum well layer 312 are repeated, and the growth cycle is N (for example, 3, 5, 8, 10, etc.) to form a multi-quantum well layer 3.

[0079] In a preferred embodiment, in step S02, Figure 6 As shown, before growing the first type semiconductor layer 2, an undoped low temperature nucleation layer 7 is grown on the substrate 1, that is, the low temperature nucleation layer 7 is located between the substrate 1 and the first type semiconductor layer 2. Preferably, the low temperature nucleation layer 7 is AlN, and its thickness is 5nm-25nm, including the end value. Specifically, after the substrate is H-treated, the temperature is lowered to 900℃-1000℃, and Al source and N source are introduced to grow the undoped low temperature nucleation layer 7.

[0080] Further, in step S02, as Figure 7 As shown, after growing the low-temperature nucleation layer 7 and before growing the first-type semiconductor layer 2, it also includes growing an undoped GaN layer 8 on the low-temperature nucleation layer 7, that is, the undoped GaN layer 8 is located between the low-temperature nucleation layer 7 and the first-type semiconductor layer 2. The purpose of providing the undoped GaN layer is to reduce the lattice mismatch between the substrate 1 and the subsequent growth material by growing a high-quality GaN layer. Preferably, the thickness of the undoped GaN is 2.0μm-4μm, including the end value. Specifically, after the undoped low-temperature nucleation layer 7 is grown, the temperature is raised to 950℃-1200℃, the Al source is turned off and the TMGa source is introduced to grow a 2.5um-3.5um undoped GaN layer.

[0081] In a preferred embodiment, if Figure 8 As shown, in step S02, after growing the multi-quantum well layer 3 and before growing the second-type semiconductor layer 4, it also includes growing an electron blocking layer 9 (EBL), that is, the electron blocking layer 9 (EBL) is located between the multi-quantum well layer 3 and the second-type semiconductor layer 4. The electron blocking layer 9 is a P-type Al GaN layer. Preferably, the thickness of the P-type Al GaN layer is 80nm-120nm, the doping element is Mg, and the doping concentration range is 5*10 18 cm -3 -10*10 18 cm -3 , including the endpoint values.

[0082] In a preferred embodiment, if Fig. 9 As shown, in step S02, it also includes growing a P-type GaN contact layer on the second-type semiconductor layer 4. Preferably, the thickness of the P-type GaN contact layer is 7nm-25nm (including the end value), and the doping concentration ranges from 1*10 19 cm -3 -5*10 19 cm -3 (including the endpoint value), and annealed at 800°C-950°C in an N2 atmosphere for 15min-35min (including the endpoint value).

[0083] In a preferred embodiment, in the preparation methods of the above embodiments, the pressure of the entire reaction growth can range from 70 torr to 350 torr.

[0084] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "horizontal", "vertical", "upper", "lower", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0085] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0086] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that: It comprises a substrate and an epitaxial structure arranged on one side surface of the substrate; the epitaxial structure comprises a first-type semiconductor layer, a multi-quantum well layer and a second-type semiconductor layer arranged in sequence along a first direction, the first direction is perpendicular to the substrate and points from the substrate to the epitaxial structure; the multi-quantum well layer comprises a periodic structure composed of first film groups, each of the first film groups comprises a quantum barrier layer and a quantum well layer arranged in sequence along the first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is a periodic structure composed of a first sublayer and a second sublayer; the first sublayer is an InGaN layer with an In content of n, and the second sublayer is an InGaN layer with an In content of m, m>n, so that the energy band of the quantum well layer is zigzag.

2. The LED chip according to claim 1, characterized in that: The value range of the period number Y of the quantum well layer is Y≥3.

3. The LED chip according to claim 1, characterized in that: The In content of the quantum well layer in each of the first film groups is X; X=(n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer, and L2 is the thickness of the second sublayer.

4. The LED chip according to claim 3, characterized in that: Each of the first film groups further includes an InN pre-layer located between the quantum barrier layer and the quantum well layer, and the In content of the InN pre-layer is greater than the In content in the quantum well layer.

5. The LED chip according to claim 1, characterized in that: The difference between m and n ranges from 0.04≤mn≤0.

3.

6. The LED chip according to claim 1, characterized in that: By regulating the growth temperature of the quantum well layer, the In content of the first sublayer is n, and the In content of the second sublayer is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer; the growth temperature of the first sublayer is T1, and the growth temperature of the second sublayer is T2, T1>T2; the value ranges of T1 and T2 are both 650°C-850°C, including the endpoint values: Alternatively, by regulating the flow rate of In per unit time, the In content of the first sublayer is n, and the In content of the second sublayer is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer; when growing the first sublayer, the In flow rate per unit time is F1, and when growing the second sublayer, the In flow rate per unit time is F2, F2>F1; the value ranges of F1 and F2 are both 100sccm-2000sccm, including the end value; Alternatively, by regulating the flow rate of Ga per unit time, the In content of the first sublayer is n, and the In content of the second sublayer is m, thereby achieving the regulation of the sawtooth energy band of the quantum well layer; wherein, the Ga flow rate per unit time when growing the first sublayer is S1, and the Ga flow rate when growing the second sublayer is S2, S2>S1; the value ranges of S1 and S2 are both 100sccm-800sccm, including the endpoint values.

7. The LED chip according to claim 1, characterized in that: The period number N of the multi-quantum well layer ranges from 3 to 15, including end points.

8. A method for preparing an LED chip, characterized in that: include: providing a substrate; An epitaxial structure is grown on a surface of one side of a substrate; growing the epitaxial structure comprises sequentially growing a first-type semiconductor layer, a multi-quantum well layer, and a second-type semiconductor layer along a first direction, wherein the first direction is perpendicular to the substrate and points from the substrate to the epitaxial structure; the multi-quantum well layer comprises a periodic structure composed of a first film group, wherein the first film group comprises a quantum barrier layer and a quantum well layer sequentially arranged along the first direction; the quantum barrier layer is a GaN layer, and the quantum well layer is a periodic structure composed of a first sublayer and a second sublayer; the first sublayer is an InGaN layer with an In content of n, and the second sublayer is an InGaN layer with an In content of m, wherein m>n, so that the energy band of the quantum well layer is zigzag-shaped.

9. The method for preparing an LED chip according to claim 8, characterized in that: The value range of the period number Y of the quantum well layer is Y≥3.

10. The method for preparing an LED chip according to claim 8, characterized in that: The In content of the quantum well layer in each of the first modules is X, where X=(n*L1+m*L2) / (L1+L2), L1 is the thickness of the first sublayer, and L2 is the thickness of the second sublayer.

11. The method for preparing an LED chip according to claim 10, characterized in that: Growing each of the first modules further includes growing an InN pre-layer between the quantum barrier layer and the quantum well layer, and the In content of the InN pre-layer is greater than the In content of the quantum well layer.

Images