Polycrystalline integrated device, manufacturing method thereof and display panel

Abstract

The invention relates to a polycrystalline integrated device, a manufacturing method thereof and a display panel. The method comprises the following steps: providing a supporting substrate; forming a temporary layer on the supporting substrate; executing a metal wiring process on the temporary layer to obtain a conductive wiring layer; respectively transferring light-emitting chips with at least three different colors to the conductive wiring layer, and respectively bonding the light-emitting chips with the conductive wiring layer; filling a light barrier layer between the adjacent light-emitting chips; and dissociating the temporary layer to expose the conductive wiring layer. Compared with the prior art, the thickness of the polycrystalline integrated device manufactured by the method is obviously reduced, so that the problem of crystal collapse in the testing and crystal fixing processes can be avoided. In addition, at a product application end, a thinner polycrystalline integrated device means that a thinner and higher PPI display device can be produced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a polycrystalline integrated device and a manufacturing method thereof, and a display panel. Background Art

[0002] Compared with other existing display technologies (LCD, PDP, OLED, etc.), Micro / Mini LED technology has the advantages of high brightness, high contrast, wide color gamut, large viewing angle, low power consumption, long life, ultra-thin flexible display, etc., and is considered to be the ultimate technology for future displays.

[0003] MIP (Micro LED In Package, a packaging architecture based on micron-level light-emitting diodes) combines Micro-LED chips with high-precision substrates to achieve fan-out packaging, which can reduce the difficulty of testing and downstream mounting. MIP devices can fully test, sort, and bin RGB Micro pixels, which can make the display consistency of the panel high.

[0004] However, if the MIP device is to be made smaller in size, the substrate and packaging layer need to be made thinner. However, it is difficult to make the BT (Bismaleimide Triazine) substrate very thin. An MIP device that is too thick will have a flip crystal problem during subsequent testing and die bonding. After the glass substrate and sapphire substrate are made thin, the substrate is prone to cracking in the subsequent manufacturing process. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a polycrystalline integrated device and a manufacturing method thereof, and a display panel, aiming to solve the problem that the existing MIP device is too large in size.

[0006] A method for manufacturing a polycrystalline integrated device, comprising:

[0007] providing a supporting substrate;

[0008] forming a temporary layer on the supporting substrate;

[0009] Performing a metal wiring process on the temporary layer to obtain a conductive wiring layer;

[0010] Transferring at least three light-emitting chips of different colors to the conductive wiring layer respectively, and bonding them to the conductive wiring layer respectively;

[0011] Filling a light blocking layer between adjacent light emitting chips; and

[0012] The temporary layer is dissociated to expose the conductive wiring layer.

[0013] The polycrystalline integrated device prepared by this method is integrated by first making a temporary layer on the supporting substrate, then making a conductive wiring layer on the temporary layer, and then transferring a plurality of light-emitting chips of different colors to the conductive wiring layer for bonding, and then filling a light blocking layer between adjacent light-emitting chips. Finally, the temporary layer is dissociated, which means that the supporting substrate bonded to the temporary layer is also removed together. Compared with the existing scheme, the corresponding polycrystalline integrated device has less thickness of the supporting substrate and the temporary layer, so that the thickness of the polycrystalline integrated device of the present application is significantly reduced, thereby avoiding the problem of easy breakage of traditional substrates and the problem of inverted crystals in traditional polycrystalline integrated devices during testing and solid crystal bonding. In addition, at the product application end, thinner polycrystalline integrated devices mean that thinner and higher PPI display devices can be produced.

[0014] In one embodiment, the conductive wiring layer includes a first wiring and at least three second wirings; the first wiring is electrically connected to the first electrode of each of the light-emitting chips, and one of the second wirings is correspondingly connected to the second electrode of the light-emitting chip.

[0015] In one embodiment, the conductive wiring layer further includes a first pad and at least three second pads; the first pad is connected to the first wiring, and one of the second pads is correspondingly connected to one of the second wirings.

[0016] In one embodiment, after the step of filling a light blocking layer between adjacent light emitting chips, the method further comprises:

[0017] A packaging layer is manufactured on the surface of each light emitting chip and the light blocking layer.

[0018] In one embodiment, it further includes:

[0019] The light blocking layer is patterned to expose the side surface of the light emitting chip; wherein the packaging layer is also filled on the side surface of the light emitting chip.

[0020] In one embodiment, the metal wiring process includes any of the following methods:

[0021] Method 1: forming a metal layer on the temporary layer;

[0022] performing a patterning process on the metal layer to form the conductive wiring layer;

[0023] Method 2: forming a sacrificial layer on the temporary layer;

[0024] Performing a patterning process on the sacrificial layer to partially expose the temporary layer; wherein the pattern of the exposed temporary layer is the same as the pattern of the conductive wiring layer;

[0025] Vapor-depositing a metal layer on the exposed surface of the temporary layer to form the conductive wiring layer;

[0026] The sacrificial layer is removed.

[0027] In one embodiment, the metal layer includes a single-layer metal structure or a multi-layer metal stack structure.

[0028] In one embodiment, the material of the metal layer includes any one of copper, aluminum, titanium, chromium, platinum, and gold.

[0029] In one embodiment, it further includes:

[0030] The dissociated material remaining on the surface of the conductive wiring layer is removed.

[0031] In one embodiment, the temporary layer comprises any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly(p-phenylene benzobisoxazole) and an organic material.

[0032] Based on the same inventive concept, the present application also provides a polycrystalline integrated device, which is manufactured using the method for manufacturing a polycrystalline integrated device as described above.

[0033] Compared with traditional solutions, the above-mentioned polycrystalline integrated devices have fewer supporting substrates and are thinner, which can avoid the problem of traditional substrates being easily broken and the problem of traditional polycrystalline integrated devices flipping during testing and solidification. In addition, on the product application side, thinner polycrystalline integrated devices mean that thinner and higher PPI display devices can be produced.

[0034] Based on the same inventive concept, the present application also provides a display panel, which includes a driving substrate and the polycrystalline integrated device as described above; wherein the driving substrate is electrically connected to the polycrystalline integrated device.

[0035] The display panel adopts the aforementioned polycrystalline integrated device, which is thinner due to the lack of a supporting substrate. Therefore, the thickness of the display panel is correspondingly thinner and has a higher PPI. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic flow chart of a method for manufacturing a polycrystalline integrated device in an embodiment;

[0037] Figure 2 is a schematic flow chart of a method for manufacturing a polycrystalline integrated device in another embodiment;

[0038] Figure 3 for Figure 1 Schematic diagram of the sub-steps of step S300;

[0039] Figure 4 for Figure 1 Schematic diagram of the sub-steps of step S300;

[0040] Figures 5 to 10b For Figure 1 Schematic diagram of structural changes corresponding to the steps of the method;

[0041] Fig.11 for Figure 1 A structural change diagram corresponding to an implementation scheme of step S300;

[0042] Fig.12 for Figure 1 FIG. 4 is a structural change diagram corresponding to another implementation scheme of step S300.

[0043] Description of reference numerals:

[0044] ST-support substrate; 110-temporary layer; 120-conductive wiring layer; P1-first pad; P2-second pad; S1-first wiring; S2-second wiring; R-red light chip; G-green light chip; B-blue light chip; 130-light blocking layer; 140-packaging layer; MT-metal layer; PR1-first photoresist; PR2-second photoresist; 150-sacrificial layer. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., can be used here to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0048] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0050] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0051] Compared with other existing display technologies (LCD, PDP, OLED, etc.), Micro / Mini LED technology has the advantages of high brightness, high contrast, wide color gamut, large viewing angle, low power consumption, long life, ultra-thin flexible display, etc., and is considered to be the ultimate technology for future displays.

[0052] MIP (Micro LED In Package, a packaging architecture based on micron-level light-emitting diodes) combines Micro-LED chips with high-precision substrates to achieve fan-out packaging, which can reduce the difficulty of testing and downstream mounting. MIP devices can fully test, sort, and bin RGB Micro pixels, which can make the display consistency of the panel high.

[0053] However, if the MIP device is to be made smaller in size, the substrate and packaging layer need to be made thinner, but it is difficult to make the BT substrate very thin. An MIP device that is too thick will have a flip-chip problem during subsequent testing and die bonding. After the glass substrate and sapphire substrate are made thin, the substrate is prone to cracking in the subsequent manufacturing process.

[0054] Based on this, the present application hopes to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in the subsequent embodiments.

[0055] Please refer to Figure 1 , is a schematic flow chart of a method for manufacturing a polycrystalline integrated device provided in the present application. The method may include steps S100-S600.

[0056] Step S100, providing a supporting substrate;

[0057] Step S200, forming a temporary layer on the supporting substrate;

[0058] Step S300, performing a metal wiring process on the temporary layer to obtain a conductive wiring layer;

[0059] Step S400, transferring at least three light-emitting chips of different colors onto the conductive wiring layer respectively, and bonding them to the conductive wiring layer respectively;

[0060] Step S500, filling a light blocking layer between adjacent light emitting chips; and

[0061] Step S600, dissociating the temporary layer to expose the conductive wiring layer.

[0062] The polycrystalline integrated device prepared by this method is integrated by first making a temporary layer on the supporting substrate, then making a conductive wiring layer on the temporary layer, and then transferring a plurality of light-emitting chips of different colors to the conductive wiring layer for bonding, and then filling a light blocking layer between adjacent light-emitting chips. Finally, the temporary layer is dissociated, which means that the supporting substrate bonded to the temporary layer is also removed together. Compared with the existing scheme, the corresponding polycrystalline integrated device has less thickness of the supporting substrate and the temporary layer, so that the thickness of the polycrystalline integrated device of the present application is significantly reduced, thereby avoiding the problem of easy breakage of traditional substrates and the problem of inverted crystals in traditional polycrystalline integrated devices during testing and solid crystal bonding. In addition, at the product application end, thinner polycrystalline integrated devices mean that thinner and higher PPI display devices can be produced.

[0063] Specifically, please refer to Figure 5 , the supporting substrate ST may be a transparent substrate, and the material of the transparent substrate may include an inorganic material or a III-V semiconductor material. Inorganic materials include silicon carbide (SiC), germanium (Ge), sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), glass or quartz. III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN) materials. The temporary layer 110 may be any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly(p-phenylene benzobisoxazole) and organic materials. Since the temporary layer 110 may be a variety of different materials, the process of forming it on the supporting substrate ST is also different. For example, when the temporary layer 110 is gallium nitride, it may be grown on the supporting substrate ST by deposition. For another example, when the temporary layer 110 is benzocyclobutene, it may be formed on the supporting substrate ST by spin coating. In addition, the thickness of temporary layer 110 can be selected between tens of nanometers to one hundred nanometers, and the application does not further limit this. For example, the thickness of temporary layer 110 in this specific embodiment can be 10 nanometers, or 20 nanometers, or 30 nanometers, or 40 nanometers, or 50 nanometers, or 60 nanometers, or 70 nanometers, or 80 nanometers, or 90 nanometers, or 100 nanometers. In other embodiments, the thickness of temporary layer 110 can also be 15 nanometers, or 25 nanometers, or 35 nanometers, or 45 nanometers, or 55 nanometers, or 65 nanometers, or 75 nanometers, or 85 nanometers, or 95 nanometers.

[0064] Please refer to Figure 6a After the temporary layer 110 is fabricated, a metal wiring process can be performed on the temporary layer 110 to obtain a conductive wiring layer 120. The conductive wiring layer 120 serves as a carrier for electrical connection of the device, providing a guarantee for the normal operation of the subsequent device.

[0065] Specifically, please refer to Figure 3 and 11 , Figure 3 A metal wiring process embodiment provided in this application is provided. Fig.11 For Figure 3 Schematic diagram of the corresponding structural changes. Figure 3 As shown, the metal wiring process may include steps: S302a-S304a.

[0066] Step S302a, forming a metal layer on the temporary layer.

[0067] Step S304a, performing a patterning process on the metal layer to form the conductive wiring layer.

[0068] Please refer to Fig.11 , a metal layer MT is formed on the temporary layer 110. The formation process of the metal layer MT includes but is not limited to evaporation and sputtering. In addition, the thickness of the formed metal layer MT can also be selected and adjusted according to actual needs, and the present application does not make further restrictions on this. After the metal layer MT is formed, a composition process can be performed on the metal layer MT. The composition process is specifically to spin-coat a layer of first photoresist PR1 on the metal layer MT, and then pre-form a photoresist pattern for the first photoresist PR1 through exposure, development, etching and other processes. After obtaining the desired photoresist pattern, the exposed part of the metal layer MT is etched by blocking the remaining photoresist material in the photoresist pattern, thereby completing the composition of the metal layer MT and obtaining the conductive wiring layer 120. Among them, the etching of the metal layer MT can be selected according to the specific material of the metal layer MT, and the selectable etching methods include dry etching or wet etching.

[0069] The metal layer MT material in this specific embodiment is selected from at least one of chromium, aluminum, titanium, platinum, gold, and copper. At the same time, the metal layer MT may include a single-layer metal structure or a multi-layer metal stack structure. Exemplarily, when the metal layer MT is a single-layer metal structure, it may be only chromium, and its thickness should at least be able to ensure the device performance requirements. When the metal layer MT is a multi-layer metal stack structure, it may be any stacking combination of aluminum, titanium, platinum, gold, and copper, or alloys containing these materials are also included. When further considering the push-pull performance and anti-tin down-string capability of the electrode, copper can also be considered as part of the multi-layer metal stack structure, for example, replacing the aluminum layer in the traditional multi-layer metal stack structure with a copper-aluminum alloy.

[0070] In other embodiments, reference may be made to Figure 4 and 12 , Figure 4 Another metal wiring process embodiment provided by this application is as follows: Fig.12 For Figure 4 Schematic diagram of the corresponding structural changes. Figure 4As shown, the metal wiring process may include steps: S302b-S308b.

[0071] Step S302b, forming a sacrificial layer on the temporary layer;

[0072] Step S304b, performing a patterning process on the sacrificial layer to partially expose the temporary layer; wherein the pattern of the exposed temporary layer is the same as the pattern of the conductive wiring layer;

[0073] Step S306b, evaporating a metal layer on the exposed surface of the temporary layer to form the conductive wiring layer;

[0074] Step S308b, removing the sacrificial layer.

[0075] Please refer to Fig.12 , a sacrificial layer 150 is formed on the temporary layer 110, and the sacrificial layer 150 may include materials such as silicon dioxide, silicon nitride, and aluminum oxide. Subsequently, the same composition process as described above is performed on the sacrificial layer 150. The specific composition process can refer to the description in the previous embodiment and will not be repeated here. It should be emphasized that the pattern obtained after the composition process of the sacrificial layer 150 is complementary to the pattern obtained by the composition process of the first photoresist PR1, that is, the pattern of the second photoresist PR2 used to shield the sacrificial layer 150 in this specific embodiment is complementary to the pattern of the first photoresist PR1. Subsequently, a metal layer MT can be evaporated between the patterns of the sacrificial layer 150. Subsequently, the sacrificial layer 150 is removed to obtain the aforementioned conductive wiring layer 120.

[0076] Please refer to Figure 7a After the conductive wiring layer 120 is manufactured, at least three different colors of light-emitting chips can be transferred to the conductive wiring layer 120 for bonding through a mass transfer process. In this specific embodiment, the light-emitting chip can be a mini LED or a micro LED. The three different colors include red, green, and blue light-emitting chips; in other embodiments, red, red, green, and blue light-emitting chips can also be included; in other embodiments, red, green, green, and blue light-emitting chips can also be included; in other embodiments, red, green, blue, and blue light-emitting chips can also be included; in other embodiments, red, green, blue, and white light-emitting chips can also be included. The present application uses a red light chip R, a green light chip G, and a blue light chip B, and the red light chip R, the green light chip G, and the blue light chip B each include two electrodes, and the two electrodes are located on the same side of the chip.

[0077] In one embodiment, Figure 6b and 7bAs shown, the conductive wiring layer 120 may include a first wiring S1 and at least three second wirings S2; the first wiring S1 is electrically connected to the first electrode of each of the light-emitting chips, and the second wiring S2 is correspondingly connected to the second electrode of the light-emitting chip. That is to say, one of the electrodes of the three-color chips of the red light chip R, the green light chip G and the blue light chip B transferred to the conductive wiring layer 120 of the present application is connected to the first wiring S1 to form a common electrode, for example, a common N electrode, and the remaining electrode (P electrode) is each connected to a second wiring S2, thus forming an electrical integration of the red light chip R, the green light chip G and the blue light chip B. This method can improve PPI. Bonding methods include but are not limited to laser bonding, gold-gold bonding, etc.

[0078] Furthermore, the aforementioned integrated device is convenient for electrical connection with an external circuit. Figure 6b and Figure 7b . The conductive wiring layer 120 of the present application may also include a first pad P1 and at least three second pads P2; the first pad P1 is connected to the first wiring S1, and one second pad P2 is correspondingly connected to one second wiring S2. The electrodes of each light-emitting chip are led out by the first pad P1 and the second pad P2, which can reduce the difficulty of subsequent bonding. It can be understood that the case of four light-emitting chips can be described with reference to the principles of the aforementioned embodiments, and the present application does not make further limitations on this.

[0079] After the transfer and bonding of the red light chip R, the green light chip G and the blue light chip B are completed, a light blocking layer 130 can be filled between adjacent light emitting chips. The light blocking layer 130 is mainly a black light absorbing dielectric insulating layer, including but not limited to BM black glue. Figure 8a and Figure 8b The light blocking layer 130 may also be patterned to expose the side of the light emitting chip.

[0080] In one embodiment, it can be helpful to refer to Figure 2 After the step of filling a light blocking layer between adjacent light emitting chips, the method may further include step S5002.

[0081] Step S5002, manufacturing a packaging layer on the surface of each of the light emitting chips and the light blocking layer.

[0082] Auxiliary reference Fig. 9 After the light blocking layer 130 is patterned, the gaps between adjacent light emitting chips can be filled with the encapsulation layer 140. In this specific embodiment, the encapsulation layer 140 can be made of a highly transparent adhesive such as epoxy resin, PI adhesive, silicone, etc. by spin coating or molding, or by vacuum lamination, or by PECVD deposition of SiOx 、SiN x Etc., or Al2O3 may be deposited using ALD process.

[0083] Auxiliary reference Fig.10a and Fig.10b . After the production of the encapsulation layer 140 is completed, the aforementioned temporary layer 110 can be dissociated to expose the conductive wiring layer 120. As an example, the temporary layer 110 includes but is not limited to any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly(p-phenylene benzobisoxazole) and organic materials. These materials are easily removed by laser, solution or mechanical dissociation. Taking the temporary layer 110 as gallium nitride as an example, the gallium nitride can be decomposed by laser stripping to decompose it into nitrogen and metallic gallium. The use of gallium nitride as the temporary layer 110 is more compatible with the existing epitaxial process, and the process is relatively simple. The specific removal methods of other materials are not further described in this application, and can be understood by referring to the prior art.

[0084] In one embodiment, in order to clean the surface of the conductive wiring layer 120 after dissociation, the Figure 2 , the method may further include step S700.

[0085] Step S700, removing the dissociated material remaining on the surface of the conductive wiring layer.

[0086] Exemplarily, a dry method or a wet method may be used to remove the residual dissociated material on the surface of the conductive wiring layer. The dry method or the wet method includes but is not limited to plasma etching and organic solvent dissolution. It should be determined that the removal method of the residual dissociated material is mainly related to the material selection of the temporary layer 110.

[0087] Based on the same inventive concept, the present application also provides a polycrystalline integrated device, which is manufactured using the method for manufacturing a polycrystalline integrated device as described above.

[0088] Compared with traditional solutions, the above-mentioned polycrystalline integrated devices have fewer supporting substrates and are thinner, which can avoid the problem of traditional substrates being easily broken and the problem of traditional polycrystalline integrated devices flipping during testing and solidification. In addition, on the product application side, thinner polycrystalline integrated devices mean that thinner and higher PPI display devices can be produced.

[0089] Specifically, the polycrystalline integrated device of the present application mainly integrates a plurality of light-emitting chips of different colors, and its final structure can be, for example, Fig.10a and Fig.10bAs shown in the figure. Compared with the traditional solution, the polycrystalline integrated device has less supporting substrate and is thinner, which can avoid the problem of traditional substrate being easy to break and the problem of traditional polycrystalline integrated devices flipping during testing and solidification. In addition, on the product application side, thinner polycrystalline integrated devices mean that thinner and higher PPI display devices can be produced.

[0090] Based on the same inventive concept, the present application also provides a display panel, which includes a driving circuit and a polycrystalline integrated device electrically connected to the driving circuit.

[0091] The light-emitting device in the above display panel adopts the aforementioned polycrystalline integrated device, which has less supporting substrate and thinner thickness than the traditional solution, thus avoiding the problem of easy breakage of the traditional substrate and the problem of flipping of the traditional polycrystalline integrated device during testing and solidification. In addition, thinner polycrystalline integrated devices mean that the produced display panel is thinner and has a higher PPI.

[0092] Specifically, the driving circuit of the present application may be an active matrix circuit (AM) or a passive matrix circuit (PM) according to different driving modes. The display panel may be a Mini LED display panel, a Micro LED display panel, etc., or a backlight module applied to a passive light-emitting display device, and the passive light-emitting display device may be a liquid crystal display device.

[0093] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for manufacturing a polycrystalline integrated device, characterized in that: The method comprises: providing a supporting substrate; forming a temporary layer on the supporting substrate; Performing a metal wiring process on the temporary layer to obtain a conductive wiring layer; Transferring at least three light-emitting chips of different colors to the conductive wiring layer respectively, and bonding them to the conductive wiring layer respectively; Filling a light blocking layer between adjacent light emitting chips; and The temporary layer is dissociated to expose the conductive wiring layer.

2. The method for manufacturing a polycrystalline integrated device according to claim 1, characterized in that: The conductive wiring layer includes a first wiring and at least three second wirings; the first wiring is electrically connected to the first electrode of each of the light-emitting chips, and one of the second wirings is correspondingly connected to the second electrode of the light-emitting chip.

3. The method for manufacturing a polycrystalline integrated device according to claim 2, characterized in that: The conductive wiring layer further includes a first pad and at least three second pads; the first pad is connected to the first wiring, and one of the second pads is correspondingly connected to one of the second wirings.

4. The method for manufacturing a polycrystalline integrated device according to claim 1, characterized in that: After the step of filling a light blocking layer between adjacent light emitting chips, the method further includes: A packaging layer is manufactured on the surface of each light emitting chip and the light blocking layer.

5. The method for manufacturing a polycrystalline integrated device according to claim 4, characterized in that: Also includes: The light blocking layer is patterned to expose the side surface of the light emitting chip; wherein the packaging layer is also filled on the side surface of the light emitting chip.

6. The method for manufacturing a polycrystalline integrated device according to claim 1, characterized in that: The metal wiring process includes any of the following methods: Method 1: forming a metal layer on the temporary layer; performing a patterning process on the metal layer to form the conductive wiring layer; Method 2: forming a sacrificial layer on the temporary layer; Performing a patterning process on the sacrificial layer to partially expose the temporary layer; wherein the pattern of the exposed temporary layer is the same as the pattern of the conductive wiring layer; Vapor-depositing a metal layer on the exposed surface of the temporary layer to form the conductive wiring layer; The sacrificial layer is removed.

7. The method for manufacturing a polycrystalline integrated device according to claim 6, characterized in that: The metal layer includes a single-layer metal structure or a multi-layer metal stacking structure.

8. The method for manufacturing a polycrystalline integrated device according to claim 7, characterized in that: The material of the metal layer includes any one of copper, aluminum, titanium, chromium, platinum and gold.

9. The method for manufacturing a polycrystalline integrated device according to claim 1, characterized in that: Also includes: The dissociated material remaining on the surface of the conductive wiring layer is removed.

10. The method for manufacturing a polycrystalline integrated device according to claim 1, characterized in that: The temporary layer includes any one of gallium nitride, benzocyclobutene, polyimide, graphite, boron nitride, poly(p-phenylene benzobisoxazole) and an organic material.

11. A polycrystalline integrated device, characterized in that: The polycrystalline integrated device is manufactured by the method for manufacturing a polycrystalline integrated device according to any one of claims 1 to 10.

12. A display panel, characterized in that: The display panel comprises a driving substrate and the polycrystalline integrated device according to claim 11; wherein the driving substrate is electrically connected to the polycrystalline integrated device.

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