Display device

Abstract

The invention relates to a display device. The display device includes pixels spaced apart from each other by a first spacing distance in a plan view. A transistor is on the base layer. The first organic layer, the second organic layer, and the third organic layer are sequentially on the transistor. A light emitting element is on the third organic layer and is electrically connected to the transistor. An outermost one of the pixels closest to an edge of the base layer is spaced from the edge of the base layer by a distance within a second spacing distance that is less than the first spacing distance. At least one of the second organic layer and the third organic layer covers the first organic layer near the edge of the base layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0113153 filed in the Korean Intellectual Property Office on August 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device and a spliced ​​display device. Background Art

[0004] The spliced ​​display device may be implemented by splicing a plurality of display panels, and when a dead zone exists in each display panel, a boundary between the display panels may be visually recognized and display quality of an image displayed on the spliced ​​display device may be deteriorated. Summary of the invention

[0005] Aspects of embodiments of the present disclosure provide a display device and a spliced ​​display device having improved stability.

[0006] Aspects and features of the embodiments of the present disclosure are not limited to the above-mentioned aspects and features, and other technical aspects and features not described will be clearly understood by those skilled in the art from the following description.

[0007] According to one or more embodiments of the present disclosure, a display device includes pixels spaced apart from each other by a first spacing distance in a plan view. Each of the pixels includes: a transistor on a base layer; a first organic layer on the transistor; a second organic layer on the first organic layer; a third organic layer on the second organic layer; and a light-emitting element on the third organic layer and electrically connected to the transistor. The outermost pixel of the pixel closest to the edge of the base layer is spaced apart from the edge of the base layer by a distance within a second spacing distance, and the second spacing distance is less than the first spacing distance. At least one of the second organic layer and the third organic layer covers the first organic layer near the edge of the base layer.

[0008] In a plan view, the second organic layer or the third organic layer may extend toward an edge of the base layer by a distance equal to or greater than an average thickness of the first organic layer, compared to the first organic layer.

[0009] In a plan view, the organic structure may not be located between the second organic layer or the third organic layer and an edge of the base layer.

[0010] The second organic layer may be directly on the first organic layer, and the third organic layer may be directly on the second organic layer, and the inorganic layer may not be located between the first to third organic layers.

[0011] The display device may further include a first conductive pattern between the first organic layer and the second organic layer, a second conductive pattern between the second organic layer and the third organic layer, and a first pixel electrode on the third organic layer. The light emitting element may be electrically connected to the transistor through the first pixel electrode, the second conductive pattern, and the first conductive pattern, a residue of the first conductive pattern may be located at an edge of the first organic layer, and the residue of the first conductive pattern may be covered by the second organic layer or the third organic layer.

[0012] The display device may further include a second pixel electrode on the third organic layer and an inorganic layer partially covering the second pixel electrode. In a cross-sectional view, the second pixel electrode may overlap the first conductive pattern and may be spaced apart from the first conductive pattern by a distance equal to or greater than an average thickness of the second organic layer or the third organic layer.

[0013] The first organic layer, the second organic layer, and the third organic layer may include the same organic material.

[0014] An edge of the second or third organic layer may contact the first surface of the base layer, and an angle between the edge of the second or third organic layer and the first surface of the base layer may be in the range of about 35 degrees to about 45 degrees.

[0015] Each of the pixels may include a plurality of sub-pixels, each of the plurality of sub-pixels may include a light-emitting element in an emission region of the pixel. Based on the emission region, the pixels may be spaced apart from each other by a first spacing distance, and the outermost pixel may be spaced apart from an edge of the base layer by a distance within a second spacing distance.

[0016] The light emitting element may be a flip chip type micro light emitting diode element.

[0017] In a plan view, the second organic layer may cover the first organic layer.

[0018] In a plan view, the third organic layer may cover the second organic layer.

[0019] In a plan view, the third organic layer may not cover the second organic layer, and an edge of the second organic layer may be exposed by the third organic layer.

[0020] An edge of the first organic layer may be exposed by the second organic layer, and the third organic layer may cover the edge of the first organic layer.

[0021] According to one or more embodiments of the present disclosure, a spliced ​​display device includes a plurality of display devices and seams between the plurality of display devices. A first display device among the plurality of display devices includes pixels spaced apart from each other by a first spacing distance in a plan view. Each of the pixels includes: a transistor on a base layer; a first organic layer on the transistor; a second organic layer on the first organic layer; a third organic layer on the second organic layer; and a light-emitting element on the third organic layer and electrically connected to the transistor. The outermost pixel of the pixel closest to the edge of the base layer is spaced apart from the edge of the base layer by a distance within a second spacing distance, and the second spacing distance is less than the first spacing distance. The second organic layer or the third organic layer covers the first organic layer near the edge of the base layer.

[0022] The light emitting element may be a flip chip type micro light emitting diode element.

[0023] The base layer may be a glass substrate.

[0024] The first display device may further include a pad on the first surface of the base layer, and a side surface line on the first surface, a second surface opposite to the first surface, and one side surface between the first surface and the second surface of the base layer and connected to the pad.

[0025] The first display device may further include a connection line on the second surface of the base layer and a flexible film connected to the connection line through the conductive adhesive member, and the side surface line is connected to the connection line.

[0026] A plurality of display devices may be arranged in a matrix form in M ​​rows and N columns.

[0027] Details of other implementations are included in the detailed description and accompanying drawings.

[0028] The display device and the spliced ​​display device according to the embodiment of the present disclosure may include the first organic layer to the third organic layer (or the first through hole layer to the third through hole layer) between the transistor and the light emitting element, and the inorganic layer may not exist between the first organic layer to the third organic layer. Therefore, defects may not occur in the adhesion between the first organic layer to the third organic layer.

[0029] In addition, the first to third organic layers may have a coating structure. The second organic layer or the third organic layer may cover not only the lower organic layer, but also the lower conductive pattern (or source metal layer) and its residue. Therefore, defects (e.g., short circuits) caused by the conductive pattern (or source metal layer) and its residues can be prevented.

[0030] In addition, the taper angles of the second organic layer and the third organic layer are in the range of about 35 to about 45 degrees, and the second organic layer or the third organic layer can cover the first organic layer by about 9 μm to about 10 μm. Therefore, while realizing the negative dead zone, defects caused by residues can be more surely prevented.

[0031] The effects according to the embodiments are not limited to the contents described above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a plan view showing a display device according to one or more embodiments;

[0034] Figure 2 It is shown Figure 1 An example diagram of pixels of ;

[0035] Figure 3 It is shown Figure 1 A diagram of another example of pixels of;

[0036] Figure 4 It is shown that the Figure 2 and Figure 3 A circuit diagram of an example of a sub-pixel in a pixel;

[0037] Figure 5 It is shown Figure 1 A plan view of an embodiment of a display device;

[0038] Figure 6 It is shown that the Figure 5 A diagram showing a connection relationship between pixel circuits and stages in a display device;

[0039] Figure 7 It is shown Figure 1 A cross-sectional view of an embodiment of a display device;

[0040] Figure 8 It is shown Figure 1 A cross-sectional view of an embodiment of a display device;

[0041] Fig. 9 It is shown Figure 1 A cross-sectional view of a comparative example of a display device;

[0042] Fig.10 and Fig.11 It is shown Figure 1 A cross-sectional view of another embodiment of a display device;

[0043] Fig.12 is a plan view showing a spliced ​​display device including a plurality of display devices according to one or more embodiments;

[0044] Fig.13 yes Fig.12 A magnified view of area AA;

[0045] Fig.14 It is shown along Fig.13 A cross-sectional view of an example of a spliced ​​display device taken along line J-J';

[0046] Fig.15 yes Fig.12 An enlarged view of area BB;

[0047] Fig.16 It is shown along Fig.15 A cross-sectional view of an example of a spliced ​​display device taken along line N-N'; and

[0048] Fig.17 is a block diagram illustrating a tiled display device according to one or more embodiments. DETAILED DESCRIPTION

[0049] The present disclosure can be modified in various ways and have various forms. Therefore, the embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents and substitutions within the spirit and technical scope of the present disclosure.

[0050] The terms "first", "second", etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the scope of the present disclosure. In the following description, a singular expression includes a plural expression unless the context clearly dictates otherwise.

[0051] It should be understood that in the present application, the terms "including", "having" and the like are used to specify the presence of features, quantities, steps, operations, components, parts or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. In addition, when a portion of a layer, a layer, a region, a plate, etc. is referred to as being "on" another portion, it includes not only the case where the portion is "directly on" another portion, but also the case where there is another portion between the portion and the other portion. In addition, in the present disclosure, when a portion of a layer, a layer, a region, a plate, etc. is formed on another portion, the formation direction is not limited to the upper direction, but includes forming the portion on the side surface or in the lower direction. On the contrary, when a portion of a layer, a layer, a region, a plate, etc. is formed "under" another portion, this includes not only the case where the portion is "directly "under" another portion, but also the case where there is another portion between the portion and the other portion.

[0052] For purposes of the present disclosure, expressions such as "at least one of," "one of," or "selected from," when preceding an element of a list, modify the elements of the entire list without modifying the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, XZ, YZ, and ZZ), or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0053] Aspects and features of the embodiments of the present disclosure and methods for implementing them will become apparent with reference to the embodiments described in detail later together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below and may be implemented in various different forms. In the following description, the case where one part is connected to another part includes the case where they are electrically connected to each other and another element is inserted between them and the case where they are directly connected to each other. In one or more embodiments of the present disclosure, the term "connection" between two configurations may mean the use of both electrical connection and physical connection inclusively.

[0054] Hereinafter, a display device according to one or more embodiments of the present disclosure is described with reference to the drawings related to the embodiments of the present disclosure.

[0055] Figure 1 is a plan view showing a display device according to one or more embodiments. Figure 2 It is shown Figure 1 Figure 3 is an example of a pixel. Figure 3 It is shown Figure 1 FIG. 1 is another example of a pixel of FIG.

[0056] refer to Figure 1 The display device 10 (or display panel) can be a device for displaying images and can be used as a display screen for various products, such as not only portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs), but also televisions, notebook computers, monitors, billboards, and Internet of Things (IoT) devices.

[0057] The display device 10 may have a rectangular shape in a plane and have a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. The corner where the long side extending in the first direction DR1 and the short side extending in the second direction DR2 intersect may be formed to be rounded to have an appropriate curvature (e.g., a predetermined curvature), or may be formed to be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed to be another polygon, a circle, or an ellipse. The display device 10 may be formed to be flat, but is not limited thereto. The display device 10 (or the planar shape of the display device 10) may have an atypical shape. For example, the display device 10 may include a curved portion formed at the left and right ends and having a constant curvature or a variable curvature. In addition, the display device 10 may be flexibly formed to be bent, curved, bent, folded, and / or curled. In an embodiment, the third direction DR3 may be the thickness direction of the display device 10.

[0058] The display device 10 may include pixels PX to display an image. The pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2, but are not limited thereto. For example, the pixels PX may be arranged along rows and columns of the matrix in the first direction DR1 and the second direction DR2. In addition, the display device 10 may further include a gate line (or scan line) extending in the first direction DR1 and a data line extending in the second direction DR2.

[0059] like Figure 2 and Figure 3 As shown in FIG. 1 , each of the pixels PX may include sub-pixels SPX1 to SPX3 . Figure 2 and Figure 3It is illustrated that each of the pixels PX includes three sub-pixels SPX1 to SPX3 , for example, a first sub-pixel SPX1 , a second sub-pixel SPX2 , and a third sub-pixel SPX3 , but the present disclosure is not limited thereto.

[0060] Each of the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may be connected to any one of the data lines and at least one of the gate lines.

[0061] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have a rectangular, square, or diamond-shaped plane shape. Figure 2 As shown in FIG. 1 , each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. Figure 3 As shown in FIG. 1 , each of the first subpixel SPX1 , the second subpixel SPX2 , and the third subpixel SPX3 may have a planar shape of a square including sides having the same length in the first direction DR1 and the second direction DR2 .

[0062] like Figure 2 As shown in , the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be arranged along the first direction DR1. Alternatively, any one of the second sub-pixel SPX2 and the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged along the first direction DR1, and the other of the second sub-pixel SPX2 and the third sub-pixel SPX3 and the first sub-pixel SPX1 may be arranged along the second direction DR2. For example, as Figure 3 As shown in FIG. 1 , the first subpixel SPX1 and the second subpixel SPX2 may be arranged along the first direction DR1 , and the first subpixel SPX1 and the third subpixel SPX3 may be arranged along the second direction DR2 .

[0063] Alternatively, the first subpixel SPX1 or the third subpixel SPX3 and the second subpixel SPX2 may be arranged along the first direction DR1, and the other of the first subpixel SPX1 and the third subpixel SPX3 and the second subpixel SPX2 may be arranged along the second direction DR2. Alternatively, the first subpixel SPX1 or the second subpixel SPX2 and the third subpixel SPX3 may be arranged along the first direction DR1, and the other of the first subpixel SPX1 and the second subpixel SPX2 and the third subpixel SPX3 may be arranged along the second direction DR2.

[0064] The first sub-pixel SPX1 may emit a first color light, the second sub-pixel SPX2 may emit a second color light, and the third sub-pixel SPX3 may emit a third color light. Here, the first color light may be light of a red wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a blue wavelength band. The red wavelength band may be a wavelength band of about 600nm to 750nm, the green wavelength band may be a wavelength band of about 480nm to 560nm, and the blue wavelength band may be a wavelength band of about 370nm to 460nm, but the present disclosure is not limited thereto.

[0065] Each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may include an inorganic light emitting element as a light emitting element that emits light, the inorganic light emitting element including an inorganic semiconductor. For example, the inorganic light emitting element may be a flip chip type micro light emitting diode (LED), but the present disclosure is not limited thereto.

[0066] like Figure 2 and Figure 3 As shown in , the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be substantially the same, but the present disclosure is not limited thereto. At least one of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from the other areas. Alternatively, any two of the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be substantially the same, and the other area may be different from the two areas. Alternatively, the area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 may be different from each other.

[0067] Figure 4 It is shown that the Figure 2 and Figure 3 A circuit diagram of an example of a sub-pixel in a pixel. Figure 4 The sub-pixel SPX shown in FIG. 1 may be included in Figure 2 and Figure 3 The sub-pixels SPX1 to SPX3 may have structures (or circuits) substantially the same as or similar to each other.

[0068] refer to Figure 4 , the sub-pixel SPX may be connected to the gate line GL, the data line DL, the first power line PL1 and the second power line PL2. In addition, the sub-pixel SPX may be further connected to at least another power line and / or a signal line.

[0069] A gate signal (or scan signal) may be provided to the gate line GL, a data signal may be provided to the data line DL, a voltage of the first power VDD may be applied to the first power line PL1, and a voltage of the second power VSS may be provided to the second power line PL2. The first power VDD and the second power VSS may have different potentials.

[0070] The sub-pixel SPX may include a light emitting element ED for generating light of brightness corresponding to each data signal. In addition, the sub-pixel SPX may further include a pixel circuit PC for driving the light emitting element ED.

[0071] The pixel circuit PC may be electrically connected to the gate line GL and the data line DL, and may be electrically connected between the first power line PL1 and the light emitting element ED.

[0072] The pixel circuit PC may include at least one transistor and a capacitor Cst. For example, the pixel circuit PC may include a first transistor M1, a second transistor M2, and a capacitor Cst.

[0073] The first transistor M1 may be connected between the first power line PL1 and the second node N2. The second node N2 may be a node to which the pixel circuit PC and the light emitting element ED are connected. For example, the second node N2 may be a node at which one electrode (e.g., a source electrode) of the first transistor M1 and the light emitting element ED are electrically connected to each other. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control a driving current provided to the light emitting element ED in response to a voltage of the first node N1. For example, the first transistor M1 may be a driving transistor of the sub-pixel SPX.

[0074] The second transistor M2 may be connected between the data line DL and the first node N1. In addition, a gate electrode of the second transistor M2 may be connected to the gate line GL. When a gate signal of a gate-on voltage (e.g., a logic high voltage or a high-level voltage) is provided from the gate line GL, the second transistor M2 may be turned on to connect the data line DL and the first node N1.

[0075] For each frame period, a data signal of the corresponding frame can be provided to the data line DL, and during the period of the gate signal providing the gate-on voltage, the data signal can be transmitted to the first node N1 through the second transistor M2. For example, the second transistor M2 can be a switching transistor for transmitting each data signal to the inside of the sub-pixel SPX.

[0076] A first electrode of the capacitor Cst may be connected to the first node N1, and a second electrode of the capacitor Cst may be connected to the second node N2. The capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period.

[0077] exist Figure 4 In the embodiment, both the first transistor M1 and the second transistor M2 included in the pixel circuit PC are n-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor M1 and the second transistor M2 may be changed to a p-type transistor. According to one or more embodiments, the structure and driving method of the sub-pixel SPX may be variously changed.

[0078] In addition, the pixel circuit PC may also include other circuit elements, such as an initialization transistor (or a sensing transistor) for initializing the anode electrode of the light-emitting element ED, a compensation transistor for compensating for the threshold voltage of the first transistor M1, an initialization transistor for initializing the voltage of the first node N1, an emission control transistor for controlling the period of providing a driving current to the light-emitting element ED, and / or a boost capacitor for boosting the voltage of the first node N1.

[0079] The light emitting element ED may emit light having a brightness corresponding to a driving current provided by the pixel circuit PC. The light emitting element ED may be connected between the first transistor M1 and the second power line PL2. The first electrode of the light emitting element ED may be connected to one electrode (or the second node N2) of the first transistor M1, and the second electrode of the light emitting element ED may be connected to the second power line PL2. Here, the first electrode of the light emitting element ED may be an anode electrode, and the second electrode of the light emitting element ED may be a cathode electrode. The light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the light emitting element ED may be a micro light emitting diode (LED) formed of an inorganic semiconductor, but is not limited thereto.

[0080] exist Figure 4 In the embodiment, the sub-pixel SPX includes only one light-emitting element ED, but the present disclosure is not limited thereto. For example, the sub-pixel SPX may also include at least one light-emitting element connected in parallel to the light-emitting element ED. As another example, the sub-pixel SPX may also include at least one light-emitting element connected in series to the light-emitting element ED. The number, type and / or structure of the light-emitting elements ED constituting the effective light source of the sub-pixel SPX may be changed according to one or more embodiments.

[0081] Figure 5 It is shown Figure 1 A plan view of an embodiment of a display device. Figure 6 It is shown that the Figure 5 A diagram showing a connection relationship between pixel circuits and stages in a display device of FIG. A plurality of stages may be configured with at least one gate driver (or scan driver).

[0082] refer to Figures 1 to 6, the display device 10 may include pixels PX. The pixels PX may be spaced apart from each other by a first horizontal spacing distance GH1 (or a first spacing distance). For example, based on the emission area EA, the pixels PX may be spaced apart by a first horizontal spacing distance GH1 in the first direction DR1. In one or more embodiments, the pixels PX located at the outermost portion of the display device 10 (i.e., the outermost pixels PX) may be spaced apart from the edge EDGE of the display device 10 (or substrate) by a distance within a minimum distance GHS1 (or a second spacing distance). The minimum distance GHS1 may be less than the first horizontal spacing distance GH1. For example, the minimum distance GHS1 may be less than half of the first horizontal spacing distance GH1. That is, the display device 10 may have a negative dead zone (i.e., the dead zone is less than the pixel distance). Refer to later Fig.13 The minimum distance GHS1 and the first horizontal separation distance GH1 are described.

[0083] The pixel PX may include first to third sub-pixels SPX1 to SPX3 .

[0084] The first sub-pixel SPX1 may include a first light emitting element ED1 and a first pixel circuit PC1, and the first pixel circuit PC1 may provide a driving current to the first light emitting element ED1. The first pixel circuit PC1 may be located in the second direction DR2 relative to the first light emitting element ED1, and the first pixel circuit PC1 may be electrically connected to the first light emitting element ED1. The second sub-pixel SPX2 may include a second light emitting element ED2 and a second pixel circuit PC2, and the second pixel circuit PC2 may provide a driving current to the second light emitting element ED2. The second pixel circuit PC2 may be located in the second direction DR2 relative to the second light emitting element ED2, and the second pixel circuit PC2 may be electrically connected to the second light emitting element ED2. The third sub-pixel SPX3 may include a third light emitting element ED3 and a third pixel circuit PC3, and the third pixel circuit PC3 may provide a driving current to the third light emitting element ED3. The third pixel circuit PC3 may be located in the second direction DR2 relative to the third light emitting element ED3, and the third pixel circuit PC3 may be electrically connected to the third light emitting element ED3.

[0085] According to one or more embodiments, each of the first to third sub-pixels SPX1 to SPX3 may include two light-emitting elements. For example, each of the first to third sub-pixels SPX1 to SPX3 may include a main light-emitting element and a repair light-emitting element, but is not limited thereto. As another example, each of the first to third sub-pixels SPX1 to SPX3 may include three or more light-emitting elements. Although reference will be made later Figure 7 Describe, but Figure 5The first to third light emitting elements ED1 to ED3 shown in may refer to electrodes (eg, anode electrodes and cathode electrodes) of each of the first to third light emitting elements ED1 to ED3.

[0086] Based on the light-emitting elements ED1 to ED3, the pixels PX can be arranged to have a uniform pixel pitch. The light-emitting elements ED1 to ED3 can be arranged along a plurality of pixel rows. For example, the light-emitting elements ED1 to ED3 can be arranged along the k-th pixel row PROWk to the (k+5)-th pixel row PROWk+5 (where k is a positive integer). The pixel circuits PC1 to PC3 can be arranged along a plurality of circuit rows. The pixel circuits PC1 to PC3 can be arranged along the k-th circuit row CROWk to the (k+5)-th circuit row CROWk+5.

[0087] The kth pixel row PROWk may be adjacent to the kth circuit row CROWk in a direction opposite to the second direction DR2, and the (k+1)th pixel row PROWk+1 may be adjacent to the (k+1)th circuit row CROWk+1 in the second direction DR2. The kth circuit row CROWk and the (k+1)th circuit row CROWk+1 may be disposed between the kth pixel row PROWk and the (k+1)th pixel row PROWk+1. Similarly, the (k+2)th pixel row PROWk+2 may be adjacent to the (k+2)th circuit row CROWk+2 in a direction opposite to the second direction DR2, and the (k+3)th pixel row PROWk+3 may be adjacent to the (k+3)th circuit row CROWk+3 in the second direction DR2. The (k+2)th circuit row CROWk+2 and the (k+3)th circuit row CROWk+3 may be disposed between the (k+2)th pixel row PROWk+2 and the (k+3)th pixel row PROWk+3. Similarly, the (k+4)th pixel row PROWk+4 may be adjacent to the (k+4)th circuit row CROWk+4 in a direction opposite to the second direction DR2, and the (k+5)th pixel row PROWk+5 may be adjacent to the (k+5)th circuit row CROWk+5 in the second direction DR2. The (k+4)th circuit row CROWk+4 and the (k+5)th circuit row CROWk+5 may be disposed between the (k+4)th pixel row PROWk+4 and the (k+5)th pixel row PROWk+5.

[0088] The k-th stage STGk may be disposed on an upper side of the k-th circuit row CROWk and the k-th pixel row PROWk. The k-th stage STGk may provide a gate signal to the k-th gate line GLk connected to the pixel circuits PC1, PC2, and PC3 of the k-th circuit row CROWk. The k-th stage STGk may be connected to the k-th gate line GLk through a connection line CL. For example, the k-th stage STGk may be connected to the k-th gate line GLk through a first connection line CL1 extending in a first direction DR1 and a second connection line CL2 extending in a second direction DR2.

[0089] The (k+1)th stage STGk+1 and the (k+2)th stage STGk+2 may be disposed between the (k+1)th pixel row PROWk+1 and the (k+2)th pixel row PROWk+2. The (k+1)th stage STGk+1 may be disposed on the lower sides of the (k+1)th circuit row CROWk+1 and the (k+1)th pixel row PROWk+1. The (k+1)th stage STGk+1 may provide a gate signal to the (k+1)th gate line GLk+1 of the pixel circuit PC connected to the (k+1)th circuit row CROWk+1. The (k+1)th stage STGk+1 may be connected to the (k+1)th gate line GLk+1 through a connection line CL.

[0090] The (k+2)th stage STGk+2 may be disposed on the upper side of the (k+2)th circuit row CROWk+2 and the (k+2)th pixel row PROWk+2. The (k+2)th stage STGk+2 may provide a gate signal to the (k+2)th gate line GLk+2 of the pixel circuit PC connected to the (k+2)th circuit row CROWk+2. The (k+2)th stage STGk+2 may be connected to the (k+2)th gate line GLk+2 through a connection line CL.

[0091] The (k+3)th stage STGk+3 and the (k+4)th stage STGk+4 may be disposed between the (k+3)th pixel row PROWk+3 and the (k+4)th pixel row PROWk+4. The (k+3)th stage STGk+3 may be disposed on the lower sides of the (k+3)th circuit row CROWk+3 and the (k+3)th pixel row PROWk+3. The (k+3)th stage STGk+3 may provide a gate signal to the (k+3)th gate line GLk+3 of the pixel circuit PC connected to the (k+3)th circuit row CROWk+3. The (k+3)th stage STGk+3 may be connected to the (k+3)th gate line GLk+3 through a connection line CL.

[0092] The (k+4)th stage STGk+4 may be disposed on the upper side of the (k+4)th circuit row CROWk+4 and the (k+4)th pixel row PROWk+4. The (k+4)th stage STGk+4 may provide a gate signal to the (k+4)th gate line GLk+4 of the pixel circuit PC connected to the (k+4)th circuit row CROWk+4. The (k+4)th stage STGk+4 may be connected to the (k+4)th gate line GLk+4 through a connection line CL.

[0093] The (k+5)th stage STGk+5 may be disposed on the lower sides of the (k+5)th circuit row CROWk+5 and the (k+5)th pixel row PROWk+5. The (k+5)th stage STGk+5 may provide a gate signal to the (k+5)th gate line GLk+5 of the pixel circuit PC connected to the (k+5)th circuit row CROWk+5. The (k+5)th stage STGk+5 may be connected to the (k+5)th gate line GLk+5 through a connection line CL.

[0094] The data lines DL may include first to third data lines DL1 to DL3. The first data line DL1 may provide a data voltage to a plurality of first pixel circuits PC1 disposed in the same column. The second data line DL2 may provide a data voltage to a plurality of second pixel circuits PC2 disposed in the same column. The third data line DL3 may provide a data voltage to a plurality of third pixel circuits PC3 disposed in the same column.

[0095] Figure 7 It is shown Figure 1 A cross-sectional view of an embodiment of a display device. Figure 7 , a cross section of the display device 10 is schematically shown based on a sub-pixel SPX.

[0096] refer to Figures 1 to 7 , the sub-pixel SPX (of the display device 10 or the display panel) may include a substrate SUB (or base layer), a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a gate layer GTL, an interlayer insulating layer ILD, a first source metal layer SDL1, a first through-hole layer VIA1, a second source metal layer SDL2, a second through-hole layer VIA2, a third source metal layer SDL3, a third through-hole layer VIA3, a pixel electrode layer, a fourth through-hole layer VIA4 and a fourth protective layer PVX4 (or protective layer).

[0097] The substrate SUB may be a base substrate or a base member for supporting the display device 10. The substrate SUB may be a flexible substrate that can be bent, folded, curled, etc. In this case, the substrate SUB may include an insulating material such as a polymer resin such as polyimide (PI). The substrate SUB may have a single-layer structure or a multi-layer structure. In addition, the substrate SUB (or base layer) may be a glass substrate.

[0098] The buffer layer BF may be disposed on one surface of the substrate SUB. The buffer layer BF may prevent the penetration of air or moisture. The buffer layer BF may be an insulating layer including an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x The buffer layer BF may be omitted according to the material of the substrate SUB, process conditions, etc.

[0099] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may include a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, and / or amorphous silicon, or may include an oxide semiconductor.

[0100] The active layer ACTL may include a channel CH of the transistor TFT, a first electrode SE, and a second electrode DE. Here, the transistor TFT may be included in Figure 4 The transistor in the pixel circuit PC of the transistor TFT may be a first transistor M1, and for example, the transistor TFT may be a first transistor M1. The channel CH of the transistor TFT may be a region overlapping with the gate electrode GE of the transistor TFT in the third direction DR3 which is the thickness direction of the substrate SUB. The first electrode SE of the transistor TFT may be disposed on one side of the channel CH, and the second electrode DE may be disposed on the other side of the channel CH. The first electrode SE and the second electrode DE of the transistor TFT may be a region not overlapping with the gate electrode GE in the third direction DR3. The channel CH of the transistor TFT may be a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. The first electrode SE and the second electrode DE of the transistor TFT may be a semiconductor pattern doped with impurities.

[0101] A gate insulating layer GI may be disposed on the active layer ACTL. The gate insulating layer GI may be an insulating layer including an inorganic material.

[0102] The gate layer GTL may be disposed on the gate insulating layer GI. The gate layer GTL may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag) and / or alloys thereof. The gate layer GTL may be formed as a single layer or multiple layers.

[0103] The gate layer GTL may include a gate electrode GE of the transistor TFT and a first capacitor electrode CE1 .

[0104] An interlayer insulating layer ILD may be disposed on the gate layer GTL. The interlayer insulating layer ILD may be an insulating layer including an inorganic material.

[0105] The first source metal layer SDL1 (or the first conductive pattern) may be disposed on the interlayer insulating layer ILD. The first source metal layer SDL1 may include a conductive material and may be formed as a single layer or a multi-layer.

[0106] The first source metal layer SDL1 may include a connection electrode CCE, a second capacitor electrode CE2, and a first connection pattern CP1 (or a bridge pattern). The connection electrode CCE may be connected to the first electrode SE (or the second electrode DE) of the transistor TFT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI. The second capacitor electrode CE2 may configure a capacitor Cst with the first capacitor electrode CE1 by overlapping the first capacitor electrode CE1 in the third direction DR3 with the interlayer insulating layer ILD therebetween. The first connection pattern CP1 may be connected to the second electrode DE (or the first electrode SE) of the transistor TFT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0107] The first via layer VIA1 (e.g., a first planarization layer or a first organic layer) may be disposed on the first source metal layer SDL1. The first via layer VIA1 may flatten the step difference caused by the active layer ACTL, the gate layer GTL, and the first source metal layer SDL1. The first via layer VIA1 may be an insulating layer including an organic material. For example, the organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0108] The second source metal layer SDL2 (or the second conductive pattern) may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include a conductive material and may be formed as a single layer or a multi-layer.

[0109] The second source metal layer SDL2 may include an anode connection line ACL and a first power line PL1. The anode connection line ACL may be connected to the connection electrode CCE through a contact hole passing through the first via layer VIA1. The first power line PL1 may be connected to the first connection pattern CP1 through a contact hole passing through the first via layer VIA1.

[0110] According to one or more embodiments, the second source metal layer SDL2 may further include other lines. For example, the other lines may include a data line DL, a second power line PL2, or may be electrically connected to the data line DL, the second power line PL2, and the like.

[0111] According to one or more embodiments, the first via layer VIA1 may be omitted. In this case, the connection electrode CCE may be included in the anode connection line ACL or may be omitted. For example, the anode connection line ACL may be connected to the first electrode SE of the transistor TFT through a contact hole passing through the interlayer insulating layer ILD and the gate insulating layer GI.

[0112] The second via layer VIA2 (or second organic layer) may be disposed on the second source metal layer SDL2. The second via layer VIA2 may be an insulating layer including an organic material. The second via layer VIA2 may include the same material as the first via layer VIA1.

[0113] The third source metal layer SDL3 (or the third conductive pattern) may be disposed on the second via layer VIA2. The third source metal layer SDL3 may include a conductive material and may be formed as a single layer or a multi-layer.

[0114] The third source metal layer SDL3 may include an anode connection electrode ACE (or a bridge electrode). The anode connection electrode ACE may be connected to the anode connection line ACL through a contact hole passing through the second via layer VIA2.

[0115] The third via layer VIA3 (or third organic layer) may be disposed on the third source metal layer SDL3. The third via layer VIA3 may be an insulating layer including an organic material. The third via layer VIA3 may include the same material as the first via layer VIA1 and / or the second via layer VIA2.

[0116] The pixel electrode layer may be disposed on the third via layer VIA3. The pixel electrode layer may include a pixel electrode AND (or a first pixel electrode) and a common electrode COM (or a second pixel electrode). The pixel electrode AND may be referred to as an anode electrode, and the common electrode COM may be referred to as a cathode electrode.

[0117] The pixel electrode AND can be connected to the anode connection electrode ACE through a contact hole passing through the third through-hole layer VIA3. In this way, the pixel electrode AND can be electrically connected to the first electrode SE of the transistor TFT. Therefore, the pixel voltage (or driving current) controlled by the transistor TFT can be applied to the pixel electrode AND.

[0118] Similar to the pixel electrode AND, the common electrode COM may be electrically connected to a power line (eg, second power line PL2 ) through a contact hole passing through the third via layer VIA3 (and the second via layer VIA2 ). In this way, a power voltage of the power line may be applied to the common electrode COM.

[0119] The pixel electrode AND and the common electrode COM may include a metal material having high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0120] A fourth through hole layer VIA4 (eg, a fourth organic layer, a bank, or a pixel defining layer) may be disposed on the third through hole layer VIA3. The fourth through hole layer VIA4 may be an insulating layer including an organic material. The fourth through hole layer VIA4 may include an opening, and at least a portion of the pixel electrode AND and the common electrode COM may be exposed through the opening.

[0121] The fourth protective layer PVX4 (or inorganic layer) may be disposed on the fourth through hole layer VIA4. The fourth protective layer PVX4 may partially cover the pixel electrode AND and the common electrode COM. For example, the fourth protective layer PVX4 may cover the edge of the pixel electrode AND and the edge of the common electrode COM. The fourth protective layer PVX4 may be an insulating layer including an inorganic material.

[0122] In one or more embodiments, the protective layer or inorganic layer (or the insulating layer or inorganic layer including an inorganic material) may not be disposed between the first through-hole layer VIA1 to the fourth through-hole layer VIA4. For example, the inorganic layer may not be disposed between the first through-hole layer VIA1 and the second through-hole layer VIA2, and the second through-hole layer VIA2 may be directly disposed on the first through-hole layer VIA1 and may contact the first through-hole layer VIA1. When the inorganic layer is disposed between the first through-hole layer VIA1 and the second through-hole layer VIA2, defects may occur in the adhesion between the first through-hole layer VIA1 and the second through-hole layer VIA2. For example, a phenomenon in which the second through-hole layer VIA2 is lifted from the first through-hole layer VIA1 may occur. In other words, when the inorganic layer is not disposed between the first through-hole layer VIA1 and the second through-hole layer VIA2, the first through-hole layer VIA1 and the second through-hole layer VIA2 may be stably attached to each other. In addition, since the process (and mask) for forming the inorganic layer is not included, the manufacturing cost of the display device 10 can be reduced. Similarly, the inorganic layer may not be disposed between the second via layer VIA2 and the third via layer VIA3 and between the third via layer VIA3 and the fourth via layer VIA4. That is, the third via layer VIA3 may be directly disposed on the second via layer VIA2, and the fourth via layer VIA4 may be directly disposed on the third via layer VIA3.

[0123] The light emitting element ED may be disposed in the opening of the fourth via layer VIA4 (and the fourth protective layer PVX4 ). The light emitting element ED may be disposed on the pixel electrode AND and the common electrode COM that are not covered by the fourth protective layer PVX4 (or exposed by the fourth protective layer PVX4 ).

[0124] For example, the light emitting element ED may be a flip chip type micro LED. The light emitting element ED may be formed of an inorganic material such as GaN. Each of the lengths in the first direction DR1, the second direction DR2, and the third direction DR3 of the light emitting element ED may be several micrometers to hundreds of micrometers. For example, each of the lengths in the first direction DR1, the second direction DR2, and the third direction DR3 of the light emitting element ED may be about 100 μm or less.

[0125] exist Figure 7 In the embodiment, the first power line PL1 and other lines (eg, data line DL) are disposed in the second source metal layer SDL2, but the present disclosure is not limited thereto. For example, the line including the first power line PL1 may be disposed in at least one of the gate layer GTL, the first source metal layer SDL1, and the third source metal layer SDL3.

[0126] Figure 8 It is shown Figure 1 A cross-sectional view of an embodiment of a display device. Figure 8 , a cross section of an outer portion of the display device 10 adjacent to the edge EDGE is briefly shown based on the first through hole layer VIA1 to the third through hole layer VIA3. The edge EDGE may be Figure 1 One side (e.g., the left side, the lower side, or the right side) of the display device 10.

[0127] refer to Figure 7 and Figure 8 , because the reference Figure 7 The substrate SUB and the first source metal layer SDL1 to the fourth protective layer PVX4 are described, so the overlapping description is not repeated. Figure 8 In, omitted Figure 7 The configuration between the substrate SUB and the first source metal layer SDL1 (eg, transistor TFT, interlayer insulating layer ILD, etc.), but it should be understood that Figure 8 Implementation methods include Figure 7 Configuration.

[0128] In one or more embodiments, the first to third via layers VIA1 to VIA3 may have a clad structure, that is, the third via layer VIA3 or the second via layer VIA2 may clad or cover a lower configuration (eg, the first via layer VIA1).

[0129] For example, Figure 8As shown in , in the outer part of the display device 10, the second via layer VIA2 may cover the first via layer VIA1, and the second via layer VIA2 may contact the substrate SUB (or the configuration under the first via layer VIA1). The second via layer VIA2 may cover the first via layer VIA1 throughout the entire display device 10.

[0130] For reference, in a process of forming (e.g., patterning) a second source metal layer SDL2 (e.g., first power line PL1) on a first via layer VIA1, near an edge of the first via layer VIA1 (i.e., near a point where the first via layer VIA1 starts to tilt relative to a reference), a portion of the second source metal layer SDL2 may not be properly etched or removed, and a portion of the second source metal layer SDL2 may appear or exist as a residue RES. The residue RES may cause defects (e.g., short circuits). The second via layer VIA2 may cover the residue RES of the second source metal layer SDL2, and defects caused by the residue RES may be prevented.

[0131] In one or more embodiments, in a plan view, the second via layer VIA2 may extend toward an edge EDGE of the substrate SUB by a length equal to or greater than the average thickness of the first via layer VIA1 (or the second via layer VIA2) (e.g., the thickness in the third direction DR3) compared to the first via layer VIA1. For example, the average thickness of the first via layer VIA1 (or each of the first to third via layers VIA1 to VIA3) in the third direction DR3 may be approximately 5 μm, and the distance D1 by which the second via layer VIA2 protrudes beyond the first via layer VIA1 in a direction opposite to the first direction DR1 may be equal to or greater than approximately 5 μm. In this case, the residue RES and the upper structure (i.e., the structure on the second via layer VIA2) may be sufficiently electrically separated, and thus defects caused by the residue RES may be prevented. As the distance D1 increases, defects caused by the residue RES may be more safely prevented. However, considering the reference Figure 5 The minimum distance GHS1 described above and the distance D1 may be limited. For example, when the minimum distance GHS1 is about 20 μm to about 30 μm, the distance D1 may be about 9 μm to about 10 μm.

[0132] In one or more embodiments, an edge portion of the second via layer VIA2 may be in contact with the first surface of the substrate SUB (or base layer), and an angle formed by the edge portion of the second via layer VIA2 and the first surface of the substrate SUB may be equal to or less than about 47 degrees. That is, the taper angle θ2 of the second via layer VIA2 may be equal to or less than about 47 degrees. In this case, an opening may not appear in the third source metal layer SDL3 on the second via layer VIA2 (specifically, the inclined surface of the second via layer VIA2). In addition, as the taper angle θ2 of the second via layer VIA2 decreases, the residue RES may not appear. Taking into account Figure 5 The minimum distance GHS1 of the second via layer VIA2 may be about 35 degrees to about 45 degrees. The taper angle θ1 of the first via layer VIA1 may be equal to or similar to the taper angle θ2 of the second via layer VIA2, but is not limited thereto.

[0133] Similar to the second via layer VIA2, the third via layer VIA3 may cover the second via layer VIA2, and the third via layer VIA3 may contact the substrate SUB (or the configuration under the first via layer VIA1). The third via layer VIA3 may cover the second via layer VIA2 throughout the entire display device 10. The third via layer VIA3 may cover the residue RES of the third source metal layer SDL3, and defects caused by the residue RES may be prevented.

[0134] In one or more embodiments, in a plan view, the third via layer VIA3 may extend toward the edge EDGE of the substrate SUB by a length equal to or greater than the average thickness of the third via layer VIA3 compared to the second via layer VIA2. For example, the third via layer VIA3 may protrude beyond the second via layer VIA2 by a distance D2 equal to or greater than 5 μm in a direction opposite to the first direction DR1. For example, considering the minimum distance GHS1 (reference Figure 5 ) may be about 9 μm to about 10 μm.

[0135] In one or more embodiments, an edge portion of the third via layer VIA3 may contact the first surface of the substrate SUB (or base layer), and an angle formed by the edge portion of the third via layer VIA3 and the first surface of the substrate SUB may be equal to or less than about 47 degrees. That is, the taper angle θ3 of the third via layer VIA3 may be equal to or less than about 47 degrees. Considering Figure 5 The minimum distance GHS1 , the taper angle θ3 of the third via layer VIA3 may be about 35 degrees to about 45 degrees.

[0136] The second power line PL2 (or common electrode COM) may be disposed on the third through-hole layer VIA3. The second power line PL2 (or common electrode COM) may be completely disposed on the substrate SUB to reduce resistance. In this case, in the outer portion of the display device 10, the second power line PL2 (or common electrode COM) may overlap with the second source metal layer SDL2 (or first power line PL1). The second source metal layer SDL2 and the second power line PL2 (or common electrode COM) may be separated by a distance D0, which is equal to or greater than the average thickness of the second through-hole layer VIA2 or the third through-hole layer VIA3. Therefore, a short circuit may not occur between the second source metal layer SDL2 and the second power line PL2 (or common electrode COM). Similarly, the residue RES of the second source metal layer SDL2 may also be separated from the second power line PL2 (or common electrode COM) by a distance D0 equal to or greater than the average thickness of the second through-hole layer VIA2 or the third through-hole layer VIA3.

[0137] The third source metal layer SDL3 and the second power line PL2 (or the common electrode COM) may be separated by the average thickness of the third through hole layer VIA3. Therefore, a short circuit may not occur between the third source metal layer SDL3 and the second power line PL2 (or the common electrode COM). Similarly, the residue RES of the third source metal layer SDL3 may also be separated from the second power line PL2 (or the common electrode COM) by the average thickness of the third through hole layer VIA3.

[0138] The fourth protection layer PVX4 may cover the second power line PL2 (or the common electrode COM).

[0139] In one or more embodiments, another organic structure (or organic layer, for example, a dam) may not be disposed between the third via layer VIA3 and the edge EDGE in the first direction DR1. When another organic structure is disposed, the minimum distance GHS1 (refer to Figure 5 ).

[0140] As described above, the protective layer (or inorganic layer) may not exist between the first through-hole layer VIA1 to the third through-hole layer VIA3 as an organic layer. Therefore, defects may not occur in the adhesion between the first through-hole layer VIA1 to the third through-hole layer VIA3. In addition, the first through-hole layer VIA1 to the third through-hole layer VIA3 may have a coating structure. The second through-hole layer VIA2 may cover the first through-hole layer VIA1 and the second source metal layer SDL2 (and the residue RES), and the third through-hole layer VIA3 may cover the second through-hole layer VIA2 and the third source metal layer SDL3 (and the residue RES). Therefore, defects (e.g., short circuits) caused by the second source metal layer SDL2 and the third source metal layer SDL3 (and the residue RES) can be prevented. The cone angles θ2 and θ3 of the second through-hole layer VIA2 and the third through-hole layer VIA3 may be equal to or less than about 47 degrees, and the occurrence of the residue RES may be reduced. The second via layer VIA2 and the third via layer VIA3 may cover the underlying configuration or structure by about 9 μm to about 10 μm, and defects caused by the residue RES may be more surely prevented.

[0141] Fig. 9 It is shown Figure 1 A cross-sectional view of a comparative example of a display device of FIG. Fig. 9 In, with Figure 8 Corresponding to the display device 10 of FIG. 1 , a cross section of an outer portion of the display device 10_C adjacent to the edge EDGE is briefly shown.

[0142] refer to Figure 8 and Fig. 9 , in addition to the arrangement of the second via layer VIA2 and the third via layer VIA3, according to Fig. 9 The display device 10_C of the comparative example is similar to Figure 8 , and therefore overlapping descriptions may not be repeated.

[0143] In the display device 10_C, the first to third via layers VIA1 to VIA3 may have a step structure instead of a wrap structure.

[0144] like Fig. 9 As shown in FIG. 1 , in the outer portion of the display device 10_C, the second via layer VIA2 may not cover (e.g., may not completely cover) the first via layer VIA1, and the first via layer VIA1 may be exposed by the second via layer VIA2. In this case, the residue RES of the second source metal layer SDL2 may be exposed, may contact the second power line PL2, and may cause a short circuit defect.

[0145] Similarly, the third via layer VIA3 may not cover (eg, may not completely cover) the second via layer VIA2, and the second via layer VIA2 may be exposed by the third via layer VIA3. In this case, the residue RES of the third source metal layer SDL3 may be exposed, may contact the second power line PL2, and may cause a short circuit defect.

[0146] As will be referenced later Fig.16 As described, in addition to the front surface, the display device 10_C may include a conductive pattern disposed on the rear surface. In order to form a conductive pattern on the rear surface of the display device 10_C, in addition to the front surface process, a rear surface process may be performed. For example, the front surface process may be performed in a state where the front surface of the display device 10_C faces upward, and the rear surface process may be performed in a state where the display device 10_C is flipped so that the rear surface of the display device 10_C faces upward. For example, a table for fixing the display device 10_C may have a surface with an embossed structure, and when the front surface of the display device 10_C rubs against the surface of the table, scratches may occur on the front surface of the display device 10_C. Scratches may cause short circuit defects.

[0147] In addition, in the process of forming the first through-hole layer VIA1 to the third through-hole layer VIA3 of the step structure, the first through-hole layer VIA1 and the second through-hole layer VIA2 may retreat, and the first data line DL1 (or the outermost line) as the second source metal layer SDL2 may be exposed. For example, in the process of etching (e.g., dry etching) the third through-hole layer VIA3 as an organic layer, the second through-hole layer VIA2 exposed by the third through-hole layer VIA3 may also be etched, the edge of the second through-hole layer VIA2 may retreat in the first direction DR1, and the second source metal layer SDL2 may be exposed by the second through-hole layer VIA2. In this case, a short circuit may occur between the second source metal layer SDL2 and the second power line PL2, and the pixel PX connected to the first data line DL1 may not emit light normally.

[0148] Even if the second source metal layer SDL2 is not exposed by the second via layer VIA2 , a short circuit between the first data line DL1 and the second power line PL2 may occur due to a scratch because the second via layer VIA2 does not sufficiently cover the second source metal layer SDL2 .

[0149] A large amount of residue RES (i.e., residue RES of the source metal layer) may appear near the edge of the first through hole layer VIA1 to the third through hole layer VIA3, adjacent residue RES may be connected to each other, and the residue RES may exist completely in a line shape. Because one residue RES is in a floating state, even if one residue RES contacts the second power line PL2, one residue RES may not cause a problem. However, the residue RES completely having a line shape may cause a short circuit when the second power line PL2 is connected to another configuration.

[0150] Therefore, the first to third via layers VIA1 to VIA3 of the display device 10 according to one or more embodiments may have a wrapping structure, and the second to third via layer VIA2 and / or the third to third via layer VIA3 may cover the lower residue RES.

[0151] As described above, when the first to third via layers VIA1 to VIA3 have a step structure, a short circuit may occur in the second source metal layer SDL2 and / or the third source metal layer SDL3. In one or more embodiments, when the first to third via layers VIA1 to VIA3 have a cladding structure, a short circuit may not occur in the second source metal layer SDL2 and / or the third source metal layer SDL3.

[0152] Fig.10 and Fig.11 It is shown Figure 1 A cross-sectional view of an embodiment of a display device. Fig.10 and Fig.11 In, with Figure 8 Corresponding to the display device 10 of FIG. 1 , a cross section of an outer portion of the display device 10 adjacent to the edge EDGE is briefly shown.

[0153] refer to Figure 8 , Fig.10 and Fig.11 , in addition to the second via layer VIA2 and the third via layer VIA3, Fig.10 implementation and Fig.11 Each of the embodiments may be substantially equal to or similar to Figure 8 Therefore, overlapping descriptions may not be repeated.

[0154] In one or more embodiments, the second via layer VIA2 may directly cover the first via layer VIA1, and the third via layer VIA3 may not cover (eg, may not completely cover) the first via layer VIA1.

[0155] The second via layer VIA2 , and an edge of the second via layer VIA2 may be exposed by the third via layer VIA3 .

[0156] like Fig.10 As shown in , the second via layer VIA2 may protrude or extend the most toward the edge EDGE of the substrate SUB, and the second via layer VIA2 may completely cover the first via layer VIA1 and the second source metal layer SDL2 (the first power line PL1, the data line DL, etc.). The second via layer VIA2 may further protrude or extend a distance D1 of about 5 μm or more (e.g., about 9 μm to about 10 μm) to cover the first via layer VIA1 and the second source metal layer SDL2. Therefore, a short circuit between the second source metal layer SDL2 and the upper metal layer (e.g., the third source metal layer SDL3 and the second power line PL2) may be prevented.

[0157] Another organic layer (or organic structure) may not be disposed between the second via layer VIA2 and the edge EDGE in the first direction DR1.

[0158] The third via layer VIA3 may be located inside the first via layer VIA1, but is not limited thereto. For example, the third via layer VIA3 may protrude further toward the edge EDGE than the first via layer VIA1.

[0159] and Figure 8 Compared with the embodiment of the present invention, since only the second via layer VIA2 protrudes toward the edge EDGE more than the first via layer VIA1, the minimum distance GHS1 can be further reduced (refer to Figure 5 That is, the dead zone of the display device 10 can be further reduced. When the outermost line of the nearest edge EDGE exists in the second source metal layer SDL2, it can be used Fig.10 Implementation methods, but not limited to this.

[0160] In one or more embodiments, the second via layer VIA2 may not cover (eg, may not completely cover) the first via layer VIA1, and an edge portion of the first via layer VIA1 may be exposed by the second via layer VIA2 (eg, see Fig.11 ), and the third via layer VIA3 may directly cover the first via layer VIA1 (or the exposed portion of the first via layer VIA1).

[0161] like Fig.11As shown in , the third via layer VIA3 may protrude or extend the most toward the edge EDGE of the substrate SUB, and the third via layer VIA3 may not only completely cover the second via layer VIA2 and the third source metal layer SDL3, but also completely cover the first via layer VIA1 and the second source metal layer SDL2 (or the first power line PL1, the data line DL, etc.). The third via layer VIA3 may further protrude or extend a distance D3 of about 5 μm or more (e.g., about 9 μm to about 10 μm) than the first via layer VIA1, and may cover the first via layer VIA1 and the second via layer VIA2. Therefore, a short circuit between the second source metal layer SDL2 and the third source metal layer SDL3 and the upper metal layer (e.g., the second power line PL2) may be prevented.

[0162] and Figure 8 Compared with the embodiment of the present invention, since only the third through hole layer VIA3 protrudes toward the edge EDGE more than the first through hole layer VIA1, the minimum distance GHS1 can be further reduced (refer to Figure 5 ). That is, the dead zone of the display device 10 can be further reduced.

[0163] As described above, only a portion of the first to third via layers VIA1 to VIA3 may have the cladding structure.

[0164] Fig.12 is a plan view showing a spliced ​​display device including a plurality of display devices according to one or more embodiments.

[0165] refer to Fig.12 , the spliced ​​display device TD may include a plurality of display devices 10_1 to 10_4 and a seam SM. For example, the spliced ​​display device TD may include a first display device 10_1 , a second display device 10_2 , a third display device 10_3 , and a fourth display device 10_4 .

[0166] The plurality of display devices 10_1 to 10_4 may be arranged in a grid shape. The plurality of display devices 10_1 to 10_4 may be arranged in a matrix form of M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device 10_1 and the second display device 10_2 may be adjacent to each other in a first direction DR1. The first display device 10_1 and the third display device 10_3 may be adjacent to each other in a second direction DR2. The third display device 10_3 and the fourth display device 10_4 may be adjacent to each other in the first direction DR1. The second display device 10_2 and the fourth display device 10_4 may be adjacent to each other in a second direction DR2.

[0167] However, the number and arrangement of the plurality of display devices 10_1 to 10_4 in the spliced ​​display device TD are not limited to Fig.12The number and arrangement of the display devices 10_1 to 10_4 in the tiled display device TD may be determined according to the size of each of the display device 10 and the tiled display device TD and the shape of the tiled display device TD.

[0168] The plurality of corresponding display devices 10_1 to 10_4 may have the same size, but are not limited thereto. For example, the plurality of corresponding display devices 10_1 to 10_4 may have different sizes.

[0169] Each of the plurality of display devices 10_1 to 10_4 may have a rectangular shape including a long side and a short side. The plurality of display devices 10_1 to 10_4 may be arranged in a state in which the long sides or the short sides are connected to each other. Some or all of the plurality of display devices 10_1 to 10_4 may be arranged at the edge of the spliced ​​display device TD and may form one side of the spliced ​​display device TD. At least one of the plurality of display devices 10_1 to 10_4 may be arranged at at least one corner of the spliced ​​display device TD and may form two adjacent sides of the spliced ​​display device TD. At least one of the plurality of display devices 10_1 to 10_4 may be surrounded by other display devices.

[0170] Each of the plurality of display devices 10_1 to 10_4 may be combined with Figures 1 to 8 The display devices 10 described are substantially the same. Therefore, the description of each of the plurality of display devices 10_1 to 10_4 is omitted.

[0171] The seam SM may include a coupling member or an adhesive member. In this case, the plurality of display devices 10_1 to 10_4 may be connected to each other by the coupling member or adhesive member of the seam SM. The seam SM may be provided between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

[0172] Fig.13 yes Fig.12 Magnified view of area AA.

[0173] refer to Fig.13, the seam SM may have a cross, a cross, or a plus sign in a central area of ​​the spliced ​​display device TD where the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4 are adjacent to each other. The seam SM may be provided between the first display device 10_1 and the second display device 10_2, between the first display device 10_1 and the third display device 10_3, between the second display device 10_2 and the fourth display device 10_4, and between the third display device 10_3 and the fourth display device 10_4.

[0174] The first display device 10_1 may include first pixels PX1 arranged in a matrix form along a first direction DR1 and a second direction DR2 to display an image. The second display device 10_2 may include second pixels PX2 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The third display device 10_3 may include third pixels PX3 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image. The fourth display device 10_4 may include fourth pixels PX4 arranged in a matrix form along the first direction DR1 and the second direction DR2 to display an image.

[0175] A minimum distance between first pixels PX1 adjacent in the first direction DR1 may be defined as a first horizontal spacing distance GH1, and a minimum distance between second pixels PX2 adjacent in the first direction DR1 may be defined as a second horizontal spacing distance GH2. The first horizontal spacing distance GH1 and the second horizontal spacing distance GH2 may be substantially the same.

[0176] The seam SM may be disposed between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1. The minimum distance GG1 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1 may be the sum of the minimum distance GHS1 in the first direction DR1 between the first pixel PX1 and the seam SM, the minimum distance GHS2 in the first direction DR1 between the second pixel PX2 and the seam SM, and the width GSM1 in the first direction DR1 of the seam SM.

[0177] The minimum distance GG1, the first horizontal spacing distance GH1, and the second horizontal spacing distance GH2 between the first pixel PX1 and the second pixel PX2 adjacent in the first direction DR1 may be substantially the same. To this end, the minimum distance GHS1 in the first direction DR1 between the first pixel PX1 and the seam SM may be smaller than the first horizontal spacing distance GH1, and the minimum distance GHS2 in the first direction DR1 between the second pixel PX2 and the seam SM may be smaller than the second horizontal spacing distance GH2. In addition, the width GSM1 of the seam SM in the first direction DR1 may be smaller than the first horizontal spacing distance GH1 or the second horizontal spacing distance GH2.

[0178] A minimum distance between third pixels PX3 adjacent in the first direction DR1 may be defined as a third horizontal spacing distance GH3, and a minimum distance between fourth pixels PX4 adjacent in the first direction DR1 may be defined as a fourth horizontal spacing distance GH4. The third and fourth horizontal spacing distances GH3 and GH4 may be substantially the same.

[0179] The seam SM may be disposed between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1. The minimum distance GG4 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be the sum of the minimum distance GHS3 in the first direction DR1 between the third pixel PX3 and the seam SM, the minimum distance GHS4 in the first direction DR1 between the fourth pixel PX4 and the seam SM, and the width GSM1 in the first direction DR1 of the seam SM.

[0180] The minimum distance GG4, the third horizontal spacing distance GH3, and the fourth horizontal spacing distance GH4 between the third pixel PX3 and the fourth pixel PX4 adjacent in the first direction DR1 may be substantially the same. To this end, the minimum distance GHS3 in the first direction DR1 between the third pixel PX3 and the seam SM may be smaller than the third horizontal spacing distance GH3, and the minimum distance GHS4 in the first direction DR1 between the fourth pixel PX4 and the seam SM may be smaller than the fourth horizontal spacing distance GH4. In addition, the width GSM1 of the seam SM in the first direction DR1 may be smaller than the third horizontal spacing distance GH3 or the fourth horizontal spacing distance GH4.

[0181] A minimum distance between first pixels PX1 adjacent in the second direction DR2 may be defined as a first vertical spacing distance GV1, and a minimum distance between third pixels PX3 adjacent in the second direction DR2 may be defined as a third vertical spacing distance GV3. The first vertical spacing distance GV1 and the third vertical spacing distance GV3 may be substantially the same.

[0182] The seam SM may be disposed between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2. The minimum distance GG2 between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2 may be the sum of the minimum distance GVS1 in the second direction DR2 between the first pixel PX1 and the seam SM, the minimum distance GVS3 in the second direction DR2 between the third pixel PX3 and the seam SM, and the width GSM2 in the second direction DR2 of the seam SM.

[0183] The minimum distance GG2, the first vertical spacing distance GV1, and the third vertical spacing distance GV3 between the first pixel PX1 and the third pixel PX3 adjacent in the second direction DR2 may be substantially the same. To this end, the minimum distance GVS1 in the second direction DR2 between the first pixel PX1 and the seam SM may be smaller than the first vertical spacing distance GV1, and the minimum distance GVS3 in the second direction DR2 between the third pixel PX3 and the seam SM may be smaller than the third vertical spacing distance GV3. In addition, the width GSM2 of the seam SM in the second direction DR2 may be smaller than the first vertical spacing distance GV1 or the third vertical spacing distance GV3.

[0184] A minimum distance between second pixels PX2 adjacent in the second direction DR2 may be defined as a second vertical spacing distance GV2, and a minimum distance between fourth pixels PX4 adjacent in the second direction DR2 may be defined as a fourth vertical spacing distance GV4. The second vertical spacing distance GV2 and the fourth vertical spacing distance GV4 may be substantially the same.

[0185] The seam SM may be disposed between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2. The minimum distance GG3 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be the sum of the minimum distance GVS2 in the second direction DR2 between the second pixel PX2 and the seam SM, the minimum distance GVS4 in the second direction DR2 between the fourth pixel PX4 and the seam SM, and the width GSM2 in the second direction DR2 of the seam SM.

[0186] The minimum distance GG3, the second vertical spacing distance GV2, and the fourth vertical spacing distance GV4 between the second pixel PX2 and the fourth pixel PX4 adjacent in the second direction DR2 may be substantially the same. To this end, the minimum distance GVS2 in the second direction DR2 between the second pixel PX2 and the seam SM may be smaller than the second vertical spacing distance GV2, and the minimum distance GVS4 in the second direction DR2 between the fourth pixel PX4 and the seam SM may be smaller than the fourth vertical spacing distance GV4. In addition, the width GSM2 of the seam SM in the second direction DR2 may be smaller than the second vertical spacing distance GV2 or the fourth vertical spacing distance GV4.

[0187] like Fig.13 As shown in , the minimum distance between pixels of mutually adjacent display devices may be substantially the same as the minimum distance between pixels of each of the display devices, so that a seam SM cannot be visually recognized between images displayed by the plurality of display devices 10_1 to 10_4.

[0188] Fig.14 It is shown along Fig.13 A cross-sectional view of an example of a spliced ​​display device taken along line J-J'.

[0189] refer to Fig.14 , the first display device 10_1 may include a first display module DPM1 and a first front cover COV1. The second display device 10_2 may include a second display module DPM2 and a second front cover COV2.

[0190] Each of the first display module DPM1 and the second display module DPM2 may include a substrate SUB, a thin film transistor layer TFTL, and a light emitting element layer EML. Figure 7 and Figure 8 The thin film transistor layer TFTL and the light emitting element layer EML are described in detail. Fig.14 In the description of Figure 7 and Figure 8 The content overlaps the content.

[0191] The substrate SUB may include a first surface 41 on which the thin film transistor layer TFTL is disposed, a second surface 42 opposite to the first surface 41, and a first side surface 43 disposed between the first surface 41 and the second surface 42. The first surface 41 may be a front surface or an upper surface of the substrate SUB, and the second surface 42 may be a rear surface or a lower surface of the substrate SUB.

[0192] In addition, the substrate SUB may further include chamfered surfaces 44_1 and 44_2 disposed between the first surface 41 and the first side surface 43 and between the second surface 42 and the first side surface 43. The thin film transistor layer TFTL and the light emitting element layer EML may not be disposed on the chamfered surfaces 44_1 and 44_2. The substrate SUB of the first display device 10_1 and the substrate SUB of the second display device 10_2 may be prevented from colliding with and being damaged by the chamfered surfaces 44_1 and 44_2.

[0193] The chamfered surfaces 44_1 and 44_2 may also be provided between the first surface 41 and each of the other side surfaces except the first side surface 43 and between the second surface 42 and each of the other side surfaces except the first side surface 43. For example, when the first display device 10_1 and the second display device 10_2 have the following Figure 8 When the rectangular plan shape is shown in , the chamfered surfaces 44_1 and 44_2 can be arranged between the first surface 41 and each of the second, third and fourth side surfaces, and between the second surface 42 and each of the second, third and fourth side surfaces.

[0194] The first front cover COV1 may be disposed above the chamfered surfaces 44_1 and 44_2 of the substrate SUB. That is, the first front cover COV1 may protrude beyond the substrate SUB in the first direction DR1 and the second direction DR2. Therefore, a distance GSUB between the substrate SUB of the first display device 10_1 and the substrate SUB of the second display device 10_2 may be greater than a distance GCOV between the first front cover COV1 and the second front cover COV2.

[0195] Each of the first front cover COV1 and the second front cover COV2 may include an adhesive member 51 , a transmittance adjustment layer 52 disposed on the adhesive member 51 , and an anti-glare layer 53 disposed on the transmittance adjustment layer 52 .

[0196] The adhesive member 51 of the first front cover COV1 attaches the light emitting element layer EML of the first display module DPM1 to the first front cover COV1. The adhesive member 51 of the second front cover COV2 attaches the light emitting element layer EML of the second display module DPM2 to the second front cover COV2. The adhesive member 51 may be a transparent adhesive member capable of transmitting light. For example, the adhesive member 51 may be an optically transparent adhesive film or an optically transparent resin.

[0197] The anti-glare layer 53 may be designed to diffusely reflect external light to prevent the external light from being directly reflected and prevent the visibility of the image from being deteriorated. Therefore, the contrast of the images displayed by the first display device 10_1 and the second display device 10_2 may be increased by the anti-glare layer 53.

[0198] The transmittance adjusting layer 52 may be designed to reduce the transmittance of external light or light reflected from the first and second display modules DPM1 and DPM2. Therefore, the distance GSUB between the substrate SUB of the first and second display modules DPM1 and DPM2 may be prevented from being visually recognized from the outside.

[0199] The anti-glare layer 53 may be implemented as a polarizing plate, and the transmittance adjustment layer 52 may be implemented as a phase retardation layer, but the present disclosure is not limited thereto.

[0200] In one or more embodiments, the light emitting element ED may be a light emitting structure including a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, a first contact electrode ELT1, and a second contact electrode ELT2. According to one or more embodiments, the light emitting element ED may further include a base substrate SSUB at the uppermost portion. The base substrate SSUB may be a sapphire substrate, but is not limited thereto.

[0201] The first semiconductor layer 11 may be disposed on one surface of the base substrate SSUB and one surface of the active layer 12. The first semiconductor layer 11 may be formed of GaN doped with a p-type dopant such as Mg, Zn, Ca, or Ba.

[0202] The active layer 12 may be disposed on a portion of one surface of the first semiconductor layer 11. The active layer 12 may include a material of a single quantum well structure or a multiple quantum well structure. When the active layer 12 includes a material having a multiple quantum well structure, the active layer 12 may have a structure in which well layers and barrier layers are alternately stacked. At this time, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer 12 may have a structure in which a type of semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may also include different III- to V-group semiconductor materials according to the wavelength band of the emitted light.

[0203] When the active layer 12 includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer 12 may move to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer 12 may move to the blue wavelength band.

[0204] The second semiconductor layer 13 may be disposed on the other surface of the active layer 12. For example, the second semiconductor layer 13 may be formed of GaN doped with an n-type conductive dopant such as Si, Ge, Se, and / or Sn.

[0205] The first contact electrode ELT1 may be disposed on one surface of the first semiconductor layer 11 , and the second contact electrode ELT2 may be disposed on one surface of the second semiconductor layer 13 .

[0206] The second contact electrode ELT2 and the pixel electrode AND may be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP). Alternatively, the second contact electrode ELT2 and the pixel electrode AND may be bonded to each other through a welding process.

[0207] Along Fig.13 Example and combination of the spliced ​​display device TD intercepted by the line K-K', the line L-L' and the line M-M' Fig.14 The described examples of the tiled display device TD taken along the line JJ′ are substantially the same, and thus the description thereof is omitted.

[0208] Fig.15 yes Fig.12 For ease of description, Fig.15 , a pad PAD and a first pixel PX1 disposed on an upper side of the first display device 10_1 are shown. Since the second, third, and fourth display devices 10_2, 10_3, and 10_4 have substantially the same configuration as the first display device 10_1, overlapping descriptions are omitted.

[0209] refer to Fig.15 , the pad PAD may be disposed on the upper edge of the first display device 10_1. When the data line DL (reference Figure 5 or Fig.16 ) When the data line DL of the first display device 10_1 extends in the second direction DR2, the pad PAD may be disposed at the upper and lower edges of the first display device 10_1. Alternatively, when the data line DL of the first display device 10_1 extends in the first direction DR1, the pad PAD may be disposed at the left and right edges of the first display device 10_1.

[0210] Each of the pads PAD may be connected to a data line DL on the upper surface of the substrate SUB. In addition, each of the pads PAD may be connected to a side surface line (refer to Fig.16 The side surface line SSL may be provided on the upper surface, the side surface, and the lower surface (or the rear surface) of the substrate SUB. The side surface line SSL may be connected to the connection line (refer to Fig.16 of the “CCL”).

[0211] Fig.16 It is shown along Fig.15 A cross-sectional view of an example of a spliced ​​display device taken along line N-N'. Fig.16 In Figure 7 , Figure 8 and Fig.14 Like the cross-sectional views shown in FIG. 1 , the same reference numerals are given to the same components, and overlapping descriptions are omitted.

[0212] refer to Fig.16 , the pad PAD may be disposed on the interlayer insulating layer ILD. A portion of the pad PAD may be exposed without being covered by the fourth protective layer PVX4. The pad PAD may include the same material as the pixel electrode AND and the common electrode COM. For example, the pad PAD may include a metal material with high reflectivity, such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO).

[0213] Gate layer GTL (reference Figure 7 ) may include a data line DL. The data line DL may be disposed on the gate insulating layer GI. The data line DL may be disposed on the same layer and may include the same material as the first capacitor electrode CE1. In contrast, the data line DL may include a first source metal layer SDL1 (reference Figure 7 ), may be disposed on the interlayer insulating layer ILD, and may include the same material as the second capacitor electrode CE2.

[0214] The pad PAD may be connected to the data line DL through a thirty-fifth contact hole CT35 passing through the interlayer insulating layer ILD.

[0215] The connection line CCL may be disposed on the lower surface of the substrate SUB. The connection line CCL may be a single layer or multiple layers formed of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0216] The fifth via layer VIA5 may be disposed on a portion of the connection line CCL. The fifth via layer VIA5 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, and / or polyimide resin.

[0217] The fifth protection layer PVX5 may be disposed on the fifth via layer VIA5. The fifth protection layer PVX5 may be formed of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0218] The side surface line SSL may be disposed on the upper surface edge, the side surface, and the lower surface edge of the substrate SUB. One end of the side surface line SSL may be connected to the pad PAD. One end of the side surface line SSL may be connected to the pad PAD through the thirty-sixth contact hole CT36 passing through the fourth protective layer PVX4. The other end of the side surface line SSL may be connected to the connection line CCL. The side surface line SSL may connect the pad PAD formed on the upper surface edge of the substrate SUB and the connection line CCL formed on the lower surface edge of the substrate SUB.

[0219] The side surface line SSL may be disposed on side surfaces of the substrate SUB, the buffer layer BF, the gate insulating layer GI, the interlayer insulating layer ILD, and the fourth protective layer PVX4.

[0220] To protect the externally exposed side surface line SSL from moisture and oxygen and to prevent the side surface line SSL from being visually recognized by a user, a coating pattern may be formed around an edge region of the display device 10_1 where the side surface line SSL is disposed.

[0221] The flexible film FPCB may be disposed on the lower surface of the fifth protective layer PVX5. The flexible film FPCB may be connected to the connection line CCL using a conductive adhesive member CAM through a thirty-seventh contact hole CT37 passing through the fifth through-hole layer VIA5 and the fifth protective layer PVX5. A source driving circuit for providing a data voltage to the data line DL may be disposed on the lower surface of the flexible film FPCB. The conductive adhesive member CAM may be an anisotropic conductive film or an anisotropic conductive paste.

[0222] As described above, in the first display device 10_1, the source driving circuit of the flexible film FPCB disposed on the lower portion of the substrate SUB can be connected to the data line DL through the connection line CCL, the side surface line SSL, and the pad PAD. That is, because the source driving circuit is disposed on the substrate SUB, the non-display area can be eliminated, and thus the pixel PX can be formed at the edge of the substrate SUB.

[0223] Fig.17 is a block diagram showing a spliced ​​display device according to one or more embodiments. Fig.17 In the figure, for the convenience of description, the first display device 10_1 and the host system HOST are shown.

[0224] refer to Fig.17According to one or more embodiments, the splicing display device TD may include a host system HOST, a broadcast tuning unit 210, a signal processing unit 220, a display unit 230, a speaker 240, a user input unit 250, an HDD 260, a network communication unit 270, a UI generation unit 280 and a control unit 290 (or a controller).

[0225] The host system HOST may be implemented as any one of a TV system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer, a mobile phone system, and a tablet computer.

[0226] The user's instructions can be input to the host system HOST in various formats. For example, the instructions input by the user's touch can be input to the host system HOST. Alternatively, the user's instructions can be input to the host system HOST through keyboard input or button input of a remote controller.

[0227] The host system HOST may receive raw video data corresponding to the raw image from the outside. The host system HOST may divide the raw video data by the number of display devices. For example, the host system HOST may divide the raw video data into first video data corresponding to the first image, second video data corresponding to the second image, third video data corresponding to the third image, and fourth video data corresponding to the fourth image in response to the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4. The host system HOST may transmit the first video data to the first display device 10_1, the second video data to the second display device 10_2, the third video data to the third display device 10_3, and the fourth video data to the fourth display device 10_4 (see, for example, Fig.12 ).

[0228] The first display device 10_1 may display a first image based on the first video data, the second display device 10_2 may display a second image based on the second video data, the third display device 10_3 may display a third image based on the third video data, and the fourth display device 10_4 may display a fourth image based on the fourth video data. Therefore, the user may view an original image in which the first image, the second image, the third image, and the fourth image displayed on the first display device 10_1, the second display device 10_2, the third display device 10_3, and the fourth display device 10_4 are combined (for example, see Fig.12 ).

[0229] The first display device 10_1 may include a broadcast tuner unit 210 , a signal processing unit 220 , a display unit 230 , a speaker 240 , a user input unit 250 , an HDD 260 , a network communication unit 270 , a UI generation unit 280 , and a control unit 290 .

[0230] The broadcast tuner unit 210 may tune a suitable channel frequency (eg, a predetermined channel frequency) under the control of the control unit 290 and receive a broadcast signal of a corresponding channel through an antenna. The broadcast tuner unit 210 may include a channel detection module and an RF demodulation module.

[0231] The broadcast signal demodulated by the broadcast tuner unit 210 is processed by the signal processing unit 220 and output to the display unit 230 and the speaker 240. Here, the signal processing unit 220 may include a signal separator 221, a video decoder 222, a video processing unit 223, an audio decoder 224, and an additional data processing unit 225.

[0232] The signal separator 221 decomposes the demodulated broadcast signal into a video signal, an audio signal and additional data. The decomposed video signal, audio signal and additional data are respectively restored by the video decoder 222, the audio decoder 224 and the additional data processing unit 225. At this time, the video decoder 222, the audio decoder 224 and the additional data processing unit 225 are restored to a decoding format corresponding to the encoding format when the broadcast signal is transmitted.

[0233] In one or more embodiments, the decoded video signal is converted by the video processing unit 223 to meet the vertical frequency, resolution, aspect ratio, etc. corresponding to the output standard of the display unit 230, and the decoded audio signal is output to the speaker 240.

[0234] The display unit 230 may include a display panel on which an image is displayed and a panel driver that controls driving of the display panel.

[0235] The user input unit 250 may receive a signal transmitted from the host system HOST. The user input unit 250 may be configured to receive data related to selection and input of instructions for communication with other display devices by a user and data related to selection and operation of a channel and a user interface (UI) menu transmitted by the host system HOST.

[0236] The HDD 260 stores various software programs including an OS program, recorded broadcast programs, dynamic pictures, photos, and other data, and may be formed of a storage medium such as a hard disk or a nonvolatile memory.

[0237] The network communication unit 270 is used to perform short-range communication with the host system HOST and other display devices, and may be implemented with a communication module including an antenna pattern that may implement mobile communication, data communication, Bluetooth, RF, Ethernet, and the like.

[0238] The network communication unit 270 can transmit and receive wireless signals using at least one of a base station, an external terminal and a server on a mobile communication network constructed according to a technical standard or a communication method for mobile communication (for example, Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Code Division Multiple Access 2000 (CDMA2000), Enhanced Voice Data Optimization or Enhanced Voice Data Only (EV-DO), Wideband CDMA (WCDMA), High Speed ​​Downlink Packet Access (HSDPA), High Speed ​​Uplink Packet Access (HSUPA), Long Term Evolution (LTE), Long Term Evolution Advanced (LTE-A), 5G, etc.) through an antenna pattern to be described later.

[0239] The network communication unit 270 can transmit and receive wireless signals on a communication network according to a wireless Internet technology through an antenna pattern to be described later. The wireless Internet technology includes, for example, wireless local area network (WLAN), wireless fidelity (WiFi), direct wireless fidelity (WiFi), digital living network alliance (DLNA), wireless broadband (WiBro), world interoperability for microwave access (WiMAX), high-speed downlink packet access (HSDPA), high-speed uplink packet access (HSUPA), long-term evolution (LTE), long-term evolution advanced (LTE-A), etc., and the antenna pattern transmits and receives data according to at least one wireless Internet technology within the scope including Internet technologies not listed above.

[0240] The UI generation unit 280 generates a UI menu for communicating with the host system HOST and other display devices, and can be implemented by an algorithm code and an OSD IC. The UI menu for communicating with the host system HOST and other display devices can be a menu for specifying a corresponding digital TV for communication and selecting a desired function.

[0241] The control unit 290 is responsible for the overall control of the first display device 10_1 and is responsible for the host system HOST and the second display device 10_2, the third display device 10_3 and the fourth display device 10_4 (see, for example, Fig.12 ) for communication control and stores corresponding algorithm codes for control, and the control unit 290 can be implemented by a microcontroller unit (MCU) in which the stored algorithm codes are executed.

[0242] The control unit 290 controls the transmission of corresponding control instructions and data to the host system HOST and the second display device 10_2, the third display device 10_3 and the fourth display device 10_4 through the network communication unit 270 according to the input and selection of the user input unit 250. Of course, when the host system HOST and the second display device 10_2, the third display device 10_3 and the fourth display device 10_4 (for example, see Fig.12 ) when appropriate control instructions (e.g., predetermined control instructions) and data are input, operations are performed according to the corresponding control instructions.

[0243] Because the block diagram of the second display device 10_2, the block diagram of the third display device 10_3, and the block diagram of the fourth display device 10_4 are combined with Fig.17 The block diagram of the described first display device 10_1 is substantially the same, so the description thereof is omitted.

[0244] Although the technical spirit of the present disclosure has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description rather than limitation. In addition, those skilled in the art can understand that various modifications are possible within the scope of the technical spirit of the present disclosure.

Claims

1. Display equipment, including: pixels, spaced apart from each other by a first spacing distance in a plan view, wherein each of the pixels comprises: transistors, on the base layer; a first organic layer on the transistor; a second organic layer, on the first organic layer; a third organic layer on the second organic layer; and a light emitting element on the third organic layer and electrically connected to the transistor, wherein an outermost pixel of the pixels closest to an edge of the base layer is spaced from the edge of the base layer by a distance within a second spacing distance, the second spacing distance being smaller than the first spacing distance, and Wherein, at least one of the second organic layer and the third organic layer covers the first organic layer near the edge of the base layer.

2. The display device according to claim 1, wherein: In a plan view, the second organic layer or the third organic layer extends toward the edge of the base layer by a distance equal to or greater than an average thickness of the first organic layer, compared to the first organic layer.

3. The display device according to claim 1, wherein: In a plan view, the organic structure is not located between the second organic layer or the third organic layer and the edge of the base layer.

4. The display device according to claim 1, wherein: The second organic layer is directly on the first organic layer, and the third organic layer is directly on the second organic layer, and The inorganic layer is not located between the first organic layer to the third organic layer.

5. The display device according to claim 4, further comprising: a first conductive pattern, located between the first organic layer and the second organic layer; a second conductive pattern, located between the second organic layer and the third organic layer; a first pixel electrode, located on the third organic layer, and a second pixel electrode and an inorganic layer, the second pixel electrode being on the third organic layer and the inorganic layer partially covering the second pixel electrode, wherein the light emitting element is electrically connected to the transistor through the first pixel electrode, the second conductive pattern and the first conductive pattern, wherein the residue of the first conductive pattern is at an edge of the first organic layer, and the residue of the first conductive pattern is covered by the second organic layer or the third organic layer, and Wherein, in a cross-sectional view, the second pixel electrode overlaps with the first conductive pattern and is separated from the first conductive pattern by a distance equal to or greater than an average thickness of the second organic layer or the third organic layer.

6. The display device according to claim 1, wherein: An edge of the second organic layer or the third organic layer contacts the first surface of the base layer, and Wherein, an angle between the edge of the second organic layer or the third organic layer and the first surface of the base layer is in a range of 35 degrees to 45 degrees.

7. The display device according to claim 1, wherein: Each of the pixels includes a plurality of sub-pixels, wherein each of the plurality of sub-pixels comprises the light emitting element in an emission region of the pixel, and Wherein, based on the emission area, the pixels are spaced apart from each other by the first spacing distance, and the outermost pixel is spaced apart from the edge of the base layer by the distance within the second spacing distance.

8. The display device according to claim 1, wherein: In a plan view, the second organic layer covers the first organic layer, and Wherein, in a plan view, the third organic layer covers the second organic layer.

9. The display device according to claim 1, wherein: In a plan view, the second organic layer covers the first organic layer, and In a plan view, the third organic layer does not cover the second organic layer, and an edge of the second organic layer is exposed by the third organic layer.

10. The display device according to claim 1, wherein: An edge of the first organic layer is exposed by the second organic layer, and the third organic layer covers the edge of the first organic layer.

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