Display panel

Abstract

The display panel includes: a substrate including a first region and a second region spaced apart from each other in a first direction; a plurality of display elements in a display area, the display area being adjacent to the first area and the second area; and a plurality of lines extending in a second direction crossing the first direction, the plurality of lines being electrically connected to the plurality of display elements, respectively, in which the plurality of lines include first and second lines adjacent to each other and bypassing an edge of the first region, and third and fourth lines adjacent to each other and bypassing an edge of the second region, wherein the first region and the second region differ from each other in at least one of size and shape.

Description

[0001] This application is a divisional application of the patent application with application number 201911104615.8 and title “Display Panel” filed on November 13, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2018-0148770 filed on November 27, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] One or more embodiments relate to a display panel, and more particularly, to a display panel including a line bypassing a specific area and a display device including the display panel. Background Art

[0005] In recent years, display devices have been widely used. In addition, as the thickness and weight of display devices are reduced, the application of display devices is increasing.

[0006] As the display device has been used in various ways, there may be various methods of designing the display device, and functions that may be linked to or associated with the display device have increased. Summary of the invention

[0007] In order to increase the functions that can be linked to or associated with the display device, a display panel and device including multiple areas where cameras, sensors, etc. that can be located inside the display area are located can be provided. However, in this case, there is a problem that the wiring around the multiple areas bypasses these areas, thereby increasing the dead area.

[0008] In order to solve various problems including the above-mentioned problems, the present disclosure may provide a structure that can reduce dead zones around a plurality of regions. However, the problems are merely examples and thus do not limit the scope of the present disclosure.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0010] According to one or more embodiments, a display panel includes: a substrate, including a first area and a second area separated from each other in a first direction; a plurality of display elements located in the display area, the display area being adjacent to the first area and the second area; and a plurality of lines extending in a second direction intersecting the first direction, the plurality of lines being electrically connected to the plurality of display elements, respectively.

[0011] The plurality of lines may include: first and second lines adjacent to each other and bypassing around an edge of a first region; and third and fourth lines adjacent to each other and bypassing around an edge of the second region, wherein the first and second regions differ from each other in at least one of size and shape.

[0012] The first line may be routed around a first side of the first region, and the second line may be routed around a second side of the first region.

[0013] The first line and the second line may extend from the first point in opposite directions, and the first point may be located on a virtual line passing through a center of the first area.

[0014] The third line may be routed around the first side of the second region, and the fourth line may be routed around the second side of the second region.

[0015] The third line and the fourth line may extend from the second point in opposite directions, and the second point may be spaced apart from a virtual line passing through the center of the second area.

[0016] The plurality of lines may include data lines or scan lines.

[0017] The display panel may further include: a middle region between the first region and the second region and the display region, wherein the first region and the second region are surrounded by the middle region.

[0018] A width between the first region and the second region in the middle region may be greater than a width between the first region and a first end of the middle region or a width between the second region and a second end of the middle region.

[0019] The number of lines between the first region and the second region in the middle region may be greater than the sum of the number of lines between the first end of the middle region and the first region and the number of lines between the second end of the middle region and the second region.

[0020] The display panel may further include: an opening corresponding to at least one of the first area and the second area.

[0021] According to one or more embodiments, a display panel includes: a substrate, including a first area and a second area separated from each other in a first direction, a display area surrounding the first area and the second area, and an intermediate area located between the first area, the second area and the display area; a plurality of display elements located in the display area; a packaging structure covering the plurality of display elements; and a plurality of lines extending in a direction crossing the first direction, the plurality of lines being electrically connected to the plurality of display elements, respectively, wherein the first area and the second area are different from each other in at least one of size and shape, and the plurality of lines include lines bypassing around the first area or the second area in the intermediate area.

[0022] The number of lines passing between the first region and the second region may be greater than half of the sum of the number of lines passing through the middle region.

[0023] The plurality of lines may include adjacent lines passing between the first region and the second region, and an interval between the adjacent lines in the intermediate region may be smaller than an interval between the adjacent lines in the display region.

[0024] The plurality of lines may include a first line and a second line adjacent to each other, wherein the first line extends along an edge of a first side of the first region, and the second line extends along an edge of a second side of the first region.

[0025] The first line and the second line may be symmetrical about a virtual line passing through the center of the first region.

[0026] A central angle of the bypass portion of the first line with respect to the center of the first region and a central angle of the bypass portion of the second line with respect to the center of the first region may be the same.

[0027] The plurality of lines may include a third line and a fourth line adjacent to each other, wherein the third line bypasses a first side of the second region, and the fourth line bypasses a second side of the second region.

[0028] The third line and the fourth line may be asymmetric about a virtual line passing through the center of the second region.

[0029] A central angle of the bypass portion of the third line with respect to the center of the second region and a central angle of the bypass portion of the fourth line with respect to the center of the second region may be different from each other.

[0030] The plurality of lines may include data lines or scan lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] These and / or other aspects will become apparent and more easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a perspective view of a display device according to an embodiment;

[0033] Figure 2A , Figure 2B and Figure 2C is a cross-sectional view of a display device according to an embodiment;

[0034] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view of a display panel according to an embodiment;

[0035] Figure 4A , Figure 4B and Figure 4C is a cross-sectional view of a display panel according to another embodiment;

[0036] Figure 5 is a plan view of a display panel according to an embodiment;

[0037] Figure 6 is an equivalent circuit diagram illustrating a pixel of a display panel according to an embodiment;

[0038] Fig. 7A is a plan view illustrating a pixel of a display panel according to an embodiment;

[0039] Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' and line BB';

[0040] Figure 8 is a plan view illustrating a first line located in a middle area of ​​a display panel according to an embodiment;

[0041] Fig. 9A It is a graphic Figure 8 The first line of the floor plan;

[0042] Fig. 9B It is a graphic Fig. 9A Modified floor plan;

[0043] Fig. 10A and Fig. 10B is a cross-sectional view illustrating a first line located in a middle area of ​​a display panel according to an embodiment;

[0044] Fig.11 is a plan view illustrating a second line located in a middle area of ​​a display panel according to an embodiment;

[0045] Fig.12 is a plan view illustrating a first line located in a middle area of ​​a display panel according to another embodiment;

[0046] Fig.13 is a plan view illustrating a second line located in a middle area of ​​a display panel according to another embodiment;

[0047] Fig.14 It is a graphic Fig.13 The plan view of the second line;

[0048] Fig.15 is a plan view illustrating a first line located in a middle area of ​​a display panel according to another embodiment;

[0049] Fig.16 is a plan view illustrating a first line located in a middle area of ​​a display panel according to another embodiment;

[0050] Fig.17 is a plan view illustrating a first line located in a middle area of ​​a display panel according to another embodiment;

[0051] Fig.18 is a plan view illustrating a second line located in a middle area of ​​a display panel according to another embodiment; and

[0052] Fig.19 is a plan view illustrating a second line located in a middle area of ​​a display panel according to another embodiment. DETAILED DESCRIPTION

[0053] The present disclosure may include various embodiments and modifications, and some embodiments of the present disclosure will be illustrated in the accompanying drawings and will be described in detail herein. The effects and features of the present disclosure and the accompanying methods thereof will become apparent from the following description of the embodiments in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and may be embodied in various modes.

[0054] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the accompanying drawings, like elements are denoted by like reference numerals, and repeated explanation thereof will not be given.

[0055] It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another.

[0056] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0057] It will be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0058] It will be understood that when a layer, region or element is referred to as being “formed on” another layer, region or element, it may be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0059] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings are arbitrarily illustrated for the convenience of explanation, the present disclosure is not limited thereto.

[0060] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed substantially at the same time, or in the reverse order of the described order.

[0061] It will be understood that when layers, regions, or elements are referred to as being "connected," the layers, regions, or elements may be directly connected or may be indirectly connected with intervening layers, regions, or elements therebetween. For example, when layers, regions, or elements are electrically connected, the layers, regions, or elements may be directly electrically connected or may be indirectly electrically connected with intervening layers, regions, or elements therebetween.

[0062] Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0063] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0064] refer to Figure 1 , the display device 1 includes a display area DA surrounding the first area RA1 and the second area RA2. The first area RA1 and the second area RA2 may have different sizes (areas) and / or shapes. For example, the first area RA1 may have a circular shape, and the second area RA2 may have an elliptical shape or a quadrilateral shape with rounded corners. Alternatively, the first area RA1 and the second area RA2 may have similar shapes and different sizes.

[0065] The display area DA may provide an image by using light emitted from a plurality of pixels located in the display area DA. The middle area MA may be located between the first area RA1 and the second area RA2 and the display area DA, and the display area DA may be surrounded by the peripheral area PA. The middle area MA and the peripheral area PA may be non-display areas in which pixels are not located. The middle area MA may be completely surrounded by the display area DA, and the display area DA may be completely surrounded by the peripheral area PA.

[0066] Although the following content is described based on the assumption that the display device 1 is an organic light-emitting display device, the display device 1 of the present disclosure is not limited thereto. In another embodiment, the display device 1 of the present disclosure may be any one of various display devices, such as a liquid crystal display device, an inorganic light-emitting display device (or an inorganic electroluminescent (EL) display device), or a quantum dot light-emitting display device.

[0067] FIG. 2A to FIG. 2C is along Figure 1 1 is a cross-sectional view of the display device 1 taken along line II-II′.

[0068] refer to Figure 2A, the display device 1 may include a display panel 10, an input sensing layer 40 located on the display panel 10, an optical function layer 50, and a window 60. The display panel 10, the input sensing layer 40, and the optical function layer 50 may be covered by the window 60. The display device 1 may be any of various electronic devices, such as a mobile phone, a notebook computer, or a smart watch.

[0069] The display panel 10 may display an image. The display panel 10 includes pixels located in a display area DA. Each of the pixels may include a display element and a pixel circuit connected to the display element. The display element may include an organic light emitting diode (OLED). Alternatively, the display element may include an inorganic light emitting diode, a liquid crystal layer, or a quantum dot light emitting diode.

[0070] The input sensing layer 40 obtains coordinate information according to an external input (e.g., a touch event). The input sensing layer 40 may include a sensing electrode (or a touch electrode) and a signal line (e.g., a trace) connected to the sensing electrode. The input sensing layer 40 may be located on the display panel 10. The input sensing layer 40 may detect an external input by using a mutual capacitance method or / and a self-capacitance method.

[0071] The input sensing layer 40 may be directly formed on the display panel 10, or may be separately formed and then coupled to the display panel 10 by using an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing layer 40 may be continuously formed after a process of forming the display panel 10, and in this case, the adhesive layer may not be located between the input sensing layer 40 and the display panel 10. Figure 2A The input sensing layer 40 is located between the display panel 10 and the optical function layer 50 . However, in another embodiment, the input sensing layer 40 may be located above the optical function layer 50 .

[0072] The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident on the display panel 10 through the window 60. The anti-reflection layer may include a retarder and a polarizer. The retarder may be a film retarder or a liquid crystal coated retarder, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be a film polarizer or a liquid crystal coated polarizer. The film polarizer may include a long synthetic resin film, and the liquid crystal coated polarizer may include liquid crystals arranged in a predetermined orientation. The retarder and the polarizer may further include a protective film. The retarder and the polarizer or the protective film may be defined as a base layer of the anti-reflection layer.

[0073] In another embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set in consideration of the color of the light emitted from each of the pixels of the display panel 10. In another embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the reflectivity of the external light.

[0074] The optical function layer 50 may include a lens layer. The lens layer may improve the light extraction efficiency of the light emitted from the display panel 10, or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, or / and may include a plurality of layers having different refractive indices. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or may include any one of the anti-reflection layer and the lens layer.

[0075] Each of the display panel 10, the input sensing layer 40, and the optical function layer 50 may include an opening (or a through hole or a hole) located in the first area RA1 and the second area RA2. Figure 2A In the embodiment, the display panel 10, the input sensing layer 40 and the optical function layer 50 include first to third openings 10H, 40H and 50H, respectively, and the first to third openings 10H, 40H and 50H overlap each other. The first to third openings 10H, 40H and 50H are positioned to correspond to the first area RA1 and the second area RA2, and the first area RA1 and the second area RA2 may be opening areas. The sizes (or diameters) of the first to third openings 10H, 40H and 50H may be the same or different from each other. In another embodiment, at least one of the display panel 10, the input sensing layer 40 and the optical function layer 50 may not include an opening.

[0076] The first opening 10H of the display panel 10 may be located only in one of the first area RA1 and the second area RA2. Figure 2B In another embodiment, the display panel 10, the input sensing layer 40 and the optical function layer 50 include first to third openings 10H, 40H and 50H in the first area RA1, respectively, and do not include first to third openings 10H, 40H and 50H in the second area RA2. Figure 2C As shown, the display panel 10 , the input sensing layer 40 , and / or the optical function layer 50 may not include openings in the first area RA1 and the second area RA2 .

[0077] The first area RA1 and the second area RA2 may be component areas (e.g., a sensor area, a camera area, and a speaker area) in which components for adding various functions to the display device 1 are located. The first component 21 and the second component 22 located in the first area RA1 and the second area RA2, respectively, may be located in the first to third openings 10H, 40H, and 50H, as shown in FIG. Figure 2A Alternatively, Figure 2B As shown, the first part 21 may be located in the first to third openings 10H, 40H and 50H, and the second part 22 may be located under the display panel 10. Alternatively, as Figure 2C As shown, the first component 21 and the second component 22 may be located under the display panel 10 .

[0078] The first component 21 and the second component 22 may include electronic components. For example, the first component 21 and the second component 22 may be electronic components that use light or sound. Examples of electronic components may include sensors that use light, such as infrared sensors, camera components such as cameras or lenses that receive light and capture images, sensors that output and detect light or sound to measure distance or identify fingerprints, etc., small lights that output light, and speakers that output sound. Electronic components that use light can use light of various bands, such as visible light, infrared light, or ultraviolet light. In some embodiments, the first area RA1 and the second area RA2 may be understood as transmission areas, and light or / and sound output from the first component 21 and the second component 22 to the outside and / or traveling from the outside toward the electronic component can pass through the transmission area.

[0079] In another embodiment, when the display device 1 is used as an instrument panel (dashboard) of a vehicle or a smart watch, the first component 21 and the second component 22 may include a pointer such as a clock hand or a pointer indicating predetermined information (e.g., vehicle speed). When the display device 1 includes a pointer such as a clock hand or a pointer for a vehicle instrument panel, the pointer may pass through the window 60 and may be exposed to the outside, and the window 60 may include an opening. Alternatively, even when the first component 21 and the second component 22 include speakers, the window 60 may include an opening.

[0080] The first member 21 and the second member 22 may include functional elements of the display panel 10 as described above, or may include elements such as accessories for enhancing the aesthetics of the display panel 10. FIG. 2A to FIG. 2C Although not shown in the figure, a layer including OCA may be located between the window 60 and the optical functional layer 50 .

[0081] The first component 21 and the second component 22 may include the same type of electronic components or different types of electronic components. For example, each of the first component 21 and the second component 22 may include a camera, and in this case, the display device 1 may provide various applications using dual cameras. Various modifications may be made. For example, one of the first component 21 and the second component 22 may include a sensor, and the other of the first component 21 and the second component 22 may include a camera. Alternatively, one of the first component 21 and the second component 22 may include a light, and the other of the first component 21 and the second component 22 may include a camera.

[0082] FIG. 3A to FIG. 3C is a cross-sectional view of a display panel 10 according to an embodiment.

[0083] refer to Figure 3A The display panel 10 includes a display layer 200 located on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may have a multi-layer structure. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104. Figure 3A As shown in the enlarged figure.

[0084] Each of the first substrate layer 101 and the second substrate layer 103 may include a polymer resin. For example, each of the first substrate layer 101 and the second substrate layer 103 may include polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0085] Each of the first barrier layer 102 and the second barrier layer 104 as a barrier layer for preventing penetration of external foreign matter may include a layer including silicon nitride (SiN x , x>0) or silicon oxide (SiO x , x>0) of a single or multilayer structure of inorganic materials.

[0086] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A and a pixel circuit layer 200B, the display element layer 200A includes display elements respectively located in each pixel, and the pixel circuit layer 200B includes pixel circuits and an insulating layer respectively located in each pixel. Each of the pixel circuits may include a thin film transistor (TFT) and a storage capacitor, and each of the display elements may include an OLED.

[0087] The display element of the display layer 200 may be covered by an encapsulation structure 300 such as a thin film encapsulation layer, and the thin film encapsulation layer includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. The inorganic encapsulation layer may include, for example, silicon nitride, silicon oxide, or silicon oxynitride. The organic encapsulation layer may include a polymer material. Examples of polymer materials may include acrylic resins, epoxy resins, PI, and polyethylene.

[0088] When the display panel 10 includes the substrate 100 having a multi-layer structure and the encapsulation structure 300 being a thin film encapsulation layer, the flexibility of the display panel 10 may be improved. The display panel 10 may include a first opening 10H formed through the display panel 10. The first opening 10H may be located in the first area RA1 and the second area RA2. Figure 3A In the embodiment, the substrate 100 , the display layer 200 , and the encapsulation structure 300 which is a thin film encapsulation layer respectively include through holes 100H, 200H, and 300H corresponding to the first opening 10H of the display panel 10 .

[0089] In another embodiment, if Figure 3B As shown, the first region RA1 may include the first opening 10H, and the second region RA2 may not include an opening. In the second region RA2, the first opening 10H may not be formed, and the pixel may not be located therein. For example, the display element layer 200A may not be located in the second region RA2. Alternatively, as Figure 3C As shown, the auxiliary display element layer 200C including the sub-pixel may be located in the second region RA2. The auxiliary display element layer 200C may include a display element having a structure or / and an operation method different from the structure or / and an operation method of the display element of the display element layer 200A. In an embodiment, each pixel of the display element layer 200A may include an active matrix OLED, and each pixel of the auxiliary display element layer 200C may include a passive matrix OLED. When the auxiliary display element layer 200C includes a display element of a passive matrix OLED, there may be no elements constituting a pixel circuit under the display element. For example, there may be no thin film transistors and storage capacitors of the pixel circuit layer 200B under the auxiliary display element layer 200C.

[0090] In another embodiment, the auxiliary display element layer 200C may include display elements of the same type as the display elements of the display element layer 200A (e.g., an active matrix OLED), and the structure of the pixel circuits located under the auxiliary display element layer 200C may be different from the structure of the pixel circuits under the display element layer 200A. For example, the pixel circuits located under the auxiliary display element layer 200C (e.g., a pixel circuit including a shielding film located between the substrate 100 and the thin film transistor) may have a structure different from the structure of the pixel circuits located under the display element layer 200A. The display elements of the auxiliary display element layer 200C and the display elements of the display element layer 200A may be operated according to different control signals.

[0091] Components that do not require relatively high transmittance (e.g., infrared sensors) may be located in the second area RA2 where the auxiliary display element layer 200C is located. In this case, the second area RA2 may be understood as a component area and an auxiliary display area. The display element layer 200A and the auxiliary display element layer 200C may be covered by an encapsulation structure 300 that is a thin film encapsulation layer.

[0092] Although thin film encapsulation layers are used as FIG. 3A to FIG. 3C The package structure 300 in FIG. 1 is a block diagram of a package structure 300, but the present disclosure is not limited thereto. The package structure 300 may have different structures, such as the reference FIG. 4A to FIG. 4C As described.

[0093] FIG. 4A to FIG. 4C is a cross-sectional view of a display panel 10 according to another embodiment.

[0094] refer to FIG. 4A to FIG. 4C , the encapsulation structure 300' includes an encapsulation substrate 340. The encapsulation substrate 340 is arranged on the substrate 100 to face the substrate 100, and the display layer 200 is located between the encapsulation substrate 340 and the substrate 100. The sealant 350 may be located between the encapsulation substrate 340 and the substrate 100, and may surround the side surface of the display layer 200. For example, in a plan view, the sealant 350 may surround the display layer 200, such as the display element layer 200A, in the peripheral area PA and the middle area MA. Although the sealant 350 of the middle area MA is located in the cross-sectional view FIG. 4A to FIG. 4C The sealant 350 in the peripheral area PA and the sealant 350 in the middle area MA may be spaced apart from each other.

[0095] like Figure 4AAs shown, the first opening 10H may be formed in each of the first area RA1 and the second area RA2, and each of the first openings 10H may be surrounded by the sealant 350. The encapsulation substrate 340 may include a through hole 340H corresponding to the first opening 10H of the display panel 10. In another embodiment, as Figure 4B As shown, when the first opening 10H is not formed in the second area RA2, the sealant 350 may surround the first opening 10H corresponding to the first area RA1 in the middle area MA. The pixel, such as the display element layer 200A, may not be located in the second area RA2. In another embodiment, as shown in FIG. Figure 4C As shown, the auxiliary display element layer 200C may be located in the second area RA2. The auxiliary display element layer 200C may include a display element having a structure or / and an operation method different from that of the display element layer 200A described above.

[0096] Figure 5 is a plan view of a display panel 10 according to an embodiment.

[0097] refer to Figure 5 , the display panel 10 may include first and second areas RA1 and RA2, a display area DA, a middle area MA, and a peripheral area PA. Figure 5 There may be illustrated a substrate 100 of the display panel 10. For example, the substrate 100 may include first and second areas RA1 and RA2, a display area DA, a middle area MA, and a peripheral area PA.

[0098] The display panel 10 includes a plurality of pixels P located in a display area DA. Each of the pixels P may include a display element such as an OLED. Each pixel P may emit light, such as one of red light, green light, blue light, and white light, through the OLED. The term "pixel" used herein may refer to a pixel that emits one of red light, green light, blue light, and white light as described above. The first area RA1 and the second area RA2 are located inside the display area DA, and the middle area MA is located between the first area RA1 and the second area RA2 and the display area DA.

[0099] The middle area MA may surround the first area RA1 and the second area RA2. The surrounding area PA may surround the display area DA. The first area RA1 and the second area RA2, the middle area MA, and the surrounding area PA are non-display areas in which a light-emitting display element such as an OLED is not located. Signal lines or / and power lines that apply signals to the pixels P may be located in the middle area MA and the surrounding area PA.

[0100] The first driving circuit 110 , the second driving circuit 120 , the terminal 140 , the data driving circuit 150 , the first power line 160 , and the second power line 170 may be located in the peripheral area PA.

[0101] The first drive circuit 110 may include a scan drive circuit and a control drive circuit. The first drive circuit 110 may apply a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL, respectively. The second drive circuit 120 may include a scan drive circuit and a control drive circuit. The second drive circuit 120 may be located opposite the first drive circuit 110, and the display area DA is arranged between the second drive circuit 120 and the first drive circuit 110. Like the first drive circuit 110, the second drive circuit 120 may apply a scan signal and an emission control signal to each pixel P through a scan line SWL and an emission control line EL, respectively.

[0102] The terminal 140 may be located in the surrounding area PA, on one side of the display area DA. The terminal 140 may be exposed without being covered by an insulating layer, and may be electrically connected to a printed circuit board (PCB). The terminal PCB-P of the PCB may be electrically connected to the terminal 140 of the display panel 10. The PCB transmits power or a control signal from the controller to the display panel 10. The control signal generated by the controller may be transmitted to the first drive circuit 110 and the second drive circuit 120 through the PCB. The controller may transmit the first power and the second power (e.g., Figure 6 The first power (e.g., ELVDD and ELVSS) is supplied to the first power line 160 and the second power line 170. The first power (e.g., ELVDD) may be supplied to each pixel P through the driving voltage line PL connected to the first power line 160, and the second power (e.g., ELVSS) may be supplied to the counter electrode of the pixel P connected to the second power line 170.

[0103] The data driving circuit 150 is electrically connected to the data line DL through the pad in the terminal PCB-P and the pad in the terminal 140. The data signal of the data driving circuit 150 can be applied to each pixel P through the connection wiring 151 connected to the terminal 140 and the data line DL connected to the connection wiring 151. Figure 5 The data driving circuit 150 is located on the PCB, but in another embodiment, the data driving circuit 150 may be located on the substrate 100. For example, the data driving circuit 150 may be located between the terminal 140 and the first power line 160 in a plan view.

[0104] The first power line 160 may include first and second sub wirings 162 and 163 extending in the x direction to be parallel to each other, with the display area DA disposed therebetween. The second power line 170 may have a ring shape with an open side, and may partially surround the display area DA.

[0105] Figure 6 is an equivalent circuit diagram illustrating a pixel of the display panel 10 according to the embodiment.

[0106] refer to Figure 6 , each pixel P includes a pixel circuit PC and an OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of TFTs and a storage capacitor. The TFTs and the storage capacitors may be connected to signal lines (e.g., a scan line SWL, a previous scan line SIL, an emission control line EL, and a data line DL), an initialization voltage line VIL, and a drive voltage line PL.

[0107] Despite Figure 6 Each pixel P is connected to a signal line (e.g., SWL, SIL, EL, and DL), an initialization voltage line VIL, and a driving voltage line PL, but the present disclosure is not limited thereto. In another embodiment, at least one of the signal line (e.g., SWL, SIL, EL, and DL), the initialization voltage line VIL, and the driving voltage line PL may be shared by adjacent pixels.

[0108] The plurality of TFTs may include a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a second initialization TFT T7.

[0109] The signal lines include a scanning line SWL transmitting a scanning signal GW, a previous scanning line SIL transmitting a previous scanning signal GI to the first initialization TFT T4 and the second initialization TFT T7, an emission control line EL transmitting an emission control signal EM to the operation control TFT T5 and the emission control TFT T6, and a data line DL crossing the scanning line SWL and transmitting a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initialization voltage line VIL transmits an initialization voltage Vint for initializing the driving TFT T1 and the pixel electrode.

[0110] The driving gate electrode G1 of the driving TFT T1 is connected to the first storage capacitor electrode Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving TFT T1 is connected to the driving voltage line PL through the operation control TFT T5, and the driving drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the OLED through the emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2, and converts the driving current I OLED Supplied to OLED.

[0111] A switching gate electrode G2 of the switching TFT T2 is connected to the scan line SWL, a switching source electrode S2 of the switching TFT T2 is connected to the data line DL, and a switching drain electrode D2 of the switching TFT T2 is connected to the driving source electrode S1 of the driving TFT T1 and is connected to the driving voltage line PL through the operation control TFT T5. The switching TFT T2 is turned on in response to the scan signal GW received through the scan line SWL, and performs a switching operation of transmitting the data signal Dm received through the data line DL to the driving source electrode S1 of the driving TFT T1.

[0112] The compensation gate electrode G3 of the compensation TFT T3 is connected to the scan line SWL, the compensation source electrode S3 of the compensation TFT T3 is connected to the driving drain electrode D1 of the driving TFT T1 and is connected to the pixel electrode of the OLED through the emission control TFT T6, and the compensation drain electrode D3 of the compensation TFT T3 is connected to the first storage capacitor electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal GW received through the scan line SWL, and is diode-connected to the driving TFT T1 by electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1.

[0113] A first initialization gate electrode G4 of the first initialization TFT T4 is connected to the previous scan line SIL, a first initialization source electrode S4 of the first initialization TFT T4 is connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VIL, and a first initialization drain electrode D4 of the first initialization TFT T4 is connected to the first storage capacitor electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on in response to a previous scan signal GI received through the previous scan line SIL, and performs an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving TFT T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1.

[0114] An operation control gate electrode G5 of the operation control TFT T5 is connected to the emission control line EL, an operation control source electrode S5 of the operation control TFT T5 is connected to the driving voltage line PL, and an operation control drain electrode D5 of the operation control TFT T5 is connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0115] The emission control gate electrode G6 of the emission control TFT T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control TFT T6 is connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 is electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the OLED.

[0116] The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on in response to the emission control signal EM received through the emission control line EL, so that the driving voltage ELVDD is transmitted to the OLED and the driving current I OLED Flow through the OLED.

[0117] The second initialization gate electrode G7 of the second initialization TFT T7 is connected to the previous scan line SIL, the second initialization source electrode S7 of the second initialization TFT T7 is connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the OLED, and the second initialization drain electrode D7 of the second initialization TFT T7 is connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VIL. The second initialization TFT T7 is turned on and initializes the pixel electrode of the OLED according to the previous scan signal GI received through the previous scan line SIL.

[0118] Despite Figure 6 The first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SIL, but the present disclosure is not limited thereto. In another embodiment, the first initialization TFT T4 may be connected to the previous scan line SIL and may be driven in response to the previous scan signal GI, and the second initialization TFT T7 may be connected to an additional signal line (e.g., the next scan line) and may be driven in response to a signal transmitted to the additional signal line.

[0119] The second storage capacitor electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the OLED is connected to the line for transmitting the common voltage ELVSS. Therefore, the OLED receives the driving current I from the driving TFT T1. OLED And emit light to display images.

[0120] Despite Figure 6 The compensation TFT T3 and the first initialization TFT T4 have a double gate electrode structure, but the compensation TFT T3 and the first initialization TFT T4 may have one single gate electrode.

[0121] Despite Figure 6 The pixel circuit PC includes seven TFTs and one storage capacitor, but the present disclosure is not limited thereto and may be variously modified. For example, the number of TFTs and storage capacitors may be equal to or less than 6 or equal to or greater than 8. For ease of explanation, the following will be based on the pixel circuit PC being Figure 6 The assumption of the pixel circuit PC in is described.

[0122] Fig. 7A is a plan view illustrating a pixel of the display panel 10 according to the embodiment. Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' and line BB'.

[0123] refer to Fig. 7A and Figure 7B , the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 are disposed along the semiconductor layer 1130. The semiconductor layer 1130 is disposed on the substrate 100. In this regard, Figure 7B In the embodiment, portions 1130a, 1130c, and 1130f of the semiconductor layer 1130 are located on the substrate 100. A buffer layer 2111 including an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride is formed between the substrate 100 and the semiconductor layer 1130.

[0124] Some portions of the semiconductor layer 1130 correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7. In other words, the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensation TFT T3, the first initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the second initialization TFT T7 may be connected to each other and may be formed in various shapes. Figure 7B A driving semiconductor layer 1130a of the driving TFT T1, a compensation semiconductor layer 1130c of the compensation TFT T3, and an emission control semiconductor layer 1130f of the emission control TFT T6 corresponding to portions of the semiconductor layer 1130 are illustrated.

[0125] The semiconductor layer 1130 includes a channel region and a source region and a drain region located on both sides of the channel region. The source region and the drain region can be understood as the source electrode and the drain electrode of the corresponding TFT. For convenience, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0126] The driving TFT T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located at both sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 may have a curved shape such as a capital Greek letter Omega shape to form a long channel width in a narrow space. When the driving channel region has a long channel width, the driving capability of the driving TFT T1 may be increased, and thus the grayscale of light emitted by the OLED may be more finely controlled, and the display quality may be improved.

[0127] The switching TFT T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located at both sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0128] The compensation TFT T3 may have a dual TFT structure. The compensation TFT T3 may include a compensation gate electrode G3 overlapping two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 located on both sides of the compensation channel region. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 through a node connection line 1174 as described below.

[0129] The first initialization TFT T4 having the double TFT structure may include a first initialization gate electrode G4 overlapping two first initialization channel regions, and may include a first initialization source electrode S4 and a first initialization drain electrode D4 located at both sides of the first initialization channel region.

[0130] The operation control TFT T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 located at both sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0131] The emission control TFT T6 may include an emission control gate electrode G6 overlapping the emission control channel region, and an emission control source electrode S6 and an emission control drain electrode D6 located at both sides of the emission control channel region. The emission control source electrode S6 may be connected to the driving drain electrode D1.

[0132] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 located at both sides of the second initialization channel region.

[0133] The above-mentioned TFTs may be connected to signal lines (eg, SWL, SIL, EL, and DL), an initialization voltage line VIL, and a driving voltage line PL.

[0134] Gate insulating layer 2141 (see Figure 7B ) may be located on the semiconductor layer 1130, and the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VIL may be located on the gate insulating layer 2141. The gate insulating layer 2141 may include an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. Each of the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1, and the initialization voltage line VIL may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or an alloy thereof.

[0135] The scan line SWL may extend in the x direction. Some portions of the scan line SWL may correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, portions of the scan line SWL overlapping the channel regions of the switching TFT T2 and the compensation TFT T3 may be the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0136] The previous scan line SIL may extend in the x-direction, and some portions of the previous scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7. For example, portions of the previous scan line SIL that overlap the channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0137] The emission control line EL extends in the x direction. Some portions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6. For example, portions of the emission control line EL that overlap the channel regions of the operation control TFT T5 and the emission control TFT T6 may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0138] The driving gate electrode G1 may have an island shape, and may be connected to the compensation TFT T3 through a node connection line 1174 .

[0139] The initialization voltage line VIL extends in the x direction. The initialization voltage line VIL may be connected to the first initialization TFT T4 and the second initialization TFT T7 through an initialization connection line 1173 as described below.

[0140] Despite Figure 7B The initialization voltage line VIL is located on the first interlayer insulating layer 2143, but in another embodiment, the initialization voltage line VIL may be located on the planarization insulating layer 2180 (see Figure 7B ), and may include the same material as that of the pixel electrode 210.

[0141] The electrode voltage line HPL may be located on the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1 and the initialization voltage line VIL, and includes a first interlayer insulating layer 2143 of an inorganic material (see Figure 7B ) is located between the electrode voltage line HPL and the scan line SWL, the previous scan line SIL, the emission control line EL, the driving gate electrode G1 and the initialization voltage line VIL.

[0142] The electrode voltage line HPL may extend in the x direction to cross the data line DL and the driving voltage line PL. Fig. 7A As shown. A portion of the electrode voltage line HPL may cover at least a portion of the driving gate electrode G1 and may form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may be a first storage capacitor electrode Cst1 of the storage capacitor Cst, and a portion of the electrode voltage line HPL may be a second storage capacitor electrode Cst2 of the storage capacitor Cst.

[0143] The electrode voltage line HPL and the second storage capacitor electrode Cst2 are electrically connected to the driving voltage line PL. Fig. 7A In the embodiment, the electrode voltage line HPL is connected to the driving voltage line PL located on the electrode voltage line HPL through the contact hole 1158. The electrode voltage line HPL and the driving voltage line PL may have the same voltage level (eg, a constant voltage). The electrode voltage line HPL may be understood as a horizontal driving voltage line.

[0144] Since the driving voltage line PL extends in the y direction and the electrode voltage line HPL electrically connected to the driving voltage line PL extends in the x direction crossing the y direction, the plurality of driving voltage lines PL and the plurality of electrode voltage lines HPL may form a grid structure in the display area.

[0145] The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may be located on the second storage capacitor electrode Cst2 and the electrode voltage line HPL, and the second interlayer insulating layer 2150 including an inorganic material (see Figure 7B) is located between the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 and the second storage capacitor electrode Cst2 and the electrode voltage line HPL. Each of the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may include aluminum (Al), copper (Cu) or titanium (Ti), and may have a single-layer or multi-layer structure. In an embodiment, each of the driving voltage line PL and the data line DL may have a multi-layer structure formed of Ti / Al / Ti.

[0146] The data line DL may extend in the y direction, and may be connected to the switching source electrode S2 of the switching TFT T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0147] The driving voltage line PL extends in the y direction and is connected to the electrode voltage line HPL through the contact hole 1158 as described above. In addition, the driving voltage line PL may be connected to the operation control TFT T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0148] One end of the initialization connection line 1173 may be connected to the first and second initialization TFTs T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VIL through the contact hole 1151 .

[0149] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156, and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157. The metal layer 1175 may be connected to the emission control drain electrode D6 through the contact hole 1153, and the pixel electrode 210 may be connected to the metal layer 1175 through the contact hole 1163.

[0150] A planarization insulating layer 2180 including an organic insulating material is located on the data line DL, the driving voltage line PL, the initialization link line 1173 , and the node link line 1174 , and the pixel electrode 210 is located on the planarization insulating layer 2180 .

[0151] refer to Fig. 7A and Figure 7B, one end of the pixel electrode 210 may be covered by a pixel defining film 2190 on the planarization insulating layer 2180, and the central portion of the pixel electrode 210 may be exposed through the opening of the pixel defining film 2190. The pixel electrode 210 may include a reflective film, the reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In another embodiment, the pixel electrode 210 may further include a layer of ITO, IZO, ZnO or In located above or below the reflective film. 2 O 3 The intermediate layer 220 is located on the pixel electrode 210 exposed through the opening.

[0152] The intermediate layer 220 includes an emission layer 222 on the pixel electrode 210 exposed through the opening of the pixel defining film 2190. The emission layer 222 may include a high molecular weight organic material or a low molecular weight organic material that emits light of a predetermined color. In an embodiment, the intermediate layer 220 may include a first functional layer 221 located below the emission layer 222 and / or a second functional layer 223 located above the emission layer 222, such as Figure 7B shown.

[0153] The first functional layer 221 may have a single layer or a multilayer structure. For example, when the first functional layer 221 is formed of a high molecular weight material, the first functional layer 221 is a hole transport layer (HTL) having a single layer structure, which may be formed of poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). When the first functional layer 221 is formed of a low molecular weight material, the first functional layer 221 may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0154] The second functional layer 223 is optional. For example, when each of the first functional layer 221 and the emission layer 222 is formed of a high molecular weight material, in order to improve the characteristics of the OLED, the second functional layer 223 is preferably formed. The second functional layer 223 may have a single layer or a multilayer structure. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0155] The counter electrode 230 faces the pixel electrode 210, and the intermediate layer 220 is arranged between the counter electrode 230 and the pixel electrode 210. The counter electrode 230 can be formed of a conductive material having a low work function. For example, the counter electrode 230 may include a (semi) transparent layer, which includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca) or an alloy thereof. Alternatively, the counter electrode 230 may further include a (semi) transparent layer composed of ITO, IZO, ZnO or In2 O 3 The formed layer.

[0156] refer to Figure 7B The layers of the display layer 200 described above (eg, the layers from the buffer layer 2111 to the counter electrode 230) may be composed of FIG. 3A to FIG. 4C The thin film encapsulation layer or encapsulation substrate is covered.

[0157] Figure 8 1 is a plan view illustrating first lines located in the middle area MA of the display panel 10 according to the embodiment. The following description will be made based on the assumption that the first lines include data lines according to the embodiment.

[0158] refer to Figure 8 , the first region RA1 and the second region RA2 may be spaced apart from each other by a predetermined interval. For example, the first region RA1 and the second region RA2 may be spaced apart from each other in the x direction. A first line (or a vertical line) extending in a direction intersecting the x direction (e.g., the y direction) may be located in the middle region MA surrounding the first region RA1 and the second region RA2. Figure 8 In the embodiment, some of the data lines DLa, DLb, DLc, DLd, and DLe pass through the middle area MA as first lines.

[0159] For convenience of explanation, among the data lines DLa, DLb, and DLc passing through the middle area MA, the data lines DLa passing between the first area RA1 and the second area RA2 are referred to as a first group. Figure 8 The data lines DLb on one side (e.g., the left side) of the first group of data lines DLa in the image are referred to as the second group, and the data lines DLc arranged on the other side (e.g., the right side) of the first group of data lines DLa are referred to as the third group. The portion of the middle area MA where the first group of data lines DLa are arranged is referred to as the first sub-middle area SMA1, the portion of the middle area MA where the second group of data lines DLb are arranged is referred to as the second sub-middle area SMA2, and the portion of the middle area MA where the third group of data lines DLc are arranged is referred to as the third sub-middle area SMA3. The first to third sub-middle areas SMA1, SMA2, and SMA3 may be arranged along the x-direction. The first sub-middle area SMA1 may be an area between the first point VCP1 and the second point VCP2, the second sub-middle area SMA2 may be an area between the first point VCP1 and the left end of the middle area MA, and the third sub-middle area SMA3 may be an area between the second point VCP2 and the right end of the middle area MA.

[0160] The first to third groups of data lines DLa, DLb, and DLc may extend substantially in the y direction in a plan view to apply signals to pixels arranged at the upper or lower portion of the middle area MA, and may go around the first area RA1 and the second area RA2 along the edges of the first area RA1 and the second area RA2 in the middle area MA. In the first to third groups of data lines DLa, DLb, and DLc, the spacing (or interval) Δd between adjacent (neighboring) data lines in the middle area MA may be smaller than the spacing (or interval) Δp between adjacent data lines in the display area DA. For example, the spacing (or interval) Δd between adjacent data lines located between the first area RA1 and the second area RA2 may be smaller than the spacing (or interval) Δp between adjacent data lines located in the display area DA.

[0161] Referring to the vicinity of the first area RA1, some of the first group of data lines DLa may bypass one side of the first area RA1 (eg, Figure 8 The second group of data lines DLb may be arranged around an edge of the first region RA1 (eg, the right side of the first region RA1), and the second group of data lines DLb may be arranged along the other side of the first region RA1 (eg, Figure 8 Some of the first group of data lines DLa and the second group of data lines DLb may bypass the first area RA1 by extending in opposite directions relative to the first point VCP1. The first point VCP1 may be located on a first vertical virtual line VCL1 that passes through a first center C1 of the first area RA1 and extends in the y direction.

[0162] The data lines bypassing the first area RA1 (eg, some of the data lines in the second group of data lines DLb and the first group of data lines DLa) may be symmetrical about the first vertical virtual line VCL1.

[0163] Referring to the vicinity of the second area RA2, some of the first group of data lines DLa may bypass one side of the second area RA2 (eg, Figure 8 The third group of data lines DLc may be around the edge of the second area RA2 (eg, the left side of the second area RA2), and the third group of data lines DLc may be around the other side of the second area RA2 (eg, Figure 8 The second point VCP2 is not located on the second vertical virtual line VCL2 that passes through the second center C2 of the second area RA2 and extends in the y direction. The second point VCP2 may be offset from the second vertical virtual line VCL2 toward the right edge of the second area RA2 in the x direction. For example, Figure 8As shown, the second point VCP2 can be separated from the second vertical virtual line VCL2 in the x direction and can be positioned away from the first region RA1. For example, Figure 8 the second point VCP2 of Figure 8 can be located on the right side of the second vertical virtual line VCL2.

[0164] The data lines bypassing the second region RA2 (e.g., some of the third group of data lines DLc and the first group of data lines DLa) can be asymmetric with respect to the second vertical virtual line VCL2.

[0165] Since the second point VCP2 is offset from the second vertical virtual line VCL2 in the x direction, a relatively large number of the data lines bypassing the second region RA2 can be located in the first sub-intermediate region SMA1. The number of the first group of data lines DLa located in the first sub-intermediate region SMA1 can be greater than half of the sum of the numbers of the data lines DLa, DLb, and DLc passing through the intermediate region MA. For example, the number of the first group of data lines DLa located in the first sub-intermediate region SMA1 can be greater than the sum of the numbers of the second group of data lines DLb located in the second sub-intermediate region SMRA2 and the third group of data lines DLc located in the third sub-intermediate region SMRA3.

[0166] Since a relatively large number of the data lines passing through the intermediate region MA are located in the first sub-intermediate region SMA1, the second width W2 of the second sub-intermediate region SMRA2 and the third width W3 of the third sub-intermediate region SMRA3 can be reduced. Each of the second width W2 of the second sub-intermediate region SMRA2 and the third width W3 of the third sub-intermediate region SMRA3 can be less than the first width W1 of the first sub-intermediate region SMA1. The sum of the second width W2 of the second sub-intermediate region SMA2 and the third width W3 of the third sub-intermediate region SMA3 can be less than the first width W1 of the first sub-intermediate region SMA1 (W2 + W3 < W1). The first width W1 can be the shortest width between the first region RA1 and the second region RA2. The second width W2 can be the shortest width between one end (boundary) of the intermediate region MA and the first region RA1, and the third width W3 can be the shortest width between one end (boundary) of the intermediate region MA and the second region RA2. In an embodiment, the second width W2 and the third width W3 can be measured on the extension line connecting the first center C1 to the second center C2. In an embodiment, the boundary of the intermediate region MA can be defined as a closed-loop shaped region formed by the pixels arranged closest to the intermediate region MA in the display region DA and configured to surround the intermediate region MA.

[0167] Fig. 9A is a diagram Figure 8 of the plan view of the first line. Fig. 9B is Fig. 9AModifications. Fig. 9A and Fig. 9B In the embodiment, the first line includes the data line according to the embodiment.

[0168] Fig. 9A and Fig. 9B The first data line DL1 is Figure 8 The second data line DL2 is one of the second data lines DLb of the Figure 8 One of the first group of data lines DLa bypasses the first area RA1. Fig. 9A and Fig. 9B The third data line DL3 is Figure 8 One of the first data lines DLa bypasses the second area RA2, and the fourth data line DL4 is Figure 8 One of the third group of data lines DLc.

[0169] refer to Fig. 9A , the first data line DL1 and the second data line DL2 are positioned adjacent to each other, and the first vertical virtual line VCL1 is inserted between the first data line DL1 and the second data line DL2. The first point VCP1 may be located between the adjacent first data line DL1 and the second data line DL2. The first point VCP1 may be located on the first vertical virtual line VCL1. The first data line DL1 extends to bypass around the left edge of the first area RA1, and the second data line DL2 extends to bypass around the right edge of the first area RA1. The central angle α1 of the bypass portion DL1-C of the first data line DL1 may be the same as the central angle α2 of the bypass portion DL2-C of the second data line DL2.

[0170] The third data line DL3 and the fourth data line DL4 may be positioned adjacent to each other, and the second point VCP2 may be located between the adjacent third data line DL3 and the fourth data line DL4. The second point VCP2 may be offset from the second vertical virtual line VCL2 by a predetermined interval (distance) in the x direction. The third data line DL3 extends to bypass around the left edge of the second area RA2, and the fourth data line DL4 extends to bypass around the right edge of the second area RA2. The central angle β1 of the bypass portion DL3-C of the third data line DL3 may be different from the central angle β2 of the bypass portion DL4-C of the fourth data line DL4. For example, the central angle β1 of the bypass portion DL3-C of the third data line DL3 may be greater than the central angle β2 of the bypass portion DL4-C of the fourth data line DL4.

[0171] The central angles α1, α2, β1, and β2 may be included angles of arcs of the bypass portions DL1-C, DL2-C, DL3-C, and DL4-C.

[0172] Although the bypass portions DL1-C, DL2-C, DL3-C, and DL4-C of the first to fourth data lines DL1, DL2, DL3, and DL4 are Fig. 9A In another embodiment, the bypass portions DL1-C, DL2-C, DL3-C, and DL4-C may have a stair-shaped line with a zigzag configuration.

[0173] refer to Fig. 9A , the bypass portions DL1-C, DL2-C, DL3-C and DL4-C of the first to fourth data lines DL1, DL2, DL3 and DL4 may be formed integrally with the linear portions DL1-L, DL2-L, DL3-L and DL4-L, respectively. In another embodiment, the bypass portions DL1-C, DL2-C, DL3-C and DL4-C of one or more of the first to fourth data lines DL1, DL2, DL3 and DL4 may be disposed on a layer different from a layer on which the linear portions DL1-L, DL2-L, DL3-L and DL4-L are disposed, and may be connected to the linear portions DL1-L, DL2-L, DL3-L and DL4-L, respectively, through contact holes. In this regard, in Fig. 9B In the embodiment, the bypass portions DL1-C, DL2-C, DL3-C and DL4-C of the first to fourth data lines DL1, DL2, DL3 and DL4 are respectively connected to the linear portions DL1-L, DL2-L, DL3-L and DL4-L through the contact holes CNT.

[0174] Fig. 10A is along Figure 8 1 and 2 are cross-sectional views taken along lines Xa-Xa′ and Xb-Xb′ of the display panel 10 , which illustrate first lines located in the middle area MA of the display panel 10 according to the embodiment. Fig. 10B is along Figure 8 1 is a cross-sectional view taken along lines Xa-Xa' and Xb-Xb' of FIG. 1 , which illustrates a first line located in the middle area MA of the display panel 10 according to another embodiment. Fig. 10A and Fig. 10B In the embodiment, the first line includes a data line.

[0175] refer to Fig. 10A The first group of data lines DLa and the second group of data lines DLb are located on the same layer. The first group of data lines DLa and the second group of data lines DLb may be located on the second interlayer insulating layer 2150 .

[0176] The first group of data lines DLa may be arranged to have a first interval Δd1, and the second group of data lines DLb may be arranged to have a second interval Δd2. The first interval Δd1 and the second interval Δd2 may be Figure 8The first distance Δd1 and the second distance Δd2 may be the same or different from each other.

[0177] refer to Fig. 10B , adjacent data lines in the first group of data lines DLa and the second group of data lines DLb may be located on different layers. For example, one of the adjacent data lines DLa of the first group may be located on the second interlayer insulating layer 2150, and the remaining one of the adjacent data lines DLa of the first group may be located on the third interlayer insulating layer 2160. Similarly, one of the adjacent data lines DLb of the second group may be located on the second interlayer insulating layer 2150, and the remaining one may be located on the third interlayer insulating layer 2160. Alternatively, one of the adjacent data lines DLb of the second group may be located on the first interlayer insulating layer 2143, and the remaining one may be located on the second interlayer insulating layer 2150. Similarly, adjacent data lines DLc of the third group may be located on different layers, with insulating layers located between different layers.

[0178] Despite Fig. 10A Compared to Fig. 10B A third interlayer insulating layer 2160 is further provided in the embodiment, but in another embodiment, one of the adjacent data lines DLa of the first group may be located on the first interlayer insulating layer 2143 and the remaining one may be located on the second interlayer insulating layer 2150.

[0179] When adjacent data lines are located on different layers, the first spacing (or first interval) Δd1′ between the first group of data lines DLa may be smaller than Fig. 10A Similarly, the second spacing (or second spacing) Δd2′ between the second group of data lines DLb may be less than Fig. 10A The second spacing (or second interval) Δd2. Fig. 10B In the embodiment, the first interval Δd1 ′ and the second interval Δd2 ′ may be the same as or different from each other.

[0180] Fig.11 1 is a plan view illustrating a second line located in the middle area MA of the display panel 10 according to the embodiment. Fig.11 In the embodiment, the second line includes a scan line according to an embodiment.

[0181] refer to Fig.11 , a second line (or horizontal line) extending in the x-direction may be located in the middle area MA surrounding the first area RA1 and the second area RA2 spaced apart from each other in the x-direction. Fig.11 In the embodiment, the second lines include a first group of scan lines SWLa and a second group of scan lines SWLb passing through the middle area MA.

[0182] In a plan view, the first group of scan lines SWLa and the second group of scan lines SWLb may extend in the x direction to apply signals to pixels located on the left and right sides of the middle area MA, and may bypass edges of the first area RA1 and the second area RA2 in the middle area MA. In the first group of scan lines SWLa and the second group of scan lines SWLb, a spacing (or interval) Δd' between adjacent scan lines in the middle area MA may be smaller than a spacing (or interval) Δp' between adjacent scan lines in the display area DA.

[0183] The first group of scan lines SWLa and the second group of scan lines SWLb may be symmetrical about the first horizontal virtual line HCL1 and the second horizontal virtual line HCL2 passing through the first center C1 and the second center C2. For example, the first group of scan lines SWLa arranged on the lower side of the virtual line connecting the first center C1 and the second center C2 may extend to bypass the lower edge of the first area RA1 and the second area RA2, and the second group of scan lines SWLb arranged on the upper side of the virtual line connecting the first center C1 and the second center C2 may extend to bypass the upper edge of the first area RA1 and the second area RA2. The number of the first group of scan lines SWLa and the number of the second group of scan lines SWLb may be the same.

[0184] Although the bypass portions of the first group of scan lines SWLa and the second group of scan lines SWLb are Fig.11 In another embodiment, the bypass portion may have a stair-shaped line with a zigzag configuration.

[0185] refer to Figure 8 and Fig.11 , a first line (e.g., a data line) passing through the vicinity of the second area RA2 may be asymmetric about a second vertical virtual line VCL2 passing through a second center C2 in the second area RA2, and a second line (e.g., a scan line) passing through the vicinity of the first area RA1 and the second area RA2 may be symmetric about a first horizontal virtual line HCL1 and a second horizontal virtual line HCL2 passing through the first center C1 and the second center C2 of the first area RA1 and the second area RA2.

[0186] Fig.12 is a plan view illustrating a first line located in the middle area MA of the display panel 10 according to another embodiment. Fig.13 is a plan view illustrating a second line located in the middle area MA of the display panel 10 according to another embodiment.

[0187] Although in Figure 8 The first region RA1 and the second region RA2 are separated from each other in the x direction, but Fig.12 and Fig.13The first region RA1 and the second region RA2 may be spaced apart from each other in an oblique (ob) direction that is inclined with respect to the x-direction and the y-direction. Fig.12 The first line is the data line, and Fig.13 The second line is the scan line.

[0188] refer to Fig.12 , the first to third groups of data lines DLa, DLb and DLc are located around the first area RA1 and the second area RA2 set in the ob direction. The first to third groups of data lines DLa, DLb and DLc may extend in the y direction crossing the ob direction and may bypass the edge of the first area RA1 or the second area RA2. The structures of the first to third groups of data lines DLa, DLb and DLc are similar to those of reference Figures 8 to 10B The structure described above is the same. For example, some of the first group of data lines DLa and the second group of data lines DLb may bypass the first area RA1 by extending from the first point VCP1 in opposite directions. Some of the first group of data lines DLa and the third group of data lines DLc may bypass the second area RA2 by extending from the second point VCP2 in opposite directions. The first point VCP1 may be located on the first vertical virtual line VCL1 that passes through the first center C1 and extends in the y direction, and the second point VCP2 may not be located on the second vertical virtual line VCL2 that passes through the second center C2 of the second area RA2 and extends in the y direction. The data lines bypassing the second area RA2 in the first area RA1 and the second area RA2 may be asymmetric, as described above with reference to FIG. Figure 8 The number of the first group of data lines DLa in the first sub-middle area SMA1 may be greater than the sum of the numbers of the second group of data lines DLb and the third group of data lines DLc in the second sub-middle area SMA2 and the third sub-middle area SMA3.

[0189] refer to Fig.13 , the first to third groups of scan lines SWLa, SWLb and SWLc are located around the first domain RA1 and the second region RA2 set in the ob direction. The first to third groups of scan lines SWLa, SWLb and SWLc may be located in the first to third sub-middle regions SMA1', SMA2' and SMA3', respectively. Fig.13 , the first to third sub-middle areas SMA1', SMA2' and SMA3' may be arranged in the y direction. The first sub-middle area SMA1' may be an area between the third point HCP1 and the fourth point HCP2, the second sub-middle area SMA2' may be an area between the third point HCP1 and the lower end of the middle area MA, and the third sub-middle area SMA3' may be an area between the fourth point HCP2 and the upper end of the middle area MA.

[0190] The first to third groups of scan lines SWLa, SWLb, and SWLc may extend in the x direction crossing the ob direction, and may detour around the edge of the first area RA1 or the second area RA2.

[0191] Referring to the vicinity of the first region RA1, some of the first group of scan lines SWLa may bypass one side of the first region RA1 (eg, Fig.13 The second group of scan lines SWLb may bypass the edge of the first region RA1 (eg, the upper side of the first region RA1), and the second group of scan lines SWLb may bypass the other side of the first region RA1 (eg, Fig.13 Some of the first group of scan lines SWLa and the second group of scan lines SWLb may bypass the first area RA1 by extending from the third point HCP1 in opposite directions. The third point HCP1 may be located on a first horizontal virtual line HCL1 that passes through the first center C1 and extends in the x-direction.

[0192] The scan lines bypassing the first area RA1 (eg, some scan lines of the first group of scan lines SWLa and the second group of scan lines SWLb) may be symmetrical about the first horizontal virtual line HCL1.

[0193] Referring to the vicinity of the second area RA2, some of the first group of scan lines SWLa may bypass one side of the second area RA2 (eg, Fig.13 The edge of the lower side of the second area RA2 may be around the edge of the lower side of the second area RA2, and may go around the other side of the second area RA2 (for example, Fig.13 Some of the first group of scan lines SWLa and the third group of scan lines SWLc may bypass the second area RA2 by extending from the fourth point HCP2 in the opposite direction. The fourth point HCP2 is not located on the second horizontal virtual line HCL2 that passes through the second center C2 of the second area RA2 and extends in the x direction. The fourth point HCP2 may be offset from the second horizontal virtual line HCL2 toward the upper edge of the second area RA2 in the y direction. For example, Fig.13 As shown, the fourth point HCP2 may be spaced apart from the second horizontal virtual line HCL2 in the y direction and may be located away from the first area RA1. Fig.13 In the embodiment, the fourth point HCP2 may be located above the second horizontal virtual line HCL2.

[0194] The scan lines bypassing the second area RA2 (eg, some scan lines of the first group of scan lines SWLa and the third group of scan lines SWLc) may be asymmetric with respect to the second horizontal virtual line HCL2.

[0195] Since the fourth point HCP2 is offset from the second horizontal virtual line HCL2 in the y-direction, a relatively large number of scan lines among the scan lines bypassing the second area RA2 may be located in the first sub-middle area SMA1 ′.

[0196] The number of the first group of scan lines SWLa located in the first sub-middle area SMA1' may be greater than half of the sum of the numbers of the scan lines SWLa, SWLb, and SWLc passing through the middle area MA. For example, the number of the first group of scan lines SWLa located in the first sub-middle area SMA1' may be greater than the sum of the numbers of the second group of scan lines SWLb and the third group of scan lines SWLc located in the second sub-middle area SMRA2' and the third sub-middle area SMRA3'.

[0197] Fig.14 It is a graphic Fig.13 The floor plan of the second line. Fig.14 The second line may include a reference Fig.13 Describes the scan line.

[0198] Fig.14 The first scan line SWL1 may be Fig.13 The second scanning line SWL2 is one of the second scanning lines SWLb of Fig.13 The third scan line SWL3 may be one of the first scan lines SWLa that bypasses the first area RA1. Fig.13 One of the first scan lines SWLa of the present invention bypasses the second area RA2, and the fourth scan line SWL4 is Fig.13 One of the third group of scan lines SWLc.

[0199] refer to Fig.14 , the first scan line SWL1 and the second scan line SWL2 are positioned adjacent to each other, and the first horizontal virtual line HCL1 is arranged between the first scan line SWL1 and the second scan line SWL2. The third point HCP1 may be located between the adjacent first scan line SWL1 and the second scan line SWL2. The third point HCP1 may be located on the first horizontal virtual line HCL1. The first scan line SWL1 bypasses around the lower edge of the first area RA1 from the third point HCP1, and the second scan line SWL2 bypasses around the upper edge of the first area RA1 from the third point HCP1. The central angle α3 of the bypass portion SWL1-C of the first scan line SWL1 may be the same as the central angle α4 of the bypass portion SWL2-C of the second scan line SWL2.

[0200] The third scan line SWL3 and the fourth scan line SWL4 may be positioned adjacent to each other, and the fourth point HCP2 may be located between the adjacent third scan line SWL3 and fourth scan line SWL4. The fourth point HCP2 may be offset from the second horizontal virtual line HCL2 by a predetermined distance. The third scan line SWL3 bypasses around the lower edge of the second area RA2 from the fourth point HCP2, and the fourth scan line SWL4 bypasses around the upper edge of the second area RA2 from the fourth point HCP2. The central angle β3 of the bypass portion SWL3-C of the third scan line SWL3 may be different from the central angle β4 of the bypass portion SWL4-C of the fourth scan line SWL4. For example, the central angle β3 of the bypass portion SWL3-C of the third scan line SWL3 may be greater than the central angle β4 of the bypass portion SWL4-C of the fourth scan line SWL4.

[0201] The central angles α3, α4, β3, and β4 may be included angles of arcs of the bypass portions SWL1-C, SWL2-C, SWL3-C, and SWL4-C.

[0202] Although the bypass portions SWL1-C, SWL2-C, SWL3-C, and SWL4-C of the first to fourth scan lines SWL1, SWL2, SWL3, and SWL4 are Fig.14 Although illustrated as a curved line, in another embodiment, the bypass portions SWL1-C, SWL2-C, SWL3-C and SWL4-C may have a stepped shape with a zigzag configuration.

[0203] The bypass portions SWL1-C, SWL2-C, SWL3-C, and SWL4-C and the linear portions of the first to fourth scan lines SWL1, SWL2, SWL3, and SWL4 may be located on the same layer. Fig. 9B Like the data lines described, the bypass portions SWL1-C, SWL2-C, SWL3-C and SWL4-C of the first to fourth scan lines SWL1, SWL2, SWL3 and SWL4 may be located on a layer different from a layer on which the linear portions are located, and may be respectively connected to the linear portions through contact holes.

[0204] Fig.15 and Fig.16 1 is a plan view illustrating a first line located in the middle area MA of the display panel 10 according to other embodiments. Fig.15 and Fig.16 In the embodiment, the first line includes the data line according to the embodiment.

[0205] refer to Fig.15 and Fig.16The third area RA3 may be located between the first area RA1 and the second area RA2. The structures and characteristics of the first to third groups of data lines DLa, DLb, and DLc in the first area RA1 and the second area RA2 are similar to those in the reference Figures 8 to 10B The structures and characteristics described are the same. The following will focus on the data lines of the third area RA3.

[0206] refer to Fig.15 , the first group of data lines DLa is located around the third area RA3. Some of the first group of data lines DLa may extend from the fifth point VCP3 toward the left side of the third area RA3 and may bypass around the left edge of the third area RA3, and some of the first group of data lines DLa may extend from the fifth point VCP3 toward the right side of the third area RA3 and may bypass around the right edge of the third area RA3. The fifth point VCP3 may be located on a third vertical virtual line VCL3 passing through a third center C3 of the third area RA3.

[0207] The data lines bypassing the third area RA3 (eg, some data lines in the first group of data lines DLa) may be symmetrical about the third vertical virtual line VCL3.

[0208] In another embodiment, reference Fig.16 , the data lines bypassing the third area RA3 (e.g., some of the first group of data lines DLa) may be asymmetric about the third vertical virtual line VCL3. In this case, the fifth point VCP3 may be offset from the third vertical virtual line VCL3 passing through the third center C3 of the third area RA3. Fig.16 In the embodiment, the fifth point VCP3 is offset from the third vertical virtual line VCL3 to be close to the second area RA2. That is, the fifth point VCP3 may be located on the right side of the third vertical virtual line VCL3. In another embodiment, the fifth point VCP3 may be offset from the third vertical virtual line VCL3 to be close to the first area RA1.

[0209] When Fig.15 and Fig.16 When a third area RA3 is further provided as shown, the second line (eg, scan line) may be as shown in FIG. Fig.11 Set up as described.

[0210] Despite Fig.15 and Fig.16 One third area RA3 is located between the first area RA1 and the second area RA2, but two or more third areas RA3 may be located between the first area RA1 and the second area RA2.

[0211] Fig.17 is a plan view illustrating a first line located in the middle area MA of the display panel 10 according to another embodiment. Fig.18 is a plan view illustrating a second line located in the middle area MA of the display panel 10 according to another embodiment.

[0212] refer to Fig.17 and Fig.18 , the first area RA1 and the second area RA2 are arranged in the ob direction inclined relative to the x direction and the y direction. The ob direction may intersect the x direction and / or the y direction. The third area RA3 may be located between the first area RA1 and the second area RA2 in the ob direction. For example, the third area RA3 may be located between the first area RA1 and the second area RA2 in the x direction and the y direction.

[0213] The data lines around the first area RA1 and the second area RA2 arranged in the ob direction are aligned with the reference Fig.12 The data lines described are the same, and therefore, the following will focus on the data lines around the third area RA3.

[0214] refer to Fig.17 , the first group of data lines DLa is located around the third area RA3. Some of the first group of data lines DLa may extend from the fifth point VCP3 to bypass the left edge of the third area RA3, and some of the first group of data lines DLa may extend from the fifth point VCP3 to bypass the right edge of the third area RA3. Fig.17 The fifth point VCP3 is located on the third vertical virtual line VCL3 passing through the third center C3 of the third area RA3, but the present disclosure is not limited thereto. In another embodiment, the fifth point VCP3 may be offset from the third vertical virtual line VCL3 in the x direction, and in this case, the data lines around the third area RA3 may be aligned with the reference line VCL3. Fig.16 The data lines described are identical.

[0215] refer to Fig.18 , the scanning lines around the first area RA1 and the second area RA2 set in the ob direction are aligned with the reference Fig.13 The scan lines described are the same, and therefore, the following will focus on the scan lines around the third area RA3.

[0216] When inspecting the vicinity of the third area RA3, some of the first group of scan lines SWLa may bypass one side of the third area RA3 (for example, Fig.18 and some of the first group of scan lines SWLa may bypass the other side of the third area RA3 (for example, Fig.18The scan lines in the first group of scan lines SWLa may bypass the third area RA3 by extending from the sixth point HCP3 in the opposite direction. The sixth point HCP3 may be located on a third horizontal virtual line HCL3 that passes through a third center C3 of the third area RA3 and extends in the x direction. Alternatively, the sixth point HCP3 may be offset from the third horizontal virtual line HCL3 in the y direction, and in this case, the scan lines bypassing the third area RA3 may be asymmetric about the third horizontal virtual line HCL3.

[0217] Fig.19 is a plan view illustrating a second line located in the middle area MA of the display panel 10 according to another embodiment.

[0218] refer to Fig.19 , the first area RA1 and the second area RA2 may be spaced apart from each other in the y direction. The first group of scan lines SWLa is located between the first area RA1 and the second area RA2. The second group of scan lines SWLb may be positioned adjacent to the first group of scan lines SWLa, the first area RA1 is arranged between the second group of scan lines SWLb and the first group of scan lines SWLa, and the third group of scan lines SWLc may be positioned adjacent to the first group of scan lines SWLa, the second area RA2 is arranged between the third group of scan lines SWLc and the first group of scan lines SWLa.

[0219] Referring to the vicinity of the first area RA1, some of the first group of scan lines SWLa and the second group of scan lines SWLb may bypass around the edge of the first area RA1 by extending from a third point HCP1 in opposite directions. The third point HCP1 may be located on a first horizontal virtual line HCL1 that passes through the first center C1 and extends in the x-direction.

[0220] Referring to the vicinity of the second area RA2, some of the first group of scan lines SWLa and the third group of scan lines SWLc bypass the second area RA2 by extending from the fourth point HCP2 in the opposite direction. The fourth point HCP2 is not located on the second horizontal virtual line HCL2 that passes through the second center C2 of the second area RA2 and extends in the x direction. The fourth point HCP2 may be offset from the second horizontal virtual line HCL2 in the y direction.

[0221] Fig.19 The arrangement of the first to third groups of scanning lines SWLa, SWLb and SWLc can be the same as that of the reference Fig.13 The arrangement described is essentially the same. Fig.19 When the direction (eg, the y direction) in which the first region RA1 and the second region RA2 are arranged is substantially perpendicular to the direction in which the scan line extends (eg, the x direction), and as shown in FIG. Fig.13As shown, when the direction in which the first area RA1 and the second area RA2 are set (e.g., the ob direction) is set to cross the direction in which the scan line extends (e.g., the x direction) to form an acute angle, the scan line in the middle area MA can be symmetrical about any one of the first area RA1 and the second area RA2, and can be asymmetrical about the remaining one of the first area RA1 and the second area RA2.

[0222] Although the first line includes a data line and the second line includes a scan line in the above embodiment, the present disclosure is not limited thereto. In another embodiment, the first line may include Fig. 7A The driving voltage line PL, and the second line may include Fig. 7A The previous scan line SIL, the emission control line EL, the electrode voltage line HPL and / or the initialization voltage line VIL.

[0223] According to one or more embodiments, since the lines around the area corresponding to a component such as a sensor or a camera are set asymmetrically, the dead zone between the display area and the area can be reduced. However, the technical effects of the present disclosure are not limited thereto, and based on the above description, other unmentioned technical effects will be obvious to those of ordinary skill in the art.

[0224] While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel, comprising: a substrate including a display area in which a plurality of light emitting diodes are arranged, a first area having a circular shape and a second area having a shape different from that of the first area, which are surrounded by the display area and are disposed to be spaced apart from each other in a first direction, and a non-display area surrounding the first area and the second area; as well as a plurality of data lines extending in a second direction intersecting the first direction in the display area, the plurality of data lines being electrically connected to the plurality of light emitting diodes, respectively; Wherein, the plurality of data lines include: A plurality of first data lines are arranged in the non-display area, bypassing the first area and along a first side of the first area; A plurality of second data lines, bypassing the first area in the non-display area and arranged along a second side of the first area opposite to the first side; A plurality of third data lines, bypassing the second area in the non-display area and disposed along a first side of the second area; and a plurality of fourth data lines, which are arranged in the non-display area, bypassing the second area and along a second side of the second area opposite to the first side of the second area, The number of the plurality of first data lines is the same as the number of the plurality of second data lines, and The number of the third data lines is different from the number of the fourth data lines.

2. The display panel according to claim 1, wherein: The number of the third data lines is greater than the number of the fourth data lines.

3. The display panel according to claim 1, wherein: The bypass portions of the plurality of second data lines and the bypass portions of the plurality of third data lines are disposed between the first area and the second area in the non-display area.

4. The display panel according to claim 3, wherein: Relative to a first virtual center line passing through the center of the first area in the second direction, a bypass portion of a data line among the multiple first data lines that is disposed closest to the first side of the first area is symmetrical to a bypass portion of a data line among the multiple second data lines that is disposed closest to the second side of the first area.

5. The display panel according to claim 3, wherein: The bypass portion of the plurality of first data lines or the plurality of second data lines includes two bypass portions adjacent to each other, and One of the two bypass portions is disposed above the insulating layer, and the other of the two bypass portions is disposed below the insulating layer.

6. The display panel according to claim 3, wherein: The bypass portions of the plurality of third data lines or the plurality of fourth data lines include two bypass portions adjacent to each other, and One of the two bypass portions is disposed above the insulating layer, and the other of the two bypass portions is disposed below the insulating layer.

7. The display panel according to claim 3, wherein: Relative to a second virtual center line passing through the center of the second area in the second direction, a bypass portion of a data line among the plurality of third data lines that is disposed closest to the first side of the second area is asymmetrical with a bypass portion of a data line among the plurality of fourth data lines that is disposed closest to the second side of the second area.

8. The display panel according to claim 3, wherein: A distance between two adjacent bypass portions of the plurality of second data lines in the non-display area is smaller than a distance between two adjacent second data lines among the plurality of second data lines in the display area.

9. The display panel according to claim 1, wherein: A first width between the first region and the second region along the first direction is greater than a second width between a first edge portion of the non-display region and the first region along the first direction and a third width between a second edge portion of the non-display region and the second region along the first direction.

10. The display panel according to claim 1, further comprising a plurality of scan lines extending in the first direction in the display area, the plurality of scan lines comprising: A first scanning line is arranged at a first side of the first region and the second region; as well as A second scanning line is disposed at a second side of the first region and the second region opposite to the first side of the first region and the second region.

11. The display panel according to claim 1, wherein: The second region has an elliptical shape or a quadrilateral shape with rounded corners.

12. A display panel, comprising: a substrate including a display area in which a plurality of light emitting diodes are arranged, a first area having a circular shape and a second area having a shape different from that of the first area, which are surrounded by the display area and are disposed to be spaced apart from each other in a first direction, and a non-display area surrounding the first area and the second area; a plurality of data lines extending in a second direction intersecting the first direction in the display area, the plurality of data lines being electrically connected to the plurality of light emitting diodes respectively; as well as a plurality of scan lines extending in the first direction in the display area, the plurality of scan lines being electrically connected to the plurality of light emitting diodes respectively, Wherein, the plurality of scan lines include: a plurality of first scanning lines, bypassing the first region and the second region and arranged along a first side of the first region and the second region; and A plurality of second scanning lines bypass the first region and the second region and are arranged along a second side of the first region and the second region opposite to the first side of the first region and the second region.

13. The display panel according to claim 12, wherein: The number of the plurality of first scan lines is the same as the number of the plurality of second scan lines.

14. The display panel according to claim 12, wherein: A distance between two adjacent bypass portions of the plurality of first scan lines in the non-display area is smaller than a distance between two adjacent first scan lines among the plurality of first scan lines in the display area, and A distance between two adjacent bypass portions of the plurality of second scan lines in the non-display area is smaller than a distance between two adjacent second scan lines among the plurality of second scan lines in the display area.

15. The display panel according to claim 12, wherein: Relative to a virtual center line passing through the center of the first area and the center of the second area, the scan line set on the first side closest to the first area and the second area among the multiple first scan lines is symmetrical to the scan line set on the second side closest to the first area and the second area among the multiple second scan lines.

16. The display panel according to claim 15, wherein: A first width between the first region and the second region along the first direction is greater than a second width between a first edge portion of the non-display region and the first region along the first direction and a third width between a second edge portion of the non-display region and the second region along the first direction.

17. The display panel according to claim 12, wherein: The plurality of data lines include: A plurality of first data lines are arranged along one side of the first area, bypassing the first area, and arranged in the non-display area; a plurality of second data lines, which bypass the first area along another side of the first area opposite to the one side of the first area and are arranged in the non-display area; a plurality of third data lines, bypassing the second area along one side of the second area, and arranged in the non-display area; and A plurality of fourth data lines are arranged in the non-display area, bypassing the second area along another side of the second area opposite to the one side of the second area.

18. The display panel according to claim 17, wherein: The number of the third data lines is greater than the number of the fourth data lines.

19. The display panel according to claim 18, wherein: The number of the plurality of first data lines is the same as the number of the plurality of second data lines.

20. The display panel according to claim 17, wherein: The bypass portions of the plurality of second data lines and the bypass portion of the third data line are disposed between the first region and the second region.

21. The display panel according to claim 20, wherein: Relative to a first virtual center line passing through the center of the first area in the second direction, the bypass portion of the data line set on the one side closest to the first area among the multiple first data lines is symmetrical with the bypass portion of the data line set on the other side closest to the first area among the multiple second data lines.

22. The display panel according to claim 20, wherein: Relative to a second virtual center line passing through the center of the second area in the second direction, a bypass portion of a data line among the plurality of third data lines that is disposed closest to the one side of the second area is asymmetrical with a bypass portion of a data line among the plurality of fourth data lines that is disposed closest to the other side of the second area.

23. The display panel according to claim 17, wherein: The bypass portions of the plurality of first data lines or the plurality of second data lines include two bypass portions disposed adjacent to each other, one of the two bypass portions being disposed above the insulating layer, and the other of the two bypass portions being disposed below the insulating layer, The bypass portions of the plurality of third data lines or the plurality of fourth data lines include two bypass portions disposed adjacent to each other, and one of the two bypass portions is disposed above the insulating layer, and the other of the two bypass portions is disposed below the insulating layer.

24. The display panel according to claim 12, wherein: The second region has an elliptical shape or a quadrilateral shape with rounded corners.

25. A display panel, comprising: a first opening region and a second opening region, spaced apart from each other in a first direction and having different sizes; a non-display area surrounding the first opening area and the second opening area; a display area surrounding the non-display area, wherein a plurality of light emitting diodes are arranged in the display area; as well as a plurality of signal lines extending in a second direction intersecting the first direction in the display area, each of the plurality of signal lines being electrically connected to a corresponding one of the plurality of light emitting diodes, Wherein, the non-display area includes: a first sub non-display area disposed between a first side of the first opening area and a first side of the second opening area, wherein the first side of the first opening area and the first side of the second opening area face each other; a second sub non-display area disposed between a second side of the first opening area opposite to the first side of the first opening area and the display area; and a third sub non-display area is disposed between a second side of the second opening area opposite to the first side of the second opening area and the display area, and the first sub non-display area is disposed between the second sub non-display area and the third sub non-display area. Wherein, the plurality of signal lines include: a first signal line passing through the first sub non-display area in the non-display area; a second signal line passing through the second sub non-display area in the non-display area; and a third signal line passing through the third sub non-display area in the non-display area, The number of the second signal lines is equal to the number of the third signal lines.

26. The display panel according to claim 25, wherein: The number of the first signal lines is greater than the sum of the number of the second signal lines and the number of the third signal lines.

27. The display panel according to claim 25, wherein: The second side of the first opening area includes a first curve, and The second side of the second opening area includes a second curve having a same radius of curvature as that of the first curve.

28. The display panel according to claim 25, wherein: One of the first signal lines that is closest to the first side of the first opening region includes a first bypass portion extending along the first side of the first opening region, One of the second signal lines closest to the second side of the first opening region includes a second bypass portion extending along the second side of the first opening region, and A central angle of the first bypass portion is equal to a central angle of the second bypass portion.

29. The display panel according to claim 28, wherein: One of the first signal lines closest to the first side of the second opening region includes a third bypass portion extending along the first side of the second opening region, One of the third signal lines closest to the second side of the second opening region includes a fourth bypass portion extending along the second side of the second opening region, and A central angle of the third bypass portion is greater than a central angle of the fourth bypass portion.

30. The display panel according to claim 29, wherein: A portion of the third bypass portions crosses a virtual line passing through a center of the second opening area in the non-display area.

31. The display panel according to claim 25, further comprising: a substrate comprising a first surface and a second surface opposite to the first surface, wherein the plurality of signal lines are arranged on the first surface of the substrate, and The substrate has a first opening disposed in a region corresponding to the first opening region and a second opening disposed in a region corresponding to the second opening region, and the first opening and the second opening respectively pass through the first surface of the substrate to the second surface of the substrate.

32. The display panel according to claim 25, wherein: The first opening area has a circular shape, and the second opening area has a non-circular shape.

33. The display panel according to claim 25, wherein: The plurality of signal lines include scan lines or data lines.

34. A display device comprising: The display panel includes a first opening area and a second opening area which are spaced apart from each other in a first direction and have different sizes; A first component is arranged in an area corresponding to the first opening area; as well as a second component disposed in an area corresponding to the second opening area, Wherein, the display panel further comprises: a non-display area surrounding the first opening area and the second opening area; and a display area surrounding the non-display area, wherein a plurality of light emitting diodes are arranged in the display area, and a plurality of signal lines extending in a second direction intersecting the first direction are arranged in the display area, each of the plurality of signal lines being electrically connected to a corresponding one of the plurality of light emitting diodes, Wherein, the non-display area includes: a first sub non-display area disposed between a first side of the first opening area and a first side of the second opening area, wherein the first side of the first opening area and the first side of the second opening area face each other; a second sub non-display area disposed between a second side of the first opening area opposite to the first side of the first opening area and the display area; and a third sub non-display area is disposed between a second side of the second opening area opposite to the first side of the second opening area and the display area, and the first sub non-display area is disposed between the second sub non-display area and the third sub non-display area. Wherein, the plurality of signal lines include: a first signal line passing through the first sub non-display area in the non-display area; a second signal line passing through the second sub non-display area in the non-display area; and a third signal line passing through the third sub non-display area in the non-display area, and The number of the second signal lines is equal to the number of the third signal lines.

35. The display device according to claim 34, wherein: The number of the first signal lines is greater than the sum of the number of the second signal lines and the number of the third signal lines.

36. The display device according to claim 34, wherein: The second side of the first opening area includes a first curve, and The second side of the second opening area includes a second curve having a same radius of curvature as that of the first curve.

37. The display device according to claim 34, wherein: One of the first signal lines that is closest to the first side of the first opening region includes a first bypass portion extending along the first side of the first opening region, One of the second signal lines closest to the second side of the first opening region includes a second bypass portion extending along the second side of the first opening region, and A central angle of the first bypass portion is equal to a central angle of the second bypass portion.

38. The display device according to claim 37, wherein: One of the first signal lines closest to the first side of the second opening region includes a third bypass portion extending along the first side of the second opening region, One of the third signal lines closest to the second side of the second opening region includes a fourth bypass portion extending along the second side of the second opening region, and A central angle of the third bypass portion is greater than a central angle of the fourth bypass portion.

39. The display device according to claim 34, wherein: Some of the first signal lines each include a bypass portion that bypasses the second opening area along the first side of the second opening area, and A portion of the bypass portions crosses a virtual line passing through a center of the second opening area in the non-display area.

40. The display device according to claim 34, wherein: The display panel further comprises: a substrate comprising a first surface and a second surface opposite to the first surface, wherein the plurality of signal lines are arranged on the first surface of the substrate, and The substrate has a first opening disposed in a region corresponding to the first opening region and a second opening disposed in a region corresponding to the second opening region, and the first opening and the second opening respectively pass through the first surface of the substrate to the second surface of the substrate.

41. The display device according to claim 34, wherein: The first opening area has a circular shape, and the second opening area has a non-circular shape.

42. The display device according to claim 34, wherein: The plurality of signal lines include scan lines or data lines.

43. The display device according to claim 34, wherein: The first component comprises a camera or a sensor.

44. The display device according to claim 34, wherein: The second component comprises a camera or a sensor.

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