Epitaxial growth method and system

Abstract

The invention provides an epitaxial growth method and system, and the method comprises the steps: reducing the heating power of a reaction chamber before a silicon wafer completely enters the reaction chamber, so as to enable the temperature difference between a contact position and a non-contact position, which are used for being in contact with a supporting part, of the back surface of the silicon wafer in a loading process to be within a target temperature difference range; and / or, before the silicon wafer completely enters the reaction chamber, etching gas is conveyed into the reaction chamber so as to etch an upper quartz clock cover and / or a lower quartz clock cover of the reaction chamber, so that the cleaning treatment of the reaction chamber is realized; and loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer. According to the method, the temperature inconsistency generated on the silicon wafer is effectively reduced, so that the temperature distribution tends to be uniform in the deposition process of the epitaxial layer, the generation of the Pin Nano defect of the epitaxial wafer is effectively inhibited, and the surface quality and the product yield of the epitaxial wafer are improved.

Description

Technical Field

[0001] The present application relates to the technical field of epitaxial wafer defect control, and in particular to an epitaxial growth method and system. Background Art

[0002] The vapor phase epitaxy process (Vapour Phase Epitaxy) is a common epitaxial growth technology, which can grow an epitaxial layer on a silicon wafer substrate that is different from the conductivity type, resistivity and structure of the silicon wafer substrate, and has controllable thickness and resistivity. It can meet a variety of different requirements and can greatly improve the flexibility and performance of device design. It has broad application prospects in various semiconductor functional device fields. Specifically, the epitaxial production process generally uses chemical vapor deposition to inject silicon source gas in a high-temperature closed reaction chamber into the surface of the silicon wafer, and deposit and grow an epitaxial layer on the surface of the silicon wafer. The wafer produced is called an epitaxial wafer. Compared with silicon wafers, epitaxial wafers have the advantages of fewer surface defects and the ability to control the thickness and resistivity of the epitaxial layer.

[0003] In the actual epitaxial growth process, Pin Nano (pin nanomorphology) defects are generated at the contact position between the silicon wafer and the supporting component (such as supporting pins), that is, contamination marks are generated on the upper surface of the contact position between the silicon wafer and the supporting component, affecting the quality and yield of the epitaxial wafer.

[0004] Based on this, the present application provides an epitaxial growth method and system to improve the relevant technology. Summary of the invention

[0005] The purpose of this application is to provide an epitaxial growth method and system to reduce Pin Nano defects generated in epitaxial wafers.

[0006] The purpose of this application is achieved by the following technical solutions:

[0007] In a first aspect, the present application provides an epitaxial growth method, the method comprising: before a silicon wafer completely enters a reaction chamber, reducing the heating power of the reaction chamber so that the temperature difference between a contact position and a non-contact position on the back side of the silicon wafer for contacting a support component during loading is within a target temperature difference range; and / or, before the silicon wafer completely enters the reaction chamber, delivering an etching gas into the reaction chamber to etch an upper quartz bell jar and / or a lower quartz bell jar of the reaction chamber, thereby cleaning the reaction chamber; loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer.

[0008] In some embodiments, reducing the heating power of the reaction chamber includes: reducing the heating power of the reaction chamber so that a ratio of the heating power after the reduction to the heating power before the reduction is within a target ratio range.

[0009] In some embodiments, the target ratio ranges from 40% to 60%.

[0010] In some embodiments, the etching gas includes hydrogen chloride.

[0011] In some embodiments, during the etching process, the flow rate of the etching gas is 3 slm, and / or the delivery time is 60s to 80s, and / or the temperature of the reaction chamber is 1180°C.

[0012] In some embodiments, the step of loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer includes: loading the silicon wafer into the reaction chamber, inputting a silicon source gas into the reaction chamber so that the silicon source gas undergoes a chemical vapor deposition reaction on the surface of the silicon wafer to deposit an epitaxial layer, thereby obtaining the epitaxial wafer.

[0013] In some embodiments, the silicon source gas is input into the reaction chamber via a gas inlet of the reaction chamber; and / or, the silicon source gas includes trichlorosilane.

[0014] In a second aspect, the present application provides an epitaxial growth system, which includes: a reaction chamber for epitaxial growth of silicon wafers; a transmission module for transmitting the silicon wafers, the transmission module being provided with a supporting component for supporting the silicon wafers; and a control module for executing any of the above methods to obtain epitaxial wafers.

[0015] In some embodiments, the reaction chamber includes: an upper quartz bell jar and a lower quartz bell jar relative to each other, which are used to define the reaction chamber; a base, which is used to support the silicon wafer; a base support rod, which is used to fix the base and drive the base to rotate; and a heating module, which is used to heat the silicon wafer.

[0016] In some embodiments, the heating module includes: an upper heating unit and a lower heating unit opposite to each other, for heating the silicon wafer from above and below the susceptor, respectively.

[0017] The present application provides an epitaxial growth method and system to reduce the non-uniformity of the temperature distribution on the back of the silicon wafer, reduce the Pin Nano defects generated by the epitaxial wafer, and improve the quality and yield of the epitaxial wafer. The present application reduces the heating power of the reaction chamber before the silicon wafer completely enters the reaction chamber to control the temperature difference at different positions on the back of the silicon wafer, and / or, before the silicon wafer completely enters the reaction chamber, the etching gas is delivered to the reaction chamber to achieve the cleaning treatment of the reaction chamber; then the silicon wafer is loaded into the reaction chamber for epitaxial growth to obtain the epitaxial wafer. During the loading process of the silicon wafer, there is a temperature inconsistency between the contact position where the back of the silicon wafer contacts the support component and the non-contact position. By lowering the heating power of the reaction chamber, the difference in the radiant heat received by the contact position and the non-contact position is reduced, and the consistency of the overall temperature field in the reaction chamber is improved, so that the temperature difference between the contact position and the non-contact position on the back of the silicon wafer is controlled within the target temperature difference range. In addition, the cleaning treatment of the reaction chamber can improve the cleanliness of the reaction chamber, and is also conducive to improving the consistency of the temperature field in the reaction chamber. Temperature difference control and / or cleaning treatment effectively reduces the temperature inconsistency generated on the silicon wafer, makes the temperature at each position of the silicon wafer more consistent during the loading process, and makes the temperature distribution during the deposition of the epitaxial layer more uniform, thereby reducing the probability of Pin Nano defects, effectively inhibiting the generation of Pin Nano defects on the epitaxial wafer, reducing the contamination marks generated at the contact position, and improving the surface quality of the epitaxial wafer and the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present application is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0019] Figure 1 It is a schematic diagram of the structure of a reaction chamber provided in an embodiment of the present application.

[0020] Figure 2 It is a structural schematic diagram of an epitaxial growth system provided in an embodiment of the present application.

[0021] Figure 3 It is a schematic flow chart of an epitaxial growth method provided in an embodiment of the present application.

[0022] Figure 4 This is a comparison chart of the Nano values ​​of an epitaxial wafer before and after Pin Nano defect improvement provided in an embodiment of the present application.

[0023] Figure 5 This is a comparison chart of epitaxial wafer maps before and after Pin Nano defect improvement provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in the implementation mode of this application. Obviously, the described implementation mode is only a part of the implementation mode of this application, not all the implementation modes. Based on the implementation mode in this application, all other implementation modes obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0025] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0026] The epitaxial growth process of silicon is an important process in the manufacture of semiconductor chips. It is a method of growing a silicon single crystal layer with controllable resistivity, thickness, no COP (Crystal Originated Particle, crystal origin voids) and oxygen precipitation on a silicon wafer (e.g., polished wafer) as a substrate under certain conditions. For example, it includes vacuum epitaxial deposition, vapor phase epitaxial deposition (as an example of chemical vapor deposition) and liquid phase epitaxial deposition. For example, in a high temperature environment, a single crystal silicon can be generated by the reaction of silicon source gas and hydrogen and deposited on the surface of a silicon wafer to obtain an epitaxial layer.

[0027] With the rapid development of the semiconductor industry, the requirements for the particle quality on the surface of epitaxial wafers are getting higher and higher. The uniformity of temperature distribution will greatly affect the generation of Pin Nano (pin nanomorphology) defects. For the reaction chamber, uniform temperature field and accurate temperature control are the main influencing factors for maintaining the flatness of the epitaxial wafer and controlling slip dislocations. Among them, a clean and translucent quartz bell jar is an important factor affecting the uniformity of the temperature field and the transmittance. At the same time, a clean and translucent quartz bell jar is also an effective factor to ensure that the thermometer reads the temperature accurately. Therefore, maintaining the cleanliness of the reaction chamber becomes a key factor affecting the quality and yield of the epitaxial wafer. However, in the actual epitaxial growth process, the problem of Dome Coating (i.e., epitaxial growth byproducts deposited on the surface of the quartz bell jar) will occur, resulting in a decrease in the cleanliness of the internal environment of the reaction chamber.

[0028] See also Figures 1 to 3 , Figure 1 is a schematic diagram of the structure of a reaction chamber provided in an embodiment of the present application, Figure 2 is a schematic diagram of the structure of an epitaxial growth system provided in an embodiment of the present application, Figure 3It is a schematic flow chart of an epitaxial growth method provided in an embodiment of the present application.

[0029] In order to improve the related technology, an embodiment of the present application provides an epitaxial growth method, which includes steps S101 and S102.

[0030] Step S101: before the silicon wafer completely enters the reaction chamber, reducing the heating power of the reaction chamber so that the temperature difference between the contact position and the non-contact position of the back side of the silicon wafer for contacting the support component during the loading process is within the target temperature difference range.

[0031] Step S102: loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer.

[0032] An embodiment of the present application provides an epitaxial growth method, which includes steps S103 and S102.

[0033] Step S103: Before the silicon wafer completely enters the reaction chamber, an etching gas is delivered into the reaction chamber to etch the upper quartz bell jar and / or the lower quartz bell jar of the reaction chamber, thereby cleaning the reaction chamber.

[0034] Step S102: loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer.

[0035] An embodiment of the present application provides an epitaxial growth method, which includes steps S101, S103 and S102.

[0036] Step S101: before the silicon wafer completely enters the reaction chamber, reducing the heating power of the reaction chamber so that the temperature difference between the contact position and the non-contact position of the back side of the silicon wafer for contacting the support component during the loading process is within the target temperature difference range.

[0037] Step S103: before the silicon wafer completely enters the reaction chamber, an etching gas is delivered into the reaction chamber to etch the upper quartz bell jar and / or the lower quartz bell jar of the reaction chamber, thereby achieving a cleaning process for the reaction chamber;

[0038] Step S102: loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer.

[0039] In the above embodiment, the order of step S101 and step S103 can be swapped, and this application does not limit this.

[0040] In some embodiments, the epitaxial growth method described above may be executed on a control module of an epitaxial growth system.

[0041] For example, the epitaxial growth system may include: a reaction chamber, a transmission module and a control module. The transmission module may include, for example, one or more wafer support rods (ie, lift pins). For example, the transmission module may include three lift pins. Figure 1 As shown, the reaction chamber is used to grow an epitaxial layer on the main surface of a wafer (i.e., a silicon wafer 8) by CVD (i.e., Chemical Vapor Deposition), and may include a relatively upper quartz bell jar 1, a lower quartz bell jar 2, and a mounting component 4. The reaction chamber may also be provided with an air inlet (not shown in the figure) and an exhaust port (not shown in the figure). The reaction chamber may also include a base 6 for placing the silicon wafer (i.e., silicon wafer 8) and a base support rod 7. The reaction chamber may also include a heating module, and the heating power of the reaction chamber refers to, for example, the heating power of the heating module. The heating module may include an upper heating unit located above the base and / or a lower heating unit located below the base, the upper heating unit may include one or more heating lamps (e.g., a halogen lamp 3), and the lower heating unit may include one or more heating lamps (e.g., a halogen lamp 3). In Figure 1 In the figure, the gas flow direction 5 is used to indicate the flow direction of the etching gas and / or the silicon source gas, for example.

[0042] As an example, when a Wafer (i.e., silicon wafer 8) is input into a Process Chember (i.e., a reaction chamber, also called a process chamber) and placed on a Suscepter (i.e., a susceptor 6) in the reaction chamber, the Wafer is heated by a heating lamp group disposed on the upper side of the Suscepter and a heating lamp group disposed on the lower side of the Suscepter. In addition, a raw material gas (i.e., a silicon source gas) is supplied to the main surface of the Wafer (e.g., the upper surface of the silicon wafer 8), thereby performing vapor phase growth (i.e., chemical vapor deposition), and after the vapor phase growth, the epitaxial wafer obtained by the vapor phase growth is output to the outside of the Process Chember. During the growth process, the susceptor support rod 7 serves to fix the susceptor 6 and drive the susceptor 6 to rotate, so that the epitaxial growth can be performed uniformly on the substrate (i.e., the silicon wafer 8).

[0043] Figure 2Schematic diagram of the structure of the epitaxial growth system. For example, the epitaxial growth system may include a reaction chamber 105, a transmission module (not shown in the figure), a control module (not shown in the figure), a transfer chamber 104, a load lock module 103, a front-end module 102, and a loading port 101. As an example, the transfer blade in the front-end module 102 transfers the silicon wafer from the loading port 101 to the load lock module 103, and the load lock module 103 is evacuated and backfilled with nitrogen. The transfer robot located in the transfer chamber 104 transfers the silicon wafer in the load lock module 103 through the transfer chamber 104 into the reaction chamber 105 for epitaxial growth, and the silicon wafer returns along the original path after the growth is completed.

[0044] The applicant has found in practice that various defects in the epitaxial layer are not only related to the quality of the substrate and the surface conditions of the substrate, but also closely related to the epitaxial growth process itself. The uniformity of the temperature distribution will greatly affect the generation of Pin Nano (pin nanomorphology) defects. Among them, Pin Nano defects refer to the contamination marks that appear on the surface of the epitaxial wafer support pin position (which can be referred to as the contact position). The following is an example of its formation source. Under relevant process conditions, the silicon wafer is at ambient temperature (for example, room temperature) before being loaded into the reaction chamber 105, and the temperature of the reaction chamber 105 is always maintained at 850°C in the Idle state (i.e., idle state). In the process of transferring the silicon wafer to the reaction chamber 105, the temperature of the transfer chamber 104 (for example, room temperature) and the temperature of the reaction chamber 105 (for example, 850°C) are quite different. Specifically, during the process of the transmission module (e.g., including a mechanical arm, a transmission blade, etc.) transmitting the silicon wafer from the transfer chamber 104 to the reaction chamber 105, the silicon wafer is in a Load state, which results in the back of the silicon wafer being divided into two types of areas. The first type of area is the contact position that contacts the support component (e.g., lift pin) of the transmission module. This type of area does not directly contact the environment in the reaction chamber 105, but indirectly conducts heat with the environment in the reaction chamber 105 through the support component. The second type of area is the non-contact position that does not contact the support component. This type of area directly contacts the environment in the reaction chamber 105 and can conduct direct heat with the environment in the reaction chamber 105. These two types of areas on the back of the silicon wafer (i.e., the contact position and the non-contact position) not only have differences in the environmental heat conduction mode, but also the radiant heat of the lower heating unit is partially blocked by the support component, so that there is a difference in the radiant heat received at the contact position and the non-contact position on the back of the silicon wafer, resulting in inconsistent temperatures at the contact position and the non-contact position on the back of the silicon wafer. Since the back of the silicon wafer is in contact with the base, this results in uneven base temperature. During the growth of the epitaxial layer, the silicon wafer is still in direct contact with the base, and the uneven temperature of the base will lead to the generation of Pin Nano defects during growth.

[0045] In order to achieve epitaxial growth of silicon wafers, the silicon wafers are transferred from the transfer chamber 104 to the reaction chamber 105. Since the temperature of the transfer chamber 104 (e.g., room temperature) and the temperature of the reaction chamber (e.g., 850° C.) are quite different, during the loading process of the transfer module transferring the silicon wafers from the transfer chamber 104 to the reaction chamber 105, there are differences in the environmental heat conduction mode and the received radiation heat between the contact position and the non-contact position where the back of the silicon wafer contacts the lift pin, and these differences lead to inconsistent temperatures between the contact position and the non-contact position on the back of the silicon wafer, which in turn leads to uneven temperature of the susceptor in contact with the back of the silicon wafer. In order to reduce the temperature difference between the contact position and the non-contact position on the back of the silicon wafer, suppress the generation of PinNano defects during growth, and ultimately improve the product yield, the above embodiment reduces the heating power (e.g., After Load Power) of the reaction chamber 105 (e.g., from 60KW to 30KW) before the silicon wafer enters the reaction chamber 105, so that the difference in the radiant heat received by the contact position and the non-contact position is reduced, thereby reducing the temperature inconsistency between the contact position and the non-contact position on the back of the silicon wafer, so that the temperature difference between the contact position and the non-contact position on the back of the silicon wafer is within the target temperature difference range; then, the silicon wafer is loaded into the reaction chamber for epitaxial growth to obtain an epitaxial wafer. The above embodiment can reduce the temperature field distribution difference on the back of the silicon wafer by optimizing the heating power of the reaction chamber 105, so that the temperature of the contact position and the non-contact position of the lift pin tends to be consistent.

[0046] The above embodiments do not limit the target temperature difference range, which can be selected or preset according to the needs of practical applications. In some embodiments, the target temperature difference range can be 0.1-100°C.

[0047] In some embodiments, reducing the heating power of the reaction chamber may include: reducing the heating power of the reaction chamber so that a ratio of the heating power after the reduction to the heating power before the reduction is within a target ratio range.

[0048] The above embodiment does not limit the target ratio range, which can be selected or preset according to the needs of practical applications. In some embodiments, the target ratio range can be 40-60%. For example, the ratio of the heating power after reduction to the heating power before reduction can be 50%.

[0049] The above embodiments do not limit the etching gas. In some embodiments, the etching gas may include hydrogen chloride.

[0050] In some embodiments, during the etching process, the flow rate of the etching gas is 3 slm, and / or the delivery time is 60s to 80s, and / or the temperature of the reaction chamber is 1180°C.

[0051] For example, before the silicon wafer enters the reaction chamber, an etching gas (e.g., HCl, i.e., hydrogen chloride) can be delivered into the reaction chamber through the gas inlet to etch the upper and lower domes (the dome is, for example, a quartz bell jar, and the upper and lower domes include, for example, an upper quartz bell jar and a lower quartz bell jar).

[0052] As an example, when the etching gas is introduced into the reaction chamber, its flow rate can be controlled to be 3slm, the delivery time can be 60s to 80s, and the temperature of the reaction chamber can be 1180°C. Among them, slm is a flow unit, which means the volume value in liters that flows per minute under the conditions of 1 atmosphere and 25 degrees Celsius. In the actual epitaxial growth process, the problem of Dome Coating (i.e., epitaxial growth byproducts deposited on the surface of the quartz bell jar) will occur. Specifically, with the increase of time, the epitaxial growth byproducts deposited on the upper quartz bell jar and the lower quartz bell jar are increasing, which leads to a decrease in the cleanliness of the internal environment of the reaction chamber and a deterioration in the uniformity of the temperature field (for example, a temperature difference occurs between the upper and lower Domes). The deterioration of the uniformity of the temperature field may lead to uneven deposition temperature of the epitaxial layer, and a temperature difference will occur on the surface of the silicon wafer, affecting the product quality and yield of the epitaxial wafer. Etching the upper quartz bell jar and / or the lower quartz bell jar of the reaction chamber to achieve cleaning of the reaction chamber can reduce the temperature difference between the upper and lower chambers of the upper quartz bell jar and the lower quartz bell jar, improve the uniformity of the temperature field, reduce the inconsistency of the epitaxial layer deposition temperature, reduce the temperature difference on the surface of the silicon wafer, and improve the product quality and yield of the epitaxial wafer. In addition, by controlling the flow rate, delivery time, and chamber temperature, on the one hand, the coating (i.e., epitaxial growth byproducts) can be fully cleaned, and on the other hand, the coating on the surface of the base (e.g., Si C coating) can be reduced. Damage.

[0053] In some embodiments, loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer may include: loading the silicon wafer into the reaction chamber, inputting a silicon source gas into the reaction chamber so that the silicon source gas undergoes a chemical vapor deposition reaction on the surface of the silicon wafer to deposit an epitaxial layer, thereby obtaining the epitaxial wafer.

[0054] In some embodiments, the silicon source gas may be introduced into the reaction chamber through a gas inlet of the reaction chamber.

[0055] In some embodiments, the silicon source gas may include trichlorosilane.

[0056] In the above embodiment, the silicon wafer is loaded into the reaction chamber, for example, the silicon wafer is placed in the reaction chamber and placed on a base (for example, a SiC base). Wherein, SiC is silicon carbide. A silicon source gas (for example, SiHCl3, i.e., trichlorosilane) is input into the reaction chamber, and a chemical vapor deposition reaction can be performed on the surface of the silicon wafer (for example, the upper surface of the silicon wafer, corresponding to the back side of the silicon wafer) to deposit an epitaxial layer to obtain an epitaxial wafer.

[0057] See also Figure 4 and Figure 5 , Figure 4 This is a comparison chart of the nano values ​​of an epitaxial wafer before and after the Pin Nano defect is improved, provided in an embodiment of the present application. Figure 5 This is a comparison chart of the epitaxial wafer Map before and after Pin Nano defect improvement provided in the embodiment of the present application. Figure 4 In the example, Sample 1 to Sample 10 are sample groups 1 to 10, each sample group contains a sample before improvement and a sample after improvement, and the unit of Na no value is nanometer. Figure 5 , Map1 to Map5 correspond to sample groups 1 to 5, respectively.

[0058] like Figure 4 As shown in the figure, 10 pieces (i.e. pieces, quantity unit) of epitaxial wafers were used for testing and verification before and after the improvement. As an example, NT (10*10) is to divide the upper surface of the epitaxial wafer into several 10mm×10mm areas, and each area is tested to get a Nano value. The darker the area color, the larger the Nano value, and the worse the quality of the epitaxial wafer. The NT (10*10) value is reduced from about 15nm before the improvement to about 6nm. Figure 5 As shown, there is a PinNano defect in the upper right corner of the upper surface of the epitaxial wafer before improvement. After improvement using the method in the above embodiment, the Pin Nano defect of the epitaxial wafer is reduced, and the product quality is improved.

[0059] In summary, the above embodiments can reduce the heating power of the reaction chamber in the epitaxial growth system before the silicon wafer enters the reaction chamber. By optimizing the heating power, the difference in temperature field distribution can be reduced, so that the temperature of the lift pin contact position and the non-contact position tends to be consistent. In addition, before the silicon wafer enters the reaction chamber, the etching gas is delivered to the reaction chamber through the air inlet to etch the upper and lower domes, which can reduce the temperature difference between the upper and lower chambers. The silicon wafer is transferred to the base inside the reaction chamber, and the silicon source gas is input into the reaction chamber through the air inlet, and the epitaxial layer is deposited on the surface of the silicon wafer to prepare an epitaxial wafer. The epitaxial wafer produced according to the above method can suppress the generation of lift pin contamination marks on the back of the epitaxial wafer, and improve the quality and yield of the epitaxial wafer.

[0060] like Figure 2 As shown, the embodiment of the present application also provides an epitaxial growth system, the system comprising a reaction chamber 105, a transmission module and a control module. The reaction chamber 105 is used for epitaxial growth of silicon wafers. The transmission module is used to transmit the silicon wafer, and the transmission module is provided with a support component for supporting the silicon wafer. The control module is used to perform any of the above methods to obtain an epitaxial wafer. The system may also include a transfer chamber 104, a load lock module 103, a front-end module 102 and a loading port 101.

[0061] like Figure 1 As shown, in some embodiments, the reaction chamber includes an upper quartz bell jar 1, a lower quartz bell jar 2, a base 6, a base support rod 7 and a heating module. The upper quartz bell jar 1 corresponds to the lower quartz bell jar 2 and is used to define the reaction chamber 105. The base 6 is used to carry the silicon wafer 8. The base support rod 7 is used to fix the base 6 and drive the base 6 to rotate. The heating module is used to heat the silicon wafer 8. Among them, the base 6 can be in a disc shape, a rectangular shape or an irregular shape, which is not limited in the above embodiment. The reaction chamber can also include a mounting component 4 for mounting various components of the reaction chamber. The reaction chamber can also include an air inlet, an exhaust port, etc., and the flow direction of the gas can be as shown in the gas flow direction 5.

[0062] In some embodiments, the heating module may include an upper heating unit and a lower heating unit, which are respectively used to heat the silicon wafer 8 from above and below the base 6. The upper heating unit may include one or more heating lamps, which may be, for example, a halogen lamp 3, which is not limited in the above embodiment. The lower heating unit may include one or more heating lamps, which may be, for example, a halogen lamp 3, which is not limited in the above embodiment.

[0063] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0064] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0065] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0066] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0067] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An epitaxial growth method, characterized in that: The method comprises: Before the silicon wafer completely enters the reaction chamber, the heating power of the reaction chamber is reduced so that the temperature difference between the contact position and the non-contact position of the back side of the silicon wafer for contacting with the support component during the loading process is within the target temperature difference range; and / or, before the silicon wafer completely enters the reaction chamber, the etching gas is delivered into the reaction chamber to etch the upper quartz bell jar and / or the lower quartz bell jar of the reaction chamber, thereby achieving a cleaning process for the reaction chamber; The silicon wafer is loaded into the reaction chamber for epitaxial growth to obtain an epitaxial wafer.

2. The epitaxial growth method according to claim 1, characterized in that: The step of reducing the heating power of the reaction chamber comprises: The heating power of the reaction chamber is set to be reduced so that the ratio of the heating power after the reduction to the heating power before the reduction is within a target ratio range.

3. The epitaxial growth method according to claim 2, characterized in that: The target ratio ranges from 40 to 60%.

4. The epitaxial growth method according to claim 1, characterized in that: The etching gas includes hydrogen chloride.

5. The epitaxial growth method according to claim 1, characterized in that: During the etching process, the flow rate of the etching gas is 3 slm, and / or the delivery time is 60s to 80s, and / or the temperature of the reaction chamber is 1180°C.

6. The epitaxial growth method according to claim 1, characterized in that: The step of loading the silicon wafer into the reaction chamber for epitaxial growth to obtain an epitaxial wafer comprises: The silicon wafer is loaded into the reaction chamber, and a silicon source gas is input into the reaction chamber, so that the silicon source gas undergoes a chemical vapor deposition reaction on the surface of the silicon wafer to deposit an epitaxial layer, thereby obtaining the epitaxial wafer.

7. The epitaxial growth method according to claim 6, characterized in that: The silicon source gas is introduced into the reaction chamber via a gas inlet of the reaction chamber; and / or the silicon source gas includes trichlorosilane.

8. An epitaxial growth system, characterized in that: The system comprises: A reaction chamber for epitaxial growth of silicon wafers; A transmission module, used for transmitting the silicon wafer, wherein the transmission module is provided with a supporting component for supporting the silicon wafer; A control module, used to execute the method according to any one of claims 1 to 7 to obtain an epitaxial wafer.

9. The epitaxial growth system according to claim 8, characterized in that: The reaction chamber comprises: An upper quartz bell jar and a lower quartz bell jar are opposite to each other, and are used to define the reaction chamber; A base, used for supporting the silicon wafer; A base support rod, used to fix the base and drive the base to rotate; A heating module is used to heat the silicon wafer.

10. The epitaxial growth system according to claim 9, characterized in that: The heating module comprises: The upper heating unit and the lower heating unit are opposite to each other and are used to heat the silicon wafer from above and below the susceptor respectively.

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