Output voltage sampling circuit and method of flyback converter

Abstract

The invention provides an output voltage sampling circuit and method of a flyback converter. The output voltage sampling circuit comprises a sampling control circuit and a sampling holding circuit. The sampling control circuit receives a node voltage signal and an input voltage signal, and judges the current zero-crossing moment of the secondary winding to generate a sampling control signal; the sampling and holding circuit receives the sampling control signal and samples and holds the voltage on the third winding so as to generate a voltage feedback signal. The method comprises the following steps: acquiring a node voltage signal representing voltage on a common node of a main switch tube and a primary winding; judging the current zero-crossing moment of the secondary winding according to the node voltage signal and the input voltage signal; and sampling and holding the voltage on the third winding at the current zero-crossing moment of the secondary winding in each switching period so as to generate a voltage feedback signal for representing the output voltage of the flyback converter. According to the invention, accurate sampling control of the output voltage of the flyback converter in a full-load range can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of switching converters, and in particular to an output voltage sampling circuit of a flyback converter. Background Art

[0002] In low-power AC-DC application scenarios such as USB chargers and smartphone adapters, flyback converters are widely used due to their simple architecture and low cost. In the overall control architecture of the flyback converter, an optocoupler device is usually required to realize the feedback of the output voltage. However, the use of optocouplers limits the optimization of system area and cost, and the performance of the optocouplers themselves limits the accuracy, overall efficiency and reliability of the output voltage. In some existing methods, a better feedback method, namely the primary side feedback method, is proposed. By adding an auxiliary winding to realize the detection of the output voltage, the use of optocouplers can be avoided. In this method, how to accurately sample the output voltage is an issue that needs to be considered. Summary of the invention

[0003] The present invention aims to solve at least one of the above-mentioned technical problems existing in the prior art.

[0004] To this end, a first aspect of the present invention provides an output voltage sampling circuit for a flyback converter.

[0005] The present invention provides an output voltage sampling circuit of a flyback converter, wherein the flyback converter includes a main switch tube, a transformer, a first diode and a second diode, wherein the transformer includes a primary winding, a secondary winding and a tertiary winding, wherein the first end of the primary winding receives an input voltage signal, the main switch tube is coupled between the second end of the primary winding and a primary reference ground, the first end of the secondary winding is coupled to the output end of the flyback converter through a first diode, and the first end of the tertiary winding is coupled to the power supply end through a second diode. The output voltage sampling circuit includes a sampling control circuit and a sampling and holding circuit.

[0006] The sampling control circuit receives a node voltage signal and an input voltage signal, and determines the zero-crossing moment of the secondary winding current according to the node voltage signal and the input voltage signal to generate a sampling control signal, wherein the node voltage signal represents the voltage at the common node of the main switch tube and the primary winding. The sampling and holding circuit has an input terminal, an output terminal and a control terminal, wherein the input terminal of the sampling and holding circuit is coupled to the first terminal of the third winding, the control terminal of the sampling and holding circuit receives the sampling control signal, the sampling and holding circuit samples and holds the voltage on the third winding according to the sampling control signal, and generates a voltage feedback signal at its output terminal, wherein the voltage feedback signal represents the output voltage of the flyback converter.

[0007] A second aspect of the present invention provides an output voltage sampling method.

[0008] The present invention provides an output voltage sampling method for a flyback converter, wherein the flyback converter includes a main switch tube, a transformer, a first diode and a second diode, the transformer includes a primary winding, a secondary winding and a tertiary winding, the first end of the primary winding receives an input voltage signal, the main switch tube is coupled between the second end of the primary winding and a primary reference ground, the first end of the secondary winding is coupled to the output end of the flyback converter through a first diode, and the first end of the tertiary winding is coupled to the power supply end through a second diode, and the output voltage sampling method includes: obtaining a node voltage signal representing the voltage on a common node of the main switch tube and the primary winding; determining a current zero-crossing moment of the secondary winding according to the node voltage signal and the input voltage signal; and sampling and holding the voltage on the tertiary winding at the current zero-crossing moment of the secondary winding in each switching cycle to generate a voltage feedback signal representing the output voltage of the flyback converter.

[0009] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are:

[0010] In the present invention, the time when the secondary winding current passes through zero is determined based on the node voltage signal and the input voltage signal. At this time, the diode conduction voltage drop remains constant. The output voltage is collected at this time, which can accurately reflect the true level of the converter output voltage, thereby achieving precise control of the output voltage within the full load range. At the same time, the acquisition circuit disclosed in the present invention has a simple structure, is easy to implement, does not need to design a complex timing circuit, and has good economy.

[0011] Additional aspects and advantages of the present invention will become apparent from the following description or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0013] Figure 1 It is a schematic diagram of the circuit principle of an output voltage sampling circuit applied to a flyback converter in one embodiment of the present invention;

[0014] Figure 2 is a circuit structure diagram of an output voltage sampling circuit according to an embodiment of the present invention;

[0015] Figure 3 1 is a waveform diagram of key signals in an output voltage sampling circuit according to an embodiment of the present invention;

[0016] Figure 4 The figure is a flow chart of an output voltage sampling method according to an embodiment of the present invention.

[0017] in, Figures 1 to 4 The corresponding relationship between the reference numerals and the component names is as follows:

[0018] 11. Sampling control module; 12. Sampling and holding circuit; 13. Control circuit;

[0019] 111, filtering unit; 112, comparing unit; 113, first voltage dividing unit; 114, second voltage dividing unit;

[0020] 121. A third voltage dividing unit. DETAILED DESCRIPTION

[0021] References to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment. The verbs "include" and "have" are used as open restrictions in this article, which neither exclude nor require the presence of undescribed features. Unless otherwise explicitly stated, the features recorded in the dependent claims can be freely combined with each other. The elements defined by "one" or "one" (i.e., singular form) throughout the document do not exclude the possibility of multiple elements. Further, the described features, structures or characteristics can be combined in any suitable manner in one or more embodiments. Unless otherwise specified, the term "connection" is used to specify the direct electrical connection between circuit elements, while the term "coupling" is used to specify the electrical connection between circuit elements that can be direct or can be via one or more other elements. In contrast, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The term "and / or" used here includes any and all combinations of one or more related listed items. When referring to the voltage of a node or terminal, unless otherwise indicated, the voltage is considered to be the voltage between the node and a reference potential (usually ground). In addition, when referring to the potential of a node or terminal, unless otherwise indicated, the potential is considered to refer to the reference potential. The voltage and potential of a given node or a given terminal will be further designated with the same reference numerals. A signal that alternates between a first logic state (e.g., a logic low state) and a second logic state (e.g., a logic high state) is referred to as a "logic signal". The high and low states of different logic signals of the same electronic circuit may be different. In particular, the high and low states of a logic signal may correspond to a voltage or current that may not be completely constant in a high or low state.

[0022] Refer to the following Figures 1 to 4 The output voltage sampling circuit and method provided according to some embodiments of the present invention are described.

[0023] Figure 1 FIG. 1 is a schematic diagram showing the circuit principle of a flyback converter according to an embodiment of the present invention. The first embodiment of the present invention proposes an output voltage sampling circuit of a flyback converter. Figure 1 The flyback converter shown is used as an example for explanation.

[0024] exist Figure 1 In the embodiment shown, the flyback converter includes a main switch tube MS, a transformer TF, a first diode D1, a second diode D2, an output capacitor C OUT and the power supply capacitor C v ; Transformer TF includes a primary winding, a secondary winding and a tertiary winding.

[0025] AC input voltage V AC After rectification, the input voltage signal is formed. The first end IN of the primary winding receives the input voltage signal V IN The main switch tube MS is coupled between the second end of the primary winding and the primary reference ground, and the common node of the main switch tube MS and the primary winding is used as the switch node SW, and the voltage on the node is shown as the node voltage signal V SW The first end of the secondary winding is coupled to the output capacitor C through the first diode D1. OUT The first end of the flyback converter is connected to the anode of the first diode D1 and the first end of the secondary winding, and the cathode of the first diode D1 and the output capacitor C OUT The first end of the output capacitor C OUT The second end of the third winding AUX is coupled to the power supply capacitor C through the second diode D2. v Specifically, the anode of the second diode D2 is coupled to the first end AUX of the third winding, and the cathode of the second diode D2 is coupled to the power supply capacitor C v The first end of the third winding is coupled to the power supply capacitor C v The second end of is coupled to the secondary reference ground. Usually, the power supply end of the flyback converter is used to provide a power supply voltage Vcc for the on-chip control circuit 13.

[0026] The main switch tube MS can be any suitable semiconductor switch device, such as a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), a junction field effect transistor (Junction Field Effect Transistor, JFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT) and other suitable power switch devices. Figure 1 In the illustrated embodiment, the main switch tube MS is illustrated as an NMOS tube. At this time, the first end, the second end and the control end of the main switch tube MS correspond to the drain, the source and the gate of the NMOS tube respectively. The first end of the main switch tube MS is coupled to the second end of the primary winding, the second end of the main switch tube MS is coupled to the primary reference ground, and the control end of the main switch tube MS receives the switch control signal CTL and is turned on and off under the control of the switch control signal CTL.

[0027] Continue reading Figure 1 The output voltage sampling circuit includes a sampling control circuit 11 and a sampling and holding circuit 12. The sampling control circuit 11 receives a node voltage signal V SW and the input voltage signal V IN , and according to the node voltage signal V SW and the input voltage signal V IN The sampling control signal Vpls is generated by determining the time when the current of the secondary winding passes through zero. The sampling and holding circuit 12 has an input terminal, an output terminal and a control terminal. The input terminal of the sampling and holding circuit 12 is coupled to the first terminal AUX of the third winding. The control terminal of the sampling and holding circuit 12 receives the sampling control signal Vpls. The sampling and holding circuit 12 samples and holds the voltage V on the third winding according to the sampling control signal Vpls. AUX , and generates a voltage feedback signal V at the output end of the sampling and holding circuit 12 FB , voltage feedback signal V FB Used to represent the output voltage V of the flyback converter OUT .

[0028] According to the principle of the flyback converter, the voltage V on the third winding AUX It is proportional to the voltage on the secondary winding, and its ratio is related to the turns ratio between the windings. When the main switch tube MS is turned off, the secondary winding supplies power to the output end through the diode D1. At this time, the voltage on the secondary winding Vs = V do +V OUT , the voltage on the third winding V AUX =n0×Vs, where V do is the conduction voltage drop of the first diode D1, and n0 is the turns ratio of the secondary winding and the third winding. At this time, the node voltage signal V SW =V IN +n×(V do +V OUT ), n is the turns ratio of the primary winding to the secondary winding. In each switching cycle, when the main switch tube MS is turned on, the primary current Ip rises from 0 to the maximum value; when the main switch tube MS is turned off, the secondary current Is drops from the maximum value to zero. In the process of the secondary current Is dropping from the maximum value to zero, the conduction voltage drop V of the first diode D1 doIt will change with the change of current. When the secondary current Is is at the zero-crossing moment, that is, the inflection point a, the conduction voltage drop V of the first diode D1 is do Constant, the voltage feedback signal V generated by sampling at this time FB , eliminating the influence of the diode conduction voltage drop, and more accurately reflecting the output voltage V OUT Based on this, in the present disclosure, according to the input voltage signal V IN and node voltage signal V SW The sampling control signal Vpls is generated by judging the zero-crossing moment of the secondary winding current, and then the sampling control signal Vpls is used to sample the voltage V on the third winding at the zero-crossing moment of the secondary winding current. AUX Forming the voltage feedback signal V FB In generating the voltage feedback signal V FB In the embodiment of the present invention, the influence of the conduction voltage drop of the diode D1 on the output voltage detection accuracy can be avoided, and the accuracy is high. In general, the voltage feedback signal V FB Then it can be input to the control circuit 13, and the control circuit 13 can be input to the control circuit 13 according to the voltage feedback signal V FB A switch control signal CTL is generated, and the on and off time of the main switch tube MS is controlled by feedback control.

[0029] Figure 2 The circuit structure of the output voltage sampling circuit in some embodiments is shown. Specifically, the sampling control circuit 11 at least includes a filtering unit 111 and a comparing unit 112 .

[0030] The filter unit 111 has a first terminal, a second terminal and a third terminal. The first terminal of the filter unit 111 is coupled to the node voltage signal V SW The second end of the filter unit 111 is coupled to the input voltage signal V IN , the filtering unit 111 is used to filter the node voltage signal V SW and the input voltage signal V IN The comparison unit 112 has a first terminal, a second terminal and an output terminal. The first terminal of the comparison unit 112 receives the ramp signal V1, and the second terminal of the comparison unit 112 receives the input voltage signal V IN The comparison unit 112 compares the ramp signal V1 with the input voltage signal V IN Compare and generate a sampling control signal Vpls at its output.

[0031] See also Figure 3 The waveform diagram of the relevant parameters shown is as follows. In each switching cycle, when the main switch tube MS is turned on, the node voltage signal V SW is zero, the ramp signal V1 will be INThe value starts to decrease linearly; when the main switch tube MS is disconnected, the node voltage signal V SW =V IN +n×(V do +V OUT ), node voltage signal V SW The value is greater than the input voltage V IN , the ramp signal V1 will linearly restore to the input voltage V IN When the ramp signal V1 rises to the value of the input voltage signal V IN The moment when the secondary winding current crosses zero is equal (inflection point a). Then, before the end of the switching cycle, ignoring the influence of parasitic parameters, the node voltage signal V SW Equal to the input voltage V IN .

[0032] exist Figure 2 In the illustrated embodiment, the comparison unit 112 is illustrated as a comparator. The first terminal, the second terminal and the output terminal of the comparison unit 112 correspond to the non-inverting input terminal, the inverting input terminal and the output terminal of the comparator, respectively. Whenever the ramp signal V1 rises to the same level as the input voltage signal V IN When the sampling control signal Vpls is equal, the sampling control signal Vpls generates a narrow pulse of a logic high level, and the narrow pulse of the sampling control signal Vpls corresponds to the moment when the secondary winding current passes through zero in each switching cycle. In other embodiments, the sampling control signal Vpls can also generate a narrow pulse of a logic low level when the secondary winding current passes through zero, and those skilled in the art can flexibly configure it as needed.

[0033] Continue reading Figure 2 In a specific embodiment, the filtering unit 111 includes a filtering resistor R0 and a filtering capacitor C0.

[0034] The filter resistor R0 has a first end and a second end, the first end of the filter resistor R0 is coupled to the first end of the filter unit 111, and the second end of the filter resistor R0 is coupled to the third end of the filter unit 111; the filter capacitor C0 has a first end and a second end, the first end of the filter capacitor C0 is coupled to the second end of the filter resistor R0, and the second end of the filter capacitor C0 is coupled to the second end of the filter unit 111.

[0035] In one embodiment, the sampling control circuit 11 may further include a first voltage dividing unit 113 and a second voltage dividing unit 114. The first voltage dividing unit 113 receives the node voltage signal V SW , and the node voltage signal V SW The first voltage division signal generated after voltage division is sent to the first end of the filter unit 111; the second voltage division unit 114 receives the input voltage signal V IN , and the input voltage signal V INThe second voltage-divided signal V2 generated after voltage division is sent to the second end of the filter unit 111; at this time, the filter unit 111 filters the voltage difference between the first voltage-divided signal and the second voltage-divided signal V2 and generates a ramp signal V1 at its third end; the comparison unit 112 compares the ramp signal V1 with the second voltage-divided signal V2 and generates a sampling control signal Vpls at its output end. It can be understood that by comparing the node voltage signal V SW and the input voltage signal V IN After the voltage is divided and filtered, a smaller filter unit and a comparison unit can be selected. In this embodiment, the ramp signal V1 generated is directly converted to the node voltage signal V SW The waveform of the ramp signal V1 generated after filtering is the same, except that its value is reduced by the same voltage division ratio relative to the previous value. In one embodiment, the voltage division ratio of the first voltage division unit 113 and the second voltage division unit 114 is the same. Figure 3 Schematic diagram of the waveform of the ramp signal V1. At this time, the maximum value of the ramp signal V1 is shown as k×V SW , the second voltage division signal V2 = k × V IN , wherein k is the voltage division ratio between the first voltage division unit 113 and the second voltage division unit 114 .

[0036] exist Figure 2 In the illustrated embodiment, the first voltage dividing unit 113 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 receives the node voltage signal V SW The second end of the first resistor R1 is coupled to the first end of the second resistor R2, and the second end of the second resistor R2 is coupled to the reference ground; the common end of the first resistor R1 and the second resistor R2 generates a first voltage division signal. The second voltage division unit 114 includes a third resistor R3 and a fourth resistor R4. The first end of the third resistor R3 receives the input voltage signal V IN , the second end of the third resistor is coupled to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is coupled to the reference ground; the common end of the third resistor R3 and the fourth resistor R4 generates a second voltage division signal V2.

[0037] In a specific embodiment, the resistance values ​​of the first resistor R1 and the third resistor R3 are equal, and the resistance values ​​of the second resistor R2 and the fourth resistor R4 are equal.

[0038] It should be noted that the above voltage division method is only a schematic representation, and those skilled in the art can use any existing voltage division method to make the node voltage signal V SW and the input voltage signal V IN Lower to a suitable level.

[0039] Figure 2The specific structure of the sampling and holding circuit 12 in some embodiments is shown. The sampling and holding circuit 12 at least includes a sampling switch tube M1 and a first capacitor C1. The sampling switch tube M1 has a first end, a second end and a control end. The second end of the sampling switch tube M1 is coupled to the input end of the sampling and holding circuit 12. The control end of the sampling switch tube M1 receives a sampling control signal Vpls, and the sampling control signal Vpls is used to control the conduction control of the sampling switch tube M1; the first capacitor C1 has a first end and a second end. The first end of the first capacitor C1 is coupled to the first end of the sampling switch tube M1. The output end of the sampling and holding circuit 12 is coupled to the common end of the first capacitor C1 and the sampling switch tube M1. In the above embodiment, the sampling control signal Vpls controls the sampling switch tube M1 to turn on at each time when the current of the secondary winding passes through zero, and uses the first capacitor C1 to sample and hold the voltage of the first end of the third winding at this time. After several cycles of collection, the voltage on the first end of the first capacitor C1 is a stable voltage feedback signal V FB .

[0040] exist Figure 2 In the embodiment shown, the sampling switch tube M1 is shown as an NMOS tube, and the first end, the second end and the control end of the sampling switch tube M1 correspond to the drain, the source and the gate of the NMOS tube respectively. Similarly, the sampling switch tube M1 can also select any suitable semiconductor switch device.

[0041] In some embodiments, a third voltage dividing unit 121 is further provided, and the third voltage dividing unit 121 receives the voltage V on the third winding. AUX , and the voltage V on the third winding AUX The third voltage-divided signal generated after voltage division is sent to the input end of the sampling and holding circuit 12. In this embodiment, the voltage V on the third winding AUX By sampling after voltage division, the size of the sampling circuit can be further reduced.

[0042] Specifically, Figure 2 As shown, the third voltage-dividing unit 121 includes a fifth resistor R5 and a sixth resistor R6, the first end of the fifth resistor R5 is coupled to the first end AUX of the third winding, the second end of the fifth resistor R5 is coupled to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is coupled to the reference ground, and the common end of the fifth resistor R5 and the sixth resistor R6 generates a third voltage-dividing signal. Similarly, the above voltage-dividing method is only schematically represented, and those skilled in the art can use any existing voltage-dividing method to achieve the same function.

[0043] Figure 4 The output voltage V of the flyback converter in some embodiments is shown OUTSampling method flow chart, the flyback converter includes a main switch tube MS, a transformer TF, a first diode D1 and a second diode D2, the transformer TF includes a primary winding, a secondary winding and a tertiary winding, the first end IN of the primary winding receives an input voltage signal V IN The main switch tube MS is coupled between the second end of the primary winding and the primary reference ground, the first end of the secondary winding is coupled to the output end of the flyback converter through the first diode D1, the first end AUX of the tertiary winding is coupled to the power supply end through the second diode D2, and the output voltage V OUT The sampling method includes the following steps S1-S3.

[0044] S1. Obtaining a node voltage signal V representing the voltage at a common node between the main switch tube MS and the primary winding SW .

[0045] S2, according to the node voltage signal V SW and the input voltage signal V IN Determine the moment when the secondary winding current passes through zero.

[0046] S3, at the moment when the secondary winding current passes through zero in each switching cycle, the voltage V on the third winding AUX The sample and hold is performed to generate a voltage representing the output voltage V of the flyback converter. OUT The voltage feedback signal V FB .

[0047] In some embodiments, step S2 includes steps S21 and S22.

[0048] S21, node voltage signal V SW and the input voltage signal V IN The voltage difference between them is filtered to generate a ramp signal V1.

[0049] S22, in each switching cycle, the ramp signal V1 is first raised to a level that is equal to the input voltage signal V IN The equal moment is taken as the zero-crossing moment of the secondary winding current.

[0050] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0051] Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An output voltage sampling circuit of a flyback converter, the flyback converter comprising a main switch tube, a transformer, a first diode and a second diode, the transformer comprising a primary winding, a secondary winding and a tertiary winding, the first end of the primary winding receiving an input voltage signal, the main switch tube coupled between the second end of the primary winding and a primary reference ground, the first end of the secondary winding coupled to the output end of the flyback converter through a first diode, the first end of the tertiary winding coupled to the power supply end through a second diode, characterized in that: The output voltage sampling circuit comprises: A sampling control circuit receives a node voltage signal and an input voltage signal, and determines the zero-crossing moment of the secondary winding current according to the node voltage signal and the input voltage signal to generate a sampling control signal, wherein the node voltage signal represents the voltage at a common node between the main switch tube and the primary winding; The sampling and holding circuit has an input end, an output end and a control end. The input end of the sampling and holding circuit is coupled to the first end of the third winding. The control end of the sampling and holding circuit receives a sampling control signal. The sampling and holding circuit samples and holds the voltage on the third winding according to the sampling control signal, and generates a voltage feedback signal at its output end. The voltage feedback signal represents the output voltage of the flyback converter.

2. The output voltage sampling circuit according to claim 1, characterized in that: The sampling control circuit comprises: A filter unit having a first end, a second end and a third end, wherein the first end of the filter unit is coupled to the node voltage signal, the second end of the filter unit is coupled to the input voltage signal, the filter unit filters the voltage difference between the node voltage signal and the input voltage signal and generates a ramp signal at the third end; The comparison unit has a first terminal, a second terminal and an output terminal. The first terminal of the comparison unit receives a ramp signal, the second terminal of the comparison unit receives an input voltage signal, and the comparison unit compares the ramp signal with the input voltage signal and generates a sampling control signal at its output terminal.

3. The output voltage sampling circuit according to claim 2, characterized in that: When the ramp signal rises to the input voltage signal, it indicates that the secondary winding current crosses zero.

4. The output voltage sampling circuit according to claim 2, characterized in that: The filtering unit comprises: A filter resistor having a first end and a second end, wherein the first end of the filter resistor is coupled to the first end of the filter unit, and the second end of the filter resistor is coupled to the third end of the filter unit; The filter capacitor has a first end and a second end. The first end of the filter capacitor is coupled to the second end of the filter resistor, and the second end of the filter capacitor is coupled to the second end of the filter unit.

5. The output voltage sampling circuit according to claim 2, characterized in that: The sampling control circuit also includes: A first voltage dividing unit receives a node voltage signal, divides the node voltage signal, and sends a first voltage dividing signal generated by dividing the node voltage signal to a first end of the filter unit; A second voltage dividing unit receives an input voltage signal, divides the input voltage signal, and sends a second voltage dividing signal generated to a second end of the filter unit; The filtering unit filters the voltage difference between the first voltage-divided signal and the second voltage-divided signal and generates the ramp signal at its third terminal; the comparing unit compares the ramp signal with the second voltage-divided signal and generates a sampling control signal at its output terminal.

6. The output voltage sampling circuit according to claim 5, characterized in that: The first voltage dividing unit and the second voltage dividing unit have the same voltage dividing ratio.

7. The output voltage sampling circuit according to claim 1, characterized in that: The sample-and-hold circuit comprises: A sampling switch tube having a first end, a second end and a control end, wherein the second end of the sampling switch tube is coupled to the input end of the sampling and holding circuit, and the control end of the sampling switch tube receives a sampling control signal, wherein the sampling control signal is used to control the conduction of the sampling switch tube; The first capacitor has a first end and a second end. The first end of the first capacitor is coupled to the first end of the sampling switch tube. The output end of the sampling and holding circuit is coupled to the common end of the first capacitor and the sampling switch tube.

8. The output voltage sampling circuit according to claim 1, characterized in that: Also includes: The third voltage dividing unit receives the voltage on the third winding, divides the voltage on the third winding, and sends the third voltage dividing signal generated to the input end of the sampling and holding circuit.

9. The output voltage sampling circuit according to claim 1, characterized in that: The flyback converter further includes: The control circuit receives the voltage feedback signal and generates a switch control signal according to the voltage feedback signal, wherein the switch control signal is used to control the on-off time of the main switch tube.

10. A method for sampling an output voltage of a flyback converter, characterized in that: The flyback converter includes a main switch tube, a transformer, a first diode and a second diode. The transformer includes a primary winding, a secondary winding and a tertiary winding. The first end of the primary winding receives an input voltage signal. The main switch tube is coupled between the second end of the primary winding and a primary reference ground. The first end of the secondary winding is coupled to the output end of the flyback converter through a first diode. The first end of the tertiary winding is coupled to the power supply end through a second diode. The output voltage sampling method includes: Acquire a node voltage signal representing a voltage at a common node between the main switch tube and the primary winding; Determine the zero-crossing moment of the secondary winding current according to the node voltage signal and the input voltage signal; At the moment when the secondary winding current passes through zero in each switching cycle, the voltage on the tertiary winding is sampled and held to generate a voltage feedback signal representing the output voltage of the flyback converter.

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