Universal discrete magnitude acquisition circuit boundary test circuit and method

Abstract

The invention discloses a universal discrete magnitude acquisition circuit boundary test circuit and method, and relates to the technical field of aviation power distribution. The device comprises a test power supply, a resistor and a configurable switch. The configurable discrete magnitude acquisition test circuit, discrete magnitude acquisition excitation input, and impedance change of discrete magnitude input signals to a power supply VD and PGND are realized through a switch. The impedance boundary test and the voltage boundary test of the high / open and ground / open discrete magnitude acquisition circuit are realized through the adjustable VD voltage and the adjustable R1 and R2 resistances. By testing the boundary and limit of the discrete magnitude acquisition circuit, the impedance critical value and the voltage critical value respectively corresponding to a ground signal, a high signal and an open circuit signal which can be identified by the discrete magnitude acquisition circuit are verified, problems are efficiently found, design defects and errors are avoided, the design robustness of discrete signal acquisition software and hardware is evaluated, and the reliability of a power distribution system is ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of aviation power distribution systems, and in particular relates to a universal discrete quantity acquisition circuit boundary test circuit and method. Background Art

[0002] Discrete quantity signals in the power distribution system of aircraft usually include 28V high signal and ground signal. Discrete quantity acquisition circuits are usually divided into 28V high / open discrete quantity acquisition circuits and ground / open discrete quantity acquisition circuits. There are many physical meanings represented by discrete quantity signals, such as excitation signal status, equipment position status, current working status of aircraft, working status of a certain equipment, etc. During the operation of the power distribution system, it is necessary for the internal devices of the system to collect these discrete quantity states from each other to determine whether the state is valid or invalid, which is used as the judgment condition for the execution of some tasks within the power distribution system or equipment. Due to the differences in the design of discrete quantity acquisition interfaces of various devices in the power distribution system and the interference to the discrete quantity acquisition interface during the operation of the system, it is very easy to cause the design tolerance of the discrete quantity acquisition circuit to fail to meet the various scenarios of system operation, and it is difficult to simulate the actual situation on the aircraft in the ground test environment, resulting in the power distribution system Failure during the actual operation of the aircraft, and the failure that occurs is often not reproducible in the ground environment. At present, although redundancy design or software non-similar redundancy design has been carried out for key and important discrete quantity acquisition functions, most flight failures have been solved, but there are still faults such as false alarms caused by unreasonable discrete quantity acquisition threshold design. Therefore, it is necessary to carry out testing and verification of the boundaries and limit indicators of discrete quantity acquisition circuits, and leave sufficient margin during design to adapt to various interference or application scenarios on the aircraft and ensure reliable and stable operation of the power distribution system. Summary of the invention

[0003] The purpose of the present invention is to complete the assessment of discrete quantity acquisition function in the test and verification of aircraft power distribution system and related equipment, and in particular to provide a general discrete quantity acquisition circuit boundary test method.

[0004] In view of this, according to one aspect of an embodiment of the present invention, a universal discrete quantity acquisition circuit boundary test circuit is provided, including: a power supply VD, a resistor R1, a resistor R2, and switches S1 to S6, the power supply VD is respectively connected to switch S5, switch S3, and switch S2, the other end of switch S2 is connected to the power interface of the circuit under test, the other end of switch S5 is connected in series with the resistor R1, and the other end of resistor R1 is connected in parallel with switch S3; the power ground PGND is connected to the resistor R2, switch S4, and switch S1, the other end of switch S1 is connected to the ground interface of the circuit under test, and the other end of resistor R2 is connected in series with switch S6; the resistor R1, switch S3, switch S6, and switch S4 are all connected to the acquisition interface of the circuit under test.

[0005] Optionally, the power supply VD is a voltage-adjustable power supply with an adjustable voltage range of 0 to 50V and a resolution of 0.1V.

[0006] Optionally, the resistors R1 and R2 are adjustable resistors, and the adjustable resistance range is 0 to 1 MΩ, and the resolution between 0 to 100 Ω is 0.1 Ω, and the resolution between 100 Ω to 1 MΩ is 10 Ω.

[0007] According to another aspect of the embodiment of the present invention, a general discrete quantity acquisition circuit boundary test method is also provided, such as the arbitrary circuit described above, the boundary test method is applicable to two discrete quantity acquisition circuits, high / open and ground / open, and the corresponding high / open and ground / open discrete quantity acquisition circuits under test are tested by different selection logics of switches S1 and S2;

[0008] When the measured discrete quantity acquisition circuit is of ground / open type, S1 is disconnected and S2 is closed, and the corresponding interfaces are the power supply interface and acquisition interface of the ground / open discrete quantity acquisition circuit;

[0009] When the measured discrete quantity acquisition circuit is of high / open type, S1 is closed and S2 is open, and the corresponding interfaces are the ground interface and acquisition interface of the high / open discrete quantity acquisition circuit;

[0010] When testing the ground / open discrete quantity acquisition circuit, S2 is closed, S4 or S6 is closed, and other switches are disconnected. The acquisition interface is grounded or grounded through resistor R2. When the ground impedance does not need to be considered, S4 closure is used as the ground signal excitation. When the ground resistance is required, S4 needs to be disconnected and S6 needs to be closed, and the ground impedance is adjusted through resistor R2.

[0011] When testing the high / open discrete quantity acquisition circuit, S1 is closed, S3 or S5 is closed, and other switches are disconnected. The acquisition interface is the power supply VD or is connected to the power supply VD through the resistor R1. When it is not necessary to consider the power supply voltage division, S3 closure is used as the high signal excitation. When there is a voltage division on the power supply VD, S3 needs to be disconnected and S5 closed, and the voltage division value or impedance is adjusted by the resistor R1.

[0012] Optionally, the power supply VD is an adjustable power supply. By adjusting the VD voltage to change continuously, the acquisition results corresponding to the upper and lower limit boundary points of the working power supply VD of the discrete quantity acquisition circuit are tested, as well as the limit voltage values ​​of the high signal, ground signal and open signal that can be collected by the discrete quantity acquisition circuit. It is judged whether the discrete quantity acquisition circuit meets the voltage threshold design and the limit voltage value corresponding to the discrete quantity signal that can be recognized by the discrete quantity acquisition circuit, and the design margin of the discrete quantity acquisition circuit is evaluated.

[0013] Optionally, the power supply VD is injected as a fault source, and the undervoltage and overvoltage fault scenarios of the power distribution system are simulated by adjusting the voltage of the power supply VD, so as to test the response of the discrete quantity acquisition circuit under the undervoltage and overvoltage fault conditions.

[0014] Optionally, resistors R1 and R2 are adjustable resistors. By adjusting the resistance values ​​of R1 and R2, the limit impedance of high signals, ground signals and open signals that can be recognized by the discrete quantity acquisition circuit when the impedance of the discrete quantity acquisition circuit to the power supply VD and the ground changes is tested, and it is determined whether the discrete quantity acquisition circuit meets the impedance threshold design, as well as the limit impedance value corresponding to the discrete quantity signal that can be recognized by the discrete quantity acquisition circuit, to evaluate the design margin of the discrete quantity acquisition circuit.

[0015] Optionally, by adjusting the impedance values ​​of R1 and R2 at the same time as fault injection, the series-parallel impedance changes to the power supply and PGND equivalent to the internal fault of the discrete quantity acquisition circuit are simulated to test whether the output characteristics of the discrete quantity acquisition circuit are correct under the fault condition.

[0016] The discrete quantity acquisition test circuit can be configured through the S1 and S2 switches. The discrete quantity acquisition excitation input is realized through the S3 and S4 switches. The impedance change of the discrete quantity input signal to the power supply VD and PGND is realized through S5, S6, R1, and R2. The impedance boundary test and voltage boundary test of the high / open and ground / open discrete quantity acquisition circuits are realized through the adjustable VD voltage and the adjustable R1 and R2 resistances. By testing the boundaries and limits of the discrete quantity acquisition circuit, the impedance critical value and voltage critical value corresponding to the ground signal, high signal, and open circuit signal that can be identified by the discrete quantity acquisition circuit are verified, problems are efficiently discovered, design defects and errors are avoided, the robustness of the discrete signal acquisition software and hardware design is evaluated, and the reliability of the power distribution system is ensured.

[0017] A universal discrete quantity acquisition circuit boundary testing method described in the present invention builds a universal test platform for discrete quantity acquisition circuits, which can be configured as high / open and ground / open discrete quantity acquisition circuit tests according to actual needs; at the same time, it realizes the boundary and limit testing of the discrete quantity acquisition circuit, verifies the impedance critical value and voltage critical value corresponding to the ground signal, high signal, and open circuit signal respectively identifiable by the discrete quantity acquisition circuit, can efficiently discover problems, avoid design defects and errors, and evaluate the robustness of discrete signal acquisition software and hardware design, and has been successfully applied to the test verification of a certain type of aircraft power distribution system. The technical solution and boundary and limit testing ideas adopted can be extended to the robustness design assessment of discrete quantity acquisition functions of other systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a schematic diagram of boundary test of a general discrete quantity acquisition circuit. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] According to one aspect of an embodiment of the present invention, a universal discrete quantity acquisition circuit boundary test circuit is provided, including: a power supply VD, a resistor R1, a resistor R2, and switches S1 to S6, wherein the power supply VD is respectively connected to switches S5, S3, and S2, the other end of switch S2 is connected to the power interface of the circuit under test, the other end of switch S5 is connected in series with the resistor R1, and the other end of resistor R1 is connected in parallel with switch S3; a power ground PGND is connected to resistor R2, switch S4, and switch S1, the other end of switch S1 is connected to the ground interface of the circuit under test, and the other end of resistor R2 is connected in series with switch S6; resistor R1, switch S3, switch S6, and switch S4 are all connected to the acquisition interface of the circuit under test.

[0021] Furthermore, the power supply VD is a voltage-adjustable power supply with an adjustable voltage range of 0 to 50V and a resolution of 0.1V.

[0022] Furthermore, the resistors R1 and R2 are adjustable resistors, and the adjustable resistance range is 0-1MΩ, and the resolution between 0-100Ω is 0.1Ω, and the resolution between 100Ω-1MΩ is 10Ω.

[0023] According to another aspect of the embodiment of the present invention, a general discrete quantity acquisition circuit boundary test method is also provided, such as the arbitrary circuit described above, the boundary test method is applicable to two discrete quantity acquisition circuits, high / open and ground / open, and the corresponding high / open and ground / open discrete quantity acquisition circuits under test are tested by different selection logics of switches S1 and S2;

[0024] When the measured discrete quantity acquisition circuit is of ground / open type, S1 is disconnected and S2 is closed, and the corresponding interfaces are the power supply interface and acquisition interface of the ground / open discrete quantity acquisition circuit;

[0025] When the measured discrete quantity acquisition circuit is of high / open type, S1 is closed and S2 is open, and the corresponding interfaces are the ground interface and acquisition interface of the high / open discrete quantity acquisition circuit;

[0026] When testing the ground / open discrete quantity acquisition circuit, S2 is closed, S4 or S6 is closed, and other switches are disconnected. The acquisition interface is grounded or grounded through resistor R2. When the ground impedance does not need to be considered, S4 closure is used as the ground signal excitation. When the ground resistance is required, S4 needs to be disconnected and S6 needs to be closed, and the ground impedance is adjusted through resistor R2.

[0027] When testing the high / open discrete quantity acquisition circuit, S1 is closed, S3 or S5 is closed, and other switches are disconnected. The acquisition interface is the power supply VD or is connected to the power supply VD through the resistor R1. When it is not necessary to consider the power supply voltage division, S3 closure is used as the high signal excitation. When there is a voltage division on the power supply VD, S3 needs to be disconnected and S5 closed, and the voltage division value or impedance is adjusted by the resistor R1.

[0028] Furthermore, the power supply VD is an adjustable power supply. By adjusting the VD voltage to change continuously, the acquisition results corresponding to the upper and lower limit boundary points of the working power supply VD of the discrete quantity acquisition circuit are tested, as well as the limit voltage values ​​of the high signal, ground signal and open signal that can be collected by the discrete quantity acquisition circuit. It is judged whether the discrete quantity acquisition circuit meets the voltage threshold design, as well as the limit voltage value corresponding to the discrete quantity signal that can be recognized by the discrete quantity acquisition circuit, and the design margin of the discrete quantity acquisition circuit is evaluated.

[0029] Furthermore, the power supply VD is injected as a fault source. By adjusting the voltage of the power supply VD, the undervoltage and overvoltage fault scenarios of the distribution system are simulated to test the response of the discrete quantity acquisition circuit under the undervoltage and overvoltage fault conditions.

[0030] Furthermore, resistors R1 and R2 are adjustable resistors. By adjusting the resistance changes of R1 and R2, the limit impedances of high signals, ground signals and open signals that can be recognized by the discrete quantity acquisition circuit are tested when the impedance of the discrete quantity acquisition circuit to the power supply VD and to the ground changes. It is determined whether the discrete quantity acquisition circuit meets the impedance threshold design, as well as the limit impedance value corresponding to the discrete quantity signal that can be recognized by the discrete quantity acquisition circuit, and the design margin of the discrete quantity acquisition circuit is evaluated.

[0031] Furthermore, by adjusting the impedance values ​​of R1 and R2 at the same time as fault injection, the series-parallel impedance changes to the power supply and PGND equivalent to the internal fault of the discrete quantity acquisition circuit are simulated to test whether the output characteristics of the discrete quantity acquisition circuit are correct under fault conditions.

[0032] Example 1

[0033] The present invention provides a universal discrete quantity acquisition circuit boundary testing method, which is applicable to two discrete quantity acquisition circuits, high / open and ground / open, and tests the corresponding high / open and ground / open discrete quantity acquisition circuits under test through different selection logics of switches S1 and S2.

[0034] The universal discrete quantity acquisition circuit boundary test method has a power supply interface, a ground interface and an acquisition interface with the discrete quantity acquisition circuit under test.

[0035] When the measured discrete quantity acquisition circuit is of ground / open type, S1 is disconnected and S2 is closed, and the corresponding interfaces are the power supply interface and acquisition interface of the ground / open discrete quantity acquisition circuit;

[0036] When the measured discrete quantity acquisition circuit is of high / open type, S1 is closed and S2 is open, and the corresponding interfaces are the ground interface and acquisition interface of the high / open discrete quantity acquisition circuit.

[0037] When testing the ground / open discrete quantity acquisition circuit, S2 is closed, S4 or S6 is closed, and other switches are disconnected. The acquisition interface is grounded or grounded through resistor R2. When the ground impedance does not need to be considered, S4 closure is used as the ground signal excitation. When the ground resistance is required, S4 needs to be disconnected and S6 needs to be closed, and the ground impedance is adjusted through resistor R2.

[0038] When testing the high / open discrete quantity acquisition circuit, S1 is closed, S3 or S5 is closed, and other switches are disconnected. The acquisition interface is the power supply VD or is connected to the power supply VD through the resistor R1. When it is not necessary to consider the power supply voltage division, S3 closure is used as the high signal excitation. When there is a voltage division on the power supply VD, S3 needs to be disconnected and S5 closed, and the voltage division value or impedance is adjusted by the resistor R1.

[0039] VD is an adjustable power supply. By adjusting the VD voltage to change continuously, the discrete quantity acquisition circuit is tested for the acquisition results corresponding to the upper and lower limit boundary points of the working power supply VD, as well as the limit voltage values ​​of the high signal, ground signal and open signal that can be acquired by the discrete quantity acquisition circuit. Determine whether the discrete quantity acquisition circuit meets the voltage threshold design, and the limit voltage value corresponding to the discrete quantity signal that can be identified by the discrete quantity acquisition circuit, evaluate the design margin of the discrete quantity acquisition circuit, and judge whether the design margin is reasonable and reliable.

[0040] R1 and R2 are adjustable resistors. By adjusting the resistance of R1 and R2, the limit impedance of the high signal, ground signal and open signal that the discrete quantity acquisition circuit can identify is tested when the impedance of the discrete quantity acquisition circuit to the power supply VD and to the ground changes. Determine whether the discrete quantity acquisition circuit meets the impedance threshold design, and the limit impedance value corresponding to the discrete quantity signal that the discrete quantity acquisition circuit can identify, evaluate the design margin of the discrete quantity acquisition circuit, and judge whether the design margin is reasonable and reliable.

[0041] By adjusting the impedance values ​​of R1 and R2, it can also be used as a fault injection to simulate the series and parallel impedance changes of the power supply and PGND equivalent to the internal fault of the discrete quantity acquisition circuit. Test whether the output characteristics of the discrete quantity acquisition circuit are correct under fault conditions.

[0042] Example 2

[0043] like Figure 1 A schematic diagram of a universal discrete quantity acquisition circuit boundary test method provided by the present invention is shown. A universal discrete quantity acquisition circuit boundary test method includes a test power supply VD, a ground PGND, a resistor R1, a resistor R2 and configurable switches S1-S6.

[0044] The general discrete quantity acquisition circuit boundary test method is applicable to two discrete quantity acquisition circuits: high / open and ground / open. The corresponding high / open and ground / open discrete quantity acquisition circuits are tested through switches S1 and S2 according to different selection logics in Table 1.

[0045] Table 1 is a general discrete quantity acquisition circuit boundary test logic table

[0046]

[0047] When the measured discrete quantity acquisition circuit is of ground / open type, S1 is disconnected and S2 is closed, and the corresponding interfaces are the power supply interface and acquisition interface of the ground / open discrete quantity acquisition circuit.

[0048] When the measured discrete quantity acquisition circuit is of high / open type, S1 is closed and S2 is open, and the corresponding interfaces are the ground interface and acquisition interface of the high / open discrete quantity acquisition circuit.

[0049] When testing the ground / open discrete quantity acquisition circuit, S2 is closed, S4 or S6 is closed, and other switches are disconnected. The acquisition interface is grounded or grounded through resistor R2. When the grounding impedance does not need to be considered, S4 closure is used as the grounding signal excitation. When the grounding resistance is required, S4 needs to be disconnected and S6 closed, and the grounding impedance is adjusted through resistor R2.

[0050] When testing the high / open discrete quantity acquisition circuit, S1 is closed, S3 or S5 is closed, and other switches are disconnected. The acquisition interface is the power supply VD or is connected to the power supply VD through the resistor R1. When it is not necessary to consider the power supply voltage division, S3 closure is used as the high signal excitation. When there is a voltage division on the power supply VD, S3 needs to be disconnected and S5 closed, and the voltage division value or impedance is adjusted by the resistor R1.

[0051] The power supply VD is an adjustable power supply. By adjusting the VD voltage to change continuously, the discrete quantity acquisition circuit is tested for the acquisition results corresponding to the upper and lower limit boundary points of the working power supply VD, as well as the limit voltage values ​​of the high signal, ground signal and open signal that can be acquired by the discrete quantity acquisition circuit. For example, when the VD voltage is adjusted from 0V to VH, the discrete quantity acquisition result jumps from "0" to "1", and when the VD voltage is adjusted from VH to VL, the discrete quantity acquisition result jumps from "1" to "0". The threshold of the upper limit of the discrete quantity acquisition is VH; the threshold of the lower limit is VL. If VH-VL is greater than 5V, it is determined that the threshold design margin of the discrete quantity acquisition circuit is reasonable and reliable, otherwise the parameters of the circuit under test need to be adjusted to ensure the threshold design margin.

[0052] Resistors R1 and R2 are adjustable resistors. By adjusting the resistance of R1 and R2, the discrete quantity acquisition circuit can be tested for the high signal, ground signal and open signal limit impedance that the discrete quantity acquisition circuit can identify when the impedance to the power supply VD and the ground changes. For example, when adjusting R1 and the resistance value increases from 0 to RH, the discrete quantity acquisition result jumps from "0" to "1", and when adjusting the R1 voltage from RH to RL, the discrete quantity acquisition result jumps from "1" to "0". The threshold of the upper limit of discrete quantity acquisition is RH; the lower limit of acquisition threshold is RL. If RH-RL is greater than 1KΩ, it is determined that the threshold design margin of the discrete quantity acquisition circuit is reasonable and reliable, otherwise the parameters of the circuit under test need to be adjusted to ensure the threshold design margin.

[0053] At the same time, by adjusting the impedance values ​​of R1 and R2, it can also be used as a fault injection. For example, by adjusting R1 to increase or decrease, the parallel impedance of the analog discrete quantity acquisition circuit to the power supply becomes larger or smaller; by adjusting R2 to increase or decrease, the parallel impedance of the analog discrete quantity acquisition circuit to PGND becomes larger or smaller; to test whether the output characteristics of the discrete quantity acquisition circuit are correct in the case of line faults.

[0054] The above is only a specific embodiment of the present invention, and the present invention is described in detail. The unexplained part is a conventional technology. However, the protection scope of the present invention is not limited to this. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A general discrete quantity acquisition circuit boundary test circuit, characterized in that: include: Power supply VD, resistor R1, resistor R2, switches S1~S6, power supply VD is connected to switch S5, switch S3, and switch S2 respectively, the other end of switch S2 is connected to the power interface of the circuit under test, the other end of switch S5 is connected in series with resistor R1, and the other end of resistor R1 is connected in parallel with switch S3; power ground PGND is connected to resistor R2, switch S4, and switch S1, the other end of switch S1 is connected to the ground interface of the circuit under test, and the other end of resistor R2 is connected in series with switch S6; resistor R1, switch S3, switch S6, and switch S4 are all connected to the acquisition interface of the circuit under test.

2. The circuit according to claim 1, characterized in that The power supply VD is a voltage adjustable power supply with an adjustable voltage range of 0 to 50V and a resolution of 0.1V.

3. The circuit according to claim 1, characterized in that The resistors R1 and R2 are adjustable resistors, and the adjustable resistance range is 0-1MΩ. The resolution between 0-100Ω is 0.1Ω, and the resolution between 100Ω-1MΩ is 10Ω.

4. A general discrete quantity acquisition circuit boundary test method, characterized in that: According to any circuit as described in claims 1 to 3, the boundary test method is applicable to two discrete quantity acquisition circuits of high / open and ground / open, and the corresponding high / open and ground / open discrete quantity acquisition circuits under test are tested by different selection logics of switches S1 and S2; When the measured discrete quantity acquisition circuit is of ground / open type, S1 is disconnected and S2 is closed, and the corresponding interfaces are the power supply interface and acquisition interface of the ground / open discrete quantity acquisition circuit; When the measured discrete quantity acquisition circuit is of high / open type, S1 is closed and S2 is open, and the corresponding interfaces are the ground interface and acquisition interface of the high / open discrete quantity acquisition circuit; When testing the ground / open discrete quantity acquisition circuit, S2 is closed, S4 or S6 is closed, and other switches are disconnected. The acquisition interface is grounded or grounded through resistor R2. When the ground impedance does not need to be considered, S4 closure is used as the ground signal excitation. When the ground resistance is required, S4 needs to be disconnected and S6 needs to be closed, and the ground impedance is adjusted through resistor R2. When testing the high / open discrete quantity acquisition circuit, S1 is closed, S3 or S5 is closed, and other switches are disconnected. The acquisition interface is the power supply VD or is connected to the power supply VD through the resistor R1. When it is not necessary to consider the power supply voltage division, S3 closure is used as the high signal excitation. When there is a voltage division on the power supply VD, S3 needs to be disconnected and S5 closed, and the voltage division value or impedance is adjusted by the resistor R1.

5. The method according to claim 4, characterized in that: The power supply VD is an adjustable power supply. By adjusting the VD voltage to change continuously, the discrete quantity acquisition circuit is tested for the acquisition results corresponding to the upper and lower limit boundary points of the working power supply VD, as well as the limit voltage values ​​of the high signal, ground signal and open signal that can be collected by the discrete quantity acquisition circuit. This is used to determine whether the discrete quantity acquisition circuit meets the voltage threshold design, as well as the limit voltage value corresponding to the discrete quantity signal that can be identified by the discrete quantity acquisition circuit, and to evaluate the design margin of the discrete quantity acquisition circuit.

6. The method according to claim 4, characterized in that: The power supply VD is injected as a fault source. By adjusting the voltage of the power supply VD, the undervoltage and overvoltage fault scenarios of the distribution system are simulated to test the response of the discrete quantity acquisition circuit under undervoltage and overvoltage fault conditions.

7. The method according to claim 4, characterized in that: Resistors R1 and R2 are adjustable resistors. By adjusting the resistance values ​​of R1 and R2, the limit impedance of the high signal, ground signal and open signal that the discrete quantity acquisition circuit can recognize when the impedance to the power supply VD and the ground changes is tested. It is judged whether the discrete quantity acquisition circuit meets the impedance threshold design, and the limit impedance value corresponding to the discrete quantity signal that the discrete quantity acquisition circuit can recognize, and the design margin of the discrete quantity acquisition circuit is evaluated.

8. The method according to claim 4, characterized in that: By adjusting the impedance values ​​of R1 and R2 at the same time as fault injection, the series-parallel impedance changes to the power supply and PGND equivalent to the internal fault of the discrete quantity acquisition circuit are simulated to test whether the output characteristics of the discrete quantity acquisition circuit are correct under fault conditions.

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