Clock signal frequency determination method and chip

Abstract

The invention discloses a clock signal frequency determination method and a chip, and the method comprises the steps: in response to a frequency detection instruction for a signal of a to-be-detected clock, controlling a linear feedback shift register to start counting the signal of the to-be-detected clock, and controlling an accumulation counter to start counting the signal of a reference clock; if it is determined that the counting end condition is met, the linear feedback shift register and the accumulation counter are controlled to stop counting, and the frequency of the signal of the to-be-tested clock is determined based on the first count value of the linear feedback shift register and the second count value of the accumulation counter. Therefore, the feedback logic circuit of the linear feedback shift register is simple in structure and has simple processing logic, and the processing speed of the counting signal is far higher than that of a common accumulation counter, so that the counting speed of the linear feedback shift register is relatively high; and the counting frequency can be higher than the frequency of the signal of the clock to be detected, so that the high-frequency clock signal can be effectively detected.

Description

Technical Field

[0001] The present application relates to the technical field of frequency determination, and in particular to a method and chip for determining the frequency of a clock signal. Background Art

[0002] Frequency detection is of great significance in the field of chip security. Physical chips are often affected by unstable environments, causing chip system errors. In cryptographic chips, these unstable factors often attack the chip entity as intentional behavior of attackers, thereby obtaining key information in the chip. Common attack methods include frequency attacks. The use of abnormal frequencies can make the original program skip specific operations, and the attacker can further obtain key information. Frequency meters are usually used to protect against frequency attacks. A frequency meter is an instrument that measures the frequency of a signal. It can accurately determine the frequency of periodic signals such as various electrical signals and optical signals, and it plays an important role in the field of electronic measurement. The current frequency meter based on digital circuits has achieved high-precision and high-stability frequency measurement. Signal spectrum analysis based on frequency meters has also expanded more application scenarios, including communications, radar, etc. According to the results of the frequency meter, abnormal frequencies can be shielded so that the system does not work at abnormal frequencies, thereby achieving the purpose of information protection.

[0003] Frequency measurement requires a wide measurement range and high test accuracy. The frequencies used in frequency attacks often have extremely high frequency characteristics, so frequency measurement needs to be able to adapt to high-frequency environments. Currently, there are detection methods based on analog circuits and frequency detection methods based on digital circuits. The analog frequency meter used in the detection method based on analog circuits uses a capacitor charge and discharge method to measure frequency. The frequency of the clock signal is calculated by detecting the relationship between the number of capacitor charge and discharge times and time. This method is not very accurate.

[0004] The frequency measurement accuracy based on digital circuits is higher than that of analog circuits, but the existing digital circuit measurement methods are also affected by circuit process conditions, making it difficult to measure high-frequency clocks. Traditional counters (such as progressive adder counters) trigger the counter value to increase by 1 every clock cycle. As the bit width increases, the circuit complexity will increase, which will in turn affect the counting frequency of the progressive adder counter. When the clock frequency is higher than the counting frequency of its counter, the counter cannot capture part of the pulse signal of the clock signal and can no longer count effectively, so it cannot detect the frequency of the high-frequency clock. Summary of the invention

[0005] The embodiments of the present application provide a method and a chip for determining the frequency of a clock signal, which can effectively detect the frequency of a high-frequency clock signal.

[0006] The technical solution of this application is implemented as follows: In a first aspect, the present application provides a method for determining the frequency of a clock signal, comprising: In response to a frequency detection instruction for a signal of a clock to be measured, a linear feedback shift register is controlled to start counting the signal of the clock to be measured, and an accumulative counter is controlled to start counting the signal of a reference clock; wherein a bit width of the linear feedback shift register is greater than a counter bit width threshold, and a circuit complexity of the linear feedback shift register is less than a circuit complexity threshold; If it is determined that the counting end condition is met, controlling the linear feedback shift register and the accumulative counter to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulative counter; The frequency of the signal of the clock to be measured is determined based on the first count value and the second count value.

[0007] In a second aspect, the present application provides a chip, including: a control unit and a processing unit, wherein: The control unit is used to control the linear feedback shift register to start counting the signal of the clock to be measured, and control the accumulator counter to start counting the signal of the reference clock in response to the frequency detection instruction for the signal of the clock to be measured corresponding to the chip; wherein the bit width of the linear feedback shift register is greater than the counter bit width threshold, and the circuit complexity of the linear feedback shift register is less than the circuit complexity threshold; The control unit is further configured to control the linear feedback shift register and the accumulative counter to stop counting if it is determined that the counting end condition is met, and obtain a first count value of the linear feedback shift register and a second count value of the accumulative counter; The processing unit is used to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

[0008] In an embodiment of the present application, a method for determining the frequency of a clock signal is provided, comprising: in response to a frequency detection instruction for a signal of a clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulator to start counting the signal of a reference clock; if it is determined that a counting end condition is met, controlling the linear feedback shift register and the accumulator to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulator; based on the first count value and the second count value, determining the frequency of the signal of the clock to be measured. In this way, since the feedback logic circuit structure of the linear feedback shift register is simple, the feedback logic circuit has a simple processing logic, and the processing speed of the counting signal is much faster than the processing speed of the counting signal of the ordinary accumulator, therefore, the counting of the linear feedback shift register is faster, and its counting frequency can be higher than the frequency of the signal of the clock to be measured, thereby realizing effective detection of high-frequency clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram of a flow chart of a method for determining the frequency of a clock signal provided in an embodiment of the present application; Figure 2 A flow chart of a frequency detection method based on linear feedback shift register counting provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a frequency detection system based on linear feedback shift register counting provided in an embodiment of the present application; Figure 4 A schematic diagram of a frequency detection process of a frequency detection system based on linear feedback shift register counting provided in an embodiment of the present application; Figure 5 A schematic diagram of the composition structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0010] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0011] In the related art, the frequency detection method based on digital circuit usually uses a clock with stable frequency and high precision, such as a quartz crystal oscillator clock as the reference clock. The frequency measurement uses the reference clock and the clock to be measured to start counting at the same time. After the same period of clocks, the counts of the two are respectively (reference clock count value during the same period of time) and (The clock count value to be measured in the same period of time). The frequency relationship can be obtained based on the count value relationship: According to this frequency relationship, the clock frequency to be measured can be obtained , as shown in formula (1): (1); Set the clock frequency to be measured Compare with the frequency threshold to determine whether the current frequency is abnormal. As shown in the above formula, the accuracy of the frequency to be measured and the count size during this period of time related. The larger the denominator, the higher the precision of the measured clock frequency (based on formula (1), the larger the denominator, the higher the precision of the clock frequency to be measured (fine), for example, the frequency precision represented by one hundredth of the numerator is higher than the frequency precision represented by one third), which means that high-precision measurement requires a large bit width counter to achieve, but a large bit width counter will be limited by high frequency. Traditional progressive adder counters will lead to circuit complexity as the bit width increases, and the increase in circuit complexity will lead to a decrease in counting frequency. When the clock frequency is higher than the counting frequency of its counter, the counter can no longer count effectively, so ordinary measuring meters are limited in application in high-frequency detection.

[0012] Based on the problems in the related art, the present application provides a method for determining the frequency of a clock signal, which can be applied to the frequency detection scenario of the clock signal of a cryptographic chip, such as Figure 1 As shown, the method includes: S101 . In response to a frequency detection instruction for a signal of a clock to be measured, control a linear feedback shift register to start counting the signal of the clock to be measured, and control an accumulative counter to start counting the signal of a reference clock.

[0013] It should be noted that the bit width of the linear feedback shift register can be greater than the counter bit width threshold, that is, the bit width of the linear feedback shift register is relatively large, wherein the bit width of the linear feedback shift register can be the number of binary bits used to store the count value in the linear feedback shift register, and the counter bit width threshold can be a pre-set large bit width value, for example, it can be 15, 18, 20, etc.

[0014] In some embodiments, the circuit structure of the linear feedback shift register is different from the circuit structure of the accumulator counter, the bit width of the accumulator counter may be smaller than the counter bit width threshold, the bit width of the linear feedback shift register may be larger than the bit width of the accumulator counter, and the circuit complexity of the linear feedback shift register is smaller than the circuit complexity of the accumulator counter.

[0015] In some embodiments, since the bit width of the linear feedback shift register is greater than the counter bit width threshold, the linear feedback shift register has a larger bit width and a wider measurement range, and can count high-frequency clock signals to achieve high-precision clock signal detection.

[0016] In some embodiments, the clock to be measured can be a clock inside the cryptographic chip or a clock outside the cryptographic chip; the reference clock can be a clock with a stable frequency and high precision, for example, the reference clock can be a quartz crystal oscillator clock. The signal of the clock to be measured and the signal of the reference clock can both be periodic signals, for example, both can be square wave signals, the linear feedback shift register can be used to count the period of the signal of the clock to be measured, and the cumulative counter can be used to count the period of the signal of the reference clock.

[0017] In some embodiments, the frequency detection instruction for the signal of the clock to be measured may be an instruction for detecting the frequency of the signal of the clock to be measured, and the frequency detection instruction may be triggered by a user through a human-computer interaction interface to detect whether the frequency of the signal of the clock to be measured is abnormal. When it is determined that the frequency detection instruction for the signal of the clock to be measured is received, the linear feedback shift register and the accumulator counter may be controlled to start counting at the same time.

[0018] S102: If it is determined that the counting end condition is met, control the linear feedback shift register and the accumulating counter to stop counting, and obtain a first counting value of the linear feedback shift register and a second counting value of the accumulating counter.

[0019] It should be noted that the counting end condition can be a condition for indicating that the linear feedback shift register and the accumulator counter need to stop counting. The counting end condition can be triggered by the counting situation of the linear feedback shift register. For example, the counting end condition can be that the count value of the linear feedback shift register reaches a pre-designed value, and the pre-designed value can be less than or equal to the maximum count value of the linear feedback shift register.

[0020] In some embodiments, when it is determined that the counting end condition is met, the linear feedback shift register and the accumulator counter can be controlled to stop counting at the same time, and the count value when the linear feedback shift register stops counting is determined as the first count value, and the count value when the accumulator counter stops counting is determined as the second count value.

[0021] In some embodiments, since the signal of the clock to be measured and the signal of the reference clock may be different, the circuit structure of the linear feedback shift register and the circuit structure of the accumulator are different, the bit width of the linear feedback shift register and the bit width of the accumulator are different, and the circuit complexity of the linear feedback shift register and the circuit complexity of the accumulator are different, therefore, a first count value obtained by counting the clock to be measured by the linear feedback shift register and a second count value obtained by counting the reference clock by the accumulator may also be different.

[0022] S103 : Determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

[0023] In some embodiments, when the linear feedback shift register is a linear feedback shift register, the linear feedback shift register may not be the true count value of the signal of the clock to be measured; when the accumulative counter is an accumulative counter, the second count value may be the true count value of the signal of the reference clock. After obtaining the first count value and the second count value, the second count value may be converted based on the first count value and the maximum count value of the linear feedback shift register to obtain the true count value of the signal of the clock to be measured, and based on the true count value and the counting duration, the frequency of the signal of the clock to be measured is determined.

[0024] In the embodiment of the present application, in response to the frequency detection instruction for the clock signal, the linear feedback shift register is controlled to start counting the signal of the clock to be measured, and the cumulative counter is controlled to start counting the signal of the reference clock; if it is determined that the counting end condition is met, the linear feedback shift register and the cumulative counter are controlled to stop counting, and the first count value of the linear feedback shift register and the second count value of the cumulative counter are obtained; based on the first count value and the second count value, the frequency of the signal of the clock to be measured is determined. In this way, since the feedback logic circuit structure of the linear feedback shift register is simple, the feedback logic circuit has a simple processing logic, and the processing speed of the counting signal is much faster than the processing speed of the counting signal of the ordinary cumulative counter, therefore, the linear feedback shift register counts faster, and its counting frequency can be higher than the frequency of the signal of the clock to be measured, thereby realizing effective detection of high-frequency clock signals.

[0025] In some embodiments of the present application, in the process of determining whether the counting end condition is met, a first sequence state of the linear feedback shift register can be obtained; based on a preset correspondence between the sequence state and the count value of the linear feedback shift register, the count value corresponding to the first sequence state is determined; if the count value corresponding to the first sequence state is a candidate count value, it is determined that the counting end condition is met.

[0026] In some embodiments, the first sequence state may be a combination state of the values ​​of the binary bits in the linear feedback shift register. For example, when the bit width of the linear feedback shift register is 16, the first sequence state may be a sequence of 16 binary values ​​(0 or 1) corresponding to the 16 binary bits, for example, 0000010010000001. The first sequence state may reflect the counting status of the linear feedback shift register for the signal of the clock to be measured, and one sequence state corresponds to one counting value.

[0027] In some embodiments, since the number of cycles of the signal of the clock to be measured is continuously increasing, the corresponding count value is also continuously changing. Therefore, the first sequence state of the linear feedback shift register is also continuously changing. The first sequence state of the linear feedback shift register can be continuously acquired, or the sequence state of the linear feedback shift register can be acquired once at a preset time interval.

[0028] In some embodiments, the preset correspondence between the sequence state and the count value of the linear feedback shift register may be pre-established, one sequence state may correspond to one count value, and after the binary sequence corresponding to one sequence state is converted into a decimal number, the decimal number and the corresponding count value may be different. The linear feedback shift register may be tested in advance to determine the actual count values ​​corresponding to different sequence states, thereby obtaining the correspondence between the sequence state and the count value of the linear feedback shift register.

[0029] In some embodiments, after the first sequence state of the linear feedback shift register is obtained, the first sequence state may be matched with each sequence state in a preset corresponding relationship to obtain a count value corresponding to the first sequence state.

[0030] In some embodiments, the candidate count value may be 2 N , N is an integer greater than or equal to 0, and the candidate count value is less than the total number of sequence states of the linear feedback shift register, for example, the candidate count value may be 1, 2, 4, etc. Exemplarily, if the bit width of the linear feedback shift register is 22, and the total number of sequence states of the linear feedback shift register is 4194303, then the candidate count value may be 1, 2, 1024, 16384, etc.

[0031] In some embodiments, the candidate count value may include one or more candidate count values, and the candidate count value may be determined by the bit width of the linear feedback shift register. For example, if the bit width of the linear feedback shift register is 22, the candidate count value may be determined by 2 n The candidate count value can be increased by (n<=22) times. When n=2, the candidate count value can be increased by 4 times, and the candidate count values ​​can be 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, 262144, and 1048576.

[0032] In some embodiments, one or more candidate count values ​​can be determined based on the bit width of the linear feedback shift register. When it is determined that the count value corresponding to the first sequence state is the same as any candidate count value, it can be determined that the counting end condition is met and the counting of the linear feedback shift register and the accumulator counter is stopped.

[0033] It is understandable that since the candidate count value is 2N , N is a non-negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register. Therefore, when the count value corresponding to the first sequence state of the linear feedback shift register obtained is the candidate count value, it can be determined that the counting end condition is met, thereby improving the efficiency of clock signal frequency detection.

[0034] In some embodiments of the present application, the process of creating a preset correspondence between the sequence state and the count value of a linear feedback shift register may include: testing the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and a reference count value corresponding to the reference sequence state; and creating a preset correspondence between the sequence state and the count value of the linear feedback shift register based on each reference sequence state and the corresponding reference count value.

[0035] It should be noted that the number of reference sequence states can be determined by the bit width of the linear feedback shift register. For example, if the bit width of the linear feedback shift register is M, the corresponding number of reference sequence states can be 2. M -1.

[0036] In some embodiments, one sequence state corresponds to one reference count value, and the reference count values ​​corresponding to different reference sequence states may be actual count values ​​corresponding to the sequence state. During the process of testing the linear feedback shift register, the reference count values ​​corresponding to each reference sequence state may be recorded, and based on the one-to-one correspondence between each reference sequence state and the corresponding reference count value, a preset correspondence between the sequence state and the count value of the linear feedback shift register may be created.

[0037] In some embodiments, the preset correspondence between the sequence state and the count value of the linear feedback shift register can be embodied in a preset correspondence table, in which a reference sequence state corresponds to a reference count value. In addition, after the preset correspondence between the sequence state and the count value of the linear feedback shift register is created, the preset correspondence table can be stored, and in the process of storing the preset correspondence table, the reference sequence state and the corresponding reference count value can be stored as one entry.

[0038] It can be understood that by testing the linear feedback shift register, obtaining each reference sequence state and the corresponding reference count value of the linear feedback shift register, and creating a preset correspondence between the sequence state and the count value of the linear feedback shift register based on the reference sequence state and the corresponding reference count value, it is convenient to quickly determine the actual count value of the linear feedback shift register based on the preset correspondence in the subsequent process of counting the signal of the clock to be tested.

[0039] In some embodiments of the present application, the candidate count values ​​corresponding to the linear feedback shift register may include multiple, each candidate count value and the number of candidate count values ​​can be predetermined, and in the process of determining each candidate count value, the maximum count value and the bit width of the linear feedback shift register can be obtained; based on the maximum count value and the bit width, each candidate count value of the linear feedback shift register is determined.

[0040] In some embodiments, the maximum count value of the linear feedback shift register can be determined by the bit width of the linear feedback shift register. The bit width of the linear feedback shift register can be determined before it leaves the factory, and different linear feedback shift registers have different bit widths.

[0041] In some embodiments, multiple candidate count values ​​may be determined based on the maximum count value and the bit width of the linear feedback shift register. For example, if the bit width of the linear feedback shift register is 20, the corresponding maximum count value is 2. 20 -1=1048575, due to 2 20 =4 10 Therefore, 10 candidate count values ​​can be set in increments of 4, and the candidate count values ​​are 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, and 262144. The bit width of the linear feedback shift register, the increment method of the candidate count value, and the candidate count value are merely exemplary descriptions, and the present application does not limit them.

[0042] It can be understood that, based on the maximum count value and bit width of the linear feedback shift register, the candidate count values ​​of the linear shift register are determined. When it is determined that the count value of the linear feedback shift register reaches the candidate count value, the counting can be stopped and the frequency of the clock signal to be measured can be detected, thereby avoiding determining each count value corresponding to the signal of the clock to be measured, thereby improving the efficiency of frequency detection.

[0043] In some embodiments of the present application, in response to a frequency detection instruction for a signal of a clock to be measured, a linear feedback shift register is controlled to start counting the signal of the clock to be measured, and an accumulator counter is controlled to start counting the signal of a reference clock, that is, after step S101, if the count value of the linear feedback shift register reaches a first value, detection of each candidate count value is started to determine whether the count value corresponding to the linear feedback shift register is the same as any candidate count value.

[0044] It should be noted that the first value is 1 / Q of the maximum count value of the cumulative counter, Q can be preset, and Q is an integer greater than 1, for example, Q can be 1 / 5, 1 / 8, etc. Q can also be determined according to the increment multiple of the candidate count value, Q can be greater than or equal to the increment multiple, for example, if the increment multiple of each candidate count value is 4, then Q can be 5, 6, 7, etc.

[0045] In some embodiments, starting the detection of each candidate count value can be to determine whether the current count value of the linear feedback shift register is the same as the candidate count value, that is, starting from the count value of the accumulator counter reaching the first value, the real-time count value of the linear feedback shift register is compared with each candidate count value.

[0046] In some embodiments, when the accumulator counter is started to count the signal of the reference clock, the actual count value of the accumulator counter can be compared with the size of the first value to determine whether the actual count value of the accumulator counter reaches the first value, and when it is determined that the first value is reached, the detection of the candidate count values ​​of the linear feedback shift register can be started, and the counting can be stopped when it is determined that the real-time count value of the linear feedback shift register is the same as any candidate count value.

[0047] It can be understood that since the first value is 1 / Q of the maximum count value of the accumulator counter of the linear feedback shift register, when the count value of the accumulator counter reaches the first value, the detection of each candidate count value is started, which can ensure that the detection of the candidate count value is completed without exceeding the maximum count value of the accumulator counter and make the count as long as possible.

[0048] In some embodiments of the present application, the frequency of the signal of the clock to be measured is determined based on the first count value and the second count value, that is, step S103 can be implemented by the following steps S1031 to S1033, and each step is described below.

[0049] S1031 . Determine a first conversion coefficient based on the first count value and the maximum count value of the linear feedback shift register.

[0050] In some embodiments, the first count value may be a real count value determined according to a sequence state of a linear feedback shift register. The first count value is less than a maximum count value of the linear feedback shift register. The maximum value of the linear feedback shift register and the first count value may be divided to obtain a first conversion coefficient, that is, the first count value may be divisible by the maximum value of the linear feedback shift register.

[0051] For example, if the bit width of the linear feedback shift register is 22, the maximum count value of the linear feedback shift register is 2 22-1=4194303, if the first count value is 4, the first conversion coefficient is 1048575; if the first count value is 16, the first conversion coefficient is 262144. The maximum value and the first count value of the linear feedback shift register are merely exemplary, and the present application does not limit this.

[0052] S1032: Use the first conversion coefficient to convert the second count value to obtain a third count value.

[0053] In some embodiments, the second count value and the first conversion coefficient may be multiplied to obtain a third count value, and obtaining the third count value may be considered as converting the second count value into a count value equivalent to the maximum count value of the linear feedback shift register.

[0054] S1033: Determine the frequency of the clock signal to be measured based on the third count value and the clock signal frequency threshold.

[0055] It should be noted that the clock signal frequency threshold can be a pre-set clock signal frequency value, which can be a larger frequency value. The clock signal frequency threshold can be used to determine whether the signal of the clock to be tested is abnormal. If it is determined that the signal of the clock to be tested is abnormal, it means that the cryptographic chip where the clock to be tested is located, or the cryptographic chip connected to the clock to be tested may be at risk of being attacked; if it is determined that the signal of the clock to be tested is abnormal, it means that the cryptographic chip where the clock to be tested is located is safe.

[0056] In some embodiments, there is a correlation between the clock signal frequency threshold, the clock signal count threshold, the third count value and the frequency of the signal of the clock to be measured. Therefore, when the third count value, the clock signal frequency threshold and the clock signal count threshold are determined, the frequency of the signal of the clock to be measured can be calculated.

[0057] It can be understood that the first conversion coefficient is determined based on the first count value and the maximum count value of the linear feedback shift register, and the second count value is converted using the first conversion coefficient. Based on the third count value obtained after the conversion and the clock signal frequency threshold, the actual frequency of the signal of the clock to be measured is avoided, thereby improving the convenience of frequency detection.

[0058] In some embodiments of the present application, after the frequency of the signal of the clock to be tested is obtained, if it is determined that the frequency of the signal of the clock to be tested is greater than the clock signal frequency threshold, the operation currently executed by the cryptographic chip corresponding to the clock to be tested is interrupted. The cryptographic chip corresponding to the clock to be tested may be the cryptographic chip where the clock to be tested is located, that is, the clock to be tested is the clock inside the cryptographic chip; the cryptographic chip corresponding to the clock to be tested may also be an external clock connected to the clock to be tested, and the external clock may be used to control the external signal input into the cryptographic chip.

[0059] In some embodiments, the operations currently performed by the cryptographic chip may include encrypting plaintext data, decrypting encrypted data, etc. The frequency of the signal of the clock to be tested is greater than the clock signal frequency threshold, indicating that the current cryptographic chip may be at risk of being attacked. In this case, interrupting the operations currently performed by the cryptographic chip corresponding to the clock to be tested can protect the operations related to the cryptographic chip from abnormalities.

[0060] In other embodiments, when it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, the secret information in the cryptographic chip may be directly cleared. The secret information may include an encryption key, a decryption key, a plain text to be encrypted, an encrypted ciphertext, etc. By clearing the secret information in the cryptographic chip, the secret information in the secret chip can be prevented from being stolen, thereby ensuring the security of the secret information.

[0061] It can be understood that when it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, by interrupting the operation currently performed by the cryptographic chip corresponding to the clock to be measured, or clearing the secret information in the cryptographic chip, the information in the cryptographic chip will not be leaked or tampered with, thereby achieving the purpose of protecting the information in the cryptographic chip.

[0062] In some embodiments of the present application, after obtaining the third count value through step S1032, a first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured can be determined based on the third count value and the clock signal count threshold; if the first ratio is less than or equal to the preset threshold, the operation currently being performed by the cryptographic chip corresponding to the clock to be measured is interrupted, or the secret information in the cryptographic chip is cleared.

[0063] In some embodiments, the preset threshold can be any pre-set positive integer, for example, the preset threshold can be 1, 2, etc. If it is determined that the first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured is less than or equal to the preset threshold, it means that the frequency of the signal of the clock to be measured is close to the clock signal frequency threshold, or the frequency of the signal of the clock to be measured exceeds the clock signal frequency threshold, which means that the frequency of the signal of the clock to be measured is abnormal, and the cryptographic chip corresponding to the clock to be measured may be at risk of being attacked. Therefore, protection measures need to be taken for the cryptographic chip.

[0064] In some embodiments, the clock signal count threshold can be any predetermined count value, and the ratio of the third count value to the clock signal count threshold is equal to the ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured. Therefore, there is no need to determine the actual frequency of the signal of the clock to be measured, and the ratio of the third count value to the clock signal count threshold can be directly determined as the first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured.

[0065] It can be understood that by determining the first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured through the third count value and the clock signal count threshold, the step of calculating the actual frequency of the signal of the clock to be measured is avoided, and the abnormality detection efficiency of the cryptographic chip is improved; the first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured is compared with the preset threshold, and when it is determined that the first ratio is less than or equal to the preset threshold, the operation currently executed by the cryptographic chip corresponding to the clock to be measured is interrupted or the secret information in the cryptographic chip is cleared, so as to protect the information in the cryptographic chip.

[0066] Next, the implementation process of the application embodiment in the actual application scenario is introduced.

[0067] The present application provides a frequency detection method based on linear feedback shift register counting, such as Figure 2 As shown, the method includes: S201: Start counting the reference clock and the clock to be measured.

[0068] In some embodiments, an accumulative counter can be used to count the period of the signal of the reference clock, and a linear feedback shift register can be used to count the period of the signal of the clock to be measured. The signals generated by the reference clock and the clock to be measured can both be periodic signals, and the reference clock and the clock to be measured can be controlled to be counted simultaneously.

[0069] S202 : Determine whether the count value of the reference clock reaches a preset ratio (equivalent to “1 / Q” in other embodiments) of the maximum count value of the accumulator counter.

[0070] If yes, then the following steps S203 to S206 are executed; otherwise, the process returns to step S201 and continues to execute. The preset ratio may be 1 / 4, 1 / 5, etc.

[0071] S203, start searching for a micro-scale value (equivalent to a “candidate count value” in other embodiments).

[0072] In some embodiments, the micro-scale value may be a real count value corresponding to the sequence state of the linear feedback shift register counter. Taking N=22 as an example, the frequency detection process of the linear feedback shift register is introduced. The linear feedback shift register with N=22 (N may also be other values, such as 23, 222, etc.) can represent 2 N -1 sequence state, and in cycle 2 N -1 and then repeat the sequence state, so its counting cycle is 2 N-1 = 4194303. This allows the measurement of clock frequencies that are 4 million times higher than the reference clock, i.e., a 1 GHz clock can be measured using a 1 kHz frequency. This also allows the construction of other linear feedback shift register counters that detect high-speed frequencies. The linear feedback shift register is a random sequence, but the designer can know the sequence state of a specific cycle and set a 4-fold increment (essentially 2 n The linear feedback shift register count is divided into multiples of the period. Here, the counts are recorded as 1, 4, 16, 64, 256, 1024, 4096, 16384, 65536, 262144, 1048576, and the timing cycle is divided into 11 microscales from 1 to 11. The microscale 11 is obtained, 2 22 =4 11 , where N=22, n=2; the microscale 22 is obtained as, 2 22 =2 22 , where N=22 and n=1.

[0073] For example, in order to improve the detection accuracy, it is necessary to ensure a sufficiently long detection time, and at the same time, it is also necessary to ensure that the microscale can be detected. Therefore, a value is first selected within 1 / 4 of the maximum count value of the cumulative counter, such as 1 / 5. When the count value of the cumulative counter reaches 1 / 5 of the maximum count value, the microscale detection begins. At this time, the time to detect the microscale must be less than or equal to 4 / 5 of the maximum count value. In this way, the detection can be completed before the count value of the cumulative counter overflows.

[0074] S204: If the count value of the linear feedback shift register reaches the microscale value, stop counting, and record the microscale value and the count value of the cumulative counter.

[0075] In some embodiments, the sequence state of the linear feedback shift register and the true count value There is a mapping relationship between them, namely Therefore, by obtaining the sequence state of the linear feedback shift register, the count value of the linear feedback shift register can be determined according to the mapping relationship. Afterwards, if it is determined that the count value of the linear feedback shift register reaches any microscale value, the counting of the clock to be measured and the reference clock can be stopped, and the microscale value obtained when the counting is stopped and the count value of the cumulative counter are recorded.

[0076] S205. Shift the count value of the cumulative counter according to the micro-scale value (equivalent to “converting the second count value” in other embodiments) to obtain the shifted count value (equivalent to “the third count value” in other embodiments).

[0077] In some embodiments, the number of bits used to shift the count value of the accumulator counter can be determined by the microscale value and the bit width of the linear feedback shift register. If the bit width of the linear feedback shift register is 22 and the microscale value is 1048576, the binary number corresponding to the count value of the accumulator counter can be shifted left by 2 bits (i.e., multiplied by 4) to obtain the shifted count value.

[0078] S206 , determining the frequency of the clock to be measured according to the shifted count value, the frequency threshold and the count threshold.

[0079] In some embodiments, the clock frequency to be measured can be calculated by using the count value (micro-scale value) corresponding to the current sequence state of the linear feedback shift register count value and the count value of the reference clock during this period of time ( ).

[0080] However, in security protection, it is often not necessary to calculate the actual frequency of the clock. Once a specific frequency threshold is reached, it can be identified as a frequency anomaly. At this time, the linear feedback shift register high-speed frequency meter can be further simplified. It can be simply calculated that when the linear feedback shift register count reaches 1048576 sequence, the count corresponding time multiplied by 4 is the count period 4194304; when the count reaches 65536 sequence, the count corresponding time multiplied by 4*4*4 is the count period 4194304. Therefore, The mapping relationship is directly superimposed on At this time, the only variables tested are , can be directly compared with a specific threshold to determine whether the frequency is abnormal. When the linear feedback shift register is in the 1048576 sequence, The count value is shifted left by 2 bits, that is, multiplied by 4, to align with the linear feedback shift register count cycle of 4194304. When the linear feedback shift register is in the 262144 sequence, The count value is shifted left by 4 bits, that is, multiplied by 16, to align with the linear feedback shift register count cycle of 4194304. By analogy, the sequence mapping of the linear feedback shift register can be converted to `, normalized to the reference frequency counting state when the linear feedback shift register executes 4194304 cycles, completing the frequency comparison.

[0081] In some embodiments, the specified frequency and the mapping threshold satisfy the relationship shown in the following formula (2): (2); in, , Represent the frequency threshold and the frequency of the reference clock respectively, , They respectively represent the maximum count value and count threshold of the linear feedback shift register.

[0082] further, The threshold value and the value to be measured are the same, so the above formula (2) is expressed by formula (3): (3); in, , is a positive integer. Combining formula (3) and formula (1), we can get formula (4): (4); Therefore, through ( `) with The ratio of the frequency threshold to the frequency of the clock to be measured can be determined by the ratio, and then the frequency of the clock to be measured can be determined based on the ratio and the frequency threshold. .in, It can be understood as the count value obtained by shifting the count value of the cumulative counter.

[0083] S207: Compare the frequency of the clock to be measured with a frequency threshold to determine whether the frequency of the clock to be measured is abnormal.

[0084] After calculating the frequency of the clock to be measured, it can be determined whether the frequency of the clock to be measured is greater than or equal to the frequency threshold. If the frequency of the clock to be measured is greater than or equal to the frequency threshold, it can be determined that the frequency of the clock to be measured is abnormal, and the cryptographic chip corresponding to the frequency of the clock to be measured may be at risk of being attacked; otherwise, it can be determined that the frequency of the clock to be measured is normal, and the cryptographic chip corresponding to the frequency of the clock to be measured is safe.

[0085] It is understandable that the use of linear feedback shift registers for counting is not only better in terms of area resources, but also better in timing than traditional counters in counting the clock to be measured, and can detect higher frequencies; by setting linear feedback shift register counters with different bit widths, wide-range and high-precision measurements can be achieved. At the same time, as part of the frequency detection, the results can be simply compared through shift normalization to determine whether the frequency is abnormal; compared to the detector that needs to fully calculate the actual frequency, it saves computing area, and only uses shift logic to complete the unification and comparison of the frequency and frequency threshold of the signal of the clock to be measured.

[0086] The frequency detection method based on linear feedback shift register counting provided in the present application uses linear feedback shift register counting instead of traditional counting methods, and can test higher frequency clock frequencies. At the same time, it adopts multi-cycle measurement and threshold selection methods to pursue the accuracy and controllability of clock frequency detection, and can achieve high-precision, wide-range, and controllable frequency measurement.

[0087] The present application provides a frequency detection system based on linear feedback shift register counting, such as Figure 3 As shown, the frequency detection system 300 based on linear feedback shift register counting includes an accumulation counter 301, a linear feedback shift register counter 302, a synchronization and enabling module 303, a micro-scale detection module 304, a shift module 305, a frequency comparison module 306 and an alarm module 307. The accumulation counter 301 includes an addition logic submodule 3011 and a first register 3012, and the linear feedback shift register counter 302 includes an exclusive OR logic submodule 3021 and a second register 3022.

[0088] The accumulator counter 301 and the linear feedback shift register counter 302 control the timing range through the synchronization and enable module 303 to ensure that the timer starts, collects and ends at the same time. The microscale detection module 304 starts under the set rule (such as the count value of the accumulator counter 301 reaches 1 / 4 of the maximum count value) to detect the linear feedback shift register counter 302. After detecting the microscale, the counting is stopped; the shift module 305 shifts the count value of the accumulator counter 301 that has ended based on the microscale, maps it to the value at the maximum linear feedback shift register, and determines the frequency of the clock to be tested based on the shifted count value; the frequency comparison module 306 compares the frequency of the clock to be tested with the frequency threshold to determine whether it is abnormal; the alarm module 307 can issue a warning message when it determines that the frequency of the clock to be tested is abnormal, so as to remind the user that the password chip corresponding to the clock to be tested may be at risk of being attacked.

[0089] In some embodiments, the frequency detection system 300 based on linear feedback shift register counting provided by the present application can detect the frequency of the signal of the clock to be tested inside the cryptographic chip. In addition, in the cryptographic chip entity, there is a risk of obtaining cryptographic information through physical attacks, including physical attacks using high-frequency clocks, such as Figure 4 As shown, the frequency detection system 300 based on linear feedback shift register counting can detect the frequency of the signal of the clock to be measured 402 outside the cryptographic chip 401. When the frequency detection system 300 based on linear feedback shift register counting determines that the signal of the clock to be measured 402 is abnormal, the frequency detection system 300 based on linear feedback shift register counting can also reset the cryptographic chip 401.

[0090] The frequency detection system based on linear feedback shift register counting provided in the present application can detect the frequency of the signal of the current clock to be measured. When a high-frequency clock is detected, the secret information in the cryptographic chip can be cleared to achieve the purpose of information protection.

[0091] The present application also provides a chip, Figure 5 A schematic diagram of the composition structure of a chip provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the chip 500 includes a control unit 501 and a processing unit 502, wherein: The control unit 501 is used to control the linear feedback shift register to start counting the signal of the clock to be measured, and control the accumulative counter to start counting the signal of the reference clock in response to the frequency detection instruction for the signal of the clock to be measured; wherein the bit width of the linear feedback shift register is greater than the counter bit width threshold, and the circuit complexity of the linear feedback shift register is less than the circuit complexity threshold; The control unit 501 is further configured to control the linear feedback shift register and the accumulator counter to stop counting if it is determined that the counting end condition is met, and obtain a first count value of the linear feedback shift register and a second count value of the accumulator counter; The processing unit 502 is configured to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

[0092] In some embodiments, the processing unit 502 is also used to determine a first conversion coefficient based on the first count value and the maximum count value of the linear feedback shift register; use the first conversion coefficient to convert the second count value to obtain a third count value; and determine the frequency of the signal of the clock to be measured based on the third count value and the clock signal frequency threshold.

[0093] In some embodiments, the control unit 501 is further used to interrupt the operation currently being performed by the cryptographic chip corresponding to the clock to be tested, or clear the secret information in the cryptographic chip if it is determined that the frequency of the signal of the clock to be tested is greater than the clock signal frequency threshold.

[0094] In some embodiments, the processing unit 502 is also used to determine a first ratio of the clock signal frequency threshold and the frequency of the signal of the clock to be measured based on the third count value and the clock signal count threshold; the control unit 501 is also used to interrupt the operation currently being performed by the cryptographic chip corresponding to the clock to be measured, or clear the secret information in the cryptographic chip if the first ratio is less than or equal to a preset threshold.

[0095] In some embodiments, the linear feedback shift register includes a linear feedback shift register; the processing unit 502 is further used to obtain a first sequence state of the linear feedback shift register; based on a preset correspondence between the sequence state and the count value of the linear feedback shift register, determine the count value corresponding to the first sequence state; if the count value corresponding to the first sequence state is a candidate count value, determine that the counting end condition is met; the candidate count value is 2N, N is a non-negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register.

[0096] In some embodiments, the processing unit 502 is further used to test the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and a reference count value corresponding to the reference sequence state; the number of the reference sequence states is determined by the bit width of the linear feedback shift register; and based on the each reference sequence state and the corresponding reference count value, a preset corresponding relationship between the sequence state and the count value of the linear feedback shift register is created.

[0097] In some embodiments, the candidate count values ​​include multiple ones; the processing unit 502 is further used to obtain the maximum count value and the bit width of the linear feedback shift register; and determine each candidate count value of the linear feedback shift register based on the maximum count value and the bit width.

[0098] In some embodiments, the control unit 501 is also used to start detecting each candidate count value if the count value of the accumulator counter reaches a first value to determine whether the count value corresponding to the linear feedback shift register is the same as any candidate count value; wherein the first value is 1 / Q of the maximum count value of the accumulator counter, and Q is an integer greater than 1.

[0099] It should be noted that the description of the chip in the embodiment of the present application is similar to the description of the clock signal frequency determination method embodiment described above, and has similar beneficial effects as the method embodiment, so it is not repeated. For technical details not disclosed in the embodiment of the device, please refer to the description of the method embodiment of the present application for understanding.

[0100] It should be noted that, in this article, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises at least one ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0101] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0102] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware.

[0103] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technical object familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A method for determining the frequency of a clock signal, characterized in that: include: In response to a frequency detection instruction for a signal of a clock to be measured, controlling a linear feedback shift register to start counting the signal of the clock to be measured, and controlling an accumulative counter to start counting the signal of a reference clock; If it is determined that the counting end condition is met, controlling the linear feedback shift register and the accumulative counter to stop counting, and obtaining a first count value of the linear feedback shift register and a second count value of the accumulative counter; The frequency of the signal of the clock to be measured is determined based on the first count value and the second count value.

2. The method according to claim 1, characterized in that The determining the frequency of the signal of the clock to be measured based on the first count value and the second count value includes: determining a first conversion coefficient based on the first count value and a maximum count value of the linear feedback shift register; Using the first conversion coefficient, converting the second count value to obtain a third count value; The frequency of the clock signal to be measured is determined based on the third count value and the clock signal frequency threshold.

3. The method according to claim 2, characterized in that The method further comprises: If it is determined that the frequency of the signal of the clock to be measured is greater than the clock signal frequency threshold, the operation currently being performed by the cryptographic chip corresponding to the clock to be measured is interrupted, or the secret information in the cryptographic chip is cleared.

4. The method according to claim 2, characterized in that: The method further comprises: Determine a first ratio of the clock signal frequency threshold to the frequency of the signal of the clock to be measured based on the third count value and the clock signal count threshold; If the first ratio is less than or equal to a preset threshold, the operation currently being performed by the cryptographic chip corresponding to the clock to be tested is interrupted, or the secret information in the cryptographic chip is cleared.

5. The method according to any one of claims 1 to 4, characterized in that: The determining that the counting end condition is satisfied includes: Acquiring a first sequence state of the linear feedback shift register; Determining the count value corresponding to the first sequence state based on a preset correspondence relationship between the sequence state and the count value of the linear feedback shift register; If the count value corresponding to the first sequence state is a candidate count value, it is determined that the counting end condition is met; the candidate count value is 2 N , N is a non-negative integer, and the candidate count value is less than the total number of sequence states of the linear feedback shift register.

6. The method according to claim 5, characterized in that The method further comprises: Testing the linear feedback shift register to obtain each reference sequence state of the linear feedback shift register and a reference count value corresponding to the reference sequence state; the number of the reference sequence states is determined by the bit width of the linear feedback shift register; Based on the respective reference sequence states and the corresponding reference count values, a preset corresponding relationship between the sequence state and the count value of the linear feedback shift register is created.

7. The method according to claim 5, characterized in that The candidate count value includes a plurality of candidate count values; and the method further includes: Obtaining a maximum count value and a bit width of the linear feedback shift register; Based on the maximum count value and the bit width, candidate count values ​​of the linear feedback shift register are determined.

8. The method according to claim 7, characterized in that The method further comprises: If the count value of the accumulator counter reaches a first value, the detection of each candidate count value is started to determine whether the count value corresponding to the linear feedback shift register is the same as any candidate count value; wherein the first value is 1 / Q of the maximum count value of the accumulator counter, and Q is an integer greater than 1.

9. A chip, characterized in that: include: A control unit and a processing unit, wherein The control unit is used to control the linear feedback shift register to start counting the signal of the clock to be measured, and control the accumulative counter to start counting the signal of the reference clock in response to a frequency detection instruction for the signal of the clock to be measured corresponding to the chip; The control unit is further configured to control the linear feedback shift register and the accumulative counter to stop counting if it is determined that the counting end condition is met, and obtain a first count value of the linear feedback shift register and a second count value of the accumulative counter; The processing unit is used to determine the frequency of the signal of the clock to be measured based on the first count value and the second count value.

10. The chip according to claim 9, characterized in that: The processing unit is also used to determine a first conversion coefficient based on the first count value and the maximum count value of the linear feedback shift register; use the first conversion coefficient to convert the second count value to obtain a third count value; and determine the frequency of the signal of the clock to be measured based on the third count value and the clock signal frequency threshold.

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