New energy commercial vehicle domain controller power failure data storage method and system

Abstract

The invention relates to a power failure data storage system and method for a new energy commercial vehicle domain controller, and the system comprises a storage battery, an N-channel MOS tube Q1 connected with the storage battery, a single-chip microcomputer and a drive circuit, the N-channel MOS tube Q1 is communicated with the single-chip microcomputer through a power circuit, and the single-chip microcomputer controls the output end of the drive circuit to be communicated with the grid electrode of the N-channel MOS tube; reverse connection prevention protection is achieved, an ON-gear signal passes through a resistor R1 and then is connected with an NPN triode Q2 and a resistor R2, and the NPN triode Q2 is communicated with a power supply circuit through a current-limiting resistor R3; the PNP triode Q3 is communicated with a power supply circuit, the PNP triode Q3 is communicated with the NPN triode Q2 through a resistor R4, the PNP triode Q3 is connected with a resistor R5 and a resistor R6 which are connected in series, the resistor R6 is connected with a grounding end, a voltage acquisition IO1 port of the single-chip microcomputer is connected with the resistor R5, the power supply voltage acquired by the IO port of the single-chip microcomputer is referred, and the hysteresis effect can reduce the sensitivity of the system in combination with the mode of a hysteresis comparator. The anti-interference capability is improved, and the signal stability is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of new energy commercial vehicles, and in particular to a method and system for preserving power-off data of a domain controller of a new energy commercial vehicle. Background Art

[0002] With the development of new energy automotive electronic products, the demand for various signal data is increasing. Therefore, the amount of data transmitted between the various electronic control units of the car is increasing, which leads to the whole vehicle system taking longer to save data when the power is off. It is very important for the domain controller to ensure the complete storage of data in any abnormal power-off situation. In the existing public power-off delay circuit, the input voltage is collected by the voltage divider unit, and then converted into a digital switch signal by the switch tube and transmitted to the single-chip microcomputer for judgment. This method has the following shortcomings: 1. After the low-voltage power supply is powered on, if the power supply sampling is always performed to determine whether the system is powered off, on the one hand, after the system is powered off, the energy stored in the back-end capacitor is released through the loop formed by the sampling resistor network, affecting the system's data storage time. On the other hand, the system in new energy vehicles has strict requirements on power consumption. Since the loop of the sampling resistor network always exists, it may not be able to meet the system requirements; 2. The digital quantity fed back by the IO port of the microcontroller is used as the basis for judging the power supply, which has relatively low reliability; 3. The anti-reverse connection MOS tube uses a P-channel MOS tube, which is relatively more expensive. The gate of the MOS tube is uncontrollable and it is continuously turned on. When the energy of the subsequent stage is greater than that of the previous stage, the energy stored in the capacitor is released to the previous stage power supply through the anti-reverse connection MOS tube, thereby shortening the discharge time of the subsequent capacitor; 4. A single-limit comparator circuit is used as a solution for power-off level judgment. It has high sensitivity but poor anti-interference ability. If the input signal has a slight jitter near the threshold voltage value, it will cause frequent jumps in the output level. Summary of the invention

[0003] In view of the above problems, the present invention provides a method and system for preserving power-off data of a domain controller of a new energy commercial vehicle, which realizes anti-reverse connection protection through an N-channel MOS tube, refers to the power supply voltage collected by the IO port of a single-chip computer, and combines a hysteresis comparator. The hysteresis effect can reduce the system sensitivity, increase the anti-interference ability, and ensure the stability of the signal.

[0004] The present application is implemented through the following technical solutions, a power-off data preservation system for a domain controller of a new energy commercial vehicle, comprising: A battery, an N-channel MOS tube Q1 connected to the battery, a single-chip microcomputer and a driving circuit, wherein the N-channel MOS tube Q1 is connected to the single-chip microcomputer through a power supply circuit, and the output end of the single-chip microcomputer controls the driving circuit to be connected to the gate of the N-channel MOS tube; It also includes an NPN transistor Q2, a PNP transistor Q3 and a comparator U1, the ON gear signal is respectively connected to the base B and the emitter E of the NPN transistor Q2 through the resistor R1, and the resistor R2 is connected in parallel between them, the collector C of the NPN transistor Q2 is connected to the power supply circuit through the current limiting resistor R3, and the emitter E of the NPN transistor Q2 and the resistor R2 are grounded; The emitter E of the PNP transistor Q3 is connected to the power supply circuit, the base B of the PNP transistor Q3 is connected to the collector C of the NPN transistor Q2 through the resistor R4, the collector C of the PNP transistor Q3 is connected to the resistor R5 and the resistor R6 connected in series, the resistor R6 is connected to the ground terminal, and the voltage collection IO1 port of the single chip is connected to the resistor R5; The same-direction input terminal of the comparator U1 is connected to the resistor R5, the reverse input terminal and the current-limiting resistor R8 are connected to the power-off reference voltage Vref terminal, and the output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer.

[0005] Preferably, a resistor R7 is provided between the positive power supply terminal of the comparator U1 and the resistor R5.

[0006] Preferably, the device further comprises a capacitor C1 , one end of which is connected to the power supply circuit, and the other end of which is grounded.

[0007] A data storage method, comprising: When the ON gear signal is at a high level, the NPN transistor Q2 is turned on and the PNP transistor Q3 is turned on. At this time, the input voltage of the battery is divided by the series resistors R5 and R6. The voltage value after the voltage division by the resistor R6 is collected through the voltage collection IO1 port of the single-chip microcomputer. At the same time, the voltage after the voltage division is compared with the power-off reference voltage Vref value after passing through the comparator U1. When the voltage value after the voltage division is greater than the power-off reference voltage Vref value, the comparator U1 outputs a high-level signal to the single-chip microcomputer I02 port; when the voltage value after the voltage division is less than the power-off reference voltage Vref value, the comparator U1 outputs a low-level signal to the single-chip microcomputer I02 port, and the single-chip microcomputer uses the values ​​collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state; When the ON gear signal is at a low level, both the NPN transistor Q2 and the PNP transistor Q3 are not connected, the voltage value of the resistor R6 is collected at the I01 port of the microcontroller, and the comparator U1 outputs a low-level signal to the I02 port of the microcontroller. The microcontroller uses the values ​​collected at the IO1 port and the I02 port as the initial conditions for judging the power supply status.

[0008] Prioritize, after the voltage value collected by the IO1 port of the single-chip computer is converted by AD, it is determined whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally and the MOS tube Q1 is turned on normally. When it is less than 8.5V, the gate of the MOS tube Q1 is turned off to determine whether the system is in sleep mode and powered off. If it is determined to be in sleep mode and powered off, the power-off data is saved.

[0009] Prioritize the voltage value output by the comparator U1 collected by the I02 port of the single-chip computer. When the value collected by the I02 port is greater than or equal to 9.5V, the drive circuit outputs normally and the MOS tube Q1 is turned on normally. When the value collected by the I02 port is less than 9.5V, continue to judge whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally and the MOS tube Q1 is turned on normally. When it is less than 8.5V, the gate of the MOS tube Q1 is closed to make an initial judgment on whether the system is in sleep mode.

[0010] Preferably, the reference voltage Vref value is 9V.

[0011] Preferably, the uplink voltage threshold and the downlink voltage threshold of the comparator U1 are 8.5V and 9.5V respectively.

[0012] The beneficial effects of this application are: 1. By monitoring the power supply status of the system, the on and off status of the anti-reverse connection N-channel MOS tube is controlled to control the discharge circuit of the subsequent capacitor and improve the data retention time when the system is powered off; 2. System power status judgment, refer to the power supply voltage collected by the MCU IO port, and combine it with the hysteresis comparator. The hysteresis effect can reduce the system sensitivity, increase the anti-interference ability, and ensure the stability of the signal; 3. Through the ON gear signal, the system power supply voltage is sampled. When the system is in sleep mode, the sampling circuit is in an open circuit state, which will not generate energy loss and effectively reduce the system standby power consumption; 4. It can reduce standby power consumption and effectively increase the data storage time after the system is powered off. The dual acquisition method of analog and digital quantities, combined with the good anti-interference ability of the hysteresis comparator, can improve the reliability of the system's power-off judgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 This is a schematic diagram of a power-off data storage system for a domain controller of a new energy commercial vehicle in an embodiment of the present invention; Figure 2 It is a schematic diagram of a power-off data preservation method in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0016] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, systems, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0017] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0018] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0019] like Figure 1 A power-off data storage system for a domain controller of a new energy commercial vehicle is shown, comprising: A battery, an N-channel MOS transistor Q1 connected to the battery, a single-chip microcomputer and a driving circuit, wherein the N-channel MOS transistor Q1 is connected to the single-chip microcomputer through a power circuit, and the output end of the single-chip microcomputer controls the driving circuit to be connected to the gate of the N-channel MOS transistor; During implementation, the vehicle battery and the domain controller are connected by a wiring harness. The output voltage of the battery under normal working conditions is 24V. The power supply voltage output by the battery is connected to the board-side connector of the domain controller circuit board by the wiring harness, and then connected to the MOS tube Q1 inside the circuit board by the connector. Q1 is an N-channel MOS tube, which is used for reverse connection protection. When the front end of Q1 is connected to the positive pole of the power supply, the internal body diode of the MOS tube Q1 is turned on. The output voltage of the battery not only charges the energy storage capacitor C1 of the domain controller, but also is converted into the voltage required for the operation of each part of the circuit of the subsequent stage through the power supply circuit inside the domain controller, and supplies the single-chip microcomputer and other related circuits. The single-chip microcomputer controls the output of the drive circuit and outputs it to the gate of the MOS tube Q1. At this time, Q1 can be turned on normally, reducing the energy loss generated on Q1 when the power supply is working normally; when the front end of Q1 is connected to the negative pole of the power supply, the MOS tube Q1 is in the cut-off state, and a closed loop cannot be formed between the input and output, and the system cannot work normally, realizing the system's power input reverse connection protection; In this embodiment, the drive circuit is controlled by a single chip microcomputer to complete the control of the NMOS gate signal. The MOS tube gate drive can be turned off when the power is off. At this time, the MOS tube is unidirectionally conductive, and energy can only flow from the front stage to the back stage, which can prevent the energy of the back stage from being released.

[0020] It also includes an NPN transistor Q2, a PNP transistor Q3 and a comparator U1. The ON-speed signal passes through the resistor R1 and is respectively connected to the base B of the NPN transistor Q2 and the resistor R2 which are connected in parallel. The emitter E of the NPN transistor Q2 is connected to the power supply circuit through the current limiting resistor R3, and the collector C of the NPN transistor Q2 and the resistor R2 are grounded. When the system is working normally, the ON-speed signal is a high-level signal, which is divided by the resistors R1 and R2, and the voltage generated on the resistor R2 decreases. At this time, the voltage at the base B end of the NPN transistor Q2 is greater than the voltage at the emitter E of the NPN transistor Q2. At this time, the NPN transistor Q2 is turned on, and the current limiting resistor R3 limits the current, and the collector C of the NPN transistor Q2 is grounded.

[0021] Since the emitter E of the PNP transistor Q3 is connected to the power supply circuit, the base B of the PNP transistor Q3 is connected to the emitter E of the NPN transistor Q2 through the resistor R4, the collector C of the PNP transistor Q3 is connected to the resistors R5 and R6 connected in series, the resistor R6 is connected to the ground terminal, and the voltage collection IO1 port of the single-chip computer is connected to the resistor R5; therefore, when the NPN transistor Q2 is turned on, the left end of the resistor R4 is in a low level state, the NPN transistor Q2 is turned on, and the battery input voltage is divided by the resistors R5 and R6 after passing through the NPN transistor Q2, and the voltage value generated after the voltage division by the resistor R6 is input to the voltage collection I01 port of the single-chip computer, and the analog data of the input power supply voltage is collected.

[0022] The positive power supply terminal of the comparator U1 is connected to the resistor R5, the negative power supply terminal and the current limiting resistor R8 are connected to the power-off reference voltage Vref terminal, and the output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer. Since the resistor R7 is provided between the resistor R5 and the positive power supply terminal of the comparator U1, the voltage value generated after the voltage division of the resistor R6 is not only transmitted to the single-chip microcomputer, but also given to the resistor R7. The other end of the resistor R7 is connected to the non-inverting input terminal of the comparator U1, and the reverse input terminal is connected to the power-off reference voltage Vref terminal through the current limiting resistor R8. If the voltage value generated on R6 is greater than the reference value of the reference voltage Vref terminal, the comparator U1 outputs a high level to the IO2 port of the single-chip microcomputer, and the value collected by the 102 port of the single-chip microcomputer is used as the reference value for finally judging the power supply status of the system; if the voltage value generated on R6 is less than the reference value of the reference voltage Vref terminal, the comparator U1 outputs a low level to the IO2 port of the single-chip microcomputer, and the single-chip microcomputer refers to the value collected by the IO1 port to finally judge the reference value of the power supply status of the system.

[0023] When the ON gear signal input from the outside does not exist, the ON gear signal is at a low level. The signal is divided by resistors R1 and R2, and the voltage value after the voltage division is still at a low level. At this time, the NPN transistor Q2 cannot be turned on normally and is in a cut-off state. The left end of the resistor R4 is connected to the power supply through the current limiting resistor R3, which is in a high level state. The PNP transistor Q3 cannot be turned on normally, so it is in a cut-off state. At this time, the resistors R5 and R6 are connected in series to the negative power supply, and a complete loop cannot be formed. The voltage value at both ends of the resistor R6 is close to 0V, which is transmitted to the IO1 port of the single-chip microcomputer to collect and process the analog data of the input power supply voltage; the non-inverting input end of the hysteresis comparator U1 is also close to the 0V power supply state, then the voltage value generated on R6 is less than the reference voltage Vref, and the hysteresis comparator U1 outputs a low level to the IO2 port of the single-chip microcomputer. The single-chip microcomputer refers to the value collected by the IO1 port as the reference value for the final judgment of the system power supply state. If it is determined to be in a dormant power-off state, the output of the driving circuit is turned off, so that the MOS tube Q1 is turned off to prevent the energy of the energy storage capacitor C1 at the rear end of the anti-reverse connection MOS tube from being consumed by the front-stage power supply.

[0024] In one embodiment, Figure 2 The figure shows a method for preserving power-off data of a domain controller of a new energy commercial vehicle. Under normal working conditions, the voltage range is 9-32V. First, the value of the power-off power reference voltage Vref is set to 9V through hardware, and the upper and lower voltage thresholds of the hysteresis comparator U1 are set to 8.5V and 9.5V respectively through resistors R7 and R9.

[0025] When the system is powered on, it is necessary to make a preliminary judgment on whether power-off data needs to be saved. At this time, due to normal operation, when the ON gear signal is at a high level, the NPN transistor Q2 is turned on and the PNP transistor Q3 is turned on. At this time, the input voltage of the battery is divided by the series resistors R5 and R6. The voltage value after the voltage division by the resistor R6 is collected through the voltage collection IO1 port of the single-chip computer. Before comparison, the data collected by the I01 port of the single-chip computer is AD converted. When the voltage value after the voltage division is greater than the power-off reference voltage Vref value, that is, greater than 8.5V, the drive circuit is normally input, and the MOS tube Q1 can be normally turned on. Otherwise, the MOS tube gate drive is turned off; At the same time, the divided voltage is compared with the power-off reference voltage Vref value after passing through the comparator U1. Before the comparison, the comparator U1 outputs a high-level signal to the I02 port of the single-chip computer. When the comparison is made, if it is greater than or equal to 9.5V, the power supply is in a normal state, the drive circuit outputs normally, and the MOS tube Q1 can be turned on normally. When it is less than 9.5V, it continues to determine whether it is greater than 8.5V. If it is greater than or equal to 8.5V, the drive circuit outputs normally, and the MOS tube Q1 can be turned on normally. If it is less than 8.5V, the gate drive of the MOS tube is turned off. When the ON gear signal is at a low level, the signal is divided by resistors R1 and R2, and the voltage value after division is still in a low level state. At this time, the NPN transistor Q2 cannot be turned on normally and is in a cut-off state. At this time, the left end of the resistor R4 is connected to the power supply through the current limiting resistor R3, which is in a high level state. The PNP transistor Q3 cannot be turned on normally and is in a cut-off state. At this time, the resistors R5 and R6 are connected in series to the negative power supply, and a complete loop cannot be formed. The voltage value across the resistor R6 is close to 0V, which is transmitted to the IO1 port of the microcontroller to collect and process the analog data of the input power supply voltage; the non-inverting input end of the hysteresis comparator U1 is also in a power supply state close to 0V, so the voltage value generated on R6 is less than the reference voltage Vref, and the hysteresis comparator U1 outputs a low level to the IO2 port of the microcontroller. Since the values ​​received by the I01 and I02 ports of the microcontroller are both less than 8.5N, it is judged to be a dormant power-off state, and the output of the drive circuit is turned off, so that the MOS tube Q1 is turned off to prevent the energy of the energy storage capacitor C1 at the rear end of the anti-reverse connection MOS tube from being consumed by the previous power supply.

[0026] In this embodiment, the single-chip microcomputer uses the values ​​collected from the IO1 port and the I02 port as the initial conditions for determining the power state. If the power state is determined to be sleep and power-off, the power-off data is saved. Otherwise, the input power sampling is continued in a cycle. In the sleep and power-off state, since the MOS tube is turned on through the body diode, when the voltage of the subsequent stage is greater than that of the previous stage, the energy stored in the subsequent stage capacitor can only be consumed in the subsequent stage, which can improve the time for the system to save power-off data.

[0027] In this embodiment, the sampling circuit is controlled by the ON gear signal. When the ON gear signal exists, the input power supply voltage can be sampled and fed back to the IO port corresponding to the single-chip microcomputer to complete the data conversion and realize the real-time sampling and calculation of the input voltage signal; When the ON signal exists, the input power supply voltage signal is collected and compared with the comparator reference voltage signal by means of resistor voltage division. When the input signal exceeds the reference signal, the comparator output signal is high level, and the power supply is normal; when the input signal is lower than the reference signal, the comparator output signal is low level, and the system then makes other related logic judgments to determine whether the system goes into sleep mode or not. When the input signal is close to the reference signal, the output signal has a hysteresis effect, that is, the output signal will not change immediately, and it will flip only when the input signal exceeds or falls below a certain threshold, thereby ensuring the stability of the output power-off signal.

[0028] When the signal fed back to the single-chip microcomputer is that the system power is off, the single-chip microcomputer controls the gate drive signal of the anti-reverse MOS tube by controlling the output of the drive circuit, so that the MOS tube changes from the on state to the off state, thereby preventing the energy of the rear-stage capacitor from being consumed in the previous stage through the loop formed by the MOS tube when the voltage of the rear stage is greater than that of the front stage; when the signal fed back to the single-chip microcomputer is that the system power state is normal, the single-chip microcomputer controls the gate drive signal of the anti-reverse MOS tube by controlling the output of the drive circuit, so that the MOS tube works in the saturated on state, which can reduce the energy consumption of the power supply in the MOS tube loop.

[0029] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application.

[0030] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A power-off data storage system for a domain controller of a new energy commercial vehicle, characterized in that: include: A battery, an N-channel MOS tube Q1 connected to the battery, a single-chip microcomputer and a driving circuit, wherein the N-channel MOS tube Q1 is connected to the single-chip microcomputer through a power supply circuit, and the output end of the single-chip microcomputer controls the driving circuit to be connected to the gate of the N-channel MOS tube; It also includes an NPN transistor Q2, a PNP transistor Q3 and a comparator U1, the ON gear signal is respectively connected to the base B and the emitter E of the NPN transistor Q2 through the resistor R1, and the resistor R2 is connected in parallel between them, the collector C of the NPN transistor Q2 is connected to the power supply circuit through the current limiting resistor R3, and the emitter E of the NPN transistor Q2 and the resistor R2 are grounded; The emitter E of the PNP transistor Q3 is connected to the power supply circuit, the base B of the PNP transistor Q3 is connected to the collector C of the NPN transistor Q2 through the resistor R4, the collector C of the PNP transistor Q3 is connected to the resistor R5 and the resistor R6 connected in series, the resistor R6 is connected to the ground terminal, and the voltage collection IO1 port of the single chip is connected to the resistor R5; The same-direction input terminal of the comparator U1 is connected to the resistor R5, the reverse input terminal and the current-limiting resistor R8 are connected to the power-off reference voltage Vref terminal, and the output terminal of the comparator U1 is connected to the IO2 interface of the single-chip microcomputer.

2. The power-off data preservation system of a domain controller for a new energy commercial vehicle according to claim 1 is characterized in that: A resistor R7 is provided between the positive power supply terminal of the comparator U1 and the resistor R5.

3. A power-off data preservation system for domain controllers of new energy commercial vehicles according to claim 2, characterized in that: The capacitor C1 is also included. One end of the capacitor C1 is connected to the power supply circuit, and the other end is grounded.

4. A data preservation method is provided according to any one of claims 1 to 3, wherein: include: When the ON gear signal is at a high level, the NPN transistor Q2 is turned on and the PNP transistor Q3 is turned on. At this time, the input voltage of the battery is divided by the series resistors R5 and R6. The voltage value after the voltage division by the resistor R6 is collected through the voltage collection IO1 port of the single-chip microcomputer. At the same time, the voltage after the voltage division is compared with the power-off reference voltage Vref value after passing through the comparator U1. When the voltage value after the voltage division is greater than the power-off reference voltage Vref value, the comparator U1 outputs a high-level signal to the single-chip microcomputer I02 port; when the voltage value after the voltage division is less than the power-off reference voltage Vref value, the comparator U1 outputs a low-level signal to the single-chip microcomputer I02 port, and the single-chip microcomputer uses the values ​​collected by the IO1 port and the I02 port as the initial conditions for judging the power supply state; When the ON gear signal is at a low level, both the NPN transistor Q2 and the PNP transistor Q3 are not connected, the voltage value of the resistor R6 is collected at the I01 port of the microcontroller, and the comparator U1 outputs a low-level signal to the I02 port of the microcontroller. The microcontroller uses the values ​​collected at the IO1 port and the I02 port as the initial conditions for judging the power supply status.

5. The method for preserving power-off data of a domain controller of a new energy commercial vehicle according to claim 4 is characterized in that: After the voltage value collected by the IO1 port of the single-chip microcomputer is converted by AD, it is determined whether the collected value is greater than or equal to 8.5V. When it is greater than or equal to 8.5V, the drive circuit outputs normally and the MOS tube Q1 is turned on normally. When it is less than 8.5V, the gate of the MOS tube Q1 is turned off to determine whether the system is in sleep mode. If it is determined to be in sleep mode, the power-off data is saved.

6. The method for preserving power-off data of a domain controller of a new energy commercial vehicle according to claim 4 is characterized in that: The voltage value output by the comparator U1 collected by the I02 port of the single-chip computer, when the value collected by the I02 port is greater than or equal to 9.5V, the drive circuit outputs normally and the MOS tube Q1 is turned on normally; When the value collected at port I02 is less than 9.5V, continue to determine whether the collected value is greater than or equal to 8.5V. If it is greater than or equal to 8.5V, the drive circuit outputs normally and MOS tube Q1 is turned on normally. If it is less than 8.5V, the gate of MOS tube Q1 is turned off to make an initial judgment on whether the system should go into sleep mode and power off.

7. The method for preserving power-off data of a domain controller of a new energy commercial vehicle according to claim 4 is characterized in that: The reference voltage Vref is 9V.

8. The method for preserving power-off data of a domain controller of a new energy commercial vehicle according to claim 4 is characterized in that: The uplink voltage threshold and the downlink voltage threshold of the comparator U1 are 8.5V and 9.5V respectively.

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