Memory system and method of operating memory system

Abstract

The invention provides a memory system and a method of operating the memory system. The memory system includes: a first memory; a second memory having a running speed different from that of the first memory; a storage unit configured to store instructions; a prefetcher configured to update prefetcher data in response to an occurrence of a cache hit; and a processor configured to execute the instructions stored in the storage unit. When executing the instruction, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer region corresponding to the first memory and a second pointer region corresponding to the second memory based on the prefetcher friendly data, and store the prefetcher friendly bit in the first pointer region corresponding to the first memory and the second pointer region corresponding to the second memory. And determining whether to migrate data of the first pointer region and the second pointer region based on the reference bits and the prefetcher friendly bits of the first pointer region and the second pointer region.

Description

Technical Field

[0001] The present disclosure relates to a memory system and a method of operating a memory system. Background Art

[0002] As the memory usage of applications in data centers increases, the desire to have or build a large memory system is growing. Therefore, some large memory systems may be built using a heterogeneous memory system that uses storage class memory or compute express link (CXL) memory together with dynamic random access memory (DRAM). However, in a heterogeneous memory environment, since the performance of each memory type is different, the execution time of an application may be minimized by storing or saving hot pages that are frequently accessed by the application in a relatively faster memory, and storing or saving cold pages that are less frequently accessed by the application in a relatively slower memory. A memory system or a data processing system including a data storage device may be more competitive because it stores more data in the data storage device, stores data faster in the data storage device, and outputs the data stored in the data storage device faster. Summary of the invention

[0003] Some objects of the present disclosure include providing a memory system with reduced latency.

[0004] Some objects of the present disclosure include providing a method of operating a memory system with reduced latency.

[0005] The objects of the present disclosure are not limited to those mentioned above, and other objects of the present disclosure not mentioned herein will be more clearly understood by those skilled in the art from the following description of the present disclosure.

[0006] According to some aspects of the present disclosure, a memory system is provided, the memory system comprising: a first memory; a second memory, the second memory having an operating speed different from the operating speed of the first memory; a storage unit, the storage unit being configured to store instructions; a prefetcher, the prefetcher being configured to update prefetcher data in response to the occurrence of a cache hit; and a processor, the processor being configured to execute the instructions stored in the storage unit. When the instructions are executed by the processor, the processor may be configured to: generate prefetcher friendly data by filtering the prefetcher data; set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data; and determine whether to migrate the data of the first pointer area and the second pointer area based on the reference bit and the prefetcher friendly bit of the first pointer area and the second pointer area.

[0007] According to some aspects of the present disclosure, a method for operating a memory system is provided, the memory system including a first memory and a second memory operating at a speed different from that of the first memory, the method including: updating prefetcher data by a prefetcher in response to the occurrence of a cache hit; generating prefetcher-friendly data by filtering the prefetcher data by a monitoring module, and providing the generated prefetcher-friendly data to a migration module by the monitoring module; setting a prefetcher-friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory by the migration module and based on the prefetcher-friendly data; and determining by the migration module whether to migrate data of the first pointer area and the second pointer area based on reference bits and prefetcher-friendly bits of the first pointer area and the second pointer area.

[0008] According to some aspects of the present disclosure, a method for operating a memory system is provided, the memory system including a first memory and a second memory whose operating speed is different from that of the first memory, the method including: updating prefetcher data by a prefetcher in response to the occurrence of a cache hit; updating a prefetcher friendly bit by a migration module, the prefetcher friendly bit indicating whether the value of a cache hit occurring in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory is equal to or greater than a threshold; and determining by the migration module whether to migrate data of the first pointer area and the second pointer area based on a reference bit indicating that data in the first memory or the second memory has been referenced and the prefetcher friendly bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

[0010] Figure 2 It is shown Figure 1 A view of the prefetcher and monitoring modules in a memory system is shown.

[0011] Figure 3 It is shown Figure 1 A view of a migration module in a memory system is shown.

[0012] Figure 4 It is shown Figure 2 A flow chart of the operation of the prefetcher and monitoring modules is shown.

[0013] Figure 5 It is shown Figure 3 A flow chart of the operation of the migration module is shown.

[0014] Figure 6 It is shown Figure 5 A flowchart of the downgrade operation of the migration module is shown.

[0015] Figure 7 It is shown Figure 6 A view of the downgrade operation.

[0016] Figure 8 It is shown Figure 5 A flowchart of the upgrade operation of the migration module is shown.

[0017] Fig. 9 It is shown Figure 8 A view of the upgrade operation.

[0018] Fig.10 and Fig.11 is a diagram showing the effect of a memory system according to some embodiments.

[0019] Fig.12 It is shown that Figure 1 A block diagram of the electronics of the illustrated memory system. DETAILED DESCRIPTION

[0020] Terms such as “unit” and “module” used in the present disclosure or functional blocks shown in the drawings may be implemented in the form of hardware, software, and / or a combination thereof configured to perform specific functions.

[0021] Hereinafter, a memory system and a method of operating the memory system according to some embodiments will be described with reference to the accompanying drawings.

[0022] Figure 1 is a block diagram illustrating a memory system according to some embodiments of the present disclosure.

[0023] refer to Figure 1 , the memory system 1 may include a prefetcher 10, a monitoring module 20, and a migration module 30. In addition, the memory system 1 may include a storage unit (not shown) configured to store instructions and a processor (not shown) configured to execute instructions.

[0024] The prefetcher 10 may be included in a processor (not shown). For example, the prefetcher 10 may be configured in hardware, but the present disclosure is not limited thereto. For example, the prefetcher 10 may be implemented in software.

[0025] The prefetcher 10 may predict a memory area that may be accessed next by using the memory access pattern of the application program, and may read data from the memory to a cache memory inside a processor (not shown) in advance based on the prediction.

[0026] The prefetcher 10 may include prefetch information 100 and prefetcher data 120. The prefetch information 100 may include an address (ADDR) of prefetch data and hit information. The number of hits in the prefetch data through the prefetch information 100 may be recorded in the prefetcher data 120. Figure 2 The prefetch information 100 and the prefetcher data 120 are described in more detail.

[0027] The monitoring module 20 may include an analysis engine 200 and prefetcher friendly data 220. The monitoring module 20 may analyze the prefetcher data 120 through the analysis engine 200. The monitoring module 20 may store the prefetcher friendly data 220 generated according to the result of the analysis engine 200. In the present disclosure, a memory area that is likely to be preloaded into a processor (not shown) by the prefetcher 10 will be defined as a prefetcher friendly (PF) memory area. This will be referred to later. Figure 2 The process of generating the prefetcher friendly data 220 is described in more detail.

[0028] The memory system 1 may include a first memory (not shown) and a second memory (not shown). The migration module 30 may include a first pointer area 320 corresponding to the first memory (not shown). The migration module 30 may include a second pointer area 340 corresponding to the second memory (not shown). The operating speed of the first memory (not shown) may be different from the operating speed of the second memory (not shown).

[0029] In some embodiments, the memory system 1 may have a heterogeneous memory environment. For example, the operation speed of the first memory (not shown) may be relatively faster than the operation speed of the second memory (not shown). For example, the first memory (not shown) may be a DRAM, and the second memory (not shown) may be a CXL (Compute Express Link).

[0030] The migration module 30 may migrate the memory in consideration of the prefetcher affinity and activation status of the data included in the first pointer area 320 and the second pointer area 340 .

[0031] The migration module 30 may include a pre-fetch filter 300. The pre-fetch filter 300 may be based on the pre-fetcher friendly data 220 received from the monitoring module 20, for a plurality of first areas (see Figure 3 3200) and multiple second regions (see Figure 3 3400) specifies the prefetcher friendly bit pfb.

[0032] The method by which the migration module 30 migrates the memory by referencing the prefetcher friendly bit pfb and the reference bit rb will be described in more detail later.

[0033] Figure 2 It is shown Figure 1 A view of the prefetcher and monitoring modules in a memory system is shown.

[0034] refer to Figure 2 The prefetcher 10 and the monitoring module 20 may classify and record the prefetcher friendly memory areas by analyzing the memory access pattern of the processor (not shown).

[0035] When the prefetcher 10 performs memory prefetching, the prefetcher 10 may store the corresponding memory address. The hit information may correspond to data indicating whether the application has accessed the prefetched memory address.

[0036] The pre-fetch information 100 may include the memory address addr where the pre-fetch occurs and the hit information of the data included in the corresponding address. For example, the hit information may be recorded in the form of an event.

[0037] Prefetcher data 120 may include a page frame number PFN and a count value CNT. The page frame number may correspond to a portion of a memory address addr where prefetching occurs. The count refers to the number of times a cache hit has occurred with respect to data corresponding to the corresponding page frame number.

[0038] In some embodiments, the prefetcher data 120 can be recorded according to the Misra-Gries algorithm. The Misra-Gries algorithm is an algorithm for finding the most frequently occurring elements in a specific data pattern by using a table of a fixed size. The table used in the Misra-Gries algorithm can correspond to a table in a key value format. That is, depending on a specific key value, there may be different values. When a certain element is found, the table can be updated. In this case, when there is an element matching the key value of the corresponding element in the table, 1 is added according to the value of the corresponding key. When there is no element matching the key value of the corresponding element in the table and there is a vacancy in the table, the corresponding key value can be added to the table. However, when there is no element matching the key value of the corresponding element in the table and there is no vacancy in the table, the values ​​of all elements are reduced by 1. When the value of some elements reaches a threshold value of zero (0), the corresponding elements can be removed from the table. For example, the prefetcher data 120 included in some embodiments of the present disclosure can have N key values. Since the size of the prefetcher data 120 is limited, it is possible to prevent the size of hardware from increasing.

[0039] The monitoring module 20 may include an analysis engine 200 and prefetcher friendly data 220 .

[0040] The data processed by analyzing the prefetcher data 120 in the analysis engine 200 may be recorded in the prefetcher friendly data 220. The prefetcher friendly data 220 may include a page frame number PFN and a count value CNT. The prefetcher friendly data 220 may correspond to data whose count value is equal to or greater than a preset threshold value among the prefetcher data 120. Therefore, only the memory area with the highest prefetcher affinity may be classified.

[0041] Figure 3 It is shown Figure 1 A view of a migration module in a memory system is shown.

[0042] refer to Figure 3 , the migration module 30 may include a pre-fetch filter 300, a first pointer area 320, and a second pointer area 340. The first pointer area 320 may correspond to a first memory (not shown). The second pointer area 340 may correspond to a second memory (not shown). The first pointer area 320 may include a plurality of first areas 3200. The first area 3200 may correspond to a first page (not shown) included in the first memory (not shown). The second pointer area 340 may include a plurality of second areas 3400. The second area 3400 may correspond to a second page (not shown) included in the second memory (not shown).

[0043] The first pointer area 320 may include a first activated area and a first inactivated area. The second pointer area 340 may include a second activated area and a second inactivated area. The activated area may correspond to an area that is accessed a lot by a processor (not shown). The inactivated area may correspond to an area that is not accessed a lot by a processor (not shown). The activated area may correspond to an area that is accessed a relatively large number of times by a processor (not shown). The inactivated area may correspond to an area that is accessed a relatively small number of times by a processor (not shown).

[0044] When a processor (not shown) does not access data corresponding to the first region 3200 and the second region 3400 or accesses data relatively infrequently, the first region 3200 and the second region 3400 may be moved from an activated region to an inactivated region.

[0045] When the first area 3200 and the second area 3400 included in the first pointer area 320 and the second pointer area 340 are often referenced, the first area 3200 and the second area 3400 may be located at the head H of the first pointer area 320 and the second pointer area 340. On the other hand, when the first area 3200 and the second area 3400 included in the first pointer area 320 and the second pointer area 340 are not often referenced, the first area 3200 and the second area 3400 may be located at the tail T of the first pointer area 320 and the second pointer area 340.

[0046] The plurality of first areas 3200 and the plurality of second areas 3400 included in the first pointer area 320 and the second pointer area 340 may include a prefetcher friendly bit pfb and a reference bit rb, respectively.

[0047] The prefetcher friendly bit PFB may be a bit for displaying a plurality of first regions 3200 and a plurality of second regions 3400 that are prefetcher friendly included in the first pointer region 320 and the second pointer region 340. For example, when the prefetcher friendly bit PFB does not correspond to a prefetcher friendly region, its value may be 0. On the other hand, when the prefetcher friendly bit PFB corresponds to a prefetcher friendly region, its value may be 1. However, the embodiments of the present disclosure are not limited to the above examples. In some embodiments of the present disclosure, the prefetcher friendly bit of the prefetcher friendly region may be 0, and the prefetcher friendly bit of the prefetcher non-friendly region may be 1.

[0048] The reference bit rb may be a bit indicating whether the data in the first memory (not shown) and / or the second memory (not shown) corresponding to the first pointer area 320 and the second pointer area 340 is referenced. For example, when the processor (not shown) does not reference the memory page corresponding to the first area 3200, the value of the reference bit rb may be 0. On the other hand, when the processor (not shown) references the memory page corresponding to the first area 3200, the value of the reference bit rb may be 1. However, the embodiments of the present disclosure are not limited to the above examples. In some embodiments of the present disclosure, the reference bit of the area referenced by the processor may be 0, and the reference bit of the area not referenced by the processor may be 1.

[0049] In the present disclosure, migrating a page of a fast memory to a slow memory will be referred to as demotion, and migrating a page of a slow memory to a fast memory will be referred to as promotion.

[0050] The migration module 30 may perform downgrade and upgrade. In some embodiments, the first area 3200 located at the tail T of the first pointer area 320 may be downgraded to the second pointer area 340. In addition, the second area 3400 located at the head H of the second pointer area 340 may be upgraded to the first pointer area 320. Figure 4 The process of performing downgrade and upgrade by the migration module 30 is described.

[0051] Figure 4 It is shown Figure 2 Flowchart of the operation of the prefetcher and monitoring modules shown in .

[0052] refer to Figure 2 and Figure 4When the application accesses the prefetched memory address, a cache hit may occur, and according to the cache hit situation, hit information may be transmitted to the prefetcher 10 (operation S400).

[0053] Therefore, the prefetch information 100 and the prefetcher data 120 may be sequentially updated (operation S410).

[0054] The method of generating the prefetch information 100 and the prefetcher data 120 is the same as the above-mentioned method.

[0055] The monitoring module 20 may determine whether an analysis cycle of the prefetcher data 120 has occurred (operation S420 ).

[0056] The monitoring module 20 may transmit an instruction language for retrieving the prefetcher data 120 from the prefetcher 10 to a processor (not shown). For example, the monitoring module 20 may transmit an instruction language for retrieving the prefetcher data 120 according to a predetermined cycle. The monitoring module 20 may determine whether an analysis cycle occurs depending on whether the instruction language appears.

[0057] When the analysis cycle does not occur (“No” branch of operation S420 ), the process of updating the prefetch information 100 and the prefetcher data 120 is repeated as a cache hit occurs.

[0058] When the analysis cycle occurs (“Yes” branch of operation S420 ), the monitoring module 20 may analyze the prefetcher data 120 received from the prefetcher 10 through the analysis engine 200 , and may update the prefetcher friendly data 220 (operation S430 ).

[0059] As the analysis cycle occurs, the monitoring module 20 may receive the prefetcher data 120 from the prefetcher 10. The analysis engine 200 may analyze the prefetcher data 120. For example, when the preset threshold of the count value of the prefetcher data 120 is X, data having a count value of X or less may not be recorded in the prefetcher friendly data 220, and only data having a count value exceeding X may be recorded in the prefetcher friendly data 220.

[0060] Therefore, only the memory regions with the highest prefetcher affinity may be classified.

[0061] The updated prefetcher friendly data 220 may be transmitted to the migration module 30 according to a predetermined period (operation S440).

[0062] After the prefetcher friendly data 220 is transmitted to the migration module 30, the process of updating the prefetch information 100 and the prefetcher data 120 may be repeated according to the cache hit situation (operation S400).

[0063] Figure 5 It is shown Figure 3 A flowchart of the operation of the migration module is shown in FIG.

[0064] refer to Figure 1 , Figure 3 and Figure 5 , the migration module 30 may receive the prefetcher friendly data 220 from the monitoring module 20 (operation S500). For example, the migration module 30 may receive the prefetcher friendly data 220 from the monitoring module 20 according to a predetermined period.

[0065] The prefetch filter 300 may set the prefetcher friendly bits pfb in the prefetcher friendly plurality of first areas 3200 and the plurality of second areas with reference to the prefetcher friendly data 220 (operation S510 ).

[0066] For example, when the prefetcher friendly bit pfb does not correspond to the prefetcher friendly area, its value may be 0. On the other hand, when the prefetcher friendly bit pfb corresponds to the prefetcher friendly area, its value may be 1. However, the embodiments of the present disclosure are not limited to the above examples. In some embodiments of the present disclosure, the prefetcher friendly bit of the prefetcher friendly area may be 0, and the prefetcher friendly bit of the prefetcher non-friendly area may be 1.

[0067] The migration module 30 may determine whether a migration cycle has occurred (operation S520). That is, the migration may be repeated according to a predetermined cycle.

[0068] When the migration cycle has not occurred (“No” branch of operation S520 ), the migration module 30 may continue to receive the prefetcher friendly data 220 from the monitoring module 20 ( S500 ), and thus may set the prefetcher friendly bit pfb ( S510 ).

[0069] On the other hand, when the migration cycle has occurred ("Yes" branch of operation S520), the migration module 30 may perform migration between the first pointer area 320 and the second pointer area 340. The migration may include upgrading and downgrading.

[0070] The migration module 30 performs downgrading (operation S530).

[0071] In some embodiments, the migration module 30 may determine whether to perform downgrading on the first region 3200 located at the tail T of the first pointer region 320. Figure 6 A more detailed downgrade process is described. The migration module 30 having completed the downgrade may perform the upgrade (operation S540).

[0072] In some embodiments, the migration module 30 may determine whether to perform an upgrade on the second area 3400 located at the head H of the second pointer area 340. Figure 8Describes the upgrade process in more detail.

[0073] When the migration module 30 completes the upgrade, the migration may be completed (operation S550).

[0074] The migration module 30 that has completed the migration may receive the prefetcher friendly data 220 from the monitoring module 20 (operation S500 ), and may repeat the above process.

[0075] Figure 6 It is shown Figure 5 A flowchart of the downgrade operation of the migration module is shown. Figure 7 It is shown Figure 6 A view of the downgrade operation.

[0076] refer to Figure 3 , Figure 6 and Figure 7 When a migration cycle occurs, the migration module 30 may determine whether to perform degradation on the first area 3200 located at the tail T of the first pointer area 320 .

[0077] First, the migration module 30 may preferentially check the prefetcher friendly bit pfb of the first region 3200 located at the tail T of the first pointer region 320 (operation S531 ).

[0078] In the following description, in the case where the prefetcher affinity of the region is high, the value of the prefetcher friendly bit pfb is defined as 1, and in the case where the prefetcher affinity of the region is low, the value of the prefetcher friendly bit pfb is defined as 0. In the case where the region is referenced by a processor (not shown), the value of the reference bit rb is defined as 1, and in the case where the region is not referenced by the processor (not shown), the value of the reference bit rb is defined as 0. However, in the present disclosure, both the prefetcher friendly bit pfb and the reference bit rb may be set differently.

[0079] When the value of the prefetcher friendly bit pfb of the first region 3200 is 1 (“Yes” branch of operation S531), the first region 3200 is demoted to any position of the second pointer region 340 regardless of the value of the reference bit rb (operation S532) ( Figure 7 This is because, since the first region 3200 is a region with a higher prefetcher affinity, the performance degradation caused by the downgrade can be minimized. If the prefetcher friendly bit pfb is 1, even if the first region 3200 is downgraded to the second pointer region 340 corresponding to the slow memory, the processor (not shown) can still quickly access the first region 3200.

[0080] When the value of the prefetcher friendly bit pfb of the first region 3200 is 0, the reference bit rb is checked (operation S533).

[0081] When the value of the reference bit rb is 1 ("Yes" branch of operation S533), the data of the first area 3200 corresponds to the data referenced by the processor (not shown), and is thus moved to another position of the first pointer area 320 (operation S534) ( Figure 7 The pfb value is 0 and the rb value is 1). That is, no downgrade is performed. Therefore, when a processor (not shown) accesses the same data later, faster access is possible.

[0082] When the value of the reference bit rb is 0 ("No" branch of operation S533), the first region 3200 is downgraded to the second pointer region 340 (operation S535) ( Figure 7 This is because, when the reference bit rb is 0, since the data of the first area 3200 corresponds to data not referenced by the processor (not shown), the data of the first area 3200 does not need to be placed in the fast memory.

[0083] The migration module 30 may perform upgrading after completing the downgrading (operation S540).

[0084] In this way, the migration module 30 can perform demotion by preferentially determining the prefetcher friendly memory area, thereby ensuring the capacity of the fast memory. In addition, the prefetcher can be used, so that the performance degradation caused by data being degraded to the slow memory can be minimized. Therefore, in a heterogeneous memory environment, the performance of the processor can be improved.

[0085] Figure 8 It is shown Figure 5 A flowchart of the upgrade operation of the migration module is shown. Fig. 9 It is shown Figure 8 A view of the upgrade operation.

[0086] refer to Figure 3 , Figure 8 and Fig. 9 After performing the downgrade (operation S530 ), the migration module 30 may determine whether to perform an upgrade on the second region 3400 located at the head H of the second pointer region 340 .

[0087] First, the migration module 30 may preferentially check a prefetcher friendly bit pfb of the second region 3400 located at the head H of the second pointer region 340 (operation S541 ).

[0088] In the following, in the case where the prefetcher affinity of the region is high, the value of the prefetcher friendly bit pfb is defined as 1, and in the case where the prefetcher affinity of the region is low, the value of the prefetcher friendly bit pfb is defined as 0. In the case where the region is referenced by a processor (not shown), the value of the reference bit rb is defined as 1, and in the case where the region is not referenced by the processor (not shown), the value of the reference bit rb is defined as 0. However, in the present disclosure, both the prefetcher friendly bit pfb and the reference bit rb may be set differently.

[0089] When the value of the prefetcher friendly bit pfb of the second region 3400 is 1 (“Yes” branch of operation S541), the second region 3400 may be moved to another position of the second pointer region 340 regardless of the value of the reference bit rb (operation S542) ( Fig. 9 This is because, when the prefetch friendly bit pfb is 1, even if the second area 3400 is located in the second pointer area 340 corresponding to the slow memory, the performance degradation can be minimized because the second area 3400 corresponds to an area with a higher prefetcher affinity.

[0090] When the value of the prefetcher friendly bit pfb of the second region 3400 is 0 (“No” branch of operation S541 ), the reference bit rb is checked (operation S543 ).

[0091] When the value of the reference bit rb is 1 ("yes" branch of operation S543), the data of the second area 3400 corresponds to the data referenced by the processor (not shown), and thus upgrading to the first pointer area 320 (operation S544) can be performed ( Figure 7 The pfb value is 0 and the rb value is 1). Therefore, when a processor (not shown) accesses the same data later, faster access is possible.

[0092] When the value of the reference bit rb is 0 ("No" branch of operation S543), the second area 3400 may be moved to another position in the second pointer area without performing an upgrade to the first pointer area 320 (operation S545) ( Figure 7 This is because, when the reference bit rb is 0, the data of the second area 3400 corresponds to data not referenced by the processor (not shown), and therefore the data of the second area 3400 does not need to be placed in the fast memory. The migration module 30 can complete the migration when the upgrade is completed (S550).

[0093] The migration module 30 can ensure the capacity of the fast memory by preferentially determining the prefetcher friendly memory area without performing the upgrade. In addition, the prefetcher can be used, so that the performance degradation caused by data being relegated to the slow memory can be minimized. Therefore, in a heterogeneous memory environment, the performance of the processor can be improved.

[0094] Fig.10 and Fig.11 is a diagram showing the effect of a memory system according to some embodiments.

[0095] refer to Fig.10 , a graph indicating the degree of performance improvement due to the use of a prefetcher in a single-core environment is shown. The horizontal axis represents the type of benchmark (e.g., benchmark A, benchmark B, etc.), and the vertical axis represents the degree of performance improvement in each benchmark compared to the case where the prefetcher is not used.

[0096] The access time of the local memory may be shorter than the access time of the remote memory. Thus, the local memory may be a relatively fast memory, while the remote memory may be a relatively slow memory.

[0097] The prefetcher may be used in a single core environment, thereby alleviating (eg, significantly alleviating) performance degradation of the processor.

[0098] Using a prefetcher in a remote memory may have a greater effect on improving performance than using a prefetcher in a local memory. This may be because the performance degradation caused by the long memory access time of the remote memory can be alleviated (e.g., significantly alleviated) by using a prefetcher.

[0099] Therefore, when using the memory system 1 according to some embodiments of the present disclosure, prefetcher-friendly memory areas can be detected in a heterogeneous memory environment and migrated in advance, thereby alleviating (e.g., significantly alleviating) performance degradation caused by excessively long memory access time.

[0100] refer to Fig.11 , shows a graph indicating the degree of performance improvement due to the use of a prefetcher in a multi-core environment. The horizontal axis represents the type of benchmark (e.g., benchmark A, benchmark B, etc.), and the vertical axis represents the degree of performance improvement in each benchmark compared to the case where the prefetcher is not used.

[0101] The prefetcher can be used even in a multi-core environment, thus mitigating the performance degradation of the processor.

[0102] Furthermore, using a prefetcher in a remote memory may have a greater effect on improving performance than using a prefetcher in a local memory because performance degradation caused by long memory access times in the remote memory may be mitigated (eg, significantly mitigated) by using a prefetcher.

[0103] Therefore, when using the memory system 1 according to some embodiments of the present disclosure, prefetcher-friendly memory areas can be detected in a heterogeneous memory environment and migrated in advance, thereby alleviating (e.g., significantly alleviating) performance degradation caused by excessively long memory access time.

[0104] Fig.12 It is shown that Figure 1 A block diagram of the electronics of the illustrated memory system.

[0105] The electronic device 601 in the network environment 600 may communicate with the electronic device 602 through a first network 698 such as a short-range wireless communication network, or may communicate with the electronic device 604 or the server 608 through a second network 699 such as a long-range wireless communication network.

[0106] The electronic device 601 can communicate with the electronic device 604 through the server 608. The electronic device 601 may include a processor 620, a memory 630, an input device 650, a sound output device 655, a display device 660, an audio module 670, a sensor module 676, an interface 677, a connection terminal 678, a haptic module 679, a camera module 680, a power management module 688, a battery 689, a communication module 690, a subscriber identification module (SIM) 696, an antenna module 697, and the like.

[0107] In some embodiments, at least one of the components such as the display device 660 or the camera module 680 may be omitted from the electronic device 601 , or one or more other components may be added to the electronic device 601 .

[0108] In some embodiments, some of the components may be integrated into a single integrated circuit (IC).For example, the sensor module 676 may include a fingerprint sensor, an iris sensor, and / or an illumination sensor, and may be embedded in the display device 660 (such as a display).

[0109] The processor 620 may perform various data processing or calculations by executing software (eg, program 640 ) that controls other components of the at least one electronic device 601 , such as hardware or software components connected to the processor 620 .

[0110] As at least part of data processing or computing, the processor 620 can load commands or data received from another component (such as, sensor module 676 or communication module 690) into volatile memory 632, process the commands or data stored in volatile memory 632, and store the resulting data in non-volatile memory 634.

[0111] The processor 620 may include a main processor, such as a central processing unit (CPU) or an application processor (AP), and an auxiliary processor 623 , which may operate independently of the main processor 621 or in association with the main processor 621 .

[0112] The auxiliary processor 623 may include, for example, a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP).

[0113] In some embodiments, the auxiliary processor 623 may be configured to consume less power than the main processor 621 or to perform a specific function. The auxiliary processor 623 may be implemented separately from the main processor 621 or as a part of the main processor 621.

[0114] When the main processor 621 is in an inactive state, the auxiliary processor 623 can control at least some of the functions or states related to at least one component of the electronic device 601 on behalf of the main processor 621, or when the main processor 621 is in an active state, the auxiliary processor 123 can control at least some of the functions or states related to at least one component of the electronic device 601 together with the main processor 621.

[0115] The memory 630 may store various data for at least one component of the electronic device 601. The data may include software such as a program 640 and input data or output data for commands related to the software. The memory 630 may include a volatile memory 632 or a nonvolatile memory 634.

[0116] The program 640 may be stored in the memory 630 as software, and includes, for example, an operating system (OS) 642 , middleware 644 , or an application 646 .

[0117] The input device 650 may receive a command or data that may be used by another component of the electronic device 601. The input device 650 may receive a command or data from outside the electronic device 601, or receive a signal outside the electronic device 601. The input device 650 may include, for example, a microphone, a mouse, or a keyboard.

[0118] The sound output device 655 may output a sound signal to the outside of the electronic device 601. The sound output device 655 may include, for example, a speaker. Multimedia data may be output through the speaker.

[0119] The display device 660 may visually provide information to the outside of the electronic device 601. The display device 660 may include, for example, a display, a holographic device, or a projector, and a control circuit configured to control a corresponding one of the display, the holographic device, and the projector.

[0120] In some embodiments, the display device 660 may include a touch circuit configured to sense a touch or a sensor circuit (such as a pressure sensor) configured to measure the intensity of a force caused by a touch.

[0121] The audio module 670 can convert sound into electrical signals, or vice versa. In some embodiments, the audio module 670 can obtain sound via the input device 650, or output sound via the sound output device 655 or the earphone of the external electronic device 602 directly connected or wirelessly connected to the electronic device 601.

[0122] The sensor module 676 may sense an operating state (e.g., power or temperature) of the electronic device 601 or an environmental state (e.g., a state of a user) outside the electronic device 601, and may generate an electrical signal or data value corresponding to the sensed state. The sensor module 676 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0123] The interface 677 may support one or more prescribed protocols for use by the electronic device 601 directly or wirelessly connected to the external electronic device 602. In some embodiments, the interface 677 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0124] The connection end 678 may include a connector, and the electronic device 601 may be physically connected to the external electronic device 602 via the connector. In some embodiments, the connection end 678 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

[0125] The haptic module 679 may convert the electrical signal into a mechanical stimulus (such as vibration or motion) that can be recognized by the user through tactile or kinesthetic sense. In some embodiments, the haptic module 679 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0126] The camera module 680 can capture still images and moving images. In some embodiments, the camera module 680 may include one or more lenses, image sensors, image signal processors, or flashes.

[0127] The power management module 688 may manage power supply to the electronic device 601. For example, the power management module 688 may be implemented as at least a part of a power management integrated circuit (PMIC), for example.

[0128] The battery 689 may power at least one component of the electronic device 601. According to some embodiments, the battery 689 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0129] The communication module 690 may support establishment of a direct communication channel or a wireless communication channel between the electronic device 601 and an external electronic device (eg, the electronic device 602 , the electronic device 604 , or the server 608 ), and may perform communication through the established communication channel.

[0130] The communication module 690 may include one or more communication processors capable of operating independently from the processor 620 and support direct communication or wireless communication.

[0131] In some embodiments, the communication module 690 may include a wireless communication module 692 (such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 694 (such as a local area network (LAN) communication module or a power line communication (PLC) module).

[0132] The corresponding communication modules in these communication modules can communicate with each other via the first network 698 (e.g., Bluetooth TM , Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA) standards) or a second network 699 (eg, a mobile communication network, the Internet, a long-distance communication network, etc.) to communicate with an external electronic device.

[0133] These various types of communication modules may be implemented as a single component, or may be implemented as multiple components separated from each other. The wireless communication module 692 may identify and authenticate the electronic device 601 in a communication network (such as the first network 698 or the second network 699) using user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 696.

[0134] The antenna module 697 may transmit or receive a signal or power to or from the outside of the electronic device 601. In some embodiments, the antenna module 697 may include one or more antennas, and the communication module 690 may select at least one antenna suitable for a communication scheme used in a communication network such as the first network 698 or the second network 699 from the plurality of antennas. A signal or power may be transmitted or received between the communication module and an external electronic device via the selected at least one antenna.

[0135] At least some of the above components may be connected to each other via an inter-peripheral communication scheme such as a bus, a general purpose input output (GPIO), a serial peripheral interface (SPI), or a mobile industry processor interface (MIPI) and transmit signals therebetween.

[0136] In some embodiments, a command or data may be sent or received between the electronic device 601 and the external electronic device 606 via a server 608 connected to the second network 699. The electronic device 602 and the electronic device 606 may be devices of the same type as the electronic device 601, or devices of a different type from the electronic device 601. All or some operations to be run in the electronic device 601 may be run in one or more of the external electronic device 602, the external electronic device 606, or the server 608. For example, all or some operations to be run in the electronic device 601 may be run in one or more of the external electronic device 602, the external electronic device 606, or the server 608.

[0137] For example, if the electronic device 601 should automatically perform a function or service or should perform a function or service in response to a request from a user or another device, the electronic device 601 may request one or more external electronic devices to perform at least part of the function or service instead of running the function or service. The one or more external electronic devices that receive the request may perform at least part of the function or service requested, or perform another function or another service associated with the request, and transmit the result of the execution to the electronic device 601. The electronic device 601 may provide the result as at least a partial reply to the request, with or without further processing the result. To this end, cloud computing technology, distributed computing technology, or client-server computing technology, for example, may be used.

[0138] Although some embodiments of the present disclosure have been described with reference to the accompanying drawings, it is clear to those skilled in the art that the present disclosure can be manufactured in various forms without being limited to the above embodiments, and the present disclosure can be implemented in other specific forms without departing from the technical spirit and basic characteristics. Therefore, the above embodiments should be considered in all aspects as illustrative rather than restrictive.

Claims

1. A memory system, comprising: a first memory; a second memory, the second memory operating at a speed different from the first memory operating speed; a storage unit, wherein the storage unit is configured to store instructions; a prefetcher configured to update prefetcher data in response to the occurrence of a cache hit; as well as a processor configured to execute the instructions stored in the storage unit, Wherein, when the instruction is executed by the processor, the processor is configured to: generating prefetcher-friendly data by filtering the prefetcher data, based on the prefetcher friendly data, setting a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory, and Whether to migrate data of the first pointer area and the second pointer area is determined based on the reference bits of the first pointer area and the second pointer area and the prefetcher friendly bit.

2. The memory system according to claim 1, wherein: The processor includes the prefetcher.

3. The memory system according to claim 1, wherein: The prefetcher data is stored according to the Misra-Gries algorithm.

4. The memory system according to claim 1, wherein: The prefetcher-friendly data is data in which the number of cache hits among the prefetcher data is equal to or greater than a threshold value.

5. The memory system according to claim 4, wherein: The processor is configured to update the prefetcher friendly data based on the occurrence of an analysis cycle.

6. The memory system according to claim 5, wherein: The prefetcher friendly bit is reset at a predetermined cycle during execution of the instruction.

7. The memory system according to claim 1, wherein: The reference bit indicates whether the processor has referenced data in the first memory or the second memory. 8 . The memory system of claim 1 , further comprising a migration module configured to move a first region located at a tail of the first pointer region to a position of the second pointer region in response to the prefetcher friendly bit having a first value.

9. The memory system according to claim 1, wherein: The first memory is a dynamic random access memory and the second memory is a computing high-speed link.

10. A method for operating a memory system, the memory system comprising a first memory and a second memory having an operating speed different from an operating speed of the first memory, the method comprising: updating prefetcher data by the prefetcher in response to the occurrence of a cache hit; The monitoring module generates prefetcher friendly data by filtering the prefetcher data, and the monitoring module provides the generated prefetcher friendly data to the migration module; The migration module sets a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data; as well as The migration module determines whether to migrate data of the first pointer area and the second pointer area based on the reference bits and the prefetcher friendly bits of the first pointer area and the second pointer area.

11. The method according to claim 10, wherein: The prefetcher-friendly data is data in which the number of cache hits among the prefetcher data is equal to or greater than a threshold value.

12. The method according to claim 11, wherein: The prefetcher friendly data is updated based on the occurrence of an analysis cycle.

13. The method according to claim 12, wherein: The prefetcher friendly bit is reset at a predetermined period.

14. The method according to claim 11, wherein: The reference bit indicates whether data in the first memory or the second memory has been referenced.

15. The method according to claim 14, further comprising, by the migration module, in response to the prefetch friendly bit having a first value and the reference bit having a third value, moving a first area located at the tail of the first pointer area to a position of the second pointer area. 16 . The method of claim 15 , further comprising changing the reference bit to a fourth value different from the third value in response to the first region moving to the location of the second pointer region.

17. The method according to claim 15, wherein: The location of the second pointer area is a first location, and wherein the method further comprises, in response to the prefetcher friendly bit having a first value and the reference bit having a fourth value different from the third value, moving the first area located at the tail of the first pointer area to a second location of the second pointer area.

18. The method of claim 14, further comprising, in response to the prefetcher friendly bit having a first value and the reference bit having a third value, moving, by the migration module, a second area located at a head of the second pointer area to another location of the second pointer area.

19. A method for operating a memory system, the memory system comprising a first memory and a second memory having an operating speed different from an operating speed of the first memory, the method comprising: updating prefetcher data by the prefetcher in response to the occurrence of a cache hit; updating, by a migration module, a prefetcher friendly bit, the prefetcher friendly bit indicating whether a number of the cache hits occurring in a first pointer region corresponding to the first memory and a second pointer region corresponding to the second memory is equal to or greater than a threshold; as well as Whether to migrate data in the first pointer area and the second pointer area is determined by the migration module based on a reference bit indicating that data in the first memory or the second memory has been referenced and the prefetcher friendly bit.

20. The method according to claim 19, wherein: The first memory is a dynamic random access memory and the second memory is a computing high-speed link.

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