A SIMD instruction conversion optimization method based on data processing mode prediction

Abstract

The invention discloses a SIMD instruction conversion optimization method based on data processing mode prediction. When an executable file is executed in a dynamic instruction conversion mode, the type of the operand is determined to be an array or a matrix according to the addressing mode of the operand of the instruction to be converted, and then the semantics of the operand is determined according to the instruction function of the functional code segment related to the instruction to be converted, so as to complete the prediction of the data processing mode, determine the segmentation mode of the operand according to the prediction result of the data processing mode, convert the instruction to be converted into ARM instructions, and determine the ARM instructions for operand loading according to the segmentation mode to form an ARM instruction sequence, form an instruction conversion strategy list according to the corresponding relationship between the instruction to be converted and the ARM instruction sequence, complete the instruction conversion according to the instruction conversion strategy list, realize the segmentation of operands related to the data processing mode, and effectively reduce the performance loss introduced by the segmentation operation.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to a SIMD instruction conversion optimization method based on data processing mode prediction. Background Art

[0002] The SIMD extended instruction set under the existing x86 architecture supports a variety of word lengths. For example, in 256-bit mode, vector registers can store 256-bit data, and common operations include arithmetic operations and logical operations on 256-bit vectors. NEON is a SIMD extended instruction set in the ARM architecture, and its data vector length is usually 128 bits. Therefore, when using NEON instructions to process longer data related to the SIMD instructions of the x86 architecture, it is necessary to first split the data of the x86 architecture into multiple shorter data that can be processed by the NEON instructions and then process them separately. However, since additional splitting and merging operations need to be performed, the execution performance of executable files may be reduced when simulating the execution of SIMD instructions of the x86 architecture in the ARM architecture based on data splitting. Summary of the invention

[0003] In view of this, the present invention provides a SIMD instruction conversion optimization method based on data processing mode prediction, which determines the type and semantics of operands by predicting the data processing mode, and realizes the conversion of SIMD instructions based on precise segmentation and loading of operands.

[0004] The present invention provides a SIMD instruction conversion optimization method based on data processing mode prediction, which specifically includes the following steps:

[0005] Step 1: If the executable file has a corresponding instruction conversion strategy list, the execution of the executable file is completed according to the instruction conversion strategy list, and this process ends; otherwise, the executable file is loaded and executed through dynamic instruction conversion;

[0006] Step 2, obtain the current instruction to be converted and its operand, determine the type of the operand, record the word length of the ARM instruction as the first word length, execute step 3 when the operand is an array arranged in a linear manner, and execute step 8 when the operand is a matrix of a non-linear arrangement logic structure;

[0007] Step 3, record the operand as the first operand, the size of the elements in the first operand is the first element size, and the length of the first operand is the first length; determine the data type of the first operand, when the first operand is image data, execute step 4, when the first operand is audio data, execute step 6;

[0008] Step 4: If the product of the first element size and the first length is greater than the first word length, the first operand is divided into N sub-operands, and then step 5 is executed; otherwise, the first operand is kept unchanged and step 11 is executed;

[0009] Step 5, establish a first loop body with a total number of loops of N, the ARM instruction with the same function as the current instruction to be converted is the first ARM instruction, set the initial value of the loop number n to 1, load the nth sub-operand into the nth ARM register, use the first ARM instruction to calculate the nth sub-operand, if n is less than N, set n to be incremented by 1 and then execute the first loop body, otherwise end the loop; convert the current instruction to be converted into the first ARM instruction sequence included in the first loop body to complete the conversion, add the corresponding relationship between the current instruction to be converted and the first ARM instruction sequence to the instruction conversion strategy list, and execute step 12;

[0010] Step 6: If the product of the first element size and the first length is greater than the first word length, the first operand is divided into N sub-operands and step 7 is executed; otherwise, the first operand is kept unchanged and step 11 is executed;

[0011] Step 7, establish a second loop body with a total number of loops of N, the ARM instruction with the same function as the current instruction to be converted is the second ARM instruction, set the initial value of the loop number n to 1, load the nth sub-operand into the nth ARM register, use the second ARM instruction to calculate the nth sub-operand, if n is less than N, set n to be incremented by 1 and then execute the second loop body, otherwise end the loop; convert the current instruction to be converted into the second ARM instruction sequence included in the second loop body to complete the conversion, add the corresponding relationship between the current instruction to be converted and the second ARM instruction sequence to the instruction conversion strategy list, and execute step 12;

[0012] Step 8, the operands are the first operand and the second operand, the element size of the first operand and the second operand is recorded as the first element size, the number of rows P and the number of columns Q of the first operand are obtained, and the number of rows Q and the number of columns S of the second operand are obtained;

[0013] Step 9, if the product of the first element size and Q is greater than the first word length, then divide each row of data of the first operand into K sub-operands, and divide each column of data of the second operand into K sub-operands; otherwise, keep the first operand and the second operand unchanged, and execute step 11;

[0014] Step 10, establish a third loop body with a total number of loops of Q, the ARM instruction with the same function as the current instruction to be converted is the third ARM instruction, set the initial value of the number of loops q to be 1 and q is not greater than Q; establish a fourth loop body with a total number of loops of K in the third loop body, load the qth column of the first operand and the qth row of the second operand into 2K ARM registers respectively; use the third ARM instruction to complete the calculation of the qth column of the first operand and the qth row of the second operand, if q is less than Q, let q be incremented by 1 and continue to execute the third loop body, otherwise end the loop; convert the current instruction to be converted into the third ARM instruction sequence contained in the third loop body to complete the conversion, add the corresponding relationship between the current instruction to be converted and the third ARM instruction sequence to the instruction conversion strategy list, and execute step 12;

[0015] Step 11, select an ARM instruction with the same function as the current instruction to be converted, add the corresponding relationship between the current instruction to be converted and the ARM instruction to the instruction conversion strategy list, and execute step 12;

[0016] Step 12: If the executable file has not been executed, the next instruction is selected as the current instruction to be converted and step 2 is executed; otherwise, the execution of the executable file is completed and this process ends.

[0017] Furthermore, the method for determining the type of the operand in step 2 is: determined according to the addressing mode of the operand, the address determined by the addressing mode is the sum of the base address and the offset, when the offset is the product of the index and the element size, the operand is determined to be an array arranged in a linear manner; when the offset is the result of the operation of two indexes, the number of columns and the element size, the operand is determined to be a matrix of a nonlinearly arranged logical structure.

[0018] Furthermore, the method for determining the data type of the first operand in step 3 is: the functional code segment related to the current instruction to be converted is the first code segment, and the first instruction set is formed by the instructions in the first code segment. When the first instruction set includes an operation code for image processing, the first operand is determined to be image data; when the first instruction set includes an operation code for audio data processing, the first operand is determined to be audio data.

[0019] Furthermore, the first code segment is determined by binary code feature analysis.

[0020] Furthermore, the method of dividing the first operand into N sub-operands in step 4 is: round up the ratio of the product of the first element size and the first length to the first word length as the first division number N, the length of the first N-1 sub-operands is the second length, the value of the second length satisfies the condition that it is a multiple of 3 and the product of the second length and the first element size is less than the first word length, and the length of the last sub-operand is the remaining length of the first operand.

[0021] Furthermore, in step 6, the first operand is divided into N sub-operands in the following manner: the ratio of the product of the first element size and the first length to the first word length is rounded up as the first division number N, the length of the first N-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of the first operand.

[0022] Furthermore, the method of dividing each row of data of the first operand into K sub-operands in step 9 is: rounding up the ratio of the product of the first element size and Q to the first word length as the second division number K, the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each row in the first operand.

[0023] Furthermore, in step 9, the manner of dividing each column of data of the second operand into K sub-operands is as follows: the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each column in the second operand.

[0024] Furthermore, the fourth loop body in step 10 is implemented as follows: let the initial value of the loop number k be 1 and k is not greater than K, load the kth sub-operand of the qth column of the first operand into the kth ARM register, and load the kth sub-operand of the qth row of the second operand into the K+kth ARM register; if k is less than K, let k be incremented by 1 and continue to execute the fourth loop body; otherwise, end the loop. Beneficial Effects

[0025] When executing an executable file in a dynamic instruction conversion mode, the present invention determines the type of the operand as an array or a matrix according to the addressing mode of the operand of the instruction to be converted, and then determines the semantics of the operand according to the instruction function of the functional code segment related to the instruction to be converted, completes the prediction of the data processing mode, determines the segmentation mode of the operand according to the prediction result of the data processing mode, converts the instruction to be converted into ARM instructions and determines the ARM instructions for loading the operands according to the segmentation mode to form an ARM instruction sequence, forms an instruction conversion strategy list based on the correspondence between the instruction to be converted and the ARM instruction sequence, completes the instruction conversion according to the instruction conversion strategy list, realizes the segmentation of operands related to the data processing mode, and effectively reduces the performance loss introduced by the segmentation operation. DETAILED DESCRIPTION

[0026] The present invention is described in detail with reference to the following embodiments.

[0027] The present invention provides a SIMD instruction conversion optimization method based on data processing mode prediction, the core idea of ​​which is: when executing an executable file in a dynamic instruction conversion mode, the type of the operand is determined as an array or a matrix according to the addressing mode of the operand of the instruction to be converted, and then the semantics of the operand is determined according to the instruction function of the functional code segment related to the instruction to be converted, the prediction of the data processing mode is completed, the segmentation method of the operand is determined according to the prediction result of the data processing mode, the instruction to be converted is converted into ARM instructions and the ARM instructions for operand loading are determined according to the segmentation method to form an ARM instruction sequence, the corresponding relationship between the instruction to be converted and the ARM instruction sequence is formed into an instruction conversion strategy list, and the instruction conversion is completed according to the instruction conversion strategy list.

[0028] The present invention provides a SIMD instruction conversion optimization method based on data processing mode prediction, which specifically includes the following steps:

[0029] Step 1: If the executable file has a corresponding instruction conversion strategy list, the execution of the executable file is completed by dynamic instruction conversion loading and execution according to the instruction conversion strategy list, and this process ends; otherwise, the executable file is executed by dynamic instruction conversion loading and execution.

[0030] Step 2, obtain the current instruction to be converted and its operands, determine the type of the current instruction operand to be converted according to the addressing mode of the operand, the address determined by the addressing mode is the sum of the base address and the offset, when the offset is the product of the index and the element size, determine that the operand is an array arranged in a linear manner, and execute step 3; when the offset is the result of the operation of two indexes, the number of columns and the element size, determine that the operand is a matrix of a non-linear arrangement logical structure, and execute step 8.

[0031] Step 3, record the operand of array type as the first operand, obtain the size of the element in the first operand and record it as the first element size, record the length of the first operand as the first length, and record the word length of the ARM instruction as the first word length; according to the binary code feature analysis, determine the functional code segment related to the current instruction to be converted, record the functional code segment as the first code segment, obtain the instructions in the first code segment to form a first instruction set, determine the instruction function according to the operation code of each instruction in the first instruction set, when the first instruction set contains the operation code of image processing, determine that the first operand is image data and execute step 4; when the first instruction set contains the operation code of audio data processing, determine that the first operand is audio data and execute step 6.

[0032] Step 4: If the product of the first element size and the first length is greater than the first word length, the ratio of the product of the first element size and the first length to the first word length is rounded up as the first division number N, and the first operand is divided into N sub-operands. The length of the first N-1 sub-operands is the second length. The value of the second length satisfies the conditions that the second length is a multiple of 3 and the product of the second length and the first element size is less than the first word length. The length of the last sub-operand is the remaining length of the first operand, and step 5 is executed; if the product of the first element size and the first length is not greater than the first word length, the first operand is kept unchanged, and step 11 is executed.

[0033] Step 5, establish a first loop body, the total number of loops is N, select N ARM registers, select an ARM instruction with the same function as the current instruction to be converted as the first ARM instruction, set the initial value of the loop number n to 1 and n is not greater than N, load the nth sub-operand into the nth ARM register, use the first ARM instruction to complete the calculation of the nth sub-operand, if n is less than N, let n be incremented by 1 and continue to execute the first loop body, otherwise end the loop; record the ARM instructions contained in the first loop body as the first ARM instruction sequence, convert the current instruction to be converted into the first ARM instruction sequence to complete the conversion, and add the correspondence between the current instruction to be converted and the first ARM instruction sequence to the instruction conversion strategy list, and execute step 12.

[0034] Step 6: If the product of the first element size and the first length is greater than the first word length, the ratio of the product of the first element size and the first length to the first word length is rounded up as the first division number N, and the first operand is divided into N sub-operands, the length of the first N-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of the first operand, and step 7 is executed; if the product of the first element size and the first length is not greater than the first word length, the first operand is kept unchanged, and step 11 is executed.

[0035] Step 7, establish a second loop body, the total number of loops is N, select N ARM registers, select an ARM instruction with the same function as the current instruction to be converted as the second ARM instruction, set the initial value of the loop number n to 1 and n is not greater than N, load the nth sub-operand into the nth ARM register, use the second ARM instruction to complete the calculation of the nth sub-operand, if n is less than N, let n be incremented by 1 and continue to execute the second loop body, otherwise end the loop; record the ARM instructions contained in the second loop body as the second ARM instruction sequence, convert the current instruction to be converted into the second ARM instruction sequence to complete the conversion, and add the correspondence between the current instruction to be converted and the second ARM instruction sequence to the instruction conversion strategy list, and execute step 12.

[0036] Step 8. Record the word length of the ARM instruction as the first word length, record the operands of matrix type as the first operand and the second operand respectively, record the element size of the first operand and the second operand as the first element size, obtain the number of rows P and the number of columns Q of the first operand, and obtain the number of rows Q and the number of columns S of the second operand.

[0037] Step 9. If the product of the first element size and Q is greater than the first word length, the ratio of the product of the first element size and Q to the first word length is rounded up as the second partition number K, and each row of data of the first operand is divided into K sub-operands, the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each row in the first operand, and each column of data of the second operand is divided into K sub-operands, the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each column in the second operand; if the product of the first element size and Q is not greater than the first word length, the first operand and the second operand are kept unchanged, and step 11 is executed.

[0038] Step 10, establish a third loop body, the total number of loops is Q, select 2K ARM registers, select an ARM instruction with the same function as the current instruction to be converted as the third ARM instruction, set the initial value of the loop number q to 1 and q is not greater than Q; establish a fourth loop body in the third loop body, the total number of loops of the fourth loop body is K, load the qth column of the first operand and the qth row of the second operand into the 2K ARM registers respectively; use the third ARM instruction to complete the calculation of the qth column of the first operand and the qth row of the second operand, if q is less than Q, let q be incremented by 1 and continue to execute the third loop body, otherwise end the loop; record the ARM instructions contained in the third loop body as the third ARM instruction sequence, convert the current instruction to be converted into the third ARM instruction sequence to complete the conversion, and add the corresponding relationship between the current instruction to be converted and the third ARM instruction sequence to the instruction conversion strategy list, and execute step 12.

[0039] Among them, the implementation method of the fourth loop body is: let the initial value of the loop number k be 1 and k is not greater than K, load the kth sub-operand of the qth column of the first operand into the kth ARM register, and load the kth sub-operand of the qth row of the second operand into the K+kth ARM register. If k is less than K, let k be incremented by 1 and continue to execute the fourth loop body, otherwise end the loop.

[0040] Step 11: Select an ARM instruction with the same function as the current instruction to be converted, add the corresponding relationship between the current instruction to be converted and the ARM instruction to the instruction conversion strategy list, and execute step 12.

[0041] Step 12: If the executable file has not been executed, the next instruction is selected as the current instruction to be converted and step 2 is executed; otherwise, the execution of the executable file is completed and this process ends. Example

[0042] In this embodiment, a SIMD instruction conversion optimization method based on data processing mode prediction provided by the present invention is adopted to realize the conversion of x86 architecture instructions to ARM architecture instructions by modifying the AVX code conversion module of the dynamic instruction conversion engine, including the following steps:

[0043] S1. During the dynamic conversion of AVX instructions, the data processing mode is predicted through x86 / AVX binary code feature analysis to determine whether it belongs to the three data processing modes of image data processing, matrix operation and audio data processing.

[0044] S1.1. Determine whether it is an image data processing scenario. The specific steps are as follows:

[0045] Data storage format analysis, the specific steps are as follows:

[0046] Image data processing usually involves operations on two-dimensional pixel data. For a color image, the data may be stored in memory and stored in row-major order. For example, for an RGB image, the data may be stored as `R1 G1 B1 R2 G2 B2...`, where R1 is the red component of the first pixel, G1 is the green component of the first pixel, B1 is the blue component of the first pixel, and so on. Each component is usually 8 bits, so a pixel occupies 24 bits, and 32 bits if the alpha channel is included.

[0047] When AVX instructions process image data, they will load a large amount of data from memory into the YMM registers, which span multiple pixels. For example, assuming that the image data is stored at the image_data address, the AVX load operation example is as follows:

[0048] vmovaps ymm0, [image_data] / / Load 256-bit data, which may contain multiple pixels

[0049] vmovaps is an instruction for loading 256-bit data from the memory into the YMM register ymm0. Since the 256-bit data may contain multiple pixels, it may be part or all of the color components of multiple pixels.

[0050] Operation type analysis, the specific steps are as follows:

[0051] Determine whether it is a pixel-level calculation, such as color space conversion, image filtering, image enhancement, etc. In the AVX instruction sequence, these instructions will process the loaded 256-bit data at the element level. For example, for image brightness adjustment, vaddps can be used to perform floating-point addition operations. Taking the image data stored as floating-point numbers as an example, the code is: vaddps ymm0, ymm0, xmm1. Assume that xmm1 stores the brightness adjustment value, where the pixel data in ymm0 is added to the brightness adjustment value in xmm1 to achieve pixel-level brightness adjustment.

[0052] Determine whether it is a convolution operation of the image, which generally involves multiple vaddps and vmulps instructions, which are used to calculate the weighted sum of the convolution kernel and the data around the pixel. The sample code is as follows:

[0053] vmulps ymm1, ymm2, ymm3 / / may be the multiplication of convolution kernel elements and pixel data

[0054] vaddps ymm0, ymm0, ymm1 / / Accumulate the result

[0055] In general, during the image processing mode judgment process, when the following situations occur in the AVX code, it is judged as an image data processing scenario: a large amount of data is loaded from the memory, and the size and storage mode of this data match the image data storage mode, for example, a continuous sequence of color components; element-level operations are performed, which are usually applied to the color components of pixels, such as addition, multiplication, shift, etc., in order to modify the attributes of the pixel such as color or brightness, or operations are performed on the pixel neighborhood, such as the combined calculation of neighborhood pixel data in the convolution operation, which usually requires processing multiple components of multiple pixels.

[0056] S1.2. Determine whether it is a matrix calculation scenario. The specific steps are as follows:

[0057] Data storage format analysis, the specific steps are as follows:

[0058] Matrix elements are usually stored in consecutive memory locations, and for two-dimensional matrices, they are stored in row-major or column-major order. For example, for a matrix A, the element A[i][j] is followed by A[i][j+1] in row-major order or A[i+1][j] in column-major order. Matrix elements can be single-precision or double-precision floating-point numbers.

[0059] The AVX instruction sequence includes loading data from memory into the YMM register for operations on matrix elements. For example, for matrix multiplication operations, assuming that the data of matrices A and B are stored at the addresses of matrix_A and matrix_B, there are the following load operations:

[0060] vmovaps ymm0, [matrix_A] / / Load 256 bits of data from matrix A

[0061] vmovaps ymm1, [matrix_B] / / Load 256 bits of data from matrix B

[0062] Here, vmovaps loads 256 bits of data, which may contain multiple matrix elements, depending on the size of the matrix elements. For example, for single-precision floating point numbers, 256 bits can contain 8 elements.

[0063] Operation type analysis, the specific steps are as follows:

[0064] Matrix operations involve operations such as matrix addition, subtraction, multiplication, and transposition. In AVX, matrix multiplication involves multiple vaddps and vmulps instructions, combined with data rearrangement and accumulation operations. For example:

[0065] vmulps ymm2, ymm0, ymm1 / / matrix element multiplication

[0066] vaddps ymm3, ymm3, ymm2 / / Accumulate the result, assuming ymm3 is the accumulator

[0067] Matrix multiplication typically requires many multiply and accumulate operations because each element of the resulting matrix is ​​the sum of the products of the corresponding row and column elements of the two matrices.

[0068] Matrix calculation processing mode judgment: When the following situations are seen in AVX code, it is judged as a matrix calculation scenario: the data loaded from the memory is consistent with the matrix element storage mode, and the operation involves linear algebra operations on the matrix elements, such as multiplication, addition, and subtraction; the code contains multiple nested loops to traverse the rows and columns of the matrix and perform multiple multiplication and accumulation operations, which are typical operations of matrix operations; data is rearranged and combined to achieve correct multiplication and accumulation of matrix elements, such as rearranging and multiplying the matrix elements according to the matrix multiplication rules to obtain the elements of the result matrix.

[0069] S1.3, determine whether it is an audio data processing scenario, the specific steps are as follows:

[0070] Data storage format analysis, the specific steps are as follows:

[0071] Audio data is a one-dimensional sample array stored in memory, which can be a 16-bit integer or a 32-bit floating point number. The storage order is in chronological order, that is, sample1 sample2 sample3...

[0072] The AVX instruction sequence includes operations to load data from the address where the audio data is stored into the YMM register. For example, assuming that the audio data is stored at the audio_data address, the following are possible load operations:

[0073] vmovaps ymm0, [audio_data] / / Load 256-bit data, which may contain multiple audio samples

[0074] The vmovaps here loads 256-bit data. For 16-bit samples, it may contain multiple sample data; for 32-bit samples, it contains less data to implement parallel processing of multiple samples.

[0075] Operation type analysis, the specific steps are as follows:

[0076] Common audio processing operations include audio filtering, audio gain adjustment, audio mixing, etc. For audio gain adjustment, the vaddps or vmulps instructions are used. For example, for gain adjustment:

[0077] vmulps ymm0, ymm0, xmm1 / / Assume xmm1 stores the gain value

[0078] Here, the audio sample data in ymm0 is multiplied by the gain value in xmm1 to achieve audio gain adjustment.

[0079] Audio data processing mode judgment: When the following situations occur in the AVX code, it is judged as an audio data processing scenario: the data loaded from the memory is consistent with the audio sampling storage mode, usually one-dimensional continuous data; the operation is mainly the modification of the audio sampling, such as multiplication for gain adjustment, addition for mixing, filtering operations, etc.; the processing of continuous audio samples, and the processing process may involve sliding window operations, such as filters, which use multiple sample data for calculation, similar to convolution operations, but usually performed on one-dimensional arrays.

[0080] S2. Pre-process the data in advance by predicting the data processing mode to make it more consistent with the operation mode of NEON instructions. The specific steps are as follows:

[0081] S2.1. For image data processing scenarios, preprocessing is to reorganize the image data into a block format that is more suitable for NEON processing. For example, the pixels of each row are rearranged in groups of 16 so that each NEON register can directly load a complete set of pixel data. The specific steps are as follows:

[0082] Each pixel of an image consists of three color channels (RGB), each of which is represented by 8 bits, so one pixel occupies 24 bits. When storing, image data is usually stored by row, that is, all pixels of the first row are stored first, then the second row, and so on. To perform some pixel-based calculation operations on the image, such as pixel-level filtering or color conversion. The unoptimized situation is: when using NEON instructions to process image data, since NEON registers are usually 128 bits (can store 16 8-bit elements), reading data directly from the original storage format may result in inefficiency because the data organization does not match the NEON instruction processing method.

[0083] The image data is stored in the memory address image_data, the image width is width pixels, the height is height pixels. The storage order of each pixel is R1 G1 B1 R2 G2 B2..., where R1 represents the red component of the first pixel, and so on.

[0084] The inserted preprocessing code converts the image data from the pixel storage format to the NEON-friendly block format. r0 points to the original image data image_data, r1 points to the preprocessed image data storage location new_image_data, r2 stores the image width (in pixels), and r3 stores the image height (in pixels). The sample code is as follows:

[0085] MOV r4, #0 / / row counter

[0086] ROW_LOOP:

[0087] MOV r5, #0 / / column counter

[0088] COL_LOOP:

[0089] MUL r6, r4, r2 / / Start offset of current row

[0090] ADD r6, r6, r5 / / Current pixel offset

[0091] LDR q0, [r0, r6, LSL #1] / / Each pixel is 24 bits, and shifting left by 1 bit is equivalent to multiplying by 2. The offset is in bytes

[0092] STR q0, [r1]

[0093] LDR q1, [r0, r6, LSL #1] / / Note that the offset may need to be adjusted and calculated accurately according to the actual storage format

[0094] ADD r6, r6, r2 / / Move to the G component of the next set of pixels

[0095] STR q1, [r1, #16]

[0096] LDR q2, [r0, r6, LSL #1] / / You may also need to adjust the offset precisely

[0097] ADD r6, r6, r2 / / Move to the B component of the next set of pixels

[0098] STR q2, [r1, #32]

[0099] ADD r5, r5, #16

[0100] ADD r1, r1, #48 / / Move the storage location forward 48 bytes (3 16-byte NEON registers)

[0101] CMP r5, r2 / / Check if a row has been processed

[0102] BNE COL_LOOP

[0103] ADD r4, r4, #1

[0104] CMP r4, r3

[0105] BNE ROW_LOOP

[0106] BX LR

[0107] The NEON instructions generated by subsequent processing of the above preprocessed image data are as follows:

[0108] After preprocessing, it is more convenient to use NEON instructions to process the image data, such as performing simple brightness adjustment, that is, increasing the RGB value of each pixel by a fixed value. Assume that r0 points to the storage location new_image_data of the preprocessed image data, r1 stores the image width (in pixels), r2 stores the image height (in pixels), and r3 stores the brightness adjustment value (8 bits).

[0109] The specific code is as follows:

[0110] ADJUST_IMAGE_BRIGHTNESS:

[0111] MOV r4, #0 / / row counter

[0112] ROW_LOOP:

[0113] MOV r5, #0 / / column counter

[0114] COL_LOOP:

[0115] LDR q0, [r0]

[0116] LDR q1, [r0, #16]

[0117] LDR q2, [r0, #32]

[0118] VMOV.I8 q3, r3

[0119] VQADD.U8 q0, q0, q3

[0120] VQADD.U8 q1, q1, q3

[0121] VQADD.U8 q2, q2, q3

[0122] STR q0, [r0]

[0123] STR q1, [r0, #16]

[0124] STR q2, [r0, #32]

[0125] ADD r0, r0, #48

[0126] ADD r5, r0, #16

[0127] CMP r5, r1

[0128] BNE COL_LOOP

[0129] ADD r4, r4, #1

[0130] CMP r4, r2

[0131] BNE ROW_LOOP

[0132] BX LR

[0133] S2.2. For matrix calculation scenarios, take matrix multiplication C = A * B as an example, where matrices A, B, and C are two-dimensional arrays stored in memory, and the matrix elements are single-precision floating-point numbers (32 bits). Preprocessing is to reorganize the elements of matrices A and B into block matrices suitable for NEON instruction processing. For example, the elements of matrix A are stored in 4x4 blocks, and the elements of each block can be loaded at one time by a 128-bit NEON register. Matrix B is processed similarly. The specific steps are as follows:

[0134] Unoptimized case: Reading data directly from the original matrix storage may result in a large number of load and store operations and may not fully utilize the parallelism of NEON instructions because the storage order of matrix elements may not be suitable for processing by NEON instructions.

[0135] Assume that the elements of matrix A are stored row by row in memory address matrix_A, the elements of matrix B are stored row by row in matrix_B, and the elements of matrix C will be stored in matrix_C.

[0136] The preprocessing assembly code generated for matrix A is used to convert matrix A from row storage format to 4x4 block storage format. r0 points to the original matrix A data matrix_A, r1 points to the preprocessed matrix A data storage location new_matrix_A, r2 stores the number of rows of matrix A, and r3 stores the number of columns of matrix A. The example is as follows:

[0137] MOV r4, #0 / / row counter

[0138] ROW_LOOP_A:

[0139] MOV r5, #0 / / column counter

[0140] COL_LOOP_A:

[0141] MUL r6, r4, r3 / / Start offset of current row

[0142] ADD r6, r6, r5 / / Current element offset

[0143] LDR q0, [r0, r6, LSL #2] / / Each element is 32 bits, and a left shift of 2 bits is equivalent to multiplying by 4. The offset is in bytes

[0144] STR q0, [r1]

[0145] ADD r6, r6, r3 / / move to the next line

[0146] LDR q1, [r0, r6, LSL #2]

[0147] STR q1, [r1, #16]

[0148] ADD r6, r6, r3

[0149] LDR q2, [r0, r6, LSL #2]

[0150] STR q2, [r1, #32]

[0151] ADD r6, r6, r3

[0152] LDR q3, [r0, r6, LSL #2]

[0153] STR q3, [r1, #48]

[0154] ADD r5, r5, #4

[0155] ADD r1, r1, #64 / / Move the storage location forward 64 bytes (4 16-byte NEON registers)

[0156] CMP r5, r3 / / Check if a row has been processed

[0157] BNE COL_LOOP_A

[0158] ADD r4, r4, #1

[0159] CMP r4, r2

[0160] BNE ROW_LOOP_A

[0161] BX LR

[0162] A similar preprocessing function is used for matrix B.

[0163] The NEON instructions generated by matrix multiplication of the above preprocessed data are as follows:

[0164] After preprocessing, using NEON instructions for matrix multiplication can more efficiently utilize registers and instruction parallelism. Assume that r0 points to the preprocessed matrix A data storage location new_matrix_A, r1 points to the preprocessed matrix B data storage location new_matrix_B, r2 points to the storage location matrix_C of the result matrix C, r3 stores the number of rows of matrix A, r4 stores the number of columns of matrix A, and r5 stores the number of columns of matrix B. The specific matrix multiplication operation code is as follows:

[0165] MATRIX_MULTIPLY:

[0166] MOV r6, #0 / / row counter

[0167] ROW_LOOP_MULT:

[0168] MOV r7, #0 / / column counter

[0169] COL_LOOP_MULT:

[0170] VMOV q8, #0.0

[0171] MOV r8, #0 / / Inner loop counter

[0172] INNER_LOOP_MULT:

[0173] LDR q0, [r0]

[0174] LDR q1, [r1]

[0175] VDOT.F32 q2, q0, q1

[0176] VADD.F32 q8, q8, q2

[0177] ADD r0, r0, #64 / / Next 4x4 block of matrix A

[0178] ADD r1, r1, #64 / / Next 4x4 block of matrix B

[0179] ADD r8, r8, #1

[0180] CMP r8, r4 / / Number of columns of matrix A

[0181] BNE INNER_LOOP_MULT

[0182] STR q8, [r2]

[0183] ADD r2, r2, #16

[0184] ADD r7, r7, #1

[0185] CMP r7, r5

[0186] BNE COL_LOOP_MULT

[0187] ADD r6, r6, #1

[0188] CMP r6, r3

[0189] BNE ROW_LOOP_MULT

[0190] BX LR

[0191] S2.3, audio data processing scenario.

[0192] For audio data processing scenarios, audio data is a series of sample values, each sample is a 16-bit or 32-bit integer or floating point number, stored in an array. Preprocessing is to group audio data into blocks according to a certain number of samples (such as 8 or 16) and store them again so that the NEON register can process a group of samples at a time. The specific steps are as follows:

[0193] Unoptimized case: Similar to image and matrix data, directly processing raw stored audio data using NEON instructions may not fully utilize its parallel processing capabilities.

[0194] Assume that the audio data is stored in the memory address audio_data and each sample is a 16-bit integer.

[0195] The generated data preprocessing assembly code converts the audio data from the original storage format to a NEON-friendly block format. r0 points to the original audio data audio_data, r1 points to the storage location new_audio_data of the preprocessed audio data, and r2 stores the length of the audio data (in samples). The code is as follows:

[0196] PREPROCESS_AUDIO_DATA:

[0197] MOV r3, #0 / / Sample counter

[0198] SAMPLE_LOOP:

[0199] LDRH q0, [r0]

[0200] STRH q0, [r1]

[0201] ADD r0, r0, #16 / / Move forward 16 samples (2 bytes per sample)

[0202] ADD r1, r1, #16

[0203] ADD r3, r3, #8

[0204] CMP r3, r2

[0205] BNE SAMPLE_LOOP

[0206] BX LR

[0207] The generated NEON instructions for subsequent audio processing of preprocessed data are as follows:

[0208] Take simple audio gain adjustment as an example, that is, multiplying each sample value by a fixed gain factor. Assume that r0 points to the storage location new_audio_data of the preprocessed audio data, r1 stores the length of the audio data (in samples), and r2 stores the gain factor (16 bits):

[0209] ADJUST_AUDIO_GAIN:

[0210] MOV r3, #0 / / Sample counter

[0211] SAMPLE_LOOP_GAIN:

[0212] LDRH q0, [r0]

[0213] VMOV.I16 q1, r2

[0214] VMUL.I16 q0, q0, q1

[0215] STRH q0, [r0]

[0216] ADD r0, r0, #16

[0217] ADD r3, r3, #8

[0218] CMP r3, r1

[0219] BNE SAMPLE_LOOP_GAIN

[0220] BX LR

[0221] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A SIMD instruction conversion optimization method based on data processing mode prediction, characterized in that: The specific steps include: Step 1: If the executable file has a corresponding instruction conversion strategy list, the execution of the executable file is completed according to the instruction conversion strategy list, and this process ends; otherwise, the executable file is loaded and executed through dynamic instruction conversion; Step 2, obtain the current instruction to be converted and its operand, determine the type of the operand, record the word length of the ARM instruction as the first word length, execute step 3 when the operand is an array arranged in a linear manner, and execute step 8 when the operand is a matrix of a non-linear arrangement logic structure; Step 3, record the operand as the first operand, the size of the elements in the first operand is the first element size, and the length of the first operand is the first length; determine the data type of the first operand, when the first operand is image data, execute step 4, when the first operand is audio data, execute step 6; Step 4: If the product of the first element size and the first length is greater than the first word length, the first operand is divided into N sub-operands, and then step 5 is executed; otherwise, the first operand is kept unchanged and step 11 is executed; Step 5, establish a first loop body with a total number of loops of N, the ARM instruction with the same function as the current instruction to be converted is the first ARM instruction, set the initial value of the loop number n to 1, load the nth sub-operand into the nth ARM register, use the first ARM instruction to calculate the nth sub-operand, if n is less than N, set n to be incremented by 1 and then execute the first loop body, otherwise end the loop; convert the current instruction to be converted into the first ARM instruction sequence included in the first loop body to complete the conversion, add the corresponding relationship between the current instruction to be converted and the first ARM instruction sequence to the instruction conversion strategy list, and execute step 12; Step 6: If the product of the first element size and the first length is greater than the first word length, the first operand is divided into N sub-operands and step 7 is executed; otherwise, the first operand is kept unchanged and step 11 is executed; Step 7, establish a second loop body with a total number of loops of N, the ARM instruction with the same function as the current instruction to be converted is the second ARM instruction, set the initial value of the loop number n to 1, load the nth sub-operand into the nth ARM register, use the second ARM instruction to calculate the nth sub-operand, if n is less than N, set n to be incremented by 1 and then execute the second loop body, otherwise end the loop; convert the current instruction to be converted into the second ARM instruction sequence included in the second loop body to complete the conversion, add the corresponding relationship between the current instruction to be converted and the second ARM instruction sequence to the instruction conversion strategy list, and execute step 12; Step 8, the operands are the first operand and the second operand, the element size of the first operand and the second operand is recorded as the first element size, the number of rows P and the number of columns Q of the first operand are obtained, and the number of rows Q and the number of columns S of the second operand are obtained; Step 9, if the product of the first element size and Q is greater than the first word length, then divide each row of data of the first operand into K sub-operands, and divide each column of data of the second operand into K sub-operands; otherwise, keep the first operand and the second operand unchanged, and execute step 11; Step 10, establish a third loop body with a total number of loops of Q, the ARM instruction with the same function as the current instruction to be converted is the third ARM instruction, and the initial value of the number of loops q is 1 and q is not greater than Q; A fourth loop body with a total number of loops of K is established in the third loop body, and the qth column of the first operand and the qth row of the second operand are loaded into 2K ARM registers respectively; the third ARM instruction is used to complete the calculation of the qth column of the first operand and the qth row of the second operand, and if q is less than Q, q is incremented by 1 and the third loop body is continued to be executed, otherwise the loop is terminated; the current instruction to be converted is converted into the third ARM instruction sequence included in the third loop body to complete the conversion, and the corresponding relationship between the current instruction to be converted and the third ARM instruction sequence is added to the instruction conversion strategy list, and step 12 is executed; Step 11, select an ARM instruction with the same function as the current instruction to be converted, add the corresponding relationship between the current instruction to be converted and the ARM instruction to the instruction conversion strategy list, and execute step 12; Step 12: If the executable file has not been executed, the next instruction is selected as the current instruction to be converted and step 2 is executed; otherwise, the execution of the executable file is completed and this process ends.

2. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The method for determining the type of the operand in step 2 is: determining it according to the addressing mode of the operand, the address determined by the addressing mode is the sum of the base address and the offset, when the offset is the product of the index and the element size, the operand is determined to be an array arranged in a linear manner; when the offset is the result of the operation of two indexes, the number of columns and the element size, the operand is determined to be a matrix of a nonlinearly arranged logical structure.

3. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The method for determining the data type of the first operand in step 3 is: the functional code segment related to the current instruction to be converted is the first code segment, and the first instruction set is formed by the instructions in the first code segment. When the first instruction set includes an operation code for image processing, the first operand is determined to be image data; when the first instruction set includes an operation code for audio data processing, the first operand is determined to be audio data.

4. The SIMD instruction conversion optimization method according to claim 3, characterized in that: The first code segment is determined by binary code feature analysis.

5. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The method of dividing the first operand into N sub-operands in step 4 is: round up the ratio of the product of the first element size and the first length to the first word length as the first division number N, the length of the first N-1 sub-operands is the second length, the value of the second length satisfies the condition that it is a multiple of 3 and the product of the second length and the first element size is less than the first word length, and the length of the last sub-operand is the remaining length of the first operand.

6. The SIMD instruction conversion optimization method according to claim 1, characterized in that: In step 6, the first operand is divided into N sub-operands in the following manner: the ratio of the product of the first element size and the first length to the first word length is rounded up as the first division number N, the length of the first N-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of the first operand.

7. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The method of dividing each row of data of the first operand into K sub-operands in step 9 is: round up the ratio of the product of the first element size and Q to the first word length as the second division number K, the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each row in the first operand.

8. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The manner of dividing each column of data of the second operand in step 9 into K sub-operands is as follows: the length of the first K-1 sub-operands is the first word length, and the length of the last sub-operand is the remaining length of each column in the second operand.

9. The SIMD instruction conversion optimization method according to claim 1, characterized in that: The fourth loop body in step 10 is implemented as follows: let the initial value of the loop number k be 1 and k is not greater than K, load the kth sub-operand of the qth column of the first operand into the kth ARM register, and load the kth sub-operand of the qth row of the second operand into the K+kth ARM register; if k is less than K, let k be incremented by 1 and continue to execute the fourth loop body; otherwise, end the loop.