Design and execution method and device of multi-register virtual machine instruction set and medium

Abstract

The invention discloses a multi-register virtual machine instruction set designing and executing method and device and a medium, and the method comprises the steps that the type of an adopted register is determined based on the data type supported by a virtual machine, and the type of the register comprises a 16-bit register and / or a 32-bit register; determining an instruction operation code based on the type of the register and the function of the instruction, and forming an instruction set according to the instruction operation code; compiling and converting the program source code into an executable file, and appointing register information used by a method in a method header of each method in the executable file; and the virtual machine loads the executable file and executes the instruction in the method body in the executable file. According to the method, registers with different sizes can be adopted in the instruction set, the advantages of a 16-bit register instruction are completely reserved on resource-limited equipment, meanwhile, data types such as long, float and double are supported by using a 32-bit register extension instruction, and application programs are supported to complete more complex functions.

Description

Technical Field

[0001] The present application relates to the field of virtual machine technology, and in particular to a design and execution method, device and medium of a multi-register virtual machine instruction set. Background Art

[0002] A virtual machine is an abstract computer generated by a software application or instruction sequence executed by a processor. The virtual machine can execute the instruction set supported by the virtual machine. The instruction set is divided into two types: operand stack-based and register-based. The execution performance of a virtual machine using register instructions is usually better than that of a virtual machine using an operand stack.

[0003] In the current scheme, the register instruction set usually uses a fixed-size register, and the instruction opcode is one byte. For devices with very limited resources, the Java virtual machine currently implemented uses 16-bit registers, supports byte, short, and int types, and does not support long, float, double and other data types. Although 16-bit registers can efficiently support short type operations, for float, double, and long, which require 32-bit or even 64-bit large data types, it is advisable to use 32-bit register instructions.

[0004] On devices with very limited resources, typical applications can use the short type (a small number of business scenarios require the int type) to meet most business needs. If all instructions use 32-bit registers, the short type needs to be sign-extended to the int type. After the int operation, the operation result is converted to the short type, resulting in the compiled and converted method bytecode requiring more storage space and low execution efficiency when executed. Summary of the invention

[0005] The embodiment of the present application provides a design and execution method, device and storage medium of a multi-register virtual machine instruction set, so as to at least solve the problem in the prior art that the size of instruction set registers is fixed and difficult to adapt to various business requirements.

[0006] According to one aspect of an embodiment of the present application, a design and execution method of a multi-register virtual machine instruction set is provided, including:

[0007] Determine the data type to be supported by the virtual machine, and determine the register type of the virtual machine instruction based on the supported data type, where the register type includes a 16-bit register and / or a 32-bit register;

[0008] Based on the function of the instruction and the register type, the operation code of the instruction is determined, and the instruction set is generated according to the instruction operation code, the 16-bit register sets the standard instructions and the optimized instructions, and the 32-bit register instructions use the composite instruction code or the multiplexed instruction;

[0009] Compile and convert the program source code into an executable file, the executable file includes a method component, the method component includes all methods defined by the program, the method includes a method header and a method body, the method body includes bytecodes composed of instructions, the method header defines register information used by the method and register information corresponding to method parameters;

[0010] The virtual machine loads the executable file and executes the method in the executable file. Before executing the bytecode in the method body, it needs to read the register information used by the method in the method header and the register information corresponding to the method parameters.

[0011] In one embodiment, determining the register type to be used based on the data type supported by the virtual machine includes:

[0012] When the data type is short, int, byte, char or reference type, a 16-bit register is used;

[0013] When the data type is long, float or double, a 32-bit register is used;

[0014] In one embodiment, the int data type is represented by two consecutive 16-bit registers;

[0015] The short, byte, char and reference types are represented by a 16-bit register.

[0016] The float data type is represented by a 32-bit register;

[0017] The long and double data types are represented by two consecutive 32-bit registers.

[0018] In one embodiment, the register types in the 16-bit register instructions are all 16 bits, and the register types in the 32-bit register instructions include at least one 32-bit register.

[0019] The 16-bit register instructions include standard instructions and optimized instructions. The functions of the optimized instructions are implemented by corresponding standard instructions. Compared with standard instructions, the bytecode size generated by the optimized instructions is smaller.

[0020] In one embodiment, a method for assigning instruction opcodes includes:

[0021] In compound instruction mode, one opcode implements multiple functional operations, and the instruction contains operands that specify specific functional operations.

[0022] In one embodiment, the method of allocating instruction opcodes further includes:

[0023] Instruction multiplexing mode, the instruction opcode of the 32-bit register reuses the opcode of the optimized instruction in the 16-bit register instruction.

[0024] In one embodiment, the register numbering method 1 is that the 16-bit registers and the 32-bit registers are numbered separately and sequentially starting from 0, and each instruction must specify whether the number of bits of all register operands is 16 bits or 32 bits;

[0025] The second register numbering method is that the 16-bit registers and the 32-bit registers are numbered uniformly, the 16-bit registers are numbered sequentially starting from 0, and the 32-bit registers are numbered sequentially starting from the number subsequent to the largest 16-bit register number.

[0026] In one embodiment, the source program is compiled / converted into an executable file, wherein the executable file includes a method component, wherein the method component includes all method declarations of the program, wherein the method declaration includes a method header and a method body, wherein the method header includes method summary information, and the method body includes bytecode generated by the instruction. The method header specifies information about 16-bit registers and 32-bit registers used by the method. The method header also specifies register information corresponding to each method parameter, wherein the register information includes the number of registers, the register type, and the register number.

[0027] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to execute the design and execution method of the multi-register virtual machine instruction set through the computer program.

[0028] According to another aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the design and execution method of the above-mentioned multi-register virtual machine instruction set at runtime.

[0029] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0030] The method provided in the present application can simultaneously adopt instruction sets of registers of different sizes, fully retain the advantages of adopting 16-bit register instructions on resource-constrained devices, and at the same time, can expand instructions to support data types such as long, float, and double.

[0031] Implementing a Java virtual machine on a resource-constrained device can compile and convert a relatively compact executable file for mainstream applications that only use byte, short, or int types, which can reduce the storage space required for application installation and reduce the application installation time. Compared with 32-bit register instruction applications, less RAM space can be used when executing, and the bytecode execution efficiency is high. This application can maintain the above advantages while also supporting long, float, and double types, supporting applications to complete more complex functions, thereby increasing usage scenarios.

[0032] Furthermore, the opcode of the present application can be set as a compound instruction, solving the problem of shortage of single-byte opcodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0034] Figure 1 It is a flowchart of a design and execution method of an optional multi-register virtual machine instruction set according to an embodiment of the present application;

[0035] Figure 2 It is a schematic diagram of the structure of an optional electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] The following is combined with Figure 1 The virtual machine execution method based on the multi-register instruction set of the embodiment of the present application is described in detail. Figure 1 As shown, the method mainly includes the following steps:

[0039] S101 determines the data type to be supported by the virtual machine, and determines the register type of the virtual machine instruction based on the supported data type. The register type includes a 16-bit register and / or a 32-bit register. The 16-bit register and the 32-bit register can be numbered separately starting from 0.

[0040] This solution adopts an instruction set based on a virtual machine and supports two sizes of register types, including 16-bit registers and 32-bit registers.

[0041] In one embodiment, determining the type of register to be used based on the data type supported by the virtual machine includes:

[0042] When the data type is short, int, byte, char, or reference type, a 16-bit register is used. The int data type is represented by two consecutive 16-bit registers, and the short, byte, char, and reference types are represented by one 16-bit register.

[0043] When the data type is long, float, or double, a 32-bit register is used. The float data type is represented by one 32-bit register, and the long and double data types are represented by two consecutive 32-bit registers.

[0044] When the data type includes one or more of short, int, byte, char or reference type, and one or more of long, float or double, 16-bit registers and 32-bit registers are used. For example, in the i2s instruction to convert int to float type, the register representing the int type is a 16-bit register, and the register representing the float type is a 32-bit register. In this case, a mixed register instruction is used.

[0045] Therefore, the solution of the present application uses registers of different sizes at the same time, which fully retains the advantages of using 16-bit register instructions on resource-constrained devices while expanding instructions to support data types such as long, float, and double.

[0046] S102 determines the operation code of the instruction based on the function of the instruction and the register type, generates an instruction set according to the instruction operation code, sets standard instructions and optimized instructions for commonly used 16-bit registers, and uses composite instruction codes for uncommon 32-bit register instructions.

[0047] In one embodiment, a 16-bit register instruction, in which the register operand in the instruction is a 16-bit register, supports operations of short and int types. The present application provides an exemplary 16-bit register instruction set, wherein instructions 1-29, 31, 33, 35-39, 41-42, 45-48, 50, 56-60, 62, 64, 70, 72-73, 80-89, 102-107, 110-115, 117-119, 125-129, 142-147, 160-163, 167-169, 183-193 represent optimized instructions, and other instructions are standard instructions. The Java compiler should give priority to generating optimized instructions (if any) for specified operations. Using optimized instructions can usually significantly reduce the size of the bytecode after method compilation compared to standard instructions, thereby increasing the application download speed, reducing the size of the memory space required to save the application, and improving the execution performance of the application. The 16-bit register instructions are as follows:

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054] When the register is a 32-bit register, the instruction opcode of the 32-bit register is specified; the following table lists the instructions that need to be added to support float, double, and long data types, which is used to schematically illustrate the design scheme of 32-bit register instructions.

[0055]

[0056]

[0057]

[0058] In the case where the registers include 16-bit registers and 32-bit registers, instructions for 16-bit registers and 32-bit registers are generated according to the data type of the operation. Preferably, the present scheme adopts an instruction set of 16 / 32-bit mixed registers, and a 16-bit register instruction refers to a register in which the register operands in the instruction are all 16 bits. A 32-bit register instruction refers to an instruction that contains at least one 32-bit register and may have a 16-bit register operand, such as an i2s instruction that converts an int to a float type, in which the register representing the int type is a 16-bit register, and the register representing the float type is a 32-bit register.

[0059] In one embodiment, extended instructions often encounter the problem of shortage of single-byte opcodes. For example, the const-M / rN instruction can assign a small constant M (such as 0-4) to a register rN with a small number N (such as 0-5). This instruction only has an opcode and no operand, that is, the instruction length is one byte long, while a normal instruction to assign a byte constant to a register requires at least 3 bytes, namely, the opcode, the register number, and the constant. A large number of optimized instructions result in a 1-byte opcode, which is not conducive to supporting new functions with existing instruction set extension instructions.

[0060] This solution provides two instruction code allocation methods to solve the problem of opcode shortage:

[0061] In one implementation, a compound instruction method uses one opcode value to implement multiple infrequently used 32-bit register related operations. Usually, each operation is set to one instruction and occupies one opcode value.

[0062] For example, one instruction implements all floating-point arithmetic operations:

[0063] binop type rAA rBB rCC;

[0064] type;

[0065] 0x10 ladd;

[0066] 0x11 lsub;

[0067] 0x12 lmul;

[0068] 0x13 ldiv;

[0069] 0x14 lrem;

[0070] 0x20 fadd;

[0071] 0x21 fsub;

[0072] 0x22 fmul;

[0073] 0x23 fdiv;

[0074] 0x24 frem;

[0075] 0x30 dadd;

[0076] 0x31 dsub;

[0077] 0x32 dmul;

[0078] 0x33 ddiv;

[0079] 0x34 drem;

[0080] rAA is the register for storing the result of arithmetic operation;

[0081] rBB source operand 1;

[0082] rCC source operand 2;

[0083] Only by adopting this method, the virtual machine of the 16 / 32-bit mixed register instruction can be binary compatible with the virtual machine of the 16-bit register instruction set, which is the preferred implementation scheme of the present invention.

[0084] In another embodiment, the method of allocating 32-bit register instruction opcodes includes: multiplexing instruction code method:

[0085] The instruction opcodes of the 32-bit register are reused with the opcodes of the optimized instructions in the 16-bit register instructions. For these reused instruction codes, the bytecode interpreter of the virtual machine needs to determine whether the instruction mode of the current virtual machine execution method is the 16-bit register mode or the 16 / 32-bit register mixed mode. In the 16-bit register mode, the 16-bit optimized instructions are executed, and in the 16 / 32-bit register mixed mode, the 32-bit register instructions are executed.

[0086] Example implementation of multiplexing instruction code:

[0087] binop rAArBB rCC;

[0088]

[0089] rAA is the register for storing the result of arithmetic operation;

[0090] rBB source operand 1;

[0091] rCC source operand 2;

[0092] After determining the opcode and the corresponding register type based on the above rules, an instruction set is generated. The instruction set of the present application can be generated based on 16-bit registers and / or 32-bit registers. And the use of composite opcodes or multiplexed opcodes can solve the problem of shortage of single-byte opcodes.

[0093] Optionally, the present solution proposes two register numbering methods, which are a separate numbering method and a unified numbering method.

[0094] In the case of a 16-bit register or a 32-bit register, the registers are numbered based on a separate numbering scheme. The first register number for both types of registers is 0. The separate numbering scheme requires that each instruction with a register operand explicitly specify the type of each register operand, whether it is 16-bit or 32-bit, and can only be one of them.

[0095] In the case where the registers are a mixture of 16-bit registers and 32-bit registers, the registers are numbered based on a unified numbering method; wherein the number of each 32-bit register is greater than the number of any 16-bit register.

[0096] Each register is represented by a byte. 16-bit registers and 32-bit registers are numbered uniformly. 16-bit registers are numbered with small values, starting from 0, and 32-bit registers are numbered with large values, that is, the number of each 32-bit register is greater than the number of any 16-bit register. The first 32-bit register number can be the maximum 16-bit register number plus 1 (or other values ​​greater than 1). The unified numbering method allows certain instructions with register operands, in which the register type can be 16 bits or 32 bits, distinguished by the size of the number.

[0097] S103 compiles the program source code and converts it into an executable file. The executable file includes a method component. The method component includes all methods defined by the program. The method includes a method header and a method body. The method body includes bytecodes composed of instructions. The method header defines register information used by the method and register information corresponding to method parameters.

[0098] In an executable file, the method component includes the execution information of all defined methods. Each method includes a method header that describes the summary information of the method.

[0099] The following information needs to be specified in the method header:

[0100] Number of registers: Specifies the number of 16-bit registers and 32-bit registers required by this method.

[0101] If the method defines formal parameters, the following information needs to be specified:

[0102] Register information corresponding to method parameters. Since the parameter type of a method can be any of short, int, long, float, and double, and short uses one 16-bit register number, int uses two consecutively numbered 16-bit registers, float uses one 32-bit register number, and long and double use two consecutively numbered 32-bit registers. That is, the registers used by the parameters are of different types, and the register numbers cannot be guaranteed to be continuous. Therefore, it is necessary to specify the register number and type used by the parameters in the method header so that when the instruction interpreter of the virtual machine executes the method call instruction, it can obtain the register information corresponding to the method parameters and correctly copy the register values ​​corresponding to the actual parameters of the calling method to the corresponding parameter registers.

[0103] S104 The virtual machine loads the executable file and executes the method in the executable file. Before executing the bytecode in the method body, it needs to read the register information used by the method in the method header and the register information corresponding to the method parameters (if any).

[0104] Furthermore, the virtual machine will parse the format of the executable file and determine that it is designed for this operating system. The executable file is loaded into the virtual machine's memory. The entry point of the program is found, which is where the program begins to execute. The instructions in the program are executed in order. The virtual machine will manage the resources required for the program to run, such as CPU time, memory, etc.

[0105] By adopting the technical solution of this application, the following good effects can be achieved:

[0106] By implementing a Java virtual machine on a resource-constrained device, for mainstream applications that only use byte, short, or int types, a more compact executable file can be compiled and converted, which can reduce the storage space and time required for application installation. Compared with 32-bit register instructions, less RAM space is required for application execution, and the bytecode execution efficiency is high.

[0107] This application can maintain the above advantages while also supporting long, float, and double types, allowing applications to complete more complex functions, thereby increasing usage scenarios.

[0108] The present application can also solve the problem of shortage of single-byte operation codes.

[0109] According to another aspect of an embodiment of the present application, an electronic device corresponding to the virtual machine execution method based on a multi-register instruction set provided in the aforementioned embodiment is also provided to execute the aforementioned virtual machine execution method based on a multi-register instruction set.

[0110] Please refer to Figure 2, which shows a schematic diagram of an electronic device provided by some embodiments of the present application. Figure 2 As shown, the electronic device includes: a processor 200, a memory 201, a bus 202 and a communication interface 203, and the processor 200, the communication interface 203 and the memory 201 are connected via the bus 202; the memory 201 stores a computer program that can be run on the processor 200, and when the processor 200 runs the computer program, it executes the virtual machine execution method based on a multi-register instruction set provided in any of the aforementioned embodiments of the present application.

[0111] The memory 201 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory. The communication connection between the system network element and at least one other network element is realized through at least one communication interface 203 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.

[0112] The bus 202 may be an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. Among them, the memory 201 is used to store programs, and the processor 200 executes the program after receiving the execution instruction. The virtual machine execution method based on a multi-register instruction set disclosed in any implementation of the aforementioned embodiment of the present application may be applied to the processor 200, or implemented by the processor 200.

[0113] The processor 200 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit or software instructions in the processor 200. The above processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a readily available programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware decoding processor to be executed, or the hardware and software modules in the decoding processor can be executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 201, and the processor 200 reads the information in the memory 201 and completes the steps of the above method in combination with its hardware.

[0114] The electronic device provided in the embodiment of the present application and the virtual machine execution method based on a multi-register instruction set provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented therein.

[0115] According to another aspect of the embodiments of the present application, a computer-readable storage medium corresponding to the virtual machine execution method based on a multi-register instruction set provided in the aforementioned embodiments is also provided, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it will execute the virtual machine execution method based on a multi-register instruction set provided in any of the aforementioned embodiments.

[0116] It should be noted that examples of computer-readable storage media may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0117] The computer-readable storage medium provided in the above-mentioned embodiments of the present application and the virtual machine execution method based on a multi-register instruction set provided in the embodiments of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0118] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A design and execution method of a multi-register virtual machine instruction set, characterized in that: include: Determine the data type to be supported by the virtual machine, and determine the register type of the virtual machine instruction based on the supported data type, where the register type includes a 16-bit register and / or a 32-bit register; Based on the function of the instruction and the register type, the operation code of the instruction is determined, and the instruction set is generated according to the instruction operation code, the 16-bit register sets the standard instructions and the optimized instructions, and the 32-bit register instructions use the composite instruction code or the multiplexed instruction; Compile and convert the program source code into an executable file, the executable file includes a method component, the method component includes all methods defined by the program, the method includes a method header and a method body, the method body includes bytecodes composed of instructions, the method header defines register information used by the method and register information corresponding to method parameters; The virtual machine loads the executable file and executes the method in the executable file. Before executing the bytecode in the method body, it needs to read the register information used by the method in the method header and the register information corresponding to the method parameters.

2. The method according to claim 1, characterized in that The register type used is determined based on the data types supported by the virtual machine, including: When the data type is short, int, byte, char or reference type, a 16-bit register is used; In the case where the data type is long, float, or double, a 32-bit register is used.

3. The method according to claim 2, characterized in that The int data type is represented by two consecutive 16-bit registers; The short, byte, char and reference types are represented by a 16-bit register; The float data type is represented by a 32-bit register; The long and double data types are represented by two consecutive 32-bit registers.

4. The method according to claim 1, characterized in that: The register types in the 16-bit register instructions are all 16 bits, and the register types in the 32-bit register instructions include at least one 32-bit register; The 16-bit register instructions include standard instructions and optimized instructions. The functions of the optimized instructions are implemented by corresponding standard instructions. Compared with standard instructions, the bytecode size generated by the optimized instructions is smaller.

5. The method according to claim 4, characterized in that A method for assigning instruction opcodes, comprising: In compound instruction mode, one opcode implements multiple functional operations, and the instruction contains operands that specify specific functional operations.

6. The method according to claim 4, characterized in that The method of assigning instruction opcodes also includes: Instruction multiplexing mode, the instruction opcode of the 32-bit register reuses the opcode of the optimized instruction in the 16-bit register instruction.

7. The method according to claim 1, characterized in that Register numbering method 1: the 16-bit registers and 32-bit registers are numbered separately starting from 0, and each instruction must specify whether the number of bits of all register operands is 16 bits or 32 bits; The second register numbering method is that the 16-bit registers and the 32-bit registers are numbered uniformly, the 16-bit registers are numbered sequentially starting from 0, and the 32-bit registers are numbered sequentially starting from the number subsequent to the largest 16-bit register number.

8. The method according to claim 1, characterized in that The source program is compiled / converted into an executable file, wherein the executable file includes a method component, wherein the method component includes all method declarations of the program, wherein the method declaration includes a method header and a method body, wherein the method header includes method summary information, and the method body includes bytecode generated by the instruction; the method header specifies information about 16-bit registers and 32-bit registers used by the method; the method header also specifies register information corresponding to each method parameter, wherein the register information includes the number of registers, the register type, and the register number.

9. An electronic device, characterized in that: It comprises a processor and a memory storing program instructions, wherein the processor is configured to execute the design and execution method of a multi-register virtual machine instruction set according to any one of claims 1 to 8 when executing the program instructions.

10. A computer-readable medium, characterized in that Computer-readable instructions are stored thereon, and the computer-readable instructions are executed by a processor to implement a design and execution method of a multi-register virtual machine instruction set as described in any one of claims 1 to 8.

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