PCIE (Peripheral Component Interface Express) link stability test method and device, equipment and storage medium

Abstract

The invention relates to a PCIE link stability test method and device, equipment and a storage medium, and relates to the technical field of chip design verification. The method comprises the following steps: acquiring equipment information of tested equipment, wherein the equipment information comprises an equipment characteristic set; cyclically executing a PCIE link test process for a preset number of times on the tested equipment to obtain a plurality of equipment target characteristic sets; matching the plurality of equipment target characteristic sets with the equipment characteristic set to obtain a matching result; and obtaining a stability test result according to a matching result. The PCIE link stability test method and device have the technical effect that the PCIE link stability test is more comprehensive.

Description

Technical Field

[0001] The present application relates to the field of chip design verification technology, and in particular to a PCIE link stability testing method, device, equipment and storage medium. Background Art

[0002] PCIE, the full name of which is PCI Express (Peripheral Component Interconnect Express), is a high-speed serial computer expansion bus standard, which is widely used in servers, data centers, high-performance computing and other fields. PCIE link stability test refers to a series of tests on the data transmission link of the PCIE interface, which aims to verify and ensure that the link can maintain stable and reliable data transmission performance under various conditions.

[0003] As data processing requirements increase, the stability of PCIE links has an increasingly important impact on system performance. In the prior art, a stress test method is usually used to detect the performance of PCIE links, by performing multiple system restarts and judging the stability of PCIE links based on whether devices can be enumerated after the restarts.

[0004] Restarting the system and judging the stability of the link based on a single result of whether the device can be enumerated after the restart will result in an incomplete stability test of the PCIE link. Summary of the invention

[0005] In order to perform a more comprehensive PCIE link stability test, the present application provides a PCIE link stability test method, device, equipment and storage medium.

[0006] In a first aspect, the present application provides a PCIE link stability testing method, which adopts the following technical solution:

[0007] Acquire device information of the device under test, wherein the device information includes a device characteristic set;

[0008] cyclically executing a preset number of PCIE link test procedures on the device under test to obtain a plurality of device target characteristic sets;

[0009] Matching the device target characteristic sets with the device characteristic set to obtain a matching result;

[0010] A stability test result is obtained according to the matching result.

[0011] Through the above technical solution, during the PCIE link testing process, in addition to the conventional test of whether the device can be enumerated after the system restart, the number of tests is increased and the enumerated device information is compared, making the PCIE link stability test more comprehensive.

[0012] In a specific implementation scheme, the PCIE link test process includes:

[0013] Automatically reset and establish a PCIE link with the device under test;

[0014] The device to be tested is enumerated a preset number of times through the PCIE link to obtain a plurality of device target characteristic sets.

[0015] Through the above technical solution, in addition to detecting whether the target device can be enumerated during the enumeration process, the device characteristics of the target device are also obtained, and the stability of the PCIE link is detected by verifying the device characteristics, making the stability test of the PCIE link more comprehensive.

[0016] In a specific implementation scheme, the enumeration step includes:

[0017] Perform a test data packet acquisition step according to the device characteristic set to obtain a plurality of test data packets;

[0018] Cache and parse a number of the test data packets to obtain a device target characteristic set.

[0019] Through the above technical solution, by sending and receiving data packets, all test data packets are cached for analysis, so that the device characteristics can be obtained more accurately and comprehensively.

[0020] In a specific implementation scheme, the device characteristic set includes several device characteristics, and the test data packet acquisition step includes:

[0021] Sending data packets to each layer of the PCIE link according to the device characteristics;

[0022] The data packets are used to obtain the data of each layer of the PCIE link to obtain the test data packets of the device characteristics.

[0023] Through the above technical solution, data of each layer of the PCIE link is obtained to achieve full link coverage (including physical layer, data link layer, transaction layer and application layer) in the PCIE link, thereby improving the comprehensiveness of the test and the efficiency of the link stability test.

[0024] In a specific implementation scheme, when caching and parsing the plurality of test data packets, the method further includes:

[0025] The test location information is recorded so that the test location information corresponds to the test data packet one by one.

[0026] Through the above technical solution, the test location information is recorded. When the test result fails, a targeted inspection can be performed based on the test location information to improve the efficiency of PCIE link error inspection.

[0027] In a specific possible implementation scheme, matching the plurality of device target characteristic sets with the device characteristic set to obtain a matching result includes:

[0028] Determining whether the device target characteristic sets and the device characteristic set are completely consistent;

[0029] If they are completely consistent, the matching result is determined to be passed and the matching result is obtained;

[0030] Otherwise, the matching result is determined to be failed, and the matching result is obtained and an erroneous test data packet with inconsistent device target characteristics is searched.

[0031] Through the above technical solution, if the PCIE link is stable and the transmitted data is not wrong, the device characteristics obtained by multiple checks should be consistent with the device characteristics specified by the device under test. By testing a large number of device characteristics and matching them, the stability of the PCIE link can be more comprehensively tested.

[0032] In a specific implementation manner, obtaining the stability test result according to the matching result includes:

[0033] Determine whether the matching result is passed;

[0034] If the matching result is passed, the stability test result is determined to be passed, and the stability test result is obtained;

[0035] Otherwise, the stability test result is determined to be failed, the stability test result is obtained and the error data packet and the test position information corresponding to the error data packet are displayed.

[0036] Through the above technical solution, in addition to obtaining the test results, the method of the present application can also obtain the test location information, which is convenient for quickly locating and solving PCIE link problems.

[0037] In a second aspect, the present application provides a PCIE link stability testing device, which adopts the following technical solution: the device comprises:

[0038] A device information acquisition module, used to acquire device information of the device under test, wherein the device information includes a device characteristic set;

[0039] A PCIE link test module, used for cyclically executing a preset number of PCIE link test procedures on the device under test to obtain a plurality of device target characteristic sets;

[0040] A matching module, used for matching a plurality of the device target characteristic sets with the device characteristic set to obtain a matching result;

[0041] The test result generating module is used to obtain the stability test result according to the matching result.

[0042] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and executes a PCIE link stability test method such as the above-mentioned one.

[0043] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute the above-mentioned PCIE link stability testing method.

[0044] In summary, this application has the following beneficial technical effects:

[0045] (1) In the process of testing the stability of the PCIE link, in addition to the conventional test of whether the device can be enumerated after the system restart, the number of loop tests is increased and the enumerated device information is compared, making the stability test of the PCIE link more comprehensive.

[0046] (2) During the PCIE link stability test, data at each layer of the PCIE link is obtained by sending and receiving data packets, achieving full coverage of the PCIE link (including the physical layer, data link layer, transaction layer, and application layer), thereby improving the comprehensiveness of the test and the efficiency of the link stability test.

[0047] (3) Completing the PCIE link stability test not only obtains the test results, but also obtains the test location information, which facilitates the rapid location and resolution of PCIE link problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a flow chart of the PCIE link stability testing method in an embodiment of the present application.

[0049] Figure 2 It is a structural block diagram of the PCIE link stability testing method in an embodiment of the present application.

[0050] Reference numerals: 201, device information acquisition module; 202, PCIE link test module; 203, matching module; 204, test result generation module. DETAILED DESCRIPTION

[0051] The following is combined with Figure 1-2 This application is described in further detail.

[0052] An embodiment of the present application discloses a PCIE link stability testing method, which is used to perform a more comprehensive PCIE link stability test.

[0053] PCIE, the full name of which is PCI Express (Peripheral Component Interconnect Express), is a high-speed serial computer expansion bus standard, which is widely used in servers, data centers, high-performance computing and other fields. PCIE link stability test refers to a series of tests on the data transmission link of the PCI Express (abbreviated as PCIE) interface, which aims to verify and ensure that the link can maintain stable and reliable data transmission performance under various conditions.

[0054] As data processing requirements increase, the stability of PCIE links has an increasingly important impact on system performance. In the prior art, a stress test method is usually used to detect the performance of PCIE links, by performing multiple system restarts and judging the stability of PCIE links based on whether devices can be enumerated after the restarts.

[0055] Restarting the system and judging the stability of the link based on a single result of whether the device can be enumerated after the restart will result in an incomplete stability test of the PCIE link.

[0056] Therefore, the present application proposes a PCIE link stability testing method, which is used to perform a more comprehensive PCIE link stability test.

[0057] like Figure 1 As shown, the method specifically comprises the following steps:

[0058] S10, obtaining device information of the device under test, where the device information includes a device feature set.

[0059] Specifically, this step is the preparation for the PCIE link stability test. The device information of the device under test is usually recorded in the manual of the device under test. The device information includes a device feature set, that is, several device features, such as manufacturer ID, device ID, device command information, device status, device version ID and other device features.

[0060] S20, cyclically executing the PCIE link test process for a preset number of times on the device under test to obtain a plurality of device target characteristic sets.

[0061] Specifically, the PCIE link test process includes system reset and restart, enumeration of the device under test, and obtaining the device characteristics of the device under test. The number of system resets and restarts and the number of times the device under test is enumerated in each restart and reset are set according to the stability test requirements of the device under test. After each enumeration, the device target characteristic set corresponding to the device characteristic set will be tested. After the cycle test is completed, several device target characteristic sets will be obtained.

[0062] S30, matching a plurality of device target characteristic sets with device characteristic sets to obtain a matching result.

[0063] Specifically, if the PCIE link is stable and the transmitted data is not wrong, the device characteristics obtained after multiple checks should be consistent with the device characteristics specified by the device under test. Match several device target characteristic sets with the device characteristic sets to obtain matching results to see if the matching is consistent.

[0064] S40, obtaining a stability test result according to the matching result.

[0065] Specifically, if the target feature sets of several devices are consistent with the device feature sets obtained before the test, it means that the PCIE link is stable, there is no error in the transmitted data, and the stability test passes; if the target feature sets of several devices are inconsistent with the device feature sets obtained before the test, it means that the PCIE link is unstable and the stability test fails.

[0066] In the process of testing the stability of the PCIE link, in addition to the conventional test of whether the device can be enumerated after the system restart, the number of loop tests is increased and the enumerated device information is compared, making the stability test of the PCIE link more comprehensive.

[0067] In one embodiment, in order to better perform the PCIE link test, the PCIE link test process can be specifically performed as follows:

[0068] First, automatically reset and establish a PCIE link with the device under test. Specifically, set the number of system resets and restarts according to the stability test requirements of the device under test. Each reset and restart will automatically reset the system and establish a PCIE link with the device under test. If the automatic reset system fails or the establishment of the PCIE link with the device under test fails, the next test cannot be performed, that is, the stability test of the PCIE link fails. In the automatic reset system, the system reset result will be recorded. The information in the system reset result mainly includes whether the system reset is successful, the number of system resets, and other information, such as the first system reset is successful; when establishing a PCIE link with the device under test, the link training result will be recorded. The information in the link training result mainly includes the link state machine status, link data packets, etc., such as abnormal link state machine LTSSM state and abnormal data packets.

[0069] Then, the device under test is enumerated a preset number of times through the PCIE link to obtain several device target feature sets. Specifically, the number of times the device under test is enumerated in each restart and reset is set according to the stability test requirements of the device under test, and the device under test is enumerated multiple times. On the one hand, it is detected whether the device is enumerated; on the other hand, the device target feature set of the device under test is obtained through enumeration, and several device target feature sets are obtained after cyclic enumeration.

[0070] In addition to detecting whether the target device can be enumerated during the enumeration process, the device characteristics of the target device are also obtained. The stability of the PCIE link is detected by verifying the device characteristics, making the stability test of the PCIE link more comprehensive.

[0071] In one embodiment, in order to better perform the PCIE link test, the enumeration step can be specifically performed as follows:

[0072] First, the test data packet acquisition step is performed according to the device characteristic set to obtain several test data packets. Specifically, to match the device characteristics that have been obtained, it is necessary to test and obtain the test characteristics corresponding to the device characteristics. According to the device characteristic set, several test data packets are obtained by sending and receiving data packets, and one test data packet corresponds to one device characteristic.

[0073] Then, several test data packets are cached and parsed to obtain a device target feature set. Specifically, several data packets are cached first, where one test data packet corresponds to a device feature. Several device features are obtained through data parsing, and the sets are sorted to obtain a device target feature set.

[0074] By sending and receiving data packets, all test data packets are cached for analysis, making the device characteristics more accurate and comprehensive.

[0075] In one embodiment, the device characteristic set includes several device characteristics, and the test data packet acquisition step can be specifically performed as follows:

[0076] First, data packets are sent to each layer of the PCIE link according to the device characteristics. Specifically, for example, to obtain the device ID, DLLP packets and TLP packets are sent to each layer of the PCIE link to obtain relevant data of the device ID.

[0077] Then, the data of each layer of the PCIE link is obtained through the data packet to obtain the test data packet of the device characteristics. Specifically, the DLLP packet and the TLP packet collect the relevant data about the device ID of each layer of the PCIE link to obtain the test data packet.

[0078] By acquiring data from each layer of the PCIE link, the full link (including the physical layer, data link layer, transaction layer and application layer) in the PCIE link is covered, thereby improving the comprehensiveness of the test and the efficiency of the link stability test.

[0079] In one embodiment, in order to better check the problem of the PCIE link, when caching and parsing several test data packets, the following steps may also be performed:

[0080] The test location information is recorded so that the test location information and the test data packet correspond one to one. Specifically, the test location information is recorded. The test location information mainly includes the restart order, enumeration order, etc. For example, a test data packet is generated during the third enumeration of the device ID in the second restart.

[0081] Record the test location information. When the test result fails, you can conduct targeted inspections based on the test location information to improve the efficiency of PCIE link error inspection.

[0082] In one embodiment, the step of matching a plurality of device target characteristic sets with device characteristic sets to obtain a matching result may be specifically performed as follows:

[0083] Determine whether several device target characteristic sets and device characteristic sets are completely consistent. Specifically, compare each device target characteristic set with the device characteristic set to see if they are completely consistent. If they are completely consistent, the matching result is determined to be passed, and a matching result is obtained. Specifically, when the compared characteristics are completely consistent one by one, the matching is passed; otherwise, the matching result is determined to be failed, and the matching result is obtained and the error test data packet of the inconsistent device target characteristic is found. Specifically, if the compared characteristics are inconsistent, the matching is failed, the inconsistent matching characteristics are found, and the error test data packet of the inconsistent device characteristic is found and recorded.

[0084] It should be noted that the prerequisite for obtaining the device target feature set is that the system reset is successful and the PCIE link is successfully established. Enumeration can only be performed after the system reset is successful and the PCIE link is successfully established. If the system reset is unsuccessful or the PCIE link is unsuccessful, the stability test will fail, and the information in the previous system reset result and link training result will be displayed.

[0085] In one embodiment, the step of obtaining the stability test result according to the matching result may be specifically performed as follows:

[0086] Determine whether the matching result is passed. If the matching result is passed, the stability test result is determined to be passed, and the stability test result is obtained. Specifically, the stability test result can be determined only when the link is successfully established and all the target characteristics of the enumerated devices are matched. The ability to obtain the target characteristics of the devices means that the PCIE link is successfully established. If the matching result is passed, the stability test result is determined to be failed, and the stability test result is obtained and the error data packet and the test position information corresponding to the error data packet are displayed.

[0087] In addition to obtaining test results, the present application method can also obtain test location information, which is convenient for quickly locating and solving PCIE link problems.

[0088] Based on the above method, the embodiment of the present application also discloses a PCIE link stability testing device. The device includes the following modules:

[0089] The device information acquisition module 201 is used to acquire the device information of the device under test, where the device information includes a device characteristic set;

[0090] The PCIE link test module 202 is used to cyclically execute a preset number of PCIE link test procedures on the device under test to obtain a plurality of device target characteristic sets;

[0091] A matching module 203, used to match a plurality of device target characteristic sets with device characteristic sets to obtain a matching result;

[0092] The test result generating module 204 is used to obtain the stability test result according to the matching result.

[0093] In one embodiment, the PCIE link test module 202 is specifically used to automatically reset and establish a PCIE link with the device under test; and obtain a plurality of device target characteristic sets by performing a preset number of enumeration steps on the device under test through the PCIE link.

[0094] In one embodiment, the PCIE link test module 202 is specifically used to perform a test data packet acquisition step according to a device characteristic set to obtain a plurality of test data packets; cache and parse the plurality of test data packets to obtain a device target characteristic set.

[0095] In one embodiment, the PCIE link test module 202 is specifically used to send data packets to each layer of the PCIE link according to device characteristics; obtain data of each layer of the PCIE link through the data packets to obtain a test data packet of the device characteristics.

[0096] In one embodiment, the PCIE link test module 202 is specifically used to record the test location information so that the test location information and the test data packet correspond one to one.

[0097] In one embodiment, the matching module 203 is specifically used to determine whether several device target characteristic sets and device characteristic sets are completely consistent; if they are completely consistent, the matching result is determined to be passed and a matching result is obtained; otherwise, the matching result is determined to be failed, a matching result is obtained and an erroneous test data packet of inconsistent device target characteristics is found.

[0098] In one embodiment, the test result generation module 204 is specifically used to determine whether the matching result is passed; if the matching result is passed, the stability test result is determined to be passed, and the stability test result is obtained; otherwise, the stability test result is determined to be failed, and the stability test result is obtained and the error data packet and the test location information corresponding to the error data packet are displayed.

[0099] The embodiment of the present application also discloses a computer device.

[0100] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute the above-mentioned PCIE link stability testing method.

[0101] The embodiment of the present application also discloses a computer-readable storage medium.

[0102] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and execute a PCIE link stability test method such as the above-mentioned one. The computer-readable storage medium includes, for example: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and other media that can store program codes.

Claims

1. A PCIE link stability testing method, characterized in that: The method is based on a device under test containing device information, and the method comprises: Acquire device information of the device under test, wherein the device information includes a device characteristic set; cyclically executing a preset number of PCIE link test procedures on the device under test to obtain a plurality of device target characteristic sets; Matching the device target characteristic sets with the device characteristic set to obtain a matching result; A stability test result is obtained according to the matching result.

2. The method according to claim 1, characterized in that: The PCIE link test process includes: Automatically reset and establish a PCIE link with the device under test; The device to be tested is enumerated a preset number of times through the PCIE link to obtain a plurality of device target characteristic sets.

3. The method according to claim 2, characterized in that: The enumeration step comprises: Perform a test data packet acquisition step according to the device characteristic set to obtain a plurality of test data packets; Cache and parse a number of the test data packets to obtain a device target characteristic set.

4. The method according to claim 3, characterized in that: The device characteristic set includes a plurality of device characteristics, and the test data packet acquisition step includes: Sending data packets to each layer of the PCIE link according to the device characteristics; The data packets are used to obtain the data of each layer of the PCIE link to obtain the test data packets of the device characteristics.

5. The method according to claim 3, characterized in that: When caching and parsing the plurality of test data packets, the method further includes: The test location information is recorded so that the test location information corresponds to the test data packet one by one.

6. The method according to claim 5, characterized in that: The matching of the plurality of device target characteristic sets with the device characteristic set to obtain a matching result includes: Determining whether the device target characteristic sets and the device characteristic set are completely consistent; If they are completely consistent, the matching result is determined to be passed and the matching result is obtained; Otherwise, the matching result is determined to be failed, and the matching result is obtained and an erroneous test data packet with inconsistent device target characteristics is searched.

7. The method according to claim 6, characterized in that: Obtaining the stability test result according to the matching result includes: Determine whether the matching result is passed; If the matching result is passed, the stability test result is determined to be passed, and the stability test result is obtained; Otherwise, the stability test result is determined to be failed, the stability test result is obtained and the error data packet and the test position information corresponding to the error data packet are displayed.

8. A PCIE link stability testing device, characterized in that: The device comprises: A device information acquisition module (201), used to acquire device information of the device under test, wherein the device information includes a device characteristic set; A PCIE link test module (202) is used to cyclically execute a preset number of PCIE link test procedures on the device under test to obtain a plurality of device target characteristic sets; A matching module (203), used for matching a plurality of the device target characteristic sets with the device characteristic set to obtain a matching result; A test result generating module (204) is used to obtain a stability test result according to the matching result.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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