Cache verification method based on multi-core processor architecture, electronic equipment and storage medium

Abstract

The invention provides a cache verification method based on a multi-core processor architecture, electronic equipment and a storage medium, the cache verification method comprises the following steps: aligning an address of a main memory according to an address of a cache unit, and allocating a space for the cache unit in the main memory; the allocation space of the cache unit is equally divided into a first part and a second part, a DMA controller is used for executing write operation on the first part, and meanwhile a CPU processor is used for executing write operation on the second part; and comparing the current data in the allocation space to verify the consistency of the cache units. According to the method, testing and verification can be synchronously carried out in the initial stage of chip design, problems can be found more timely, the testing period is shorter, and the positions of the problems can be located more quickly; the test efficiency is higher, the problem is found more quickly, and the user experience is improved.

Description

Technical Field

[0001] The present application relates to the field of processor architecture technology, and in particular to a cache verification method, electronic device and storage medium based on a multi-core processor architecture. Background Art

[0002] CPU Cache, or processor cache, is a storage function module inside a chip that can be used to reduce the average time required for the CPU to access the main memory. The CPU's computing speed is much faster than the CPU's reading and writing speed of the main memory. If data is read and written directly from the main memory, the CPU's computing efficiency will be greatly reduced, and the CPU often needs to read and write the same data block repeatedly, so the existence of cache can improve the CPU's computing efficiency.

[0003] Cache Line is the smallest data transmission unit between cache and main memory. When the CPU reads a byte of data from the main memory, if the data is not in the cache, that is, a cache miss, the cache controller will fetch a cache unit of data from the main memory to the cache, and then the CPU will fetch the data from the cache; if the data is in the cache, it is a cache hit, and the CPU will fetch the data directly from the cache. Usually, the size of a cache unit is 64 bytes. The purpose of doing this is to improve the access efficiency of data, because adjacent data is most likely to be accessed quickly.

[0004] During the research process of conceiving and forming this application, the applicant discovered at least the following problem: in a multi-core architecture, after reading the main memory data into the cache copy, if the main memory data changes, the original cache copy data is inconsistent with the main memory data, and a multi-core cache data consistency problem will occur. Summary of the invention

[0005] In order to alleviate the above problems, the present application provides a cache verification method based on a multi-core processor architecture, comprising: In response to system initialization, aligning the address of the main memory according to the address of the cache unit, and allocating space in the main memory for the cache unit; Divide the allocated space of the cache unit into a first part and a second part equally, and use a DMA controller to perform a write operation on the first part, and use a CPU processor to perform a write operation on the second part; The current data in the allocated space is compared to verify the consistency of the cache unit.

[0006] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize the multi-core operating environment of the CPU processor.

[0007] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize main memory, DMA controller and UART serial port, and randomly store data in main memory address.

[0008] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: A cache space of a preset size is allocated in the main memory, and the cache space is divided into a first number of shares, where the first number is an even number.

[0009] Optionally, the step of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part comprises: When each DMA controller performs a write operation on the first part, it writes one byte to each cache space in turn, and traverses all cache spaces of the first part.

[0010] Optionally, the step of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part comprises: When each CPU processor performs a write operation on the second part, it writes one byte to each cache space in turn, and traverses all cache spaces of the second part.

[0011] Optionally, the step of comparing the current data in the allocated space to verify the consistency of the cache unit includes: Compare the current data of all addresses in the allocated main memory space to see if they are the written data; If the data comparison is wrong, the test ends to find the problem.

[0012] Optionally, the step of comparing the current data in the allocated space to verify the consistency of the cache unit further includes: If the data comparison is correct, the next test cycle will be entered until the preset number of tests is reached.

[0013] The present application also provides an electronic device, the electronic device comprising a processor and a memory; The memory stores a computer program, and when the computer program is executed by the processor, the steps of the cache verification method based on the multi-core processor architecture as described above are implemented.

[0014] The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the cache verification method based on a multi-core processor architecture as described above are implemented.

[0015] The present application provides a cache verification method based on a multi-core processor architecture, which allocates space to the cache unit in the main memory by aligning the address of the main memory according to the address of the cache unit; equally divides the allocated space of the cache unit into a first part and a second part, and uses a DMA controller to perform a write operation on the first part, and uses a CPU processor to perform a write operation on the second part; compares the current data in the allocated space to verify the consistency of the cache unit. Testing and verification can be performed simultaneously in the initial stage of chip design, problems can be discovered more timely, the test cycle is shorter, and the location of the problem can be located faster; the test efficiency is higher, problems are discovered faster, and the user experience is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0017] Figure 1 This is a flow chart of a cache verification method based on a multi-core processor architecture according to an embodiment of the present application.

[0018] Figure 2 A schematic diagram of a quad-core processor architecture according to an embodiment of the present application.

[0019] Figure 3 A schematic diagram of the operation logic of an electronic device according to an embodiment of the present application.

[0020] The realization of the purpose, functional features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. The above-mentioned drawings have shown clear embodiments of this application, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0021] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0022] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0023] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0024] First embodiment This application provides a cache verification method based on a multi-core processor architecture. Figure 1 This is a flow chart of a cache verification method based on a multi-core processor architecture according to an embodiment of the present application.

[0025] like Figure 1 As shown, in one embodiment, a cache verification method based on a multi-core processor architecture includes: S10: In response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and space is allocated to the cache unit in the main memory.

[0026] Address alignment means that the storage of data in the memory complies with certain rules. For example, in a 32-bit system, common alignment methods include byte alignment (8bit), halfword alignment (16bit), and word alignment (32bit), which are aligned to consecutive addresses, even addresses, and addresses divisible by 4, respectively. For example, in a 32-bit system, integer and floating-point data are usually stored in 4-byte alignment, which means that the starting address of data storage must be a multiple of 4.

[0027] Address alignment is a time-space trade-off in CPU design, using a space-for-time strategy. The main purpose is to quickly read a given variable. If the data is not correctly aligned, the CPU reading data from a non-aligned address may cause performance degradation or even errors. In addition, address alignment can meet certain hardware and software requirements to ensure that programs or data are loaded and executed correctly.

[0028] Exemplarily, when the data size of each cache unit is 64 bytes and the space size allocated by the main memory DDR is LINE_MAX cache units, that is, 64 x LINE_MAX bytes of space.

[0029] S20: Divide the allocated space of the cache unit equally into a first part and a second part, and use a DMA controller to perform a write operation on the first part, and use a CPU processor to perform a write operation on the second part.

[0030] Exemplarily, in each cache unit, the space is divided into 8 parts, the first part is set for cache DMA (memory controller) writing, the fifth part is set for CPU writing, and it is set that the write operation can be performed simultaneously.

[0031] S30: Compare the current data in the allocated space to verify the consistency of the cache unit.

[0032] For example, all cache lines to be tested are traversed to compare the current data of all addresses in the allocated DDR space to see if they are written. If the data comparison is wrong, the test ends and the problem is found. If the data comparison is correct, the test is successful. This embodiment aligns the address of the main memory according to the address of the cache unit, allocates space to the cache unit in the main memory; divides the allocated space of the cache unit into a first part and a second part, and uses a DMA controller to perform a write operation on the first part, while using a CPU processor to perform a write operation on the second part; compares the current data in the allocated space to verify the consistency of the cache unit. Testing and verification can be performed simultaneously in the initial stage of chip design, problems can be discovered more timely, the test cycle is shorter, and the location of the problem can be located more quickly.

[0033] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize the multi-core operating environment of the CPU processor.

[0034] Exemplarily, during the simulation environment test, the CPU multi-core operating environment is first initialized to run subsequent read and write controls.

[0035] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize main memory, DMA controller and UART serial port, and randomly store data in main memory address.

[0036] For example, during the simulation environment test process, the main memory DDR, the memory controller, and the uart serial port unit may be initialized to facilitate the execution of read and write control commands.

[0037] Optionally, in response to system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: A cache space of a preset size is allocated in the main memory, and the cache space is divided into a first number of shares, where the first number is an even number.

[0038] Figure 2 A schematic diagram of a quad-core processor architecture according to an embodiment of the present application.

[0039] like Figure 2 As shown, in one embodiment, the eight-core processor architecture includes a first core core0, a second core core1, a third core core2, and a fourth core core3.

[0040] The main memory DDR address where data is randomly stored is aligned with the cache unit address. The space allocated by DDR is LINE_MAX cache units Cache Line (i.e. 64 x LINE_MAX bytes). Each cache unit CacheLine is divided into 8 parts, each with 8 bytes, which are allocated to the first core core0, the second core core1, the third core core2, the fourth core core3, the first core core0, the second core core1, the third core core2, and the fourth core core3 in sequence.

[0041] Optionally, the step of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part comprises: During the process of executing the write operation on the first part, each DMA controller writes one byte to each cache space in turn, and traverses all the cache spaces of the first part.

[0042] For example, each core and each Cache Line DMA writes 8 bytes, and the CPU writes 8 bytes. For example, for the first core core0, each cache unit Cache Line is divided into 8 spaces, and the first space is for DMA writing, and the writing operation is performed simultaneously with the CPU.

[0043] Each core DMA writes one byte from the first cache unit Cache Line, and immediately writes one byte to the next cache unit Cache Line until all cache units Cache Line to be tested are traversed, and then starts one byte from the first cache unit Cache Line until all data areas to be tested are written.

[0044] Optionally, the step of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part comprises: When each CPU processor performs a write operation on the second part, it writes one byte to each cache space in turn, and traverses all cache spaces of the second part.

[0045] For example, each core and each Cache Line DMA writes 8 bytes, and the CPU writes 8 bytes. For example, for the first core core0, each cache unit Cache Line is divided into 8 spaces, and the 5th space is written by the CPU, and the writing operation is performed simultaneously with the DMA.

[0046] Each core CPU writes one byte from the first cache unit Cache Line, and immediately writes one byte to the next cache unit Cache Line until all cache units Cache Line to be tested are traversed, and then starts one byte from the first cache unit Cache Line until all data areas to be tested are written.

[0047] Optionally, the step of comparing the current data in the allocated space to verify the consistency of the cache unit includes: Compare the current data of all addresses in the allocated main memory space to see if they are the written data; If the data comparison is wrong, the test ends to find the problem.

[0048] Optionally, the step of comparing the current data in the allocated space to verify the consistency of the cache unit further includes: If the data comparison is correct, the next test cycle will be entered until the preset number of tests is reached.

[0049] For example, the current data of all addresses in the allocated DDR space can be compared to see if they are written data. If the data comparison is wrong, the test ends and the problem is found. If the data comparison is correct, the test succeeds, and the number of tests to be performed has not been reached, the next cycle test can be entered. The test ends until the number of tests is reached.

[0050] Second embodiment The present application also provides an electronic device, which includes a processor and a memory.

[0051] The memory stores a computer program, and when the computer program is executed by the processor, the steps of the cache verification method based on the multi-core processor architecture as described above are implemented.

[0052] For example, multi-core cache consistency mainly involves the following three situations: 1) The consistency of instruction and data caches of a single core in a multi-core system.

[0053] For example, when the data in the main memory is updated by a peripheral device and a single core reads the cache copy of the main memory address, if it is old data, there will be a consistency problem.

[0054] 2) Consistency of multi-core L1 Cache.

[0055] For example, core 0 (core0 for short) and core 1 (core1 for short) first read data from the same main memory address, and core0 and core1 have the same copy of this address in their L1 cache. Then core0 writes different data to this address in the main memory. If core1 reads the old data when reading the data, there will be a consistency problem.

[0056] 3) Consistency between multi-core L2 Cache and peripherals (main memory, PCIE with DMA, GMAC, etc.).

[0057] For example, DMA moves the data in the main memory from address A to address B. If there is a copy of address B in the cache of core0, and then core0 reads the cache copy data of address B, the data read is old, and there will be a consistency problem.

[0058] Figure 3 A schematic diagram of the operation logic of an electronic device according to an embodiment of the present application.

[0059] Please also refer to Figure 1 , Figure 2 and Figure 3 ,In the operation process of the electronic device in this embodiment, there are mainly two steps: 1) simulation environment test; 2) FPGA environment test.

[0060] In the process of simulation environment: ①Initialize the CPU multi-core operating environment.

[0061] ②Initialize DDR, DMA controller, and uart serial port.

[0062] The DDR address where data is stored randomly is aligned with the cache line address of the cache unit.

[0063] ③The space allocated by DDR is LINE_MAX cache lines (i.e. 64 x LINE_MAX bytes). Each cache line is divided into 8 parts, each with 8 bytes, and is allocated to core0, core1, core2, core3, core0, core1, core2, core3 in sequence. Figure 2 .

[0064] ④ For each core, each Cache Line DMA writes 8 bytes, and the CPU writes 8 bytes. For example, for core0, each cache unit Cache Line is divided into 8 parts of space, the first part is written by DMA, and the fifth part is written by CPU, and the write operation is performed simultaneously.

[0065] Each core DMA writes one byte from the first cache unit Cache Line, and immediately writes one byte to the next cache unit Cache Line until all cache units Cache Line to be tested are traversed, and then starts one byte from the first cache unit Cache Line until all data areas to be tested are written. Each CPU write operation is performed simultaneously in the same way.

[0066] ⑤ Compare the current data of all addresses in the allocated DDR space to see if they are written data. If the data comparison is wrong, the test ends and the problem is found. If the data comparison is correct, the test is successful, and the number of tests to be performed has not been reached, start from step 3 to enter the next cycle test.

[0067] ⑥When the required number of tests is reached, the test ends.

[0068] In the FPGA test process, as in the above simulation test process, increase LINE_MAX, expand the data volume, preferably several times the secondary cache, and increase the number of cache eliminations.

[0069] In this embodiment, DMA and CPU write operations are performed on the same cache unit Cache Line at the same time, and when DMA or CPU completes the write operation of the current cache unit Cache Line, it immediately performs the write operation of the next cache unit Cache Line until all cache unit Cache Lines to be tested are traversed, and then the write operation is started from the first cache unit Cache Line until all data areas to be tested are written. In this way, the turbulence of each core Cache is more intense, and the abnormal situation of multi-core Cache consistency can be better tested. The electronic device provided by this embodiment is simple to code and is convenient to be ported to various platforms for testing. It can be tested in a simulation test environment or in an FPGA environment. The electronic device provided by this embodiment has a small amount of test data in a simulation test environment, but it is easy to analyze and solve problems. In the FPGA environment, the test data volume is large, the test time is short, the efficiency is high, and the abnormal situation of secondary cache elimination can be better tested.

[0070] The traditional CPU Cache consistency function verification method requires running the operating system in the corresponding CPU operating environment first, and developing a test application on the system. Compared with the traditional method, the present invention has a shorter test cycle, and can perform testing and verification simultaneously in the initial stage of chip design, so that problems can be discovered more promptly. At the same time, compared with the traditional method, the present invention can locate problems more quickly when consistency-related functional errors are discovered.

[0071] The present invention is applicable to simulation environments and FPGA verification environments, and can be transplanted from simulation test environments to FPGA environment tests without almost any need to modify codes, thereby achieving higher test efficiency, faster problem discovery, and making up for the problems of small test data volume and long simulation time in the simulation test environment.

[0072] The present invention utilizes the concurrent reading and writing mechanism of DMA and CPU to perform correctness test and stress test of consistency logic, which can simultaneously cover the consistency of single-core Cache and multi-core L1 Cache as well as the consistency of multi-core L2 Cache and peripherals (main memory, PCIE with DMA, GMAC, etc.), which is closer to actual usage and easier to find problems.

[0073] Third embodiment The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the cache verification method based on a multi-core processor architecture as described above are implemented.

[0074] The present application provides a cache verification method based on a multi-core processor architecture, which allocates space to the cache unit in the main memory by aligning the address of the main memory according to the address of the cache unit; equally divides the allocated space of the cache unit into a first part and a second part, and uses a DMA controller to perform a write operation on the first part, and uses a CPU processor to perform a write operation on the second part; compares the current data in the allocated space to verify the consistency of the cache unit. Testing and verification can be performed simultaneously in the initial stage of chip design, problems can be discovered more timely, the test cycle is shorter, and the location of the problem can be located faster; the test efficiency is higher, problems are discovered faster, and the user experience is improved.

[0075] It should be noted that in the present application, step codes such as S10, S20, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S20 first and then S10, etc., but these should all be within the scope of protection of the present application.

[0076] In the embodiments of the system and storage medium provided in the present application, all technical features of any of the above-mentioned method embodiments may be included, and the expanded and explained contents of the specification are basically the same as those of the above-mentioned method embodiments, and will not be repeated here.

[0077] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.

[0078] An embodiment of the present application also provides a chip, including a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device equipped with the chip executes the methods in various possible implementation modes as described above.

[0079] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0080] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0081] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0082] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0083] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0084] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0085] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0086] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A cache verification method based on a multi-core processor architecture, characterized in that: include: In response to system initialization, aligning the address of the main memory according to the address of the cache unit, and allocating space in the main memory for the cache unit; Divide the allocated space of the cache unit into a first part and a second part equally, and use a DMA controller to perform a write operation on the first part, and use a CPU processor to perform a write operation on the second part; The current data in the allocated space is compared to verify the consistency of the cache unit.

2. A cache verification method based on a multi-core processor architecture according to claim 1, characterized in that: In response to the system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize the multi-core operating environment of the CPU processor.

3. A cache verification method based on a multi-core processor architecture according to claim 2, characterized in that: In response to the system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: Initialize main memory, DMA controller and UART serial port, and randomly store data in main memory address.

4. A cache verification method based on a multi-core processor architecture according to claim 3, characterized in that: In response to the system initialization, the address of the main memory is aligned according to the address of the cache unit, and the step of allocating space in the main memory to the cache unit includes: A cache space of a preset size is allocated in the main memory, and the cache space is divided into a first number of shares, where the first number is an even number.

5. A cache verification method based on a multi-core processor architecture according to claim 4, characterized in that: The steps of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part include: When each DMA controller performs a write operation on the first part, it writes one byte to each cache space in turn, and traverses all cache spaces of the first part.

6. A cache verification method based on a multi-core processor architecture according to claim 5, characterized in that: The steps of equally dividing the allocated space of the cache unit into a first part and a second part, and using a DMA controller to perform a write operation on the first part, and using a CPU processor to perform a write operation on the second part include: When each CPU processor performs a write operation on the second part, it writes one byte to each cache space in turn, and traverses all cache spaces of the second part.

7. A cache verification method based on a multi-core processor architecture according to any one of claims 1 to 6, characterized in that: The step of comparing the current data in the allocated space to verify the consistency of the cache unit includes: Compare the current data of all addresses in the allocated main memory space to see if they are the written data; If the data comparison is wrong, the test ends to find the problem.

8. The cache verification method based on a multi-core processor architecture according to claim 7, characterized in that: The step of comparing the current data in the allocated space to verify the consistency of the cache unit also includes: If the data comparison is correct, the next test cycle will be entered until the preset number of tests is reached.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory; The memory stores a computer program, and when the computer program is executed by the processor, the steps of the cache verification method based on a multi-core processor architecture as described in any one of claims 1 to 8 are implemented.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the steps of the cache verification method based on a multi-core processor architecture as described in any one of claims 1 to 8 are implemented.

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