Complementary complementary metal oxide semiconductor (CMOS) switch multiplication circuit for time division multiplier

Abstract

The invention discloses a complementary CMOS (Complementary Metal Oxide Semiconductor) switch multiplication circuit for a time division multiplier, which relates to the technical field of integrated circuits, and comprises a CMOS transmission gate, the function of reducing nonlinearity is realized by using the complementary CMOS transmission gate, the on resistance of an NMOS (N-channel Metal Oxide Semiconductor) switch is increased along with the increase of input Vin, the on resistance of a PMOS (P-channel Metal Oxide Semiconductor) switch is reduced along with the increase of the input Vin, and the on resistance of the NMOS switch is reduced along with the increase of the input Vin. According to the complementary CMOS switch multiplication circuit for the time-division multiplier, the oscillation amplitude of the complementary CMOS switch is larger, and the generated resistance Ron and eq changes more gently along with input Vin, the complementary CMOS switch multiplication circuit for the time-division multiplier is used for developing the complementary CMOS switch multiplier obtained by a CMOS transmission gate composed of two MOS tubes, resistance nonlinearity introduced by a single-tube switch and charge injection of a switch tube are reduced, and the time-division multiplier is improved. And the linearity of the multiplier is increased, so that the linearity of the whole metering chip is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a complementary CMOS switch multiplication circuit for a time division multiplier. Background Art

[0002] In the power system, measuring the power transmitted on the transmission line requires extracting the corresponding voltage and current signals from the transmission line and performing multiplication operations on them. In the hardware circuit, the traditional analog power measurement circuit uses a time-division multiplier structure. First, the voltage signal is PWM modulated to make it a single bit stream signal with only high and low. Then, the input current signal with opposite phase is multiplied. This multiplication is implemented using a switch. When the bit stream signal is high, the positive current signal is selected, and when it is low, the negative current signal is selected to achieve the multiplication of voltage and current.

[0003] In integrated circuits, traditional switches are implemented using single-tube MOS tubes, whose on-resistance is affected by the input signal and introduces nonlinearity to the signal, or using bootstrap switches. Although their resistance is not affected by the input signal, the switch tube introduces the problem of charge injection. Therefore, how to reduce the nonlinearity introduced by the switch tube in the time division circuit in the multiplication stage is a key issue in the implementation of the time division multiplier circuit from the board level to the integrated circuit. Therefore, a complementary CMOS switch multiplication circuit for time division multipliers is proposed. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a complementary CMOS switch multiplication circuit for a time division multiplier, which solves the problems raised in the above background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: a complementary CMOS switch multiplication circuit for a time division multiplier, including a CMOS transmission gate, which realizes the function of reducing nonlinearity by using a complementary CMOS transmission gate, and the CMOS transmission gate is composed of two MOS tubes.

[0006] Optionally, the on-resistance of the NMOS switch increases as the input Vin increases, and the on-resistance of the PMOS switch decreases as the input Vin increases.

[0007] Optionally, the complementary CMOS switch has a larger swing, and the generated resistance Ron,eq changes more smoothly with the input Vin, and its on-resistance is: (1) Right now: (2) Optionally, the formula (1) and formula (2) are analyzed to obtain When the on-resistance Independent of the input level, the change in on-resistance is much smaller than that of a single-tube switch.

[0008] Optionally, the complementary CMOS switch has two types of carriers: holes and electrons. During the transmission process, opposite charges are injected into each other by the two channels. hour, Exactly offset .

[0009] Optionally, for the input level of Vin changing, the complementary CMOS switch can reduce the nonlinearity caused by it.

[0010] The present invention provides a complementary CMOS switch multiplication circuit for a time division multiplier, which has the following beneficial effects: The complementary CMOS switch multiplication circuit for time division multiplier uses a complementary CMOS switch multiplier developed by using a CMOS transmission gate composed of two MOS tubes, thereby reducing the resistance nonlinearity introduced by a single-tube switch and the charge injection of the switch tube, increasing the linearity of the multiplier, and thus improving the linearity of the entire metering chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0012] Figure 1 A block diagram showing the position of the multiplier of the present invention in a time division multiplier; Figure 2 A diagram of a complementary CMOS transmission gate switch of the present invention; Figure 3 FIG. 4 is a diagram of the on-resistance of the complementary switch of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] See also Figures 1 to 3 The present invention provides a technical solution: a complementary CMOS switch multiplication circuit for a time division multiplier, including a CMOS transmission gate, which realizes the function of reducing nonlinearity by using a complementary CMOS transmission gate, and the CMOS transmission gate is composed of two MOS tubes.

[0015] The existing time division multiplier multiplication circuit includes a TIA, a multiplier, an ADC and a PWM modulator.

[0016] The difference between a CMOS transmission gate and a single-tube MOS switch is that a complementary MOS tube is introduced. For an NMOS switch, its on-resistance increases with the increase of input Vin, and for a PMOS switch, its on-resistance decreases with the increase of input Vin. Figure 2 The complementary CMOS switch shown has a larger swing and produces a resistance Ron,eq that varies more gradually with input Vin. Its on-resistance is: (1) Right now: (2) It can be considered that when When the on-resistance Independent of input level. Figure 3 Describe the general situation The characteristics of the on-resistance are much smaller than those of a single-tube switch. Among them, the single-tube switch and the bootstrap switch have serious charge injection problems because they are both powered by a single tube. However, the complementary CMOS switch proposed in the present invention has two types of carriers, holes and electrons. Therefore, during the transmission process, opposite charges are injected into each other by the two channels, such as Figure 2 ; when hour, Exactly offset For the input level of Vin changes, although the complementary CMOS switch cannot completely eliminate the impact of charge injection, it can reduce the nonlinearity caused by it.

[0017] In the description of the present invention, it is necessary to understand that the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inside", "front", "center", "both ends" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0018] In addition, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include at least one of such features.

[0019] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "screw-on" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0020] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A complementary CMOS switch multiplication circuit for a time division multiplier, characterized in that: The invention comprises a CMOS transmission gate, and the function of reducing nonlinearity is realized by using a complementary CMOS transmission gate, wherein the CMOS transmission gate is composed of two MOS tubes.

2. A complementary CMOS switch multiplication circuit for a time division multiplier according to claim 1, characterized in that: The on-resistance of the NMOS switch increases as the input Vin increases, and the on-resistance of the PMOS switch decreases as the input Vin increases.

3. A complementary CMOS switch multiplication circuit for a time division multiplier according to claim 1, characterized in that: The complementary CMOS switch has a larger swing, and the resistance Ron,eq generated changes more smoothly with the input Vin, and its on-resistance is: (1) Right now: 。（2) 4. A complementary CMOS switch multiplication circuit for a time division multiplier according to claim 1, characterized in that: By analyzing the formula (1) and formula (2), we can conclude that When the on-resistance Independent of the input level, the change in on-resistance is much smaller than that of a single-tube switch.

5. A complementary CMOS switch multiplication circuit for a time division multiplier according to claim 1, characterized in that: The complementary CMOS switch has two types of carriers: holes and electrons. During the transmission process, opposite charges are injected into each other by the two channels. hour, Exactly offset .

6. A complementary CMOS switch multiplication circuit for a time division multiplier according to claim 1, characterized in that: For the input level of Vin changing, the complementary CMOS switch can reduce the nonlinearity caused by it.

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