Display panel and display device

Abstract

The invention relates to a display panel and a display device, the display panel comprises a plurality of light-emitting pixels arranged in an array, each light-emitting pixel comprises a pixel circuit and a light-emitting element, and each pixel circuit comprises a driving transistor, a data write-in transistor and a threshold compensation transistor; the first shift register unit is at least used for providing a first control signal for the grid electrode of the data write-in transistor; the second shift register unit is at least used for providing a second control signal for the threshold compensation transistor; the first conduction time period of the data writing transistor and the second conduction time period of the threshold compensation transistor are at least partially overlapped, and the cut-off time of the second conduction time period is earlier than the cut-off time of the first conduction time period. According to the invention, the level jump of the first control signal of the first shift register unit does not influence the voltage of the data signal stored in the pixel circuit any more, so that the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements for display panels. For example, when the display panel displays dynamic images such as videos and games, the refresh frequency of the display screen needs to be higher to prevent flickering. On the other hand, in static display screens such as web page text browsing, the refresh frequency of the display screen needs to be lower to reduce power consumption.

[0003] In order to drive the display of the display panel, a driving circuit is provided in the existing display panel. The driving circuit includes a plurality of cascaded shift registers. The shift registers are electrically connected to the scan lines in the display panel. The scan signals are sequentially input to the plurality of scan lines in the display panel through the cascaded shift registers, so that the display panel is scanned from top to bottom or from bottom to top, thereby realizing the display of the display panel.

[0004] To improve the low-frequency display effect, the pixel circuit usually splits the scanning signal and sets a separate shift register to drive the split scanning signal. However, the level jump of the output signal of each shift register after the split will affect the accuracy of data writing, thereby affecting the display effect. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a display panel and a display device.

[0006] In a first aspect, the present application provides a display panel, comprising:

[0007] A plurality of light-emitting pixels arranged in an array, wherein the light-emitting pixels include a pixel circuit and a light-emitting element, wherein the pixel circuit includes a driving transistor, a data writing transistor and a threshold compensation transistor; wherein the driving transistor is used to provide a driving current for the light-emitting element; a first electrode of the data writing transistor is electrically connected to a data signal line, and a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor; a first electrode of the threshold compensation transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is electrically connected to a gate of the driving transistor;

[0008] A first shift register unit, wherein the first shift register unit is at least used to provide a first control signal to the gate of the data writing transistor;

[0009] a second shift register unit, the second shift register unit being at least used for providing a second control signal to the threshold compensation transistor;

[0010] The first conduction period of the data writing transistor at least partially overlaps with the second conduction period of the threshold compensation transistor, and the end time of the second conduction period is earlier than the end time of the first conduction period.

[0011] In a second aspect, based on the same inventive concept, the present application also provides a display device, comprising the display panel as described in the first aspect.

[0012] Compared with the prior art, the technical solution provided by this application has the following advantages:

[0013] In the technical solution provided in the present application, the first shift register unit is used to provide a first control signal to the gate of the data writing transistor so that the data writing transistor is turned on in the first conduction period; the second shift register unit is at least used to provide a second control signal to the threshold compensation transistor so that the threshold compensation transistor is turned on in the second conduction period. Among them, the first conduction period of the data writing transistor and the second conduction period of the threshold compensation transistor at least partially overlap, so that the data signal can be written to the gate of the driving transistor. In addition, in the present application, the cut-off time of the second conduction period is earlier than the cut-off time of the first conduction period, that is, the threshold compensation transistor is turned off first, and the data writing transistor is turned off later. This setting can ensure that the data writing process stops immediately after the threshold compensation transistor is turned off, and the level jump of the first control signal of the first shift register unit no longer affects the data signal voltage stored in the pixel circuit, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0015] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0018] Figure 3 A display panel driving timing diagram provided in an embodiment of the present application;

[0019] Figure 4 A driving timing diagram of the related technology;

[0020] Figure 5 A connection diagram of a shift register unit in the related art;

[0021] Figure 6 A schematic diagram of the delay of control signals of threshold compensation transistors at different positions of a special-shaped display panel in the related art;

[0022] Figure 7 A connection diagram of a shift register unit provided in an embodiment of the present application;

[0023] Figure 8 Another display panel driving timing diagram provided in an embodiment of the present application;

[0024] Fig. 9 Another display panel driving timing diagram provided in an embodiment of the present application;

[0025] Fig.10 A connection diagram of another shift register unit provided in an embodiment of the present application;

[0026] Fig.11 A connection diagram of another shift register unit provided in an embodiment of the present application;

[0027] Fig.12 Another display panel driving timing diagram provided in an embodiment of the present application;

[0028] Fig.13 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0029] Fig.14 A connection diagram of another shift register unit provided in an embodiment of the present application;

[0030] Fig.15 Another display panel driving timing diagram provided in an embodiment of the present application;

[0031] Fig.16 Another display panel driving timing diagram provided in an embodiment of the present application;

[0032] Fig.17 Another display panel driving timing diagram provided in an embodiment of the present application;

[0033] Fig.18 Another display panel driving timing diagram provided in an embodiment of the present application;

[0034] Fig.19 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] It is obvious to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present invention can be combined with each other without contradiction.

[0038] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown in FIG. Figure 2 A schematic diagram of the structure of a pixel circuit provided in this application. Figure 1 as well as Figure 2 As shown, the display panel includes a plurality of light-emitting pixels 10 arranged in an array, and the light-emitting pixels include a pixel circuit 11 and a light-emitting element 12. The pixel circuit includes a driving transistor M1, a data writing transistor M2 and a threshold compensation transistor M3. The driving transistor M1 is used to provide a driving current for the light-emitting element 12. The first electrode of the data writing transistor M2 is electrically connected to the data signal line Vdata, and the second electrode of the data writing transistor M2 is electrically connected to the first electrode of the driving transistor M1; the first electrode of the threshold compensation transistor M3 is electrically connected to the second electrode of the driving transistor M1, and the second electrode of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor M1. It should be noted that one of the first electrode and the second electrode is a source electrode and the other is a drain electrode. The driving transistor generates a driving current under the control of the gate voltage. The driving transistor M1 is electrically connected to the light-emitting element 12, and providing a driving current to the light-emitting element 12 can control the light-emitting element 12 to emit light.

[0039] The display panel further includes a first shift register unit VSR1, which is at least used to provide a first control signal SP to the gate of the data writing transistor M2. When the first control signal SP is at an effective level, the data writing transistor M2 is turned on.

[0040] The display panel further includes a second shift register unit VSR2, which is at least used to provide a second control signal SN2 to the threshold compensation transistor M3. When the second control signal SN2 is at an effective level, the threshold compensation transistor M3 is turned on.

[0041] Figure 3 A display panel driving timing diagram provided in an embodiment of the present application, such as Figure 3 As shown, the effective level of the first control signal SP is exemplarily set to a low level, that is, the data writing transistor is turned on when the first control signal SP is at a low level; the effective level of the second control signal SN2 is a low level, that is, the threshold compensation transistor is turned on when the second control signal SN2 is at a low level. Figure 3 In the example, A1 is shown as the first conduction period of the data writing transistor M2, and A2 is shown as the second conduction period of the threshold compensation transistor M3. In the present application, the first conduction period A1 of the data writing transistor M2 overlaps at least partially with the second conduction period A2 of the threshold compensation transistor M3, and the cut-off time t2 of the second conduction period precedes the cut-off time t1 of the first conduction period A1.

[0042] When the data writing transistor M2 is turned on, the data signal on the data signal line Vdata is transmitted to the first electrode of the driving transistor M1. When the threshold compensation transistor M3 is turned on, the first electrode of the driving transistor M1 and the gate of the driving transistor M1 are turned on. Therefore, in the overlapping period of the first conduction period A1 and the second conduction period A2, the data writing transistor M2 and the threshold compensation transistor M3 are turned on at the same time, and the data signal on the data signal line can be written into the gate (node ​​N1) of the driving transistor M1. Since the data writing transistor M2 and the threshold compensation transistor M3 are driven by different shift register units, if the data writing transistor M2 is turned off before the threshold compensation transistor M3, such as Figure 4 In the timing sequence of the related art, the first control signal SP of the data write transistor M2 first jumps to a high level (exemplarily setting the first control signal SP to a low level as a valid level), and then the second control signal SN2 of the threshold compensation transistor M3 jumps to a high level (exemplarily setting the second control signal SN2 to a low level as a valid level). In this timing sequence of the related art, since the threshold compensation transistor M3 is still in the on state after the data write transistor M2 is turned off, the potential at the gate of the driving transistor M1 may no longer be the potential after threshold compensation. The data writing process is affected by the jumps of the first control signal SP and the second control signal SN2 at the same time, which affects the accuracy of data writing.

[0043] See also Figure 3It can be seen from the driving timing of the present application that the first conduction period A1 of the data writing transistor M2 and the second conduction period A2 of the threshold compensation transistor M3 at least partially overlap, and the cut-off time t2 of the second conduction period is earlier than the cut-off time t1 of the first conduction period. Therefore, the threshold compensation transistor M3 is turned off first, and the data writing transistor M2 is turned off later. After the threshold compensation transistor M3 is turned off, the data writing process stops randomly, and the jump of the first control signal SP will no longer affect the data signal voltage stored in the pixel circuit.

[0044] In some embodiments, the number of rows of pixel circuits electrically connected to the first shift register unit may be set to be the same as the number of rows of pixel circuits electrically connected to the second shift register unit.

[0045] In the related art, the number of rows of pixel circuits to which the shift register unit driving the data writing transistor is connected is different from the number of rows of pixel circuits to which the shift register unit driving the threshold compensation transistor is electrically connected. Figure 5 FIG. 1 is a connection diagram of a shift register unit provided in the related art. Figure 5 As shown, each shift register unit VSR2 ( Figure 5 The example shows two cascaded shift register units VSR2 j , VSR2 (j+1) Bear the load of four rows of pixels and drive each shift register unit VSR1 ( Figure 5 The example shows six cascaded shift register units VSR1. i , VSR1 (i+1) , VSR1 (i+2) , VSR1 (i+3) , VSR1 (i+4) , VSR1 (i+5) Takes the load of a row of pixels. Wherein, i and j are both positive integers greater than or equal to 1.

[0046] like Figure 6 As shown in FIG. 1 , in a special-shaped display panel (such as a display screen of a round watch, a display screen with a hole in the camera area), the number of luminous pixels in each row at different positions of the special-shaped display panel is different. The number of luminous pixels in each row at position B is greater than the number of luminous pixels in each row at position A, so the load of the shift register driving the threshold compensation transistor at position B is significantly greater than the load at position A. Figure 5As shown, each shift register unit VSR2 driving the threshold compensation transistor needs to bear four rows of loads, while each shift register unit driving the data writing transistor bears one row of loads, which will aggravate the delay difference of the control signal of the shift register unit driving the threshold compensation transistor and the shift register unit driving the data writing transistor at different positions. Since data writing can only be performed when the data writing transistor and the threshold compensation transistor are turned on at the same time, the above delay difference will cause the data writing transistor and the threshold compensation transistor to be turned on at the same time. The length of time has a difference, which causes different charging times at different positions of the display panel, causing display differences. Therefore, the present application sets the number of rows of pixel circuits electrically connected to the first shift register unit to be the same as the number of rows of pixel circuits electrically connected to the second shift register unit. Since the first shift register unit is used to provide a first control signal to the gate of the data writing transistor to control the on or off of the data writing transistor, and the second shift register unit is used to provide a second control signal to the gate of the threshold compensation transistor to control the on or off of the threshold compensation transistor, in this way, regardless of whether it is the first shift register unit or the second shift register unit, each level of shift register unit will carry the same number of pixel row loads.

[0047] For example, see Figure 7 , Figure 7 A connection diagram of a shift register unit provided in an embodiment of the present application. Each shift register unit VSR1 ( Figure 7 The example shows two cascaded shift register units VSR1 j , VSR1 (j+1) Bear the load of two rows of pixels and drive each shift register unit VSR2 ( Figure 7 The example shows four cascaded shift register units VSR2 i , VSR2 (i+1) , VSR2 (i+2) , VSR2 (i+3) Bear the load of two rows of pixels. Wherein, i and j both represent positive integers greater than or equal to 1. In this way, each level of the first shift register unit VSR1 and each level of the second shift register unit VSR2 carry the load of two rows of pixel circuits, so the first shift register unit VSR1 and the second shift register unit VSR2 carry the load more evenly, and the control signals of the data writing transistors and the threshold compensation transistors of the pixel circuits at different positions will be more coordinated, thereby avoiding the problem of uneven delay caused by the load differences of the shift register units connected to the pixel circuits at different positions, thereby improving the display effect.

[0048] It should be noted that in this application Figure 7Exemplarily, the number of rows of pixel circuits electrically connected to the first shift register unit and the number of rows of pixel circuits electrically connected to the second shift register unit are both two rows. In other embodiments, the number of rows of pixel circuits electrically connected to the first shift register unit and the number of rows of pixel circuits electrically connected to the second shift register unit can be set to three rows or four rows, or other integer rows, according to the actual needs of the display panel. The embodiment of the present application does not limit the number of rows of pixel circuits electrically connected to the first shift register unit and the number of rows of pixel circuits electrically connected to the second shift register unit.

[0049] In some embodiments, the pixel circuit may further include a first initialization transistor connected between the gate of the driving transistor and the first initialization signal line.

[0050] In the same pixel circuit, the cut-off time of the third conduction period of the first initialization transistor is earlier than the start time of the second conduction period.

[0051] See also Figure 2 The first initialization transistor M4 is connected between the gate of the driving transistor M1 and the first initialization signal line Vref1. When the first initialization transistor M4 is turned on, it is used to provide a first initialization signal to the gate of the driving transistor to initialize the gate of the driving transistor M1. Figure 8 Another driving timing diagram provided in the embodiment of the present application is as follows: Figure 8 As shown, the end time t4 of the third conduction period A3 of the first initialization transistor M4 is earlier than the start time t3 of the second conduction period A2. SN1 is used to represent the control signal of the gate of the first initialization transistor. SN2 represents the control signal of the gate of the data writing transistor. Before data is written (before the threshold compensation transistor M3 is turned on), the first initialization transistor M4 is turned on to provide the first initialization signal to the gate of the driving transistor M1 to avoid the influence of the gate potential of the driving transistor M1 of the previous frame on the display of the current frame. Therefore, the end time t4 of the third conduction period A3 of the first initialization transistor M4 is set to be earlier than the start time t3 of the second conduction period A2.

[0052] In some embodiments, a second shift register unit is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the i+x-th row; wherein i and X are both positive integers greater than or equal to 1.

[0053] The present application sets a second shift register unit connected to the gate of the threshold compensation transistor of the pixel circuit of the i-th row and the gate of the first initialization transistor of the pixel circuit of the i+x-th row, so that one second shift register unit can drive two rows of loads. Compared with setting a shift register unit separately for the first initialization transistor and the threshold compensation transistor, the first initialization transistor and the threshold compensation transistor can reduce the number of shift register units set in the border area of ​​the display panel by multiplexing the control signal output by the shift register unit, thereby achieving the effect of reducing cost and reducing the border size.

[0054] In some embodiments, the second shift register unit is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the i+2-th row. Figure 7 , each second shift register unit is connected to a row of pixel circuits, and the corresponding driving timing can be seen, for example, Fig. 9 , Figure 8 Take the driving of the first row of pixel circuits line1 and the second row of pixel circuits line2 as an example for explanation. SN1-line1 represents the control signal of the first initialization transistor gate of the first row of pixel circuits, SN1-line2 represents the control signal of the first initialization transistor gate of the second row of pixel circuits, SN2-line1 represents the control signal of the threshold compensation transistor gate of the first row of pixel circuits, SN2-line2 represents the control signal of the threshold compensation transistor gate of the second row of pixel circuits, and SP represents the control signal of the data writing transistor gate of the first row of pixel circuits and the second row of pixel circuits.

[0055] See also Figure 7 , the first shift register unit VSR1 adopts a one-drive-two design, and the second shift register unit VSR2 adopts a one-drive-one design with a borrow setting. The borrow setting means that each second shift register unit VSR2 provides a second control signal for the threshold compensation transistor of the corresponding row of pixel circuits, and provides a control signal for the first initialization transistor of a row of pixel circuits after the row. For example Figure 7 Medium VSR2 i The second control signal SN2 is provided for the threshold compensation transistors of the pixel circuits in the i-th row, and the control signal SN1 is provided for the first initialization transistors of the pixel circuits in the (i+2)-th row.

[0056] Since each second shift register is electrically connected to a row of pixel circuits, the interval between SN1 and SN2 is long for the pixel circuits in the same row, and the reset of the driving transistor by the first initialization transistor of each row of pixel circuits starts from the falling edge of SN1 corresponding to the pixel circuit in the row to the falling edge of SN2 of the pixel circuit in the row ( Fig. 9In the exemplary setting of SN1 and SN2 as low levels are effective levels), the reset time of the first initialization transistor can be set relatively long, thereby better improving the afterimage problem.

[0057] In some embodiments, the second shift register unit is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the i+1-th row. Fig.10 In the present application, each second shift register unit is arranged to connect two adjacent rows of pixel circuits. Since this layout does not require cross-row wiring, the wiring is short and simple.

[0058] See also Fig.10 , the first shift register unit VSR1 adopts a one-drive-two design, and the second shift register unit VSR2 adopts a one-drive-one design with a borrow setting. The borrow setting means that each second shift register unit VSR2 provides a second control signal for the threshold compensation transistor of the corresponding pixel circuit of the same row, and provides a control signal for the first initialization transistor of the pixel circuit of the next row. For example Fig.10 Medium VSR2 i The second control signal SN2 is provided for the threshold compensation transistors of the pixel circuits in the i-th row, and the control signal SN1 is provided for the first initialization transistors of the pixel circuits in the (i+1)-th row.

[0059] In some embodiments, the first shift register unit is electrically connected to the gate of the data writing transistor corresponding to the pixel circuit of the i-th row and the gate of the data writing transistor corresponding to the pixel circuit of the i+1-th row. Figure 7 and Fig.10 , each first shift register unit can drive two rows of loads, compared to the related art (e.g. Figure 5 ) One shift register unit VSR1 drives one row of load, which can reduce the number of shift register units set in the border area of ​​the display panel, thereby reducing the border size.

[0060] In some embodiments, the pixel circuit includes a light emitting control transistor, which is connected in series with the driving transistor, and the light emitting control transistor is used to selectively allow the light emitting element to enter the light emitting stage. Correspondingly, the display panel also includes a third shift register unit, which is electrically connected to the gate of the light emitting control transistor in the pixel circuit, and the third shift register unit is used to provide a third control signal to the pixel circuit; the light emitting control transistor is turned on in response to the third control signal.

[0061] For example, Figure 2As shown, the light-emitting control transistor may include a first light-emitting control transistor M6 and a second light-emitting control transistor M7, and the gate of the first light-emitting control transistor M6 and the gate of the second light-emitting control transistor M7 are both electrically connected to the third shift register unit, and the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are controlled to be turned on and off by the third control signal Emit outputted from the output end of the third shift register unit. If the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are P-type transistors, the first light-emitting control transistor M6 and the second light-emitting control transistor M7 are turned on when the third control signal Emit outputted by the third shift register unit is a low-level signal, and are turned off when the third control signal Emit outputted by the third shift register unit is a high-level signal. The first electrode of the first light-emitting control transistor M6 is electrically connected to the first power supply voltage terminal PVDD, and the second electrode of the first light-emitting control transistor M6 is electrically connected to the first electrode of the driving transistor M1. The second electrode of the driving transistor M1 is electrically connected to the first electrode of the second light-emitting control transistor M7, and the second electrode of the second light-emitting control transistor M7 is electrically connected to the anode of the light-emitting element 12.

[0062] In some embodiments, the third shift register unit is electrically connected to the gate of the light emitting control transistor in the pixel circuit of the i-th row and the gate of the light emitting control transistor in the pixel circuit of the i+1-th row, and the third shift register unit is used to provide a third control signal for the pixel circuits of two adjacent rows. Fig.11 , each third shift register unit can drive two rows of loads ( Fig.11 The example shows two cascaded shift register units VSR3 j , VSR3 (j+1) Compared with the technical solution in the prior art in which each row of pixel circuits is electrically connected to a shift register unit, a third control signal can be provided to two rows of pixel circuits through one shift register unit, thereby reducing the number of shift register units, saving the number of shift register units set in the border area of ​​the display panel, and reducing the width of the border area.

[0063] In some embodiments, the data writing transistor and the threshold compensation transistor may be both P-type transistors. If the data writing transistor and the threshold compensation transistor are both P-type transistors, since they are of the same type, the first shift register unit driving the data writing transistor and the second shift register unit driving the threshold compensation transistor may use the same driving architecture, thereby reducing the complexity of the structural setting of the shift register unit and reducing the cost.

[0064] In some embodiments, the data writing transistor can be set to a P-type transistor, and the threshold compensation transistor can be set to an N-type transistor. The driving transistor needs to generate a driving current, and the P-type transistor has a higher mobility. The driving transistor can have a relatively strong driving capability by using a P-type transistor. The N-type transistor has a lower leakage current. The threshold compensation transistor is connected to the gate of the driving transistor. The threshold compensation transistor uses an N-type transistor to reduce the leakage current problem of the gate of the driving transistor, thereby improving the brightness flicker problem.

[0065] It is understandable that the threshold compensation transistor M3 is usually an oxide transistor, and the data writing transistor M2 is usually a low-temperature polysilicon transistor. The oxide transistor is usually an N-type transistor, and the low-temperature polysilicon transistor is usually a P-type transistor.

[0066] In some embodiments, the pixel circuit may further include a second initialization transistor connected between the anode of the light emitting element and the second initialization signal line, wherein the gate of the second initialization transistor is electrically connected to the gate of the data writing transistor.

[0067] See also Figure 2 , the second initialization transistor M5 is connected between the anode of the light emitting element 12 and the second initialization signal line Vref2. The gate of the second initialization transistor M5 and the gate of the data writing transistor M2 are connected to the same control signal. The first control signal SP output by the first shift register unit can also be reused as a control signal for the gate of the second initialization transistor M5, so that the second initialization signal line is connected to the anode of the light emitting element 12 to initialize the anode of the light emitting element 12. Since the first control signal SP output by the first shift register unit is used as the control signal for the gate of the second initialization transistor M5, the shift register unit for driving the second initialization transistor M5 alone can be omitted, so that the number of shift register units set in the border area of ​​the display panel can be significantly reduced, thereby saving the border area of ​​the display panel and improving the screen-to-body ratio of the display area.

[0068] In some implementations, the frequency of the first control signal may be set to be greater than the frequency of the second control signal.

[0069] As users' requirements for the battery life of electronic devices increase, low-frequency display modes with lower power consumption are becoming more and more popular among users. In low-frequency mode, the pixel circuit will write the data signal Vdata to the gate of the driving transistor when writing a frame, and the subsequent holding frame will maintain the gate voltage of the driving transistor. For example, in low-frequency mode, the refresh frequency of the picture is lower than the refresh frequency in normal display mode. Exemplarily, the refresh frequency in normal display mode is 60Hz, and the refresh frequency in low-frequency mode can be 30Hz, for example. In low-frequency mode, a display cycle can include 1 write frame and at least one hold frame. In the hold frame, there is no initialization of the gate of the driving transistor like the write frame, and no new data signal is written, that is, the screen can be switched for a long period of time during low-frequency display, thereby reducing the power consumption caused by screen switching.

[0070] like Figure 2 As shown, when writing a frame, the potential of the first electrode (N2 node) of the data writing transistor is refreshed from PVDD to Vdata. The node potential of the anode (N3 node) of the light-emitting element 12 is refreshed from the potential corresponding to the light-emitting current of the previous frame to the potential Vref2 provided by the second initialization signal line. However, after the writing frame is completed, after the second initialization transistor M5 writes Vref2 to the N3 node, since Vref2 is generally a negative bias voltage, the light-emitting element 12 is in a state of stopping emitting light at this time, but in the subsequent longer low-frequency holding stage, the light-emitting element 12 is still emitting light, which will cause a difference in brightness. In the embodiment of the present application, the gate of the second initialization transistor M5 and the gate of the data writing transistor M2 are electrically connected to the same shift register unit, that is, the first control signal SP of the first shift register unit is used for driving, and see Fig.12 In a driving timing provided by an embodiment of the present application, the frequency of the first control signal SP is greater than the frequency of the second control signal SN2. The second control signal SN2 driving the threshold compensation transistor M3 maintains a relatively low frequency to realize low-frequency display of the display panel, and the first control signal SP driving the second initialization transistor M5 maintains a relatively high frequency. The first control signal SP drives the second initialization transistor M5 at a high frequency to reset the N3 node, so that the light-emitting element can also have a process of extinguishing and then emitting light in the holding frame, thereby reducing the display flickering.

[0071] In some embodiments, the pixel circuit includes a second initialization transistor connected between the anode of the light-emitting element and the second initialization signal line; the gate of the second initialization transistor is electrically connected to the gate of the first initialization transistor.

[0072] When low-frequency display and the flicker problem caused by low-frequency display are not considered, the second initialization transistor can also be controlled by a control signal together with the first initialization transistor, that is, the gate of the second initialization transistor and the gate of the first initialization transistor are electrically connected to the same shift register unit to achieve the reset of the gate of the driving transistor and the anode of the light-emitting element, thereby avoiding the afterimage caused by the residual potential of the previous frame.

[0073] Combine the following Figure 2 and Fig.12 The driving principle of the display panel provided in the embodiment of the present application is described in detail.

[0074] Writing a frame is divided into six stages:

[0075] In stage T1, SN1-line1 is at an effective level (exemplarily, the effective level of SN1-line1 is set to a low level), and the first initialization transistor M4 of the first row of pixel circuits is turned on to reset the gate of the driving transistor M1 of the first row of pixel circuits.

[0076] In stage T2, SN1-line2 is at an effective level (exemplarily setting the effective level of SN1-line2 to a low level), and the first initialization transistor M4 of the second row pixel circuit is turned on to reset the gate of the second row pixel circuit driving transistor M1.

[0077] In the T3 phase, SP is at an effective level (exemplarily setting the effective level of SP to a low level), the data writing transistor M2 of the first row of pixel circuits is turned on; SN2-line1 is at an effective level, the threshold compensation transistor M3 of the first row of pixel circuits is turned on, so the data signal can be written into the gate node N1 of the driving transistor M1 of the first row of pixel circuits. At this time, SN2-line2 is at a high level, so the threshold compensation transistor M3 of the second row is turned off, so the data signal will not be mistakenly written into the gate of the driving transistor M1 of the second row of pixel circuits.

[0078] In the T4 phase, SN2-line1 is at a high level, and the threshold compensation transistor M3 of the first row of pixel circuits is turned off; SN2-line2 is at a low level, and the threshold compensation transistor M3 of the second row of pixel circuits is turned on, so the data signal can be written into the gate node N1 of the second row of pixel circuit driving transistors M1.

[0079] In the T5 stage, SP is at a high level, and the data absorption transistors M2 of the first and second row pixel circuits are turned off. At this time, since SN2-line1 and SN2-line2 have both jumped to a high level, the threshold compensation transistors M3 of the first and second row pixel circuits are both turned off, that is, the end time of the second conduction period of the threshold compensation transistor M3 is earlier than the end time of the first conduction period of the data writing transistor M2D, so the jump of SP will not cause coupling to the potential of the N1 node.

[0080] In the T6 phase, Emit is at an effective level (exemplarily, the effective level of Emit is set to a low level), the light emitting control transistors (M6 and M7) are turned on, and the light emitting element 12 starts to emit light.

[0081] In the holding frame, SN1-line1, SN1-line2, SN2-line1, and SN2-line1 all maintain a high level without jumping, and the holding frame maintains the gate voltage of the driving transistor. In order to maintain the gate-source voltage of the driving transistor in the holding frame displayed at a low frequency and maintain a bias state similar to the writing frame, the present application controls SP to jump at least once in the holding frame, that is, the frequency of the first control signal SN2 is greater than the frequency of the second control signal SP. In addition, the gate of the second initialization transistor M5 is electrically connected to the gate of the data writing transistor M2, and both are controlled to be turned on and off by the second control signal SP. The second initialization transistor M5 can also be driven by the first control signal SP at a high frequency to reset the N3 node, so that the light-emitting element can also have a process of extinguishing and then emitting light in the holding frame, thereby reducing the display flickering.

[0082] In some embodiments, the pixel circuit further includes a bias transistor; a first electrode of the bias transistor is electrically connected to the bias signal line, and a second electrode of the bias transistor is electrically connected to a first electrode of the driving transistor and / or a second electrode of the driving transistor.

[0083] The display panel further includes a fourth shift register unit, which is used to provide a fourth control signal to the gate of the bias transistor.

[0084] The start time of the fourth conduction period of the bias transistor is located after the end time of the first conduction period.

[0085] Fig.13 A schematic diagram of a structure of another pixel circuit provided in an embodiment of the present application is shown in FIG. Fig.13 As shown, the pixel circuit further includes a bias transistor M8, a first electrode of the bias transistor M8 is electrically connected to the bias signal line DVH, Fig.13 The following description is made by taking the case where the second electrode of the bias transistor M8 is electrically connected to the first electrode of the driving transistor M1 as an example. The display panel further includes a fourth shift register unit, which is used to provide a fourth control signal SPX to the gate of the bias transistor M8. Fig.14 A connection diagram of a shift register unit provided in an embodiment of the present application is shown in FIG. Fig.14 The fourth shift register unit is exemplarily set to be electrically connected to the gate of the bias transistor in the pixel circuit of the i-th row and the gate of the bias transistor in the pixel circuit of the i+1-th row, and the fourth shift register unit is used to provide a fourth control signal for two adjacent rows of pixel circuits. Fig.14The example shows two cascaded shift register units VSR4 j , VSR4 (j+1) .

[0086] Fig.15 A driving timing diagram provided in an embodiment of the present application, such as Fig.15 As shown, in the embodiment of the present application, a bias transistor M8 is newly added, and the start time t5 of the fourth conduction period A4 of the bias transistor M8 is set to be after the end time t1 of the first conduction period A1, that is, after data is written, the bias transistor M8 is controlled to be turned on by the fourth control signal SPX provided by the fourth shift register unit, so that the bias signal DVH on the bias signal line DVH (in this application, the signal line and the signal transmitted by the signal line are represented by the same symbol for convenience of description) is written to the N2 node to achieve resetting of the N2 node. By adjusting the potential applied to the N2 node, the bias state of the driving transistor M1 can be adjusted, thereby improving the offset or hysteresis phenomenon of the characteristics of the driving transistor M1 after long-term operation.

[0087] In some embodiments, if the display panel supports a low frequency mode, such as Fig.15 As shown, the first conduction period A1, the second conduction period A2 and the fourth conduction period A4 can be set in the writing frame; the fourth shift register unit is also used to provide the effective level of the fourth control signal SPX to the bias transistor M8 in the fifth conduction period A5 of the holding frame ( Fig.15 In the example, the effective level of the fourth control signal SPX is set to a low level), and the bias transistor M8 is controlled to be turned on.

[0088] When the display panel is in low-frequency mode, the writing frame has a data writing process and a resetting process of the gate of the driving transistor, but the holding frame does not have the above process. For example, in the writing frame, after resetting the gate of the driving transistor, the gate potential of the driving transistor is the first initialization signal provided by the first initialization signal line. Fig.13In the N1 node, Vref1 is Vref1, and Vref1 is generally a negative potential, such as -3V. The N2 node potential is still the PVDD when the previous frame was illuminated, so the voltage difference between the N1 node and the N2 node (the gate-source voltage difference of the driving transistor) will be relatively large when the frame is written. In the holding frame, the gate of the driving transistor is no longer reset or initialized, and the N1 node of the holding frame is Vdata+Vth, where Vth is the threshold voltage of the driving transistor. Therefore, the voltage difference between the N1 node and the N2 node of the holding frame is much smaller than the voltage difference between the N1 node and the N2 node when the writing frame is written, which will cause flickering problems during low-frequency display. Based on the above problems, the present application also performs a process similar to the large voltage difference between the N1 node and the N2 node of the writing frame in the holding frame, that is, in the fifth conduction period A5 of the holding frame, the effective level of the fourth control signal SPX is provided to the bias transistor M8, and the bias transistor M8 is controlled to be turned on, so that the states of the driving transistors of the holding frame and the writing frame are closer, thereby avoiding the flickering problem of low-frequency display.

[0089] In some implementations, the duration of the fifth conduction period is greater than or equal to the duration of the fourth conduction period.

[0090] See also Fig.15 The duration of the fifth conduction period A5 is greater than or equal to the duration of the fourth conduction period A4, that is, the duration of the OBS bias in the hold frame is greater than the duration of the OBS bias in the write frame.

[0091] In the write frame, after the N1 node is reset, the voltage difference between the N1 node potential and the N2 node potential is large, for example, the N1 node potential Vref may be -3V, and the N2 node is PVDD or Vdata, for example, 3V. In the hold frame, the N1 node potential is Vdata+Vth, for example, 2V, and the bias caused by the voltage difference between the N1 node potential and the N2 node potential in the write frame is constructed by providing the bias signal line DVH potential to the N2 node. However, in order to avoid high power consumption caused by excessive DVH, the embodiment of the present application sets the duration of the fifth conduction period A5 to be greater than or equal to the duration of the fourth conduction period A4, and increases the OBS duration of the hold frame (the duration during which the fourth control signal SPX is at an effective level) to achieve similar bias strengths for the hold frame and the write frame.

[0092] In some implementations, the fourth shift register unit is electrically connected to the gate of the bias transistor corresponding to the pixel circuit in the i-th row and the gate of the bias transistor corresponding to the pixel circuit in the (i+1)-th row.

[0093] In the embodiment of the present application, a fourth shift register unit is arranged to be electrically connected to the gates of the bias transistors corresponding to two adjacent rows of pixel circuits. Compared with the technical solution in the prior art in which each row of pixel circuits is electrically connected to one shift register unit, a fourth control signal can be provided to two rows of pixel circuits through one shift register unit, thereby reducing the number of shift register units, saving the number of shift register units arranged in the border area of ​​the display panel, and reducing the width of the border area.

[0094] In some embodiments, the data writing transistor is multiplexed as a biasing transistor; the data writing transistor is used to perform bias adjustment on the driving transistor during a bias period.

[0095] The bias period is located between the cut-off time of the second conduction period of a row of pixel circuits and the cut-off time of the first conduction period of the row of pixel circuits.

[0096] Fig.16 Another driving timing diagram provided in the embodiment of the present application is still based on Figure 2 Taking the pixel circuit shown as an example, the embodiment of the present application reuses the data writing transistor M2 as a bias transistor. Taking the second row pixel circuit as an example, when SN2-line2 and SP are both low level, the data writing transistor and the threshold compensation transistor of the second row pixel circuit are both turned on, so that the data signal can be written into the gate N1 node of the second row pixel circuit driving transistor M1. The moment when SN2-line2 jumps to a high level is the end time t2 of the second conduction period of the second row pixel circuit. After SN2-line2 jumps to a high level, the threshold compensation transistor of the second row pixel unit is turned off, and SP is still at a valid level ( Fig.16 Take the effective level of SP as a low level as an example). From the cut-off time t2 of the second conduction period of the second row pixel circuit to the cut-off time t1 of the first conduction period of the second row pixel circuit, SP is at an effective level, so the data writing transistor of the second row pixel circuit can bias the driving transistor during the period (bias period) from the cut-off time t2 of the second conduction period to the cut-off time t1 of the first conduction period.

[0097] In some embodiments, the first conduction period and the second conduction period are located in the writing frame; the first shift register unit is further used to provide a fifth control signal to the data writing transistor in the sixth conduction period of the holding frame to control the data writing transistor to be turned on.

[0098] When the display panel is displayed in the low-frequency mode, since the writing frame has a data writing process and a resetting process of the gate of the driving transistor, but the holding frame does not have the above process. The above difference will cause the brightness difference between the writing frame and the holding frame, causing low-frequency flicker. Therefore, the embodiment of the present application provides the effective level of the fifth control signal Vpark to the data writing transistor M2 in the sixth conduction period A6 of the holding frame, controls the data writing transistor M2 to be turned on, and makes the driving transistor closer in the holding frame and the writing frame, thereby avoiding the flicker problem of low-frequency display.

[0099] In some implementations, the duration of the sixth conduction period may be set equal to the duration of the first conduction period.

[0100] In the embodiment of the present application, the data writing transistor is multiplexed as a bias transistor to perform OBS bias, and the OBS bias is performed in the low level signal stage of the SP of the writing frame and the holding frame. In this embodiment, the sixth conduction period ( Fig.16 The duration of the low level signal phase of SP of the frame is equal to the first conduction period ( Fig.16 The length of the low level signal phase of the SP of the write frame) can make the driving timing of the SP simpler.

[0101] In some implementations, the duration of the sixth conduction period A6 may be set to be shorter than the duration of the first conduction period A1.

[0102] In the writing frame, taking the second row of pixel circuits as an example, SP first jumps to the effective level, and then SN1-line2 and SN2-line2 jump to the effective level in sequence. Therefore, the effective level period of SP in the writing frame (the first conduction period A1 of the data writing transistor) is relatively long.

[0103] but Figure 2 In the scheme of multiplexing the data writing transistor into the biasing transistor, the biasing time in the writing frame is Fig.16 Therefore, in the first conduction period A1, the data signal is mainly written. In the hold frame, it is necessary to provide a fifth control signal to the N2 node of the drive transistor through the data write transistor in the sixth conduction period A6 for OBS bias. In order to make the OBS bias of the hold frame and the write frame as consistent as possible, the embodiment of the present application sets the duration of the sixth conduction period A6 to be shorter than the duration of the first conduction period A1.

[0104] For example, the time interval between the end time of the second conduction period and the end time of the first conduction period can be set ( Fig.16 The time from t2 to t1 in the figure is the same as the length of the sixth conduction period.

[0105] In some implementations, a time interval between a cut-off time of the second conduction period and a cut-off time of the first conduction period is less than 100 microseconds.

[0106] See for example Figure 8 , Fig. 9 , Fig.12 , Fig.15 , Fig.16 , the rising edge of the first control signal SP of each row of pixel circuits lags behind the rising edge of the second control signal SN2 of the row, that is, the cut-off time of the second conduction period is earlier than the cut-off time of the first conduction period, so as to achieve the problem of avoiding the level jump of the first control signal SP affecting the data signal voltage stored in the pixel circuit as in the above embodiments. The time between the cut-off time of the second conduction period and the cut-off time of the first conduction period can also achieve the effect of OBS biasing the driving transistor in the writing frame. The embodiment of the present application is based on the effect of OBS bias and the consideration of the overall light-emitting time, for example, the time interval between the cut-off time of the second conduction period and the cut-off time of the first conduction period can be set to be less than 100 microseconds.

[0107] In some embodiments, the start time of the first conduction period of the data writing transistor connected to the first shift register unit is earlier than the start time of the second conduction period of the threshold compensation transistor connected to the second shift register unit;

[0108] The second shift register unit is a second shift register unit connected to a pixel circuit electrically connected to the first shift register unit and corresponding to the pixel circuit.

[0109] A first shift register unit can be electrically connected to the data writing transistors of the multiple rows of pixel circuits to Fig. 9 Taking the driving timing shown in the figure as an example, a first shift register unit is connected to the data writing transistor of the first row pixel circuit line1 and the data writing transistor of the second row pixel circuit line2. The second control signal provided by the second shift register unit corresponding to the threshold compensation transistor of the first row pixel circuit is SN2-line1, and the second control signal provided by the second shift register unit corresponding to the threshold compensation transistor of the second row pixel circuit is SN2-line2.

[0110] The present application sets the start time of the first conduction period of the data writing transistor connected to the first shift register unit to be earlier than the start time of the second conduction period of the threshold compensation transistor connected to the second shift register unit. The second shift register unit is a second shift register unit corresponding to the pixel circuit electrically connected to the first shift register unit. Fig. 9, the start time t6 of the first conduction period A1 of the data writing transistor connected to the first shift register unit is earlier than the start time t31 of the second conduction period A2 of the threshold compensation transistor connected to the first row of pixel circuits connected to the first shift register unit, and is earlier than the start time t32 of the second conduction period A2 of the threshold compensation transistor connected to the second row of pixel circuits connected to the first shift register unit.

[0111] Since the overlapping time of the first conduction period of the data writing transistor and the second conduction period of the threshold compensation transistor of the same pixel circuit is the charging time of the pixel circuit, the start time t6 of the first control signal SP needs to be earlier than the control signal SN2-line1 of the gate of the threshold compensation transistor of the first row of pixel circuits, so as to ensure that the charging time of the two rows of pixel circuits is consistent and avoid display differences.

[0112] In some embodiments, the first conduction period may include multiple sub-periods. Each sub-period corresponds to the second conduction period of the threshold compensation transistor of each row of pixel circuits connected to the same second shift register unit, and at least partially overlaps; in the one-to-one corresponding sub-period and the second conduction period, the end time of the second conduction period is earlier than the end time of the sub-period. For example, see Fig.17 , the exemplary setting of the first conduction period may include two sub-times A11 and A12. The sub-period A11 corresponds to the second conduction period A2 of the threshold compensation transistor of the first row of pixel circuits connected to the second shift register unit, and at least partially overlaps, so that the data signal can be written to the gate of the driving transistor of the first row of pixel circuits during the overlapping period. The sub-period A12 corresponds to the second conduction period A2 of the threshold compensation transistor of the second row of pixel circuits connected to the second shift register unit, and at least partially overlaps, so that the data signal can be written to the gate of the driving transistor of the second row of pixel circuits during the overlapping period. The cut-off time of the second conduction period A2 of the threshold compensation transistor of the first row of pixel circuits is earlier than the cut-off time of the sub-period A11. The cut-off time of the second conduction period A2 of the threshold compensation transistor of the second row of pixel circuits is earlier than the cut-off time of the sub-period A121, so that the threshold compensation transistor of each row of pixel circuits is turned off first, and the data writing transistor is turned off later. After the threshold compensation transistor is turned off, the data writing process stops randomly, and the jump of the first control signal SP no longer affects the data signal voltage stored in the pixel circuit.

[0113] In some embodiments, the data write transistor is multiplexed as a bias transistor; the data write transistor is used to write a data signal to the drive transistor for biasing during the seventh conduction period. The start time of the seventh conduction period is after the end time of the first conduction period.

[0114] Fig.18Another driving timing diagram provided in the embodiment of the present application is as follows: Fig.18 As shown, the start time of the seventh conduction period A7 is after the end time of the first conduction period A1. The first conduction period A1 is used for data writing. After the first conduction period A1 ends, in the seventh conduction period A7, the data writing transistor of the pixel circuit is multiplexed as a biasing transistor. For example, the data writing transistor writes a data signal to the source of the driving transistor in the seventh conduction period A7 for biasing, thereby improving the offset or hysteresis of the characteristics of the driving transistor after long-term operation.

[0115] It should be noted that Figure 15-18 The driving timing shown in FIG. 1 is exemplarily described by taking each second shift register unit connected to two adjacent rows of pixel circuits as an example. Fig.10 The connection structure of the shift register unit shown in the figure is as follows: For example, a second shift register unit is connected to the gate of the threshold compensation transistor of the first row of pixel units and the gate of the first initialization transistor of the second row of pixel units.

[0116] It should be noted that in the driving timing diagram of the embodiment of the present application, the exemplary setting of the signal received by the gate of each transistor in the pixel circuit is a valid signal when it is at a low level, and the transistor is turned on; when it is at a high level, the transistor is turned off. Therefore, the transistor is a P-type transistor. In other embodiments, according to the design requirements of the display panel, it can be set that each transistor in the pixel circuit is an N-type transistor, and when the signal received by the gate of the transistor is at a high level, it is a valid signal, and the transistor is turned on; when it is at a low level, the transistor is turned off. It is also possible to set the pixel circuit to include N-type transistors and P-type transistors according to design requirements, and select the corresponding driving timing according to the type of transistor (the effective level of the control signal corresponding to the N-type transistor is a high level, and the effective level of the control signal corresponding to the P-type transistor is a low level).

[0117] Fig.19 A schematic structural diagram of a display device provided in an embodiment of the present application, wherein the display device includes a display panel according to any one of the above display panel embodiments.

[0118] Fig.19 The display panel is shown as 1000. The display device provided in the embodiment of the present application includes the display panel in the above embodiment, and thus can also achieve the same or at least similar technical effects as the above display panel embodiment, which will not be described in detail here.

[0119] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0120] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A plurality of light-emitting pixels arranged in an array, wherein the light-emitting pixels include a pixel circuit and a light-emitting element, wherein the pixel circuit includes a driving transistor, a data writing transistor and a threshold compensation transistor; wherein the driving transistor is used to provide a driving current for the light-emitting element; a first electrode of the data writing transistor is electrically connected to a data signal line, and a second electrode of the data writing transistor is electrically connected to a first electrode of the driving transistor; a first electrode of the threshold compensation transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is electrically connected to a gate of the driving transistor; A first shift register unit, wherein the first shift register unit is at least used to provide a first control signal to the gate of the data writing transistor; a second shift register unit, the second shift register unit being at least used for providing a second control signal to the threshold compensation transistor; The first conduction period of the data writing transistor at least partially overlaps with the second conduction period of the threshold compensation transistor, and the end time of the second conduction period is earlier than the end time of the first conduction period.

2. The display panel according to claim 1, characterized in that: The number of rows of pixel circuits electrically connected to the first shift register unit is the same as the number of rows of pixel circuits electrically connected to the second shift register unit.

3. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first initialization transistor connected between the gate of the driving transistor and a first initialization signal line; In the same pixel circuit, a cut-off time of the third conduction period of the first initialization transistor is earlier than a start time of the second conduction period.

4. The display panel according to claim 3, characterized in that: One of the second shift register units is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the i+x-th row; Wherein, i and X are both positive integers greater than or equal to 1.

5. The display panel according to claim 4, characterized in that: The second shift register unit is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the (i+2)-th row.

6. The display panel according to claim 4, characterized in that: The second shift register unit is electrically connected to the gate of the threshold compensation transistor corresponding to the pixel circuit of the i-th row and the gate of the first initialization transistor corresponding to the pixel circuit of the (i+1)-th row.

7. The display panel according to claim 1, characterized in that: The first shift register unit is electrically connected to the gate of the data writing transistor corresponding to the pixel circuit of the i-th row and the gate of the data writing transistor corresponding to the pixel circuit of the (i+1)-th row.

8. The display panel according to claim 1, characterized in that: The pixel circuit comprises a light emitting control transistor, the light emitting control transistor is connected in series with the driving transistor, and the light emitting control transistor is used to selectively allow the light emitting element to enter a light emitting stage; The display panel also includes a third shift register unit, which is electrically connected to the gate of the light emitting control transistor in the pixel circuit; the third shift register unit is used to provide a third control signal for the pixel circuit; the light emitting control transistor is turned on in response to the third control signal.

9. The display panel according to claim 8, characterized in that: The third shift register unit is electrically connected to the gate of the light emitting control transistor in the pixel circuit of the i-th row and the gate of the light emitting control transistor in the pixel circuit of the i+1-th row, and is used to provide a third control signal for two adjacent rows of pixel circuits.

10. The display panel according to claim 1, characterized in that: The data writing transistor and the threshold compensation transistor are both P-type transistors.

11. The display panel according to claim 1, characterized in that: The data writing transistor is a P-type transistor, and the threshold compensation transistor is an N-type transistor.

12. The display panel according to claim 1, characterized in that: The pixel circuit includes a second initialization transistor connected between the anode of the light emitting element and the second initialization signal line; A gate of the second initialization transistor is electrically connected to a gate of the data writing transistor.

13. The display panel according to claim 12, characterized in that: The frequency of the first control signal is greater than the frequency of the second control signal.

14. The display panel according to claim 3, characterized in that: The pixel circuit includes a second initialization transistor connected between the anode of the light emitting element and the second initialization signal line; A gate of the second initialization transistor is electrically connected to a gate of the first initialization transistor.

15. The display panel according to claim 1, characterized in that: The pixel circuit further includes a bias transistor; a first electrode of the bias transistor is electrically connected to a bias signal line, and a second electrode of the bias transistor is electrically connected to a first electrode of the drive transistor and / or a second electrode of the drive transistor; The display panel further comprises a fourth shift register unit, wherein the fourth shift register unit is used to provide a fourth control signal to the gate of the bias transistor; The start time of the fourth conduction period of the bias transistor is located after the end time of the first conduction period.

16. The display panel according to claim 15, characterized in that: The first on-time period, the second on-time period and the fourth on-time period are located in a write frame; the fourth shift register unit is further used to provide an effective level of a fourth control signal to the bias transistor in a fifth on-time period of a hold frame to control the bias transistor to turn on.

17. The display panel according to claim 1, characterized in that: The data writing transistor is multiplexed as a biasing transistor; the data writing transistor is used to perform bias adjustment on the driving transistor during a biasing period; The bias period is located between a cut-off time of the second conduction period of a row of pixel circuits and a cut-off time of the first conduction period of the row of pixel circuits.

18. The display panel according to claim 1, characterized in that: The start time of the first conduction period of the data writing transistor connected to the first shift register unit is earlier than the start time of the second conduction period of the threshold compensation transistor connected to the second shift register unit; The second shift register unit is a second shift register unit connected to a pixel circuit electrically connected to the first shift register unit and corresponding to the pixel circuit.

19. The display panel according to claim 2, characterized in that: The first conduction period includes a plurality of sub-periods; Each of the sub-periods corresponds one-to-one to a second conduction period of a threshold compensation transistor of each row of pixel circuits connected to the same second shift register unit, and at least partially overlaps; In the one-to-one corresponding sub-periods and the second conduction period, the end time of the second conduction period is earlier than the end time of the sub-period.

20. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1-19.

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