Display panel, driving method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof and a display device, relates to the technical field of display, and can effectively improve the flicker phenomenon under low-frequency driving. The display panel comprises a pixel circuit, the pixel circuit comprises a driving module and a bias adjusting module, the control end of the bias adjusting module is electrically connected with a first scanning line, the first end of the bias adjusting module is electrically connected with a bias signal line, the second end of the bias adjusting module is electrically connected with the first end of the driving module, the first scanning line provides a first scanning signal, and the bias signal line provides bias voltage; the display panel has a first frequency, a driving period under the first frequency comprises a write-in frame and a plurality of holding frames, and the write-in frame and the holding frames respectively comprise at least one light emitting period; in the light emitting period, the total duration of the effective level of the first scanning signal is the first duration; at the first frequency, the first durations corresponding to at least part of the holding frames and the write-in frames are different, and / or the bias voltages corresponding to at least part of the holding frames and the write-in frames are different.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] Affected by factors such as transistor leakage in the pixel circuit, when the display panel is driven at a low frequency, the panel brightness cannot be continuous and uniform as expected, causing the displayed image to flicker.

[0003] The flicker problem will impose some restrictions on the range of the driving frequency of the display panel, so that the display panel cannot better exert the advantages of low frequency and low power consumption. Summary of the invention

[0004] The embodiments of the present invention provide a display panel and a driving method thereof, and a display device, which can effectively improve the flicker phenomenon under low-frequency driving.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including: A pixel circuit, comprising a driving module and a bias adjustment module, wherein a control end of the bias adjustment module is electrically connected to a first scanning line, a first end is electrically connected to a bias signal line, and a second end is electrically connected to a first end of the driving module, the first scanning line provides a first scanning signal, and the bias signal line provides a bias voltage; The display panel has a first frequency, a driving period under the first frequency includes a writing frame and a plurality of holding frames, and the writing frame and the holding frame each include at least one light emitting period; In the light-emitting period, the total duration of the effective level of the first scanning signal is a first duration; At the first frequency, at least part of the holding frames and the writing frames correspond to different first time lengths, and / or at least part of the holding frames and the writing frames correspond to different bias voltages.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, wherein the display panel includes a pixel circuit, a driving module and a bias adjustment module, wherein a control end of the bias adjustment module is electrically connected to a first scan line, a first end is electrically connected to a bias signal line, and a second end is electrically connected to a first end of the driving module, the first scan line provides a first scan signal, and the bias signal line provides a bias voltage; The display panel has a first frequency, a driving period under the first frequency includes a writing frame and a plurality of holding frames, and the writing frame and the holding frame each include at least one light emitting period; In the light-emitting period, the total duration of the effective level of the first scanning signal is a first duration; The driving method comprises: At the first frequency, at least part of the holding frame and the writing frame correspond to different first durations, and / or at least part of the holding frame and the writing frame correspond to different bias voltages.

[0007] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0008] The technical solution provided by the embodiment of the present invention has the following beneficial effects: In the pixel circuit, the bias adjustment transistor is turned on in response to the effective level of the first scanning signal, and the bias voltage is written into the gate of the driving transistor, thereby adjusting the bias state of the driving transistor. Among them, the conduction time of the bias adjustment transistor and the magnitude of the bias voltage will affect the degree of regulation of the bias adjustment transistor on the bias state of the driving transistor, thereby affecting the device characteristics of the driving transistor, thereby affecting the magnitude of the driving current, and thereby affecting the pixel brightness.

[0009] Compared with the writing frame, the embodiment of the present invention dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor in at least part of the holding frame, so that the bias state of the driving transistor can be further adjusted during the holding stage, the driving current during the holding stage is adjusted, the trend of brightness change during the holding stage is suppressed, and the brightness difference between the holding stage and the writing frame is weakened, thereby effectively improving the flicker phenomenon under low-frequency driving.

[0010] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be pulled lower, and the display panel can better play the advantages of low frequency and power consumption reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 A schematic diagram of brightness change in the related art; Figure 2 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 3 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention; Figure 4 A timing diagram provided by an embodiment of the present invention; Figure 5 Another timing diagram provided by an embodiment of the present invention; Figure 6 Another timing diagram provided by an embodiment of the present invention; Figure 7 Another timing diagram provided by an embodiment of the present invention; Figure 8 Another timing diagram provided by an embodiment of the present invention; Fig. 9 Another timing diagram provided by an embodiment of the present invention; Fig.10 Another timing diagram provided by an embodiment of the present invention; Fig.11 Another timing diagram provided by an embodiment of the present invention; Fig.12 Another timing diagram provided by an embodiment of the present invention; Fig.13 Another timing diagram provided by an embodiment of the present invention; Fig.14 Another timing diagram provided by an embodiment of the present invention; Fig.15 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0014] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0016] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0017] At present, low-frequency driving of display panels is usually achieved by reducing the frequency on the basic frequency. For example, the basic frequency of the display panel is 120Hz, and one frame corresponding to the basic frequency is 8.33ms. When the display panel needs to be driven at an ultra-low frequency of 1Hz, a driving cycle at 1Hz includes 1 write frame and 119 hold frames. The duration of the write frame and the hold frame is 8.33ms. The data voltage is only written to the gate of the drive transistor in the write frame, and is not written to the gate of the drive transistor in the hold frame.

[0018] During low-frequency driving, the brightness in the hold phase may change due to the leakage of the gate reset transistor and the threshold compensation transistor connected to the gate of the driving transistor in the pixel circuit. For example, when driving at 1Hz, Figure 1 As shown, Figure 1 This is a schematic diagram of brightness change in the related art. The brightness continues to rise during the maintenance stage, and the difference with the brightness of the write frame becomes larger and larger until the next write frame is entered, and the brightness is restored. However, this will cause a very obvious brightness jump when entering the next write frame, causing a flicker once every 1s, which seriously affects the display quality.

[0019] In this regard, an embodiment of the present invention proposes a technical solution to effectively improve the above-mentioned flickering problem by adjusting the driving timing in the holding phase.

[0020] An embodiment of the present invention provides a display panel, such as Figure 2 As shown, Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention, the display panel includes a pixel circuit 1.

[0021] like Figure 3 As shown, Figure 3 A schematic diagram of the structure of a pixel circuit 1 provided in an embodiment of the present invention, wherein the pixel circuit 1 includes a driving module 2 and a bias adjustment module 3. The control end of the bias adjustment module 3 is electrically connected to a first scanning line Spx for providing a first scanning signal, a first end is electrically connected to a bias signal line DVH for providing a bias voltage, and a second end is electrically connected to a first end of the driving module 2. More specifically, the driving module 2 includes a driving transistor M0. The bias adjustment module 3 includes a bias adjustment transistor M1, the gate of the bias adjustment transistor M1 is electrically connected to the first scan line Spx, the first electrode is electrically connected to the bias signal line DVH, and the second electrode is electrically connected to the first electrode of the driving transistor M0. The bias adjustment transistor M1 is turned on in response to the effective level provided by the first scan line Spx, writes the bias voltage to the first electrode of the driving transistor M0, and adjusts the bias state of the driving transistor M0.

[0022] See also Figure 4~Figure 7 The display panel has a first frequency f1, which can be a relatively low frequency, such as 1 Hz, 2 Hz, 5 Hz, 10 Hz, 20 Hz, etc. The driving period T at the first frequency f1 includes a writing frame WF and a plurality of holding frames HF, and the writing frame WF and the holding frame HF each include at least one light-emitting period T2.

[0023] Regarding the writing frame WF and holding frame HF: the display panel has a basic frequency f, and a frame corresponding to the basic frequency f is The driving cycle T at the first frequency f1 includes a writing frame WF and The time for writing frame WF and holding frame HF is s.

[0024] Regarding the lighting period T1: Figure 3 The display panel further includes a first light emitting control module 4 and a second light emitting control module 5. The control end of the first light emitting control module 4 is electrically connected to the light emitting control signal line Emit, the first end is electrically connected to the first power line PVDD, and the second end is electrically connected to the first end of the driving module 2. The control end of the second light emitting control module 5 is electrically connected to the light emitting control signal line Emit, the first end is electrically connected to the second end of the driving module 2, and the second end is electrically connected to the light emitting element D.

[0025] More specifically, the first light-emitting control module 4 includes a first light-emitting control transistor M2, the gate of the first light-emitting control transistor M2 is electrically connected to the light-emitting control signal line Emit, the first electrode is electrically connected to the first power line PVDD, and the second electrode is electrically connected to the first electrode of the driving transistor M0. The second light-emitting control module 5 includes a second light-emitting control transistor M3, the gate of the second light-emitting control transistor M3 is electrically connected to the light-emitting control signal line Emit, the first electrode is electrically connected to the second electrode of the driving transistor M0, and the second electrode is electrically connected to the light-emitting element D. See also Figure 4~Figure 7 , the light control signal line Emit provides a light control signal, and a light cycle T1 can be understood as a pulse cycle of the light control signal. In the embodiment of the present invention, the writing frame WF and the holding frame HF can be as follows Figure 5 and Figure 7 As shown, each includes a lighting period T1, or it can also be as shown Figure 4 and Figure 6 The writing frame WF and the holding frame HF each include at least two light-emitting periods T1. When the writing frame WF and the holding frame HF each include at least two light-emitting periods T1, the brightness can be more finely regulated using the light-emitting control signal. The accompanying drawings of the embodiments of the present invention are illustrated by taking the writing frame WF and the holding frame HF each including three light-emitting periods T1 as an example.

[0026] like Figure 4and Figure 5 As shown, Figure 4 A timing diagram provided by an embodiment of the present invention, Figure 5 Another timing diagram provided by an embodiment of the present invention, at a first frequency f1, at least a portion of the first duration corresponding to the frame HF and the write frame WF is different, wherein the first duration is the total duration of the effective level of the first scanning signal in the light-emitting period T1. That is, for one light-emitting period T1, when the first scanning signal provides only one pulse, the first duration is the duration of the effective level in the pulse, and when the first scanning signal provides more than two pulses, the first duration is the sum of the durations of the effective levels in the at least two pulses. At least a portion of the first duration corresponding to the frame HF and the write frame WF is different, which means that at least a portion of the total duration of the conduction of the bias adjustment transistor M1 in the frame HF is different from the total duration of the conduction of the bias adjustment transistor M1 in the write frame WF.

[0027] In the embodiment of the present invention, the bias adjustment transistor M1 is a P-type transistor, and accordingly, the effective level of the first scanning signal is a low level.

[0028] and / or, if Figure 6 and Figure 7 As shown, Figure 6 Another timing diagram provided by an embodiment of the present invention is: Figure 7 In another timing diagram provided by an embodiment of the present invention, at the first frequency f1, at least a portion of the bias voltages corresponding to the hold frame HF and the write frame WF are different.

[0029] In the pixel circuit 1, the bias adjustment transistor M1 is turned on in response to the effective level of the first scanning signal, and the bias voltage is written into the gate of the driving transistor M0, thereby adjusting the bias state of the driving transistor M0. Among them, the conduction time of the bias adjustment transistor M1 and the magnitude of the bias voltage will affect the degree of regulation of the bias adjustment transistor M1 on the bias state of the driving transistor M0, thereby affecting the device characteristics of the driving transistor M0, thereby affecting the magnitude of the driving current, and thereby affecting the pixel brightness.

[0030] Compared with the writing frame WF, the embodiment of the present invention dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor M1 in at least part of the holding frame HF, so that the bias state of the driving transistor M0 can be further adjusted during the holding stage, and the driving current during the holding stage can be adjusted to suppress the trend of brightness change during the holding stage, thereby weakening the brightness difference between the holding stage and the writing frame WF, thereby effectively improving the flicker phenomenon under low-frequency driving.

[0031] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be pulled lower, and the display panel can better play the advantages of low frequency and power consumption reduction.

[0032] See also Figure 3 The pixel circuit 1 further includes a gate reset module 6 and a threshold compensation module 7. The control end of the gate reset module 6 is electrically connected to the second scan line S1N, the first end is electrically connected to the first reset line Ref1, and the second end is electrically connected to the control end of the driving module 2. The control end of the threshold compensation module 7 is electrically connected to the third scan line S2N, the first end is electrically connected to the second end of the driving module 2, and the second end is electrically connected to the control end of the driving module 2.

[0033] More specifically, the gate reset module 6 includes a gate reset transistor M4, which may be an indium gallium zinc oxide (IGZO) transistor, the gate of which is electrically connected to the second scan line S1N, the first electrode of which is electrically connected to the first reset line Ref1, and the second electrode of which is electrically connected to the gate of the driving transistor M0. The threshold compensation module 7 includes a threshold compensation transistor M5, which may also be an IGZO transistor, the gate of which is electrically connected to the third scan line S2N, the first electrode of which is electrically connected to the second electrode of the driving transistor M0, and the second electrode of which is electrically connected to the gate of the driving transistor M0.

[0034] Typically, see Figure 1 ,Affected by the leakage of the gate reset transistor M3 and the threshold compensation transistor M4, when driven at a low frequency, the brightness in the holding stage will show an upward trend.

[0035] In order to suppress this upward trend, in a feasible implementation method, see Figure 4 and Figure 5 , at least partially maintaining the first duration corresponding to the frame HF to be greater than the first duration corresponding to the write frame WF.

[0036] That is, compared with the write frame WF, in at least part of the hold frame HF, the total conduction time of the bias adjustment transistor M1 is increased, and the regulation time of the bias adjustment transistor M1 on the drive transistor M0 is prolonged, so that the device characteristics of the drive transistor M0 can be regulated to a greater extent, thereby suppressing the rising trend of brightness in the hold stage and weakening the brightness difference between the hold stage and the write frame WF.

[0037] In a possible implementation, Figure 8 As shown, Figure 8In another timing diagram provided by an embodiment of the present invention, the hold frame HF includes a first hold frame HF1 and a second hold frame HF2. The first hold frame HF1 is located between the write frame WF and the second hold frame HF2.

[0038] The first time length corresponding to the second holding frame HF2 is greater than the first time length corresponding to the first holding frame HF1.

[0039] In the related art, see Figure 1 The farther the holding frame HF is from the writing frame WF, the greater the difference between its brightness and the brightness of the writing frame WF. In the above setting, by setting the first duration corresponding to the first holding frame HF1 close to the writing frame WF to be slightly smaller, and setting the first duration corresponding to the second holding frame HF2 far from the writing frame WF to be slightly larger, the timing setting of the first holding frame HF1 and the second holding frame HF2 can be adjusted more specifically, so that the brightness of the first holding frame HF1 and the second holding frame HF2 are adjusted in a direction closer to the brightness of the writing frame WF.

[0040] When the first duration corresponding to at least a portion of the frame HF is kept greater than the first duration corresponding to the write frame WF, in a feasible implementation manner, see Figure 4 , Figure 5 and Figure 8 , the second time length t corresponding to at least part of the hold frame HF can be made greater than the second time length t corresponding to the write frame WF, wherein the second time length t is the time length of a single effective level in the first scanning signal, that is, the low level time length of a single pulse in the first scanning signal.

[0041] Compared with the writing frame WF, this driving mode may not change the number of pulses of the first scanning signal in the holding frame HF, but only increase the duration of the effective level in the first scanning signal. The increase in the duration of the effective level in the first scanning signal may increase the adjustment time of the bias adjustment transistor M1 on the bias state of the driving transistor M0, thereby suppressing the rising trend of the brightness in the holding stage and weakening the brightness difference between the holding stage and the writing frame WF.

[0042] In this regard, the embodiment of the present invention tests the brightness of the maintained frame based on some different second durations. At 1Hz, when the second duration is 24H, the brightness of the maintained frame HF is 0.01640nits; when the second duration is 28H, the brightness of the maintained frame HF is 0.01609nits; when the second duration is 32H, the brightness of the maintained frame HF is 0.01580nits; when the second duration is 36H, the brightness of the maintained frame HF is 0.01556nits. It can be seen that the larger the second duration, the lower the brightness of the maintained frame, which can effectively suppress the rising trend of the brightness in the maintenance stage.

[0043] Furthermore, if Fig. 9As shown, Fig. 9 In another timing diagram provided by an embodiment of the present invention, the second time length corresponding to at least a portion of the continuously maintained frames HF is increased.

[0044] For example, see Fig. 9 The driving period T at 1 Hz includes the 1st holding frame HF(1) to the 119th holding frame HF(119), wherein the second time lengths corresponding to the 12th holding frame HF(12) to the 119th holding frame HF(119) are increased.

[0045] This setting method is to incrementally adjust the second time length corresponding to multiple holding frames HF, so that the brightness control within these multiple holding frames HF is more precise, and the brightness of each holding frame HF in these multiple holding frames HF can be adjusted to be close to the brightness of the write frame WF, and the improvement effect is better.

[0046] Or, if Fig.10 As shown, Fig.10 Another timing diagram provided by an embodiment of the present invention, the driving period T includes a first holding period K1 and a second holding period K2, the first holding period K1 and the second holding period K2 each include at least two holding frames HF, and the first holding period K1 is located between the writing frame WF and the second holding period K2.

[0047] The second durations corresponding to different holding frames HF in the first holding period K1 are equal, the second durations corresponding to different holding frames HF in the second holding period K2 are equal, and the second duration corresponding to the second holding period K2 is greater than the second duration corresponding to the first holding period K1.

[0048] For example, see Fig.10 The driving period T at 1 Hz includes the 1st holding frame HF(1) to the 119th holding frame HF(119), wherein the first holding period K1 includes the 12th holding frame HF(12) to the x1th holding frame HF(x1), and the second holding period K2 includes the x1+1th holding frame HF(x1+1) to the x2th holding frame HF(x2).

[0049] The number of holding frames HF included in the first holding period K1 and the second holding period K2 may be the same or different.

[0050] In a specific driving mode, the driving cycle T includes a plurality of holding periods, each holding period includes at least two holding frames HF. The second durations corresponding to different holding frames HF in each holding period are equal, and the second durations corresponding to the plurality of holding periods are increased. Among them, the first holding period of any two adjacent holding periods can be understood as the first holding period K1, and the second holding period can be understood as the second holding period K2.

[0051] This setting method adjusts the second duration in units of the holding period. The setting of the second duration is relatively simple and is more suitable for the case where a large number of HF frames are held.

[0052] Furthermore, the difference of the second time lengths corresponding to at least some of the adjacent holding frames HF is Δt, and 2H≤Δt≤8H.

[0053] Where H is the row time, , f is the basic frequency of the display panel, and n is the number of rows of pixel circuits 1 in the display panel.

[0054] Setting the minimum value of Δt to 2H can ensure that the rising trend of brightness in the holding stage is suppressed to a sufficient degree. Setting the maximum value of Δt to 8H can prevent the second duration corresponding to the later holding frame HF from being too long when the number of holding frames HF is large. Because the high level of the light-emitting control signal needs to cover the low level of the first scanning signal, if the second duration corresponding to the holding frame HF is too long, the high level duration of the light-emitting control signal needs to be set longer, which will compress the light-emitting time and affect the brightness.

[0055] When the first duration corresponding to at least a portion of the frame HF is kept greater than the first duration corresponding to the write frame WF, in another feasible implementation manner, as Fig.11 As shown, Fig.11 Another timing diagram provided by an embodiment of the present invention at least partially maintains that the first number corresponding to the frame HF is greater than the first number corresponding to the write frame WF, wherein the first number is the number of effective levels of the first scanning signal in the light-emitting period T1, that is, the number of pulses of the first scanning signal in the light-emitting period T1.

[0056] For example, see Fig.11 At 1 Hz, in the write frame WF, the first scanning signal in one light-emitting period T1 has one pulse, and in the 12th holding frame HF (12) to the 119th holding frame HF (119), the first scanning signal in one light-emitting period T1 has two or more pulses.

[0057] Compared with the writing frame WF, this driving mode can maintain the effective level of the first scanning signal in the frame HF without changing the duration, and only increase the number of pulses of the first scanning signal in the light-emitting period T1. The increase in the number of pulses of the first scanning signal in the light-emitting period T1 can also increase the total conduction time of the bias adjustment transistor M1, thereby increasing the degree of adjustment of the bias adjustment transistor M1 on the bias state of the driving transistor M0, and suppressing the rising trend of the brightness in the holding stage.

[0058] Regarding the influence of bias voltage on brightness, the inventors found during the research process that the effect of bias voltage is mainly reflected in two aspects.

[0059] First, the bias voltage affects the bias of the driving transistor M0, and thus affects the device state of the driving transistor M0. The higher the bias voltage, the more negative the gate-source voltage Vgs of the driving transistor M0, and the more negative the threshold voltage of the driving transistor M0. When the gate voltage of the driving transistor M0 remains unchanged, the more negative the threshold voltage of the driving transistor M0 is, the lower the brightness of the pixel.

[0060] Secondly, the bias voltage will affect the charging of the light-emitting element. The higher the bias voltage is, the more positive charges are stored in the pixel circuit 1 for the light-emitting element to light up, resulting in an increase in the brightness of the pixel.

[0061] In low grayscale display, the charging of the light-emitting element will be greatly affected by the positive charge in the pixel circuit 1, so the influence of the bias voltage on the brightness is mainly reflected in the second aspect. In high grayscale display, the brightness of the light-emitting element is mainly affected by the device state of the driving transistor M0, so the influence of the bias voltage on the brightness is mainly reflected in the first aspect.

[0062] In this regard, in a feasible implementation manner, as Fig.12 As shown, Fig.12 In another timing diagram provided by an embodiment of the present invention, at the first gray scale G1 of the first frequency f1, at least a bias voltage corresponding to the frame HF is kept smaller than a bias voltage corresponding to the write frame WF. The first gray scale G1 is smaller than gray scale 128, which can be understood as a low gray scale.

[0063] At the first gray scale G1, the display panel performs low gray scale display. As mentioned above, the influence of the bias voltage on the brightness at this time is mainly reflected in the second aspect. Therefore, compared with the writing frame WF, by setting the bias voltage corresponding to the holding frame HF lower, the positive charge stored in the pixel circuit 1 for the light-emitting element to light up can be reduced, so as to achieve the purpose of reducing the brightness, and then effectively suppress the rising trend of the brightness in the holding stage, and improve the flicker phenomenon at low gray scale.

[0064] In this regard, the embodiment of the present invention also tests the frame brightness maintenance based on some different bias voltages. When driven at 1Hz, when the bias voltage is 7.2V, the brightness is 0.02246nits; when the bias voltage is 7.15V, the brightness is 0.02079nits; when the bias voltage is 7.1V, the brightness is 0.01887nits; when the bias voltage is 7.05V, the brightness is 0.01733nits; when the bias voltage is 7V, the brightness is 0.01574nits. It can be seen that the smaller the bias voltage, the lower the brightness, and the more obvious the suppression of the brightness increase trend.

[0065] Furthermore, the first gray scale G1 is less than or equal to 16 gray scales.

[0066] The lower the grayscale, the easier it is for the human eye to see the screen flicker. The embodiment of the present invention makes the above settings more specifically for the display of grayscales 16 and below, which can significantly improve the low grayscale flicker while saving some power consumption.

[0067] In a possible implementation, Fig.13 As shown, Fig.13 In another timing diagram provided by an embodiment of the present invention, at the second grayscale G2 of the first frequency f1, at least partially maintaining the bias voltage corresponding to the frame HF is greater than the bias voltage corresponding to the write frame WF. The second grayscale G2 is greater than or equal to 128 grayscales, which can be understood as a high grayscale.

[0068] At the second gray scale G2, the display panel performs high gray scale display. As mentioned above, the influence of the bias voltage on the brightness at this time is mainly reflected in the first aspect. Therefore, compared with the writing frame WF, the bias voltage corresponding to at least part of the holding frame HF is set higher. After the bias state of the driving transistor M0 is adjusted by the bias adjustment transistor M1, the negative bias degree of the threshold voltage of the driving transistor M0 can be increased to achieve the purpose of reducing the brightness, thereby effectively suppressing the rising trend of the brightness in the holding stage and improving the flicker phenomenon at high gray scale.

[0069] In a feasible implementation manner, the bias voltage corresponding to the frame HF is at least partially and continuously maintained to gradually change, and further, may be gradually changed with equal difference values.

[0070] Exemplarily, at 1 Hz, at the first gray scale G1, the bias voltages corresponding to the 12th holding frame HF (12) to the 119th holding frame HF (119) decrease, for example, sequentially to 7.15 V, 7.14 V, 7.13 V, ..., and at the second gray scale G2, the bias voltages corresponding to the 12th holding frame HF (12) to the 119th holding frame HF (119) increase, for example, sequentially to 7 V, 7.01 V, 7.02 V, ...

[0071] This setting method gradually adjusts the bias voltage corresponding to multiple holding frames HF, so that the brightness control within these multiple holding frames HF is more precise. The brightness of each holding frame HF in these multiple holding frames HF can be adjusted to be close to the brightness of the write frame WF, and the improvement effect is better.

[0072] Alternatively, the driving period T includes a first holding period K1 and a second holding period K2, the first holding period K1 and the second holding period K2 each include at least two holding frames HF, and the first holding period K1 is located between the writing frame WF and the second holding period K2.

[0073] The bias voltages corresponding to the first holding period K1 are equal, the bias voltages corresponding to the second holding period K2 are equal, and the bias voltages corresponding to the first holding period K1 and the second holding period K2 are different.

[0074] Exemplarily, at 1 Hz, the first holding period K1 includes the 12th holding frame HF (12) to the x1th holding frame HF (x1), and the bias voltages corresponding to the 12th holding frame HF (12) to the x1th holding frame HF (x1) are equal, and the second holding period K2 includes the x1+1th holding frame HF (x1+1) to the x2th holding frame HF (x2), and the bias voltages corresponding to the x1+1th holding frame HF (x1+1) to the x2th holding frame HF (x2) are equal. At the first gray scale G1, the bias voltage corresponding to the first holding period K1 is greater than the bias voltage corresponding to the second holding period K2, and at the second gray scale G2, the bias voltage corresponding to the first holding period K1 is less than the bias voltage corresponding to the second holding period K2.

[0075] The number of holding frames HF included in the first holding period K1 and the second holding period K2 may be the same or different.

[0076] In a specific driving mode, the driving cycle T includes multiple holding periods, each of which includes at least two holding frames HF. The bias voltages corresponding to different holding frames HF in the holding period are equal, and the bias voltages corresponding to multiple holding periods increase or decrease. In this driving mode, the first holding period of any two adjacent holding periods can be understood as the first holding period K1, and the second holding period can be understood as the second holding period K2.

[0077] This setting method adjusts the bias voltage in units of holding period. The setting of the bias voltage is relatively simple and is more suitable for the situation where a large number of HF frames are held.

[0078] Further, the difference between the bias voltages corresponding to at least some adjacent holding frames HF is ΔV, and 0.01V≤|ΔV|≤0.1V.

[0079] Setting the minimum value of |ΔV| to 0.01V can ensure that the rising trend of brightness in the holding stage is suppressed to a sufficient extent. Setting the maximum value of |ΔV| to 0.1V can prevent the bias voltage corresponding to the later holding frame HF from being too large or too small when there are a large number of holding frames HF, thereby reducing the difficulty of bias voltage design.

[0080] In one possible implementation, see Fig. 9 , Fig.12 and Fig.13 The driving period T includes a first period P1 and a second period P2, the first period P1 is located between the writing frame WF and the second period P2, and the first period P1 and the second period P2 include a plurality of holding frames HF respectively.

[0081] The first period P1 is equal to the first duration corresponding to the write frame WF, and the first period P1 is equal to the bias voltage corresponding to the write frame WF. The second period P2 is different from the first duration corresponding to the write frame WF, and / or the second period P2 is different from the bias voltage corresponding to the write frame WF.

[0082] The first period P1 is close to the writing frame WF, and the brightness change in this period is not very obvious, and the brightness difference with the writing frame WF is small. Therefore, the first duration and bias voltage corresponding to the first period P1 can be set to be the same as the writing frame WF, and only the first duration and / or bias voltage corresponding to the second period P2 can be set to be different from the writing frame WF, thereby saving power consumption.

[0083] Furthermore, the display panel also has a basic frequency f and a second frequency f2, f>f2>f1. The driving period T under the first frequency f1 includes The first time period P1 includes the first to the second holding frames HF. The second period P2 includes the first holding frame HF. 1~2 A holding frame HF.

[0084] In a specific driving mode, see Fig. 9 , Fig.12 and Fig.13 , the base frequency f is 120 Hz, the first frequency f1 is 1 Hz, and the second frequency f2 is 10 Hz. The driving period T at 1 Hz includes 1 writing frame WF and 119 holding frames HF, and the driving period T at 10 Hz includes 1 writing frame WF and 11 holding frames HF. At the first frequency f1, the first period P1 includes the 1st holding frame HF (1) to the 11th holding frame HF (11), and the second period P2 includes the 12th holding frame HF (12) to the 119th holding frame HF (119).

[0085] This driving mode is more suitable for the case where the first frequency f1 is an ultra-low frequency. The second frequency f2 is greater than the first frequency f1, which means that the number of holding frames HF in the driving cycle T corresponding to the second frequency f2 is smaller, and the corresponding brightness increase in the holding stage will not be too large, and the flicker is not obvious.

[0086] In order to save power consumption and reduce the difficulty of designing the first duration and bias voltage, at the first frequency f1, the front Keep the settings in the frame HF unchanged. is the number of holding frames HF in the driving cycle T corresponding to the second frequency f2. The first duration and / or the bias voltage corresponding to the first and subsequent hold frames HF are adjusted.

[0087] In a possible implementation, combining Figure 3 and Figure 4 , at least a portion of the first duration corresponding to the holding frame HF is different from that corresponding to the writing frame WF. Specifically, at least a portion of the first duration corresponding to the holding frame HF is greater than a first duration corresponding to the writing frame WF.

[0088] The pixel circuit 1 further includes an anode reset module 8 , a control end of the anode reset module 8 is electrically connected to the first scan line Spx, a first end of the anode reset module 8 is electrically connected to the first reset line Ref1 , and a second end of the anode reset module 8 is electrically connected to the light emitting element D.

[0089] More specifically, the anode reset module 8 includes an anode reset transistor M6 , a gate of the anode reset transistor M6 is electrically connected to the first scan line Spx, a first electrode is electrically connected to the first reset line Ref1 , and a second electrode is electrically connected to the light emitting element D.

[0090] The anode reset transistor M6 is turned on in response to the effective level of the first scanning signal, and writes the first reset voltage into the light emitting element D to reset the anode voltage of the light emitting element D. The first duration corresponding to at least part of the holding frame HF is increased, which means that the total turn-on time of the anode reset transistor M6 in this part of the holding frame HF is also longer, which can increase the degree of resetting the anode potential of the light emitting element D by the anode reset transistor M6, so that the anode potential is reset more thoroughly, thereby reducing the light emitting brightness, and can also suppress the rising trend of the brightness in the holding stage, and further improve the flicker.

[0091] In a possible implementation, Fig.14 As shown, Fig.14 This is another timing diagram provided by an embodiment of the present invention. The pixel circuit 1 further includes an anode reset module 8. A first end of the anode reset module 8 is electrically connected to a first reset line Ref1 for providing a first reset voltage, and a second end of the anode reset module 8 is electrically connected to the light emitting element D.

[0092] At least a first reset voltage corresponding to a portion of the holding frame HF is smaller than a first reset voltage corresponding to the writing frame WF.

[0093] Compared with the writing frame WF, reducing at least part of the first reset voltage corresponding to the holding frame HF can reduce the anode potential of the light-emitting element D after being reset, thereby reducing the luminous brightness, and can also suppress the rising trend of the brightness in the holding stage, further improving the flicker.

[0094] In a feasible implementation manner, the first frequency f1 is less than 10 Hz.

[0095] The lower the frequency, the more holding frames HF included in the driving cycle T, the greater the degree of brightness increase in the holding stage, and the more obvious the brightness difference with the writing frame WF. Therefore, the embodiment of the present invention can make the above adjustment more targeted to the ultra-low frequency below 10Hz, effectively improving the flicker problem under ultra-low driving and saving some power consumption.

[0096] For pixel circuit 1, see Figure 3 The pixel circuit 1 also includes a data writing module 9, a control end of the data writing module 9 is electrically connected to the fourth scanning line Sp, a first end is electrically connected to the data line Data, and a second end is electrically connected to the first end of the driving module 2.

[0097] More specifically, the data writing module 9 includes a data writing transistor M9 , a gate of which is electrically connected to the fourth scanning line Sp, a first electrode of which is electrically connected to the data line Data, and a second electrode of which is electrically connected to the first electrode of the driving transistor M0 .

[0098] The pixel circuit 1 further includes a storage capacitor Cst, which is electrically connected between the first power line PVDD and the gate of the driving transistor M0 .

[0099] The cathode of the light emitting element D is electrically connected to the second power line PVEE.

[0100] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a display panel, see Figure 2 and Figure 3 The display panel includes a pixel circuit 1, the pixel circuit 1 includes a driving module 2 and a bias adjustment module 3, wherein the control end of the bias adjustment module 3 is electrically connected to the first scan line Spx, the first end is electrically connected to the bias signal line DVH, and the second end is electrically connected to the first end of the driving module 2, the first scan line Spx provides a first scan signal, and the bias signal line DVH provides a bias voltage.

[0101] See also Figure 4~Figure 7 The display panel has a first frequency f1, and the driving period T under the first frequency f1 includes a writing frame WF and a plurality of holding frames HF, and the writing frame WF and the holding frame HF each include at least one light emitting period T1.

[0102] The driving method includes: at a first frequency f1, controlling at least part of the frame HF to be maintained and the first time length corresponding to the write frame WF to be different, the first time length being the total time length of the effective level of the first scanning signal in the light-emitting period T1, and / or controlling at least part of the frame HF to be maintained and the bias voltage corresponding to the write frame WF to be different.

[0103] Combined with the above analysis, by adopting this driving method, compared with the writing frame WF, the embodiment of the present invention dynamically sets the total conduction time and / or bias voltage of the bias adjustment transistor M1 in at least part of the holding frame HF, so that the bias state of the driving transistor M0 can be further adjusted during the holding stage, and the driving current during the holding stage can be adjusted to suppress the trend of brightness change during the holding stage, thereby weakening the brightness difference between the holding stage and the writing frame WF, thereby effectively improving the flicker phenomenon under low-frequency driving.

[0104] On the other hand, because this technical solution can effectively improve the flicker problem of low-frequency driving, the display panel can be driven at a lower frequency, the selection range of the minimum driving frequency of the display panel can be pulled lower, and the display panel can better play the advantages of low frequency and power consumption reduction.

[0105] In one possible implementation, see Figure 4 and Figure 5 , at least partially maintaining the first duration corresponding to the frame HF to be greater than the first duration corresponding to the write frame WF.

[0106] That is, compared with the write frame WF, in at least part of the hold frame HF, the total conduction time of the bias adjustment transistor M1 is increased, and the regulation time of the bias adjustment transistor M1 on the drive transistor M0 is prolonged, so that the device characteristics of the drive transistor M0 can be regulated to a greater extent, thereby suppressing the rising trend of brightness in the hold stage and weakening the brightness difference between the hold stage and the write frame WF.

[0107] In one possible implementation, see Figure 4 , Figure 5 and Figure 8 , at least partially maintaining the second time length t corresponding to the frame HF is greater than the second time length t corresponding to the write frame WF, and the second time length t is the time length of the effective level in the first scanning signal.

[0108] Compared with the writing frame WF, this driving mode may not change the number of pulses of the first scanning signal in the holding frame HF, but only increase the duration of the effective level in the first scanning signal. The increase in the duration of the effective level in the first scanning signal may increase the adjustment time of the bias adjustment transistor M1 on the bias state of the driving transistor M0, thereby suppressing the rising trend of the brightness in the holding stage and weakening the brightness difference between the holding stage and the writing frame WF.

[0109] and / or, see Fig.11 In the light-emitting period T1, the number of effective levels in the first scanning signal is a first number, and the first number corresponding to at least part of the holding frame HF is greater than the first number corresponding to the writing frame WF.

[0110] Compared with the writing frame WF, this driving mode can maintain the effective level of the first scanning signal in the frame HF without changing the duration, and only increase the number of pulses of the first scanning signal in the light-emitting period T1. The increase in the number of pulses of the first scanning signal in the light-emitting period T1 can also increase the total conduction time of the bias adjustment transistor M1, thereby increasing the degree of adjustment of the bias adjustment transistor M1 on the bias state of the driving transistor M0, and suppressing the rising trend of the brightness in the holding stage.

[0111] In one possible implementation, see Fig.12 , at the first gray scale G1 of the first frequency f1, at least partially maintaining the bias voltage corresponding to the frame HF is less than the bias voltage corresponding to the write frame WF, and the first gray scale G1 is less than 128 gray scales. And / or, at the second gray scale G2 of the first frequency f1, at least partially maintaining the bias voltage corresponding to the frame HF is greater than the bias voltage corresponding to the write frame WF, and the second gray scale G2 is greater than or equal to 128 gray scales.

[0112] As mentioned above, the role of bias voltage is mainly reflected in two aspects.

[0113] At the first gray scale G1, the display panel performs low gray scale display. As mentioned above, the influence of the bias voltage on the brightness at this time is mainly reflected in the second aspect. Therefore, compared with the writing frame WF, by setting the bias voltage corresponding to the holding frame HF lower, the positive charge stored in the pixel circuit 1 for the light-emitting element to light up can be reduced, so as to achieve the purpose of reducing the brightness, and then effectively suppress the rising trend of the brightness in the holding stage, and improve the flicker phenomenon at low gray scale.

[0114] At the second gray scale G2, the display panel performs high gray scale display. As mentioned above, the influence of the bias voltage on the brightness at this time is mainly reflected in the first aspect. Therefore, compared with the writing frame WF, the bias voltage corresponding to at least part of the holding frame HF is set higher. After the bias state of the driving transistor M0 is adjusted by the bias adjustment transistor M1, the negative bias degree of the threshold voltage of the driving transistor M0 can be increased to achieve the purpose of reducing the brightness, thereby effectively suppressing the rising trend of the brightness in the holding stage and improving the flicker phenomenon at high gray scale.

[0115] In one possible implementation, see Fig. 9 , Fig.12 and Fig.13The driving period T includes a first period P1 and a second period P2, the first period P1 is located between the writing frame WF and the second period P2, and the first period P1 and the second period P2 include a plurality of holding frames HF respectively.

[0116] The first period P1 is equal to the first duration corresponding to the write frame WF, and the first period P1 is equal to the bias voltage corresponding to the write frame WF. The second period P2 is different from the first duration corresponding to the write frame WF, and / or the second period P2 is different from the bias voltage corresponding to the write frame WF.

[0117] The first period P1 is close to the writing frame WF, and the brightness change in this period is not very obvious, and the brightness difference with the writing frame WF is small. Therefore, the first duration and bias voltage corresponding to the first period P1 can be set to be the same as the writing frame WF, and only the first duration and / or bias voltage corresponding to the second period P2 can be set to be different from the writing frame WF, thereby saving power consumption.

[0118] Furthermore, the display panel also has a basic frequency f and a second frequency f2, where f>f2>f1.

[0119] The driving cycle T includes The first time period P1 includes the first to the second holding frames HF. The second period P2 includes the first holding frame HF. 1~2 A holding frame HF.

[0120] In a specific driving mode, see Fig. 9 , Fig.12 and Fig.13 , the base frequency f is 120 Hz, the first frequency f1 is 1 Hz, and the second frequency f2 is 10 Hz. The driving period T at 1 Hz includes 1 writing frame WF and 119 holding frames HF, and the driving period T at 10 Hz includes 1 writing frame WF and 11 holding frames HF. At the first frequency f1, the first period P1 includes the 1st holding frame HF (1) to the 11th holding frame HF (11), and the second period P2 includes the 12th holding frame HF (12) to the 119th holding frame HF (119).

[0121] This driving mode is more suitable for the case where the first frequency f1 is an ultra-low frequency. The second frequency f2 is greater than the first frequency f1, which means that the number of holding frames HF in the driving cycle T corresponding to the second frequency f2 is smaller, and the corresponding brightness increase in the holding stage will not be too large, and the flicker is not obvious.

[0122] In order to save power consumption and reduce the difficulty of designing the first duration and bias voltage, at the first frequency f1, the front Keep the settings in the frame HF unchanged. is the number of holding frames HF in the driving cycle T corresponding to the second frequency f2. The first duration and / or the bias voltage corresponding to the first and subsequent hold frames HF are adjusted.

[0123] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.15 As shown, Fig.15 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.15 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0124] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A pixel circuit, comprising a driving module and a bias adjustment module, wherein a control end of the bias adjustment module is electrically connected to a first scanning line, a first end is electrically connected to a bias signal line, and a second end is electrically connected to a first end of the driving module, the first scanning line provides a first scanning signal, and the bias signal line provides a bias voltage; The display panel has a first frequency, a driving period under the first frequency includes a writing frame and a plurality of holding frames, and the writing frame and the holding frame each include at least one light emitting period; In the light-emitting period, the total duration of the effective level of the first scanning signal is a first duration; At the first frequency, at least part of the holding frames and the writing frames correspond to different first time lengths, and / or at least part of the holding frames and the writing frames correspond to different bias voltages.

2. The display panel according to claim 1, characterized in that: The first duration corresponding to at least some of the retaining frames is greater than the first duration corresponding to the writing frames.

3. The display panel according to claim 2, characterized in that: The holding frame includes a first holding frame and a second holding frame, the first holding frame is located between the writing frame and the second holding frame, and the first time length corresponding to the second holding frame is greater than the first time length corresponding to the first holding frame.

4. The display panel according to claim 2, characterized in that: The duration of the effective level in the first scanning signal is a second duration; The second duration corresponding to at least some of the retaining frames is greater than the second duration corresponding to the writing frames.

5. The display panel according to claim 4, characterized in that: The second duration corresponding to at least part of the continuous maintained frames increases gradually; Alternatively, the driving cycle includes a first holding period and a second holding period, the first holding period is located between the writing frame and the second holding period, and the first holding period and the second holding period each include at least two holding frames; The second duration corresponding to the first holding period is equal, the second duration corresponding to the second holding period is equal, and the second duration corresponding to the second holding period is greater than the second duration corresponding to the first holding period.

6. The display panel according to claim 5, characterized in that: The difference of the second time lengths corresponding to at least some adjacent holding frames is Δt, 2H≤Δt≤8H; , wherein f is the base frequency of the display panel, and n is the number of rows of pixel circuits in the display panel.

7. The display panel according to claim 2, characterized in that: In the light-emitting period, the number of effective levels in the first scanning signal is a first number; The first number corresponding to at least some of the retaining frames is greater than the first number corresponding to the writing frames.

8. The display panel according to claim 1, characterized in that: At the first gray scale of the first frequency, the bias voltage corresponding to at least part of the hold frames is smaller than the bias voltage corresponding to the write frame, and the first gray scale is smaller than 128 gray scales.

9. The display panel according to claim 8, characterized in that: The first gray scale is less than or equal to gray scale 16.

10. The display panel according to claim 1, characterized in that: At the second gray scale of the first frequency, the bias voltage corresponding to at least part of the holding frames is greater than the bias voltage corresponding to the writing frame, and the second gray scale is greater than or equal to 128 gray scales.

11. The display panel according to claim 8 or 10, characterized in that: The bias voltage corresponding to at least part of the continuous holding frames gradually changes; Alternatively, the driving cycle includes a first holding period and a second holding period, the first holding period is located between the writing frame and the second holding period, and the first holding period and the second holding period each include at least two holding frames; The bias voltages corresponding to the first holding period are equal, the bias voltages corresponding to the second holding period are equal, and the bias voltages corresponding to the first holding period and the second holding period are different.

12. The display panel according to claim 11, characterized in that: The difference between the bias voltages corresponding to at least some adjacent holding frames is ΔV, and 0.01V≤|ΔV|≤0.1V.

13. The display panel according to claim 1, characterized in that: The driving cycle includes a first period and a second period, the first period is between the writing frame and the second period, and the first period and the second period respectively include a plurality of the holding frames; The first time period is equal to the first duration corresponding to the write frame, and the first time period is equal to the bias voltage corresponding to the write frame; The second time period is different from the first time length corresponding to the write frame, and / or the second time period is different from the bias voltage corresponding to the write frame.

14. The display panel according to claim 13, characterized in that: The display panel further has a basic frequency and a second frequency, the basic frequency is f, the first frequency is f1, the second frequency is f2, and f>f2>f1; The driving cycle at the first frequency includes The holding frames, wherein the first time period includes the first to the The second time period includes the 1~2 The holding frame.

15. The display panel according to claim 1, characterized in that: At least part of the holding frames and the writing frames correspond to different first durations; The pixel circuit further comprises an anode reset module, wherein a control end of the anode reset module is electrically connected to the first scan line, a first end of the anode reset module is electrically connected to the first reset line, and a second end of the anode reset module is electrically connected to the light emitting element.

16. The display panel according to claim 1, characterized in that: The pixel circuit further comprises an anode reset module, a first end of the anode reset module is electrically connected to a first reset line, and a second end of the anode reset module is electrically connected to a light emitting element, and the first reset line provides a first reset voltage; The first reset voltage corresponding to at least part of the hold frames is smaller than the first reset voltage corresponding to the write frame.

17. The display panel according to claim 1, characterized in that: The first frequency is less than 10 Hz.

18. A method for driving a display panel, characterized in that: The display panel includes a pixel circuit, including a driving module and a bias adjustment module, wherein a control end of the bias adjustment module is electrically connected to a first scan line, a first end is electrically connected to a bias signal line, and a second end is electrically connected to a first end of the driving module, the first scan line provides a first scan signal, and the bias signal line provides a bias voltage; The display panel has a first frequency, a driving period under the first frequency includes a writing frame and a plurality of holding frames, and the writing frame and the holding frame each include at least one light emitting period; In the light-emitting period, the total duration of the effective level of the first scanning signal is a first duration; The driving method comprises: At the first frequency, at least part of the holding frame and the writing frame correspond to different first durations, and / or at least part of the holding frame and the writing frame correspond to different bias voltages.

19. The driving method according to claim 18, characterized in that: The first duration corresponding to at least some of the retaining frames is greater than the first duration corresponding to the writing frames.

20. The driving method according to claim 19, characterized in that: The duration of the effective level in the first scanning signal is a second duration, and the second duration corresponding to at least part of the holding frames is greater than the second duration corresponding to the writing frame; And / or, in the light-emitting period, the number of valid levels in the first scanning signal is a first number, and the first number corresponding to at least some of the holding frames is greater than the first number corresponding to the writing frame.

21. The driving method according to claim 18, characterized in that: At the first gray scale of the first frequency, the bias voltage corresponding to at least part of the holding frames is smaller than the bias voltage corresponding to the writing frame, and the first gray scale is smaller than 128 gray scales; And / or, at the second gray scale of the first frequency, the bias voltage corresponding to at least part of the hold frames is greater than the bias voltage corresponding to the write frame, and the second gray scale is greater than or equal to 128 gray scales.

22. The driving method according to claim 18, characterized in that: The driving cycle includes a first period and a second period, the first period is between the writing frame and the second period, and the first period and the second period respectively include a plurality of the holding frames; The first time period is equal to the first duration corresponding to the write frame, and the first time period is equal to the bias voltage corresponding to the write frame; The second time period is different from the first time length corresponding to the write frame, and / or the second time period is different from the bias voltage corresponding to the write frame.

23. The driving method according to claim 22, characterized in that: The display panel further has a basic frequency and a second frequency, the basic frequency is f, the first frequency is f1, the second frequency is f2, and f>f2>f1; The driving cycle includes The holding frames, wherein the first time period includes the first to the The second time period includes the 1~2 The holding frame.

24. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 17.

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