Interface circuit and semiconductor device including same

Abstract

The invention discloses an interface circuit and a semiconductor device including the same. The interface circuit may include: a data pad; a first driving circuit connected between the data pad and the first power supply node, and configured to adjust a first resistance value applied between the data pad and the first power supply node according to a termination mode, and selectively drive the data pad with a first power supply voltage; and a first tuning circuit connected between the first power supply node and the first voltage power supply terminal, and configured to tune the first resistance value according to the termination mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0116185, filed on September 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor design technology, and more particularly, to an interface circuit and a semiconductor device including the interface circuit. Background Art

[0004] In order to transmit signals between semiconductor devices, each of the semiconductor devices includes an interface circuit. The signal transmitted through the interface circuit may be reflected at the end terminal of the transmission line. The reflected signal as a noise component may reduce the quality of the signal (ie, signal integrity).

[0005] The interface circuit supports a termination mode in which a termination resistor is connected to an end terminal of a transmission line to prevent the signal from being reflected. The end terminal of the transmission line can be terminated at a constant voltage level by a termination resistor. Depending on the target voltage level of the end terminal, the termination mode can be a center tap termination (CTT) mode, a low tap termination (LTT) mode, etc.

[0006] Recently, an interface circuit supporting a plurality of termination modes such as a CTT mode and an LTT mode has been developed. Summary of the invention

[0007] Various embodiments of the present disclosure relate to an interface circuit having optimized performance in various termination modes and a semiconductor device including the interface circuit.

[0008] According to an embodiment of the present disclosure, an interface circuit may include: a data pad; a first driving circuit connected between the data pad and a first power supply node and configured to adjust a first resistance value applied between the first power supply node and the data pad according to a termination mode, and selectively drive the data pad using a first power supply voltage; and a first tuning circuit connected between the first power supply node and a first voltage power supply terminal and configured to tune the first resistance value according to the termination mode.

[0009] According to an embodiment of the present disclosure, an interface circuit may include: a data pad; an output circuit, connected to the data pad and configured to adjust a pull-up resistance value and a pull-down resistance value applied to the data pad according to a termination mode, and output output data corresponding to a selection mode among the termination modes through the data pad; and a tuning circuit, connected to the output circuit and configured to tune the pull-up resistance value and the pull-down resistance value according to the termination mode.

[0010] According to an embodiment of the present disclosure, a semiconductor device may include: a control circuit, configured to generate first to third pull-up control signals and first to third pull-down control signals corresponding to a termination mode and a power-off mode based on data, a first mode signal and a second mode signal, a plurality of first trimming code signals and a second trimming code signal, and a power gate signal; an interface circuit, configured to: adjust the pull-up resistance value and the pull-down resistance value applied to a data pad according to the termination mode based on the first pull-up control signal and the second pull-up control signal and the first pull-down control signal and the second pull-down control signal, selectively tune the pull-up resistance value and the pull-down resistance value according to a selection mode among the termination modes based on the third pull-up control signal and the plurality of third pull-down control signals; and output data corresponding to the data connected by the interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 The detailed configuration of the control circuit is shown in the circuit diagram.

[0013] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 1 The detailed configuration of the interface circuit is shown in the circuit diagram.

[0014] Figure 4 is a graph showing pull-up resistance values.

[0015] Figure 5 is a graph showing pull-down resistance values.

[0016] Figure 6 is a block diagram illustrating a semiconductor system to which a semiconductor device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0017] Various embodiments of the present disclosure are described below with reference to the accompanying drawings to describe the present disclosure in detail so that those skilled in the art to which the present disclosure belongs can easily realize the technical spirit of the present disclosure.

[0018] It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, the element may be directly connected to or coupled to another element, or electrically connected to or coupled to another element through one or more elements interposed therebetween. In addition, it should be understood that, unless otherwise mentioned, the terms "include", "comprise", "include" and "include" when used in this specification do not exclude the presence of one or more other elements, but may further include or have one or more other elements. In the description throughout the specification, some components are described in the singular, but the present disclosure is not limited thereto, and it should be understood that these components may be formed in the plural.

[0019] Figure 1 is a block diagram showing a semiconductor device 100 according to an embodiment of the present disclosure.

[0020] Reference Figure 1 , the semiconductor device 100 may include a control circuit 110 and an interface circuit 120 .

[0021] The control circuit 110 may generate a plurality of output control signals CTRL based on a plurality of input control signals EN. The plurality of input control signals EN may include Figure 1 The data DIN, which is not shown and will be described below, the first mode signal CTT_EN and the second mode signal LTT_EN, a plurality of first fine-tuning code signals PU_TRIM<1:N>, a plurality of second fine-tuning code signals PD_TRIM<1:N> (where "N" is a natural number), and a power gate signal PG_EN. The plurality of output control signals CTRL may include Figure 1 A first pull-up control signal PUEN, multiple second pull-up control signals PU_TR<1:N>, multiple third pull-up control signals PGB<1:3>, a first pull-down control signal PDEN, multiple second pull-down control signals PD_TR<1:N> and multiple third pull-down control signals PG<1:3> are not shown and will be described below.

[0022] The interface circuit 120 may output (or interface) the output data DOUT corresponding to the data DIN to an external device, such as an external controller, etc., based on a plurality of output control signals CTRL. The interface circuit 120 may adjust the pull-up resistance value and the pull-down resistance value associated with the output data DOUT according to the first termination mode and the second termination mode based on the first pull-up control signal PUEN and the plurality of second pull-up control signals PU_TR<1:N>. The interface circuit 120 may tune the pull-up resistance value and the pull-down resistance value based on the plurality of third pull-up control signals PGB<1:3> and the plurality of third pull-down control signals PG<1:3>. For example, during the first termination mode, the interface circuit 120 may not tune the pull-up resistance value and the pull-down resistance value, and during the second termination mode, the interface circuit 120 may tune the pull-up impedance value and the pull-down impedance value. The first termination mode may include a center tap termination (CTT) mode, and the second termination mode may include a low tap termination (LTT) mode.

[0023] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A circuit diagram of a detailed configuration of the control circuit 110 is shown in FIG.

[0024] Reference Figure 2 , the control circuit 110 may include first to fifth control logic circuits LG1 , LG2 , LG3 , LG4 , and LG5 .

[0025] The first control logic circuit LG1 may generate a first pull-up control signal PUEN based on the data DIN and the first mode signal CTT_EN. For example, the first control logic circuit LG1 may include a NAND gate ND1. The NAND gate ND1 may generate the first pull-up control signal PUEN by performing a NAND operation on the data DIN and the first mode signal CTT_EN.

[0026] The second control logic circuit LG2 can generate a plurality of second pull-up control signals PU_TR<1:N> based on the data DIN and a plurality of first fine-tuning code signals PU_TRIM<1:N>. For example, the second control logic circuit LG2 may include a NAND gate ND2 and an inverter INV1. The NAND gate ND2 may perform a NAND operation on the data DIN and corresponding bits in the plurality of first fine-tuning code signals PU_TRIM<1:N>, and the inverter INV1 may invert corresponding bits in the output signal of the NAND gate ND2 to generate corresponding bits in the plurality of second pull-up control signals PU_TR<1:N>. Although Figure 2It is shown that the second control logic circuit LG2 representatively includes only one unit circuit, but in fact, the second control logic circuit LG2 may include N unit circuits corresponding to the number of bits of the plurality of first fine-tuning code signals PU_TRIM<1:N>.

[0027] The third control logic circuit LG3 may generate a first pull-down control signal PDEN based on the data DIN. For example, the third control logic circuit LG3 may include an inverter INV2. The inverter INV2 may invert the data DIN to generate the first pull-down control signal PDEN.

[0028] The fourth control logic circuit LG4 can generate a plurality of second pull-down control signals PD_TR<1:N> based on the data DIN and a plurality of second fine-tuning code signals PD_TRIM<1:N>. For example, the fourth control logic circuit LG4 may include an inverter INV3 and a NOR gate NO1. The inverter INV3 may invert corresponding bits in the plurality of second fine-tuning code signals PD_TRIM<1:N>, and the NOR gate NO1 may perform a NOR operation on the data DIN and the corresponding bits in the output signal of the inverter INV3 to generate a plurality of second pull-down control signals PD_TR<1:N>. Although Figure 2 It is shown that the fourth control logic circuit LG4 representatively includes only one unit circuit, but in fact, the fourth control logic circuit LG4 may include N unit circuits corresponding to the number of bits of the plurality of second trimming code signals PD_TRIM<1:N>.

[0029] The fifth control logic circuit LG5 may generate a plurality of third pull-up control signals PGB<1:3> and a plurality of third pull-down control signals PG<1:3> based on the first mode signal CTT_EN and the second mode signal LTT_EN and the power gate signal PG_EN. For example, the fifth control logic circuit LG5 may include first circuits INV4, INV5, and INV6, second circuits XOR1, ND3, and INV7, and third circuits ND4, INV8, and INV9.

[0030] The first circuit INV4, INV5 and INV6 may include three inverters INV4, INV5 and INV6. The inverter INV4 may invert the power gate signal PG_EN, and the inverter INV5 may invert the output signal of the inverter INV4 to generate a first pull-down signal PG among the plurality of third pull-down control signals PG<1:3>. <1> , the inverter INV6 can pull down the first signal PG <1> Invert to generate the first pull-up signal PGB among the plurality of third pull-up control signals PGB<1:3> <1> .

[0031] The second circuit XOR1, ND3 and INV7 may include an XOR gate XOR1, a NAND gate ND3 and an inverter INV7. The XOR gate XOR1 may perform an XOR operation on the first mode signal CTT_EN and the second mode signal LTT_EN, and the NAND gate ND3 may perform an XOR operation on the first pull-down signal PG <1> The output signal of the XOR gate XOR1 performs a NAND operation to generate a second pull-up signal PGB among the plurality of third pull-up control signals PGB<1:3>. <2> , the inverter INV7 can pull up the second signal PGB <2> Invert to generate the second pull-down signal PG among the plurality of third pull-down control signals PG<1:3> <2> .

[0032] The third circuit ND4, INV8 and INV9 may include a NAND gate ND4 and two inverters INV8 and INV9. The NAND gate ND4 may be configured to generate a second pull-down signal PG <2> The inverter INV8 can invert the output signal of the NAND gate ND4 to generate a third pull-down signal PG among the plurality of third pull-down control signals PG<1:3> by performing a NAND operation with the first mode signal CTT_EN. <3> , the inverter INV9 can pull down the third signal PG <3> The third pull-up signal PGB is inverted to generate the third pull-up control signal PGB<1:3> <3> .

[0033] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A circuit diagram of a detailed configuration of the interface circuit 120 is shown in FIG.

[0034] Reference Figure 3 , the interface circuit 120 may include a data pad DQ, output circuits DC1 and DC2 , and tuning circuits PC1 and PC2 .

[0035] The data pad DQ may output output data DOUT to an external device.

[0036] The output circuits DC1 and DC2 may be connected to the data pad DQ. The output circuits DC1 and DC2 may output output data DOUT corresponding to a selection mode among the first termination mode and the second termination mode through the data pad DQ. For example, the output circuits DC1 and DC2 may include a pull-up driving circuit DC1 and a pull-down driving circuit DC2.

[0037] The pull-up driving circuit DC1 may be connected between the data pad DQ and the first power node SN1 and may adjust a pull-up resistance value according to a selection mode among the first termination mode and the second termination mode and pull-up drive the data pad DQ.

[0038] The pull-up driving circuit DC1 may include a first pull-up driver D1 and a plurality of second pull-up drivers D2. The first pull-up driver D1 may be independently controlled in a predetermined mode in a first termination mode and a second termination mode based on a first pull-up control signal PUEN. For example, the first pull-up driver D1 may be independently controlled in a first termination mode (i.e., CTT mode). The plurality of second pull-up drivers D2 may be jointly controlled in the first termination mode and the second termination mode based on a plurality of second pull-up control signals PU_TR<1:N>.

[0039] The pull-down driving circuit DC2 may be connected between the data pad DQ and the second power supply node SN2. The pull-down driving circuit DC2 may adjust a pull-down resistance value according to a selection mode and pull-down drive the data pad DQ.

[0040] The pull-down driving circuit DC2 may include a first pull-down driver D3 and a plurality of second pull-down drivers D4. The first pull-down driver D3 may be independently controlled in a predetermined mode in a first termination mode and a second termination mode based on a first pull-down control signal PDEN. For example, the first pull-down driver D3 may be independently controlled in a first termination mode (i.e., CTT mode). The plurality of second pull-down drivers D4 may be jointly controlled in the first termination mode and the second termination mode based on a plurality of second pull-down control signals PD_TR<1:N>.

[0041] The tuning circuits PC1 and PC2 may be connected to the output circuits DC1 and DC2, respectively. The tuning circuits PC1 and PC2 may tune the pull-up resistance value and the pull-down resistance value according to the first termination mode and the second termination mode. The tuning circuits PC1 and PC2 may further adjust the pull-up resistance value and the pull-down resistance value according to the first termination mode and the second termination mode. The tuning circuits PC1 and PC2 may be indirectly connected to the data pad DQ through the output circuits DC1 and DC2, respectively. The tuning circuits PC1 and PC2 may tune the pull-up resistance value and the pull-down resistance value without being directly connected to the data pad DQ. For example, the tuning circuits PC1 and PC2 may include a pull-up tuning circuit PC1 and a pull-down tuning circuit PC2.

[0042] The pull-up tuning circuit PC1 may be connected between the high-voltage power supply terminal VCCQ and the first power supply node SN1. The pull-up tuning circuit PC1 may tune the pull-up resistance value according to the first termination mode and the second termination mode based on the first to third pull-up signals PGB<1:3>. The pull-up tuning circuit PC1 may include a third pull-up driver PD1, PD2, and PD3 connected in parallel between the high-voltage power supply terminal VCCQ and the first power supply node SN1. The third pull-up driver PD1, PD2, and PD3 may selectively operate according to the first termination mode and the second termination mode based on the first to third pull-up signals PGB<1:3>, respectively. During the power-off mode, the pull-up tuning circuit PC1 may electrically disconnect the high-voltage power supply terminal VCCQ from the first power supply node SN1.

[0043] The pull-down tuning circuit PC2 may be connected between the second power node SN2 and the low-voltage power terminal VSSI. The pull-down tuning circuit PC2 may tune the pull-down resistance value according to the first termination mode and the second termination mode. The pull-down tuning circuit PC2 may include a third pull-down driver PD4, PD5, and PD6 connected in parallel between the second power node SN2 and the low-voltage power terminal VSSI. The third pull-down driver PD4, PD5, and PD6 may selectively operate according to the first termination mode and the second termination mode based on the first to third pull-down signals PG<1:3>, respectively. During the power-off mode, the pull-down tuning circuit PC2 may electrically disconnect the second power node SN2 from the low-voltage power terminal VSSI.

[0044] In the following, reference is made to Figure 4 and Figure 5 The operation of the semiconductor device 100 having the above-described configuration according to the embodiment of the present disclosure is described.

[0045] The power gate signal PG_EN and the first mode signal CTT_EN and the second mode signal LTT_EN may be controlled as shown in the following Table 1. In Table 1, "X" may refer to a case of "ignore". For reference, the logic levels of the first to third pull-up signals PGB<1:3> are not indicated in Table 1, but the first to third pull-up signals PGB<1:3> may correspond to inverted signals of the first to third pull-down signals PG<1:3> (refer to Figure 2 ).

[0046] Table 1

[0047] model PG_EN CTT_EN LTT_EN PG<1> PG<2> PG<3> Power-off mode 0 X X 0 0 0 First termination mode 1 1 0 1 1 1 Second termination mode 1 0 1 1 1 0

[0048] During the power-off mode, the power gate signal PG_EN may be enabled. For example, the power gate signal PG_EN may have a low logic level, i.e., "0". Therefore, regardless of the logic levels of the first mode signal CTT_EN and the second mode signal LTT_EN, the first to third pull-up signals PGB<1:3> and the first to third pull-down signals PG<1:3> may be disabled. For example, the first to third pull-up signals PGB<1:3> may all have a high logic level, i.e., "1", and the first to third pull-down signals PG<1:3> may all have a low logic level, i.e., "0".

[0049] During the power-off mode, the pull-up tuning circuit PC1 can electrically disconnect the high voltage power terminal VCCQ from the first power node SN1 based on the disabled first to third pull-up signals PGB<1:3>, and the pull-down tuning circuit PC2 can electrically disconnect the second power node SN2 from the low voltage power terminal VSSI.

[0050] During the first termination mode (ie, CTT mode) and the second termination mode (ie, LTT mode), the power gate signal PG_EN may be disabled. For example, the power gate signal PG_EN may have a high logic level, ie, “1”.

[0051] During the first termination mode, the first mode signal CTT_EN may be enabled and the second mode signal LTT_EN may be disabled. For example, the first mode signal CTT_EN may have a high logic level, i.e., "1", and the second mode signal LTT_EN may have a low logic level, i.e., "0". Therefore, all pull-up signals in the first to third pull-up signals PGB<1:3> and all pull-down signals in the first to third pull-down signals PG<1:3> may be enabled. For example, the first to third pull-up signals PGB<1:3> may all have a low logic level, i.e., "0", and the first to third pull-down signals PG<1:3> may all have a high logic level, i.e., "1". Although it is described as an example in the present embodiment that in the first termination mode, all pull-up signals in the first to third pull-up signals PGB<1:3> and all pull-down signals in the first to third pull-down signals PG<1:3> are enabled, it is not necessary to be limited thereto, and according to design, some of the first to third pull-up signals PGB<1:3> and some of the first to third pull-down signals PG<1:3> may be enabled.

[0052] During the first termination mode, the pull-up driving circuit DC1 may adjust the pull-up resistance value applied to the data pad DQ. In this case, the pull-up tuning circuit PC1 may not tune the pull-up resistance value. During the first termination mode, the pull-up tuning circuit PC1 may only reflect a predetermined default value in the pull-up resistance value.

[0053] During the first termination mode, the pull-down driving circuit DC2 may adjust the pull-down resistance value applied to the data pad DQ. In this case, the pull-down tuning circuit PC2 may not tune the pull-down resistance value. During the first termination mode, the pull-down tuning circuit PC2 may only reflect a predetermined default value in the pull-down resistance value.

[0054] During the second termination mode, the first mode signal CTT_EN may be disabled and the second mode signal LTT_EN may be enabled. For example, the first mode signal CTT_EN may have a low logic level, i.e., "0", and the second mode signal LTT_EN may have a high logic level, i.e., "1". Therefore, the first to third pull-up signals PGB<1:3> and the first to third pull-down signals PG<1:3> may be selectively enabled. For example, the first pull-up signal PGB <1> The second pull-up signal PGB may have a low logic level, ie, "0". <2> The third pull-up signal PGB may have a low logic level, ie, "0". <3> The first pull-down signal PG may have a high logic level, ie, "1". <1> The second pull-down signal PG may have a high logic level, that is, "1". <2> The third pull-down signal PG may have a high logic level, ie, "1". <3> It may have a low logic level, i.e., "0". Although it is described as an example in the present embodiment that in the second termination mode, the first and second pull-up signals PGB<1:2> among the first to third pull-up signals PGB<1:3> are enabled, and the first and second pull-down signals PG<1:2> among the first to third pull-down signals PG<1:3> are enabled, it is not necessarily limited thereto, and according to design, at least one of the first to third pull-up signals PGB<1:3> and at least one of the first to third pull-down signals PG<1:3> may be enabled.

[0055] During the second termination mode, the pull-up driving circuit DC1 can adjust the pull-up resistance value applied to the data pad DQ. In this case, the pull-up tuning circuit PC1 can tune the pull-up resistance value. During the second termination mode, the pull-up tuning circuit PC1 can reflect an additional resistance value different from a default value in the pull-up resistance value.

[0056] During the second termination mode, the pull-down driving circuit DC2 can adjust the pull-down resistance value applied to the data pad DQ. In this case, the pull-down tuning circuit PC2 can tune the pull-down resistance value. During the second termination mode, the pull-down tuning circuit PC2 can reflect an additional resistance value different from a default value in the pull-down resistance value.

[0057] The first pull-up driver D1 and the plurality of second pull-up drivers D2 included in the pull-up driving circuit DC1 and the first pull-down driver D3 and the plurality of second pull-down drivers D4 included in the pull-down driving circuit DC2 may be controlled as shown in the following Table 2. For ease of description, Table 2 representatively represents one fine-tuning code signal PU_TRIM<K> among the plurality of first fine-tuning code signals PU_TRIM<1:N>, one fine-tuning code signal PD_TRIM<K> among the plurality of second fine-tuning code signals PD_TRIM<1:N>, one pull-up driver D2_K corresponding to one fine-tuning code signal PU_TRIM<K> among the plurality of second pull-up drivers D2, and one pull-down driver D4_K corresponding to one fine-tuning code signal PD_TRIM<K> among the plurality of second pull-down drivers D4.

[0058] Table 2

[0059]

[0060] Figure 4 is a graph showing pull-up resistance values ​​(labeled here with reference character “RPU”).

[0061] Reference Figure 4 During the first termination mode, the pull-up driving circuit DC1 can adjust the pull-up resistance value RPU so that the pull-up resistance value RPU corresponds to the target resistance value TRPU1. When the pull-up resistance value RPU meets the target resistance value TRPU1, that is, when the pull-up resistance value RPU and the target resistance value TRPU1 are consistent, the change amount of the pull-up resistance value RPU according to the change amount of the second pull-up control signal PU_TR<1:N>, that is, the change amount per step or per code is relatively small, that is, the slope of the solid line is relatively gentle, and therefore, the pull-up tuning circuit PC1 can maintain the default value reflected in the pull-up resistance value RPU, and no additional tuning can be performed on the pull-up resistance value RPU.

[0062] During the second termination mode, the pull-up drive circuit DC1 can adjust the pull-up resistance value RPU so that the pull-up resistance value RPU corresponds to the target resistance value TRPU2. According to the prior art, during the second termination mode, when the pull-up resistance value RPU meets the target resistance value TRPU2, that is, when the pull-up resistance value RPU is consistent with the target resistance value TRPU2, the change amount of the pull-up resistance value RPU according to the change amount of the second pull-up control signal PU_TR<1:N>, that is, the change amount of each step may be relatively large, that is, the slope of the double dotted line may be relatively steep. This is because, compared with the amount of current flowing through the pull-up drive circuit DC1 at each step in the first termination mode, the amount of current flowing through the pull-up drive circuit DC1 at each step in the second termination mode increases. Therefore, according to this embodiment, during the second termination mode, the pull-up tuning circuit PC1 can reflect an additional resistance value different from the default value in the pull-up resistance value RPU. According to this embodiment, during the second termination mode, when the pull-up resistance value RPU meets the target resistance value TRPU2, the pull-up resistance value RPU can be tuned so that the change in the pull-up resistance value RPU according to the change in the second pull-up control signal PU_TR<1:N>, that is, the change in each step becomes relatively small, that is, the slope of the single-point dashed line becomes relatively gentle.

[0063] Figure 5 is a graph showing pull-down resistance values ​​(labeled here with reference symbol “RPD”).

[0064] Reference Figure 5 During the first termination mode, the pull-down driving circuit DC2 can adjust the pull-down resistance value RPD so that the pull-down resistance value RPD corresponds to the target resistance value TRPD. When the pull-down resistance value RPD meets the target resistance value TRPD, the change in the pull-down resistance value RPD according to the change in the second pull-down control signal PD_TR<1:N>, that is, the change in each step is relatively small, that is, the slope of the solid line is relatively gentle, therefore, the pull-down tuning circuit PC2 can maintain the default value reflected in the pull-down resistance value RPD, and no additional tuning can be performed on the pull-down resistance value RPD.

[0065] During the second termination mode, the pull-down drive circuit DC2 can adjust the pull-down resistance value RPD so that the pull-down resistance value RPD corresponds to the target resistance value TRPD. According to the prior art, during the second termination mode, when the pull-down resistance value RPD meets the target resistance value TRPD, that is, when the pull-down resistance value RPD is consistent with the target resistance value TRPD, the change amount of the pull-down resistance value RPD according to the change amount of the second pull-down control signal PD_TR<1:N>, that is, the change amount of each step may be relatively large, that is, the slope of the double dotted line may be relatively steep. This is because, compared with the amount of current flowing through the pull-down drive circuit DC2 in each step in the first termination mode, the amount of current flowing through the pull-down drive circuit DC2 in each step in the second termination mode increases. Therefore, according to this embodiment, during the second termination mode, the pull-down tuning circuit PC2 can reflect an additional resistance value different from the default value in the pull-down resistance value RPD. For example, the additional resistance value may be less than the default value. According to this embodiment, during the second termination mode, when the pull-down resistance value RPD satisfies the target resistance value TRPD, that is, when the pull-down resistance value RPD is consistent with the target resistance value TRPD, the pull-down resistance value RPD can be tuned so that the change in the pull-down resistance value RPD according to the change in the second pull-down control signal PD_TR<1:N>, that is, the change in each step becomes relatively small, that is, the slope of the single-point dashed line becomes relatively gentle.

[0066] According to the present embodiment, the pull-up resistance value and the pull-down resistance value applied to the data pad can be optimally tuned according to various termination modes.

[0067] Figure 6 It shows that the application Figure 1 1 is a block diagram of a semiconductor system 10000 of a semiconductor device 100 .

[0068] Reference Figure 6 , the semiconductor system 10000 may include a memory system 1100 storing data and a host 2000 controlling the memory system 1000. The memory system 1000 may include a memory device 1100 storing data, a buffer memory 1300 for temporarily storing data required for the operation of the memory system 1000, and a memory controller 1200 controlling the memory device 1100 and the buffer memory 1300 according to a request from the host 2000.

[0069] The host 2000 may communicate with the memory system 1000 by using at least one of various communication standards or interfaces such as: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0070] The memory device 1100 may be implemented as a volatile memory device in which data is lost when power is cut off, or a non-volatile memory device in which data is retained even if power is cut off. The memory device 1100 may perform a programming operation (or a write operation), a read operation, or an erase operation under the control of the memory controller 1200. For example, during a programming operation, the memory device 1100 may receive a command, an address, and data from the memory controller 1200, and perform a programming operation. During a read operation, the memory device 1100 may receive a command and an address from the memory controller 1200, and output read data to the memory controller 1200. To this end, the memory device 1100 may include an interface circuit for inputting and outputting data. The memory device 1100 may correspond to Figure 1 The semiconductor device 100 shown in FIG.

[0071] The memory controller 1200 may generally control the operation of the memory system 1000 and control data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 may control the memory device 1100 to program, read, or erase data according to a request from the host 2000. In addition, the memory controller 1200 may receive data and a logical address from the host 2000, and convert the logical address into a physical address indicating an area where the data will actually be stored in the memory device 1100. In addition, the memory controller 1200 may store a logical-to-physical address mapping table constituting a mapping relationship between a logical address and a physical address in the buffer memory 1300.

[0072] The buffer memory 1300 may be used as an operation memory or a cache memory of the memory controller 1200, and store system data other than the above information used in the memory system 1000. According to an embodiment, the buffer memory 1300 may include a double data rate synchronous dynamic random access memory (DDR SDRAM), a DDR4 SDRAM, a fourth generation low power double data rate (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), or a Rambus dynamic random access memory (RDRAM).

[0073] According to an embodiment of the present disclosure, a pull-up resistance value and a pull-down resistance value applied to a data pad can be optimally tuned according to various termination modes, which makes it possible to minimize current consumption.

[0074] According to an embodiment of the present disclosure, a circuit for optimally adjusting a pull-up resistance value and a pull-down resistance value may be designed not to be directly connected to a data pad, and thus the capacitance of the data pad may not be further increased by the above circuit.

[0075] According to the embodiments of the present disclosure, a circuit can be designed only by simple logic circuits and active elements, which makes it possible to minimize the increased area.

[0076] Although the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for illustration and are not intended to be limiting. In addition, it should be noted that, as will be appreciated by those skilled in the art from the present disclosure, the present disclosure may be implemented in various ways by substitutions, changes and modifications falling within the scope of the claims. Furthermore, these embodiments may be combined to form additional embodiments.

Claims

1. An interface circuit, comprising: Data pad; a first driving circuit connected between the data pad and a first power supply node, adjusting a first resistance value applied between the data pad and the first power supply node according to a termination mode, and selectively driving the data pad using a first power supply voltage; as well as A first tuning circuit is connected between the first power supply node and a first voltage supply terminal and tunes the first resistance value according to the termination mode.

2. The interface circuit according to claim 1, wherein: The first driving circuit comprises: a first driver independently controlled according to one of the termination modes; and A plurality of second drivers are controlled together according to the termination mode.

3. The interface circuit according to claim 1, wherein: The first tuning circuit includes a plurality of third drivers connected in parallel between the first voltage supply terminal and the first power supply node and selectively operated according to the termination mode based on a plurality of first control signals.

4. The interface circuit according to claim 1, wherein: During a power-down mode, the first tuning circuit electrically disconnects the first voltage supply terminal from the first supply node.

5. The interface circuit according to claim 1, further comprising: a second driving circuit connected between the data pad and a second power supply node, adjusting a second resistance value applied between the data pad and the second power supply node according to the termination mode, and selectively driving the data pad using a second power supply voltage; as well as A second tuning circuit is connected between the second power supply node and a second voltage supply terminal and tunes the second resistance value according to the termination mode.

6. The interface circuit according to claim 5, wherein: The second driving circuit comprises: a fourth driver independently controlled according to one of the termination modes; and A plurality of fifth drivers are controlled together according to the termination mode.

7. The interface circuit according to claim 5, wherein: The second tuning circuit includes a plurality of sixth drivers connected in parallel between the second power supply node and the second voltage supply terminal and selectively operated according to the termination mode based on a plurality of second control signals.

8. The interface circuit according to claim 5, wherein: During the power-off mode, the second tuning circuit electrically disconnects the second supply node from the second voltage supply terminal.

9. An interface circuit comprising: Data pad; an output circuit connected to the data pad, adjusting a pull-up resistance value and a pull-down resistance value applied to the data pad according to a termination mode, and outputting output data corresponding to a selection mode among the termination modes through the data pad; as well as A tuning circuit is connected to the output circuit and tunes the pull-up resistance value and the pull-down resistance value according to the termination mode.

10. The interface circuit according to claim 9, wherein: The output circuit comprises: a pull-up driving circuit connected between the data pad and a first power supply node, adjusting the pull-up resistance value according to the selection mode, and pull-up driving the data pad using a first power supply voltage based on a first pull-up control signal and a second pull-up control signal; and The pull-down driving circuit is connected between the data pad and a second power supply node, adjusts the pull-down resistance value according to the selection mode, and pulls down the data pad using a second power supply voltage based on a first pull-down control signal and a second pull-down control signal.

11. The interface circuit according to claim 10, wherein: The pull-up driving circuit comprises: a first pull-up driver independently controlled in a predetermined mode of the termination mode based on the first pull-up control signal; and A plurality of second pull-up drivers are commonly controlled in the termination mode based on the second pull-up control signal.

12. The interface circuit according to claim 10, wherein: The pull-down driving circuit comprises: a first pull-down driver independently controlled in a predetermined mode in the termination mode based on the first pull-down control signal; and A plurality of second pull-down drivers are commonly controlled in the termination mode based on the second pull-down control signal.

13. The interface circuit according to claim 9, wherein: The tuning circuit comprises: a pull-up tuning circuit connected between a first power supply node connected to the output circuit and a high voltage power supply terminal and tuning the pull-up resistance value according to the termination mode; and The pull-down tuning circuit is connected between a second power supply node connected to the output circuit and a low voltage power supply terminal, and tunes the pull-down resistance value according to the termination mode.

14. The interface circuit according to claim 13, wherein: The pull-up tuning circuit includes a plurality of third pull-up drivers connected in parallel between the high voltage power terminal and the first power node and selectively operated according to the termination mode based on a plurality of third pull-up control signals.

15. The interface circuit according to claim 13, wherein: During a power-down mode, the pull-up tuning circuit electrically disconnects the high voltage supply terminal from the first supply node.

16. The interface circuit according to claim 13, wherein: The pull-down tuning circuit includes a plurality of third pull-down drivers connected in parallel between the second power supply node and the low voltage power supply terminal and selectively operated according to the termination mode based on a plurality of third pull-down control signals.

17. The interface circuit according to claim 13, wherein: During a power-off mode, the pull-down tuning circuit electrically disconnects the second power supply node from the low voltage power supply terminal.

18. A semiconductor device comprising: a control circuit that generates first to third pull-up control signals and first to third pull-down control signals corresponding to a termination mode and a power-off mode based on data, a first mode signal and a second mode signal, a plurality of first fine-tuning code signals and a second fine-tuning code signal, and a power gate signal; as well as An interface circuit, wherein the interface circuit: adjusting a pull-up resistance value and a pull-down resistance value applied to the data pad according to the termination mode based on the first pull-up control signal and the second pull-up control signal and the first pull-down control signal and the second pull-down control signal; selectively tuning the pull-up resistance value and the pull-down resistance value according to a selection mode among the termination modes based on the third pull-up control signal and a plurality of third pull-down control signals; and The interface outputs data corresponding to the data.

19. The semiconductor device according to claim 18, wherein: The control circuit comprises: a first control logic circuit, generating the first pull-up control signal based on the data and the first mode signal; a second control logic circuit, generating the second pull-up control signal based on the data and a plurality of first fine-tuning code signals; a third control logic circuit, generating the first pull-down control signal based on the data and a plurality of second fine-tuning code signals; a fourth control logic circuit, generating the second pull-down control signal based on the data and the plurality of second fine-tuning code signals; and The fifth control logic circuit generates a plurality of third pull-up control signals and a plurality of third pull-down control signals based on the first mode signal, the second mode signal and the power gate signal.

20. The semiconductor device according to claim 18, wherein The interface circuit comprises: a pull-up driving circuit connected between the data pad and a first power supply node, adjusting the pull-up resistance value according to the selection mode, and pull-up driving the data pad using a first power supply voltage based on the first pull-up control signal and the second pull-up control signal; a pull-down driving circuit connected between the data pad and a second power supply node, adjusting the pull-down resistance value according to the selection mode, and pull-down driving the data pad using a second power supply voltage based on the first pull-down control signal and the second pull-down control signal; a pull-up tuning circuit connected between the first power supply node connected to the pull-up driving circuit and a terminal supplying the first power supply voltage, and tuning the pull-up resistance value according to the termination mode; and A pull-down tuning circuit is connected between the second power supply node connected to the pull-down driving circuit and a terminal supplying the second power supply voltage, and tunes the pull-down resistance value according to the termination mode.

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