Winding structure and power converter

Abstract

The invention provides a winding structure which comprises a circuit board with a plurality of sub-layers and a winding circuit arranged in the circuit board. The winding circuit comprises a plurality of single-layer coils, different single-layer coils are arranged in different sub-layers, and all the single-layer coils are located in the same relative positions in the sub-layers where the single-layer coils are located; wherein the plurality of single-layer coils form a plurality of turns of primary windings and a plurality of turns of secondary windings; two adjacent pairs are formed in the plurality of single-layer coils, and each adjacent pair comprises two single-layer coils which are respectively positioned in two adjacent sub-layers and respectively belong to the primary winding and the secondary winding. The invention also provides a power converter.

Description

Technical Field

[0001] The present disclosure relates to the technical field of power conversion, and in particular to a winding structure and a power converter. Background Art

[0002] Common-mode electromagnetic interference (EMI) noise is generated during the operation of the planar transformer. It is desirable to suppress the common-mode noise by improving the planar transformer itself, thereby eliminating the need to set up filters.

[0003] However, the existing noise reduction structure of the planar transformer has a limited scope of application, cannot completely eliminate the common mode noise, and will increase the volume and loss of the planar transformer. Summary of the invention

[0004] The present invention provides a winding structure and a power converter.

[0005] In a first aspect, an embodiment of the present disclosure provides a winding structure, comprising a circuit board having a plurality of sub-layers, and a winding circuit disposed in the circuit board; the winding circuit comprises a plurality of single-layer coils, different single-layer coils are disposed in different sub-layers, and all the single-layer coils are in the same relative position in their respective sub-layers; wherein,

[0006] A plurality of the single-layer coils constitute a multi-turn primary winding and a multi-turn secondary winding;

[0007] Two adjacent pairs are formed among the plurality of single-layer coils, and each of the adjacent pairs includes two single-layer coils respectively located in two adjacent sub-layers and belonging to the primary winding and the secondary winding respectively.

[0008] In a second aspect, an embodiment of the present disclosure provides a power converter, comprising:

[0009] Any winding structure of the embodiments of the present disclosure.

[0010] In the disclosed embodiment, common-mode noise shielding is achieved by making the primary winding and the secondary winding "adjacent" in a specific manner. It is independent of the potential static point and has a wide range of applications (such as full-bridge topology). It also has a good shielding effect and can completely eliminate common-mode noise. At the same time, there is no need to set a shielding layer or filter, which will not increase the volume (such as the number of layers or thickness of a circuit board) and loss of the power converter, making it easy to achieve miniaturization and high power density, thereby reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings of the embodiments of the present disclosure:

[0012] Figure 1A schematic cross-sectional structure diagram of a winding structure provided in an embodiment of the present disclosure;

[0013] Figure 2 A schematic cross-sectional view of another winding structure provided in an embodiment of the present disclosure;

[0014] Figure 3 A schematic cross-sectional view of another winding structure provided in an embodiment of the present disclosure;

[0015] Figure 4 A schematic cross-sectional view of another winding structure provided in an embodiment of the present disclosure;

[0016] Figure 5 It is a cross-sectional structural schematic diagram of a winding structure in the related art;

[0017] Figure 6 A block diagram of a power converter provided by an embodiment of the present disclosure;

[0018] Figure 7 is a circuit diagram of a full-bridge transformer;

[0019] Figure 8 for Figure 7 The common mode noise spectrum of the full-bridge transformer with different winding circuits;

[0020] Fig. 9 A common mode noise transmission path in a planar transformer;

[0021] Fig.10 A simplified noise model for a planar transformer;

[0022] Fig.11 A voltage distribution of a winding circuit in a planar transformer;

[0023] Fig.12 It is a two-capacitor model of a planar transformer;

[0024] In the embodiments of the present disclosure, the meanings of the reference numerals include:

[0025] 1. Circuit board; 11. Sub-layer; 12. Sub-board; 19. Conductive through hole; 2. Single-layer coil; 29. ​​Adjacent pair; P. Primary winding; S. Secondary winding. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the winding structure and the power converter provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0027] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0028] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0029] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0030] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0031] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0033] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0034] As a key component for energy transmission of isolated power converters, planar transformers have the advantages of small size, high energy density and low cost, and are widely used in fields such as switching power supplies. Switching power supplies are widely used as power supplies for wireless communication base stations due to their small size and high efficiency.

[0035] With the use of wide-bandgap power electronic devices such as silicon carbide and gallium nitride, power converters are also developing towards high frequency, high density, and high electromagnetic interference. However, power electronic devices often cause large electromagnetic interference (EMI) noise during high-speed turn-on / off processes, affecting the operation of other equipment and polluting the power grid.

[0036] For example, a large number of power electronic devices (such as MOS tubes) are installed in the planar transformer. Therefore, as the frequency increases, the physical isolation of the planar transformer can no longer completely block the transmission of noise, so the planar transformer carries a key link in the common-mode noise path. Therefore, multi-order filters can be set up in engineering to achieve noise suppression for the planar transformer, but since a separate filter is required, the overall volume and cost of the planar transformer (including the filter) increase, and the power density decreases.

[0037] Therefore, if the common-mode noise can be directly suppressed by optimizing the structure of the planar transformer without using a filter, the power converter can be further miniaturized and its cost can be reduced.

[0038] In some related technologies, a shielding winding that is grounded or connected to a static point of the primary side may be added between the primary winding and the secondary winding of the planar transformer to act as a shielding layer in an attempt to block the common-mode noise generated by the primary side noise source.

[0039] However, a potential static point shielding winding must exist in the planar transformer in order to be connected to it. Therefore, in a topology without a potential static point (such as a full-bridge topology), even if a shielding winding is used, it is still difficult to reduce noise or the noise reduction effect is poor, that is, the scope of application of the shielding winding is limited.

[0040] Moreover, when the shielded winding is connected to the primary quiet point, although it can effectively suppress the common-mode noise generated by the primary noise source, it still cannot prevent the common-mode noise generated by the secondary noise source from propagating to the primary side through the parasitic capacitance, so it cannot completely eliminate the common-mode noise on the primary and secondary sides.

[0041] In addition, providing a shielding winding will inevitably increase the volume (thickness) of the planar transformer and increase the loss of the planar transformer, which is not conducive to the miniaturization of the power converter and the improvement of the power density.

[0042] First, refer to Figures 1 to 4 , an embodiment of the present disclosure provides a winding structure.

[0043] The embodiments of the present disclosure provide a winding structure, which can be connected to a location where other circuits need to use a winding, and serve as a winding device for other circuits.

[0044] Reference Figure 1 The winding structure of the embodiment of the present disclosure includes a circuit board 1 having multiple sub-layers 11, and a winding circuit arranged in the circuit board 1; the winding circuit includes multiple single-layer coils 2, different single-layer coils 2 are arranged in different sub-layers 11, and all single-layer coils 2 are in the same relative position in their respective sub-layers 11.

[0045] Multiple single-layer coils 2 constitute a multi-turn primary winding P and a multi-turn secondary winding S; two adjacent pairs 29 are formed among the multiple single-layer coils 2, and each adjacent pair 29 includes two single-layer coils 2 respectively located in two adjacent sub-layers 11 and belonging to the primary winding P and the secondary winding S respectively.

[0046] The winding structure of the embodiment of the present disclosure is based on a circuit board 1, or a printed circuit board 1 (PCB, Print Circuit Board), and therefore belongs to a "planar winding structure".

[0047] Among them, the circuit board 1 is divided into multiple "sub-layers 11", that is, the circuit board 1 includes multiple stacked sub-boards 12 of insulating material, and the areas between adjacent sub-boards 12 and both sides of all sub-boards 12 are the "sub-layers 11" used to set up circuits. The structures in different sub-layers 11 can be electrically connected to each other through conductive through holes 19 in the sub-boards 12.

[0048] The winding circuit is arranged in the above circuit board 1, and the winding circuit includes multiple single-layer coils 2 ("one circle" lead of the winding), and different single-layer coils 2 are arranged in different sub-layers 11. Each single-layer coil 2 is a routing of a certain shape (such as a copper foil routing) in its sub-layer 11, and the relative position of each single-layer coil 2 in its respective sub-layer 11 is the same, that is, if there is a plane parallel to the main body of the circuit board 1, the orthographic projections of all single-layer coils 2 in the plane coincide, so the winding circuit is equivalent to being composed of multiple stacked and insulated coils.

[0049] Among them, multiple single-layer coils 2 located in different sub-layers 11 are electrically connected to each other to form a "winding"; the winding in the winding circuit includes a "primary winding P (primary winding)" located on the first side and a "secondary winding S (secondary winding)" located on the second side, wherein each winding has "multiple turns", wherein multiple single-layer coils 2 are multi-turn windings if connected in series, and are one-turn windings if connected in parallel (winding in parallel).

[0050] Reference Figure 1All the single-layer coils 2 in the disclosed embodiment form two "adjacent pairs 29", that is, there are only two single-layer coils 2 in the primary winding P, which are respectively in adjacent sub-layers 11 with one single-layer coil 2 in the secondary winding S; correspondingly, there are also only two single-layer coils 2 in the secondary winding S, which are respectively in adjacent sub-layers 11 with one single-layer coil 2 in the primary winding P.

[0051] It has been found through research that when the primary winding P and the single-layer coil 2 in the secondary winding S are adjacent to each other in the above manner, the distributed capacitance can be reduced, thereby better eliminating common mode noise.

[0052] In some related technologies, reference Figure 5 The primary winding P and the secondary winding S are adjacent to each other in a "fully staggered" manner, that is, in each sub-layer 11 along the thickness direction of the circuit board 1, the single-layer coil 2 of the primary winding P and the single-layer coil 2 of the secondary winding S are "alternatingly" arranged, and each single-layer coil 2 is adjacent to a single-layer coil 2 of another winding.

[0053] Therefore, compared with the related art of the “full interleaved” structure, the winding structure of the embodiment of the present disclosure has small distributed capacitance and low common mode noise.

[0054] It should be understood that the winding structure may also include other structures, such as a planarized magnetic core or iron core passing through each single-layer coil 2, which will not be described in detail here.

[0055] In the embodiment of the present disclosure, common-mode noise shielding is achieved by making the primary winding P and the secondary winding S "adjacent" in a specific manner. It is independent of the potential static point and has a wide range of applications (such as full-bridge topology). It also has a good shielding effect and can completely eliminate common-mode noise. At the same time, there is no need to set a shielding layer or filter, which will not increase the volume (such as the number of layers or thickness of the circuit board 1) and loss of the power converter, and it is easy to achieve miniaturization and high power density, thereby reducing costs.

[0056] In some embodiments, each turn of the primary winding P includes a single-layer coil 2 ; each turn of the secondary winding S includes a plurality of single-layer coils 2 connected in parallel.

[0057] As one embodiment of the present disclosure, each turn of the primary winding P can be “a” single-layer coil 2, for example, Figures 1 to 4 , six single-layer coils 2 are connected in series to form six turns of primary winding P (P1-P6); in contrast, each turn of secondary winding S includes multiple single-layer coils 2 connected in parallel, that is, the secondary winding S adopts a "parallel winding" method, for example, refer to Figures 1 to 4 , four single-layer coils 2 are wound together to form one turn of the secondary winding S, so that the eight single-layer coils 2 form a total of two turns of the secondary winding S (S1~S2).

[0058] In some embodiments, all single-layer coils 2 are arranged in a plurality of consecutive sub-layers 11 .

[0059] As one method of the embodiment of the present disclosure, all sub-layers 11 where all single-layer coils 2 of all windings are located can be continuously distributed, for example, Figures 1 to 4 The primary winding P and the secondary winding S have a total of eight turns, specifically fourteen single-layer coils 2 , which are distributed in fourteen consecutive sub-layers 11 .

[0060] It should be understood that the embodiments of the present disclosure are not limited thereto. For example, the circuit board 1 may also include a sub-layer 11 without a single-layer coil for setting other circuit structures.

[0061] In some embodiments, the distance between the sub-layers 11 where the two single-layer coils 2 of one adjacent pair 29 are located is equal to the distance between the sub-layers 11 where the two single-layer coils 2 of another adjacent pair 29 are located.

[0062] It has been found through research that better noise reduction effect can be achieved if the spacing between "multiple pairs" of adjacent single-layer coils 2 (adjacent pairs 29) belonging to different windings in the winding structure is the same.

[0063] In the embodiment of the present disclosure, there are two adjacent pairs, so it is sufficient to control the distance between the "two pairs" of single-layer coils 2 (the spacing between the sub-layers 11 and the thickness of the sub-plate 12) to be equal; in contrast, in the related art Figure 5 The "full interlaced" method requires precise control of the thickness of many sub-plates 12, so the winding structure process of the embodiment of the present disclosure is easy to implement with low difficulty.

[0064] In some embodiments, in two adjacent pairs 29, the sum of the number of turns of the two single-layer coils 2 belonging to the primary winding P in the primary winding P is subtracted from the sum of the number of turns of the two single-layer coils 2 belonging to the secondary winding S in the secondary winding S, and the difference obtained is equal to the difference between the total number of turns of the primary winding P and the total number of turns of the secondary winding S.

[0065] As one method of the embodiment of the present disclosure, if the “number of turns” of the single-layer coils 2 in the adjacent pairs 29 in their respective windings meets certain requirements, the noise reduction effect will be better.

[0066] Specifically, assuming that in two adjacent pairs 29, the single-layer coil 2 of the m1-th turn primary winding P is adjacent to the single-layer coil 2 of the n1-th turn secondary winding S, and the single-layer coil 2 of the m2-th turn primary winding P is adjacent to the single-layer coil 2 of the n2-th turn secondary winding S, then the above m1, n1, m2, and n2 should satisfy the formula:

[0067] (m1-n2)+(m2-n2)=N p -N s ;

[0068] Among them, N p 、N s is the “turn ratio” of the winding circuit, that is, the total number of turns of the primary winding P and the secondary winding S respectively.

[0069] For example, refer to Figures 1 to 4 , assuming the turns ratio is 6:2, that is, the total number of turns of the primary winding P is six turns (P1~P6), and the total number of turns of the secondary winding S is a number of turns (S1~S2); then refer to Figure 1 , the single-layer coil 2 of the first turn of the primary winding P is adjacent to a single-layer coil 2 of the first turn of the secondary winding S, and the single-layer coil 2 of the sixth turn of the primary winding P is adjacent to a single-layer coil 2 of the second turn of the secondary winding S, so the above formula is equivalent to: (1-1)+(6-2)=6-2.

[0070] It should be understood that Figure 1 This is just a specific example that satisfies the above formula, and the parameters in the above formula may also be in other forms.

[0071] For example, in N p 6, N s When it is 2, you can also refer to Figure 3 , m1 is 2, n1 is 2, m2 is 5, n2 is 1; or you can refer to Figure 4 , m1 is 2, n1 is 1, m2 is 5, n2 is 2, etc., which will not be described in detail here.

[0072] It should be understood that the "number of turns" of the above windings is based on the series connection sequence (current sequence) of the turns in the windings, and the reference Figures 2 to 4 It is not necessarily required that the numbering of each turn of the winding is arranged in the thickness direction of the circuit board 1, but it is sufficient as long as the arrangement of each turn of the winding can satisfy the above formula.

[0073] In some embodiments, all single-layer coils 2 of the multi-turn primary winding P are arranged in multiple continuous sub-layers 11; the multi-turn secondary winding S is divided into two groups, and the sub-layers 11 where the single-layer coils 2 of the two groups of secondary windings S are located are respectively located on both sides of the multiple continuous sub-layers 11 where all the single-layer coils 2 of the primary winding P are located.

[0074] As one embodiment of the present disclosure, refer to Figure 1 , Figure 3To meet the requirements of the above formula, multiple turns of the primary winding P may be arranged continuously together (i.e., the single-layer coils 2 of the multiple turns of the primary winding P are located in multiple continuous sub-layers 11), and the multiple turns of the secondary winding S are respectively located on both sides of the primary winding P (for example, when the secondary winding S has two turns, one turn of the secondary winding S may be provided on each side of the primary winding P), so that the "outermost" two turns of the single-layer coils 2 of the primary winding P form adjacent pairs 29 with the "innermost" two single-layer coils 2 of the secondary winding S.

[0075] In some embodiments, all single-layer coils 2 of the multi-turn secondary winding S are arranged in multiple continuous sub-layers 11; the multi-turn primary winding P is divided into two groups, and the sub-layers 11 where the single-layer coils 2 of the two groups of primary windings P are located are respectively located on both sides of the multiple continuous sub-layers 11 where all the single-layer coils 2 of the secondary winding S are located.

[0076] As another embodiment of the present disclosure, it is also possible to refer to Figure 2 , Figure 4 To meet the requirements of the above formula, the multi-turn secondary winding S is arranged continuously (i.e., the single-layer coils 2 of the multi-turn secondary winding S are located in multiple continuous sub-layers 11), and the multi-turn primary winding P is located on both sides of the secondary winding S (for example, when the primary winding P has six turns, there can be three turns of the primary winding P on each side of the secondary winding S), so that the two "outermost" single-layer coils 2 of the secondary winding S form adjacent pairs 29 with the "innermost" two single-layer coils 2 of the primary winding P.

[0077] Reference Figures 1 to 4 It can be seen that in the above two methods, one winding is divided into two parts (two groups), and the other winding has the two parts "sandwiched" between them, so its form is similar to a "sandwich", which can also be called a "sandwich" structure.

[0078] That is, in the winding structure of the embodiment of the present disclosure, it is equivalent to replacing the "full interleaved" structure of the winding circuit in the related art with a "sandwich" structure.

[0079] Second, refer to Figure 6 , the present disclosure provides a power converter, comprising:

[0080] Any winding structure of the embodiments of the present disclosure.

[0081] The above winding structure can be used as a winding device in a "power converter".

[0082] In some embodiments, the power converter is a planar power converter; the planar power converter includes a power conversion circuit, which is disposed in a circuit board of the winding structure and is electrically connected to the winding circuit of the winding structure.

[0083] As one mode of an embodiment of the present disclosure, the above power converter may specifically be a planar power converter, that is, other circuits in the power converter except the winding circuit (power conversion circuit) are also arranged in the above circuit board (that is, the devices of the power conversion circuit are also arranged in each sublayer of the circuit board), and the power conversion circuit is electrically connected to the winding circuit in the circuit board in a required manner.

[0084] In some embodiments, the power converter includes a transformer.

[0085] As one mode of an embodiment of the present disclosure, the power converter may specifically be a transformer, that is, the above winding structure may be applicable to a transformer (especially a planar transformer).

[0086] In some embodiments, the transformer comprises a full-bridge transformer or a two-switch forward transformer.

[0087] Furthermore, the above transformer may be a transformer without a potential static point, such as a full-bridge transformer, a double-tube forward transformer, etc.

[0088] Among them, the specific circuit forms of the transformer are various. For example, the circuit diagram of the full-bridge transformer can be used as a reference. Figure 7 form.

[0089] In the above full-bridge transformer, if the winding structure adopts the "full interleaved" structure in the related art, it can be known through simulation calculation that the distributed capacitance between the second side and the two ends of the first side is 225.38pF and 456.84pF respectively; conversely, if the winding structure adopts the form of the embodiment of the present disclosure, it can be known through simulation calculation that the distributed capacitance between the second side and the two ends of the first side is 28.9pF and 58.1pF respectively.

[0090] When the winding structure adopts the "full interleaved" structure of the related art and the "sandwich" structure of the embodiment of the present disclosure, the spectrum of the common mode noise is simulated and obtained respectively. The results refer to Figure 8 .

[0091] It can be seen that the winding structure ("sandwich" structure) of the embodiment of the present disclosure can greatly reduce the distributed capacitance, thereby significantly reducing the even harmonics (by about 18dB), and basically reducing the odd harmonics to the bottom noise, which is equivalent to reducing the common mode noise to 0, thereby completely eliminating the common mode noise.

[0092] It should be understood that the power converter of the embodiment of the present disclosure is not limited to the above examples, and may also be other forms of transformers or other types of power converters.

[0093] Example:

[0094] The following is an exemplary introduction to a planar transformer (planar power converter) and a design method thereof according to an embodiment of the present disclosure.

[0095] The design process of the planar transformer may include:

[0096] (A) Analysis of noise transmission mechanism

[0097] The planar transformer adopts a full-bridge circuit. If the switch tube of the full-bridge circuit adopts a surface-mount device, its common-mode noise transmission path can be referred to Fig. 9 The common-mode noise current starts from points A and B of the primary winding port of the planar transformer, passes through the distributed capacitance between the primary and secondary windings of the planar transformer to reach points C and D of the secondary winding port, passes through the two noise sources VT6 and VT8 on the secondary side, and then returns to the primary side along EFGIJK and EFGK.

[0098] (B) Modeling of noise sources and noise transmission

[0099] right Fig. 9 After analyzing and simplifying the common-mode noise transmission path, the switch tube is equivalent to a voltage source according to the substitution theorem, and the simplified noise model is obtained. Fig.10 , where Rcm is the LISN (Line Impedance Stabilization Network) common mode equivalent resistance of 25Ω.

[0100] From this, it can be seen that the common-mode conduction capacitors C1 and C2 are the main path impedances, and their size is determined by the winding structure of the planar transformer, specifically by the relative area of ​​the turns of the primary and secondary windings, the spacing of the turns (the distance between sub-layers), the dielectric constant (i.e. the dielectric constant of the sub-board), etc.

[0101] Among them, there are four noise sources in the full-bridge circuit, and each noise source has odd-order noise and even-order noise. Therefore, Fourier decomposition and analysis of the noise source plays an important role in the subsequent optimization design.

[0102] Therefore, the prototype is connected to the rated load to make it work under rated working conditions, and the differential probe is connected through the oscilloscope to measure the time domain waveform of the noise source with two noise sources as a group. The measured time domain waveform of the noise source is decomposed by Fourier, and the decomposition results are sorted and analyzed.

[0103] (C) Noise source characteristics analysis

[0104] Based on the measured time domain waveform of the full-bridge circuit noise source, the amplitude and phase of each noise source are obtained through Fourier decomposition. According to the Fourier decomposition results, it can be obtained:

[0105]

[0106] In formula (1), V 2odd 、V4odd 、V 6od d and V 8odd Respectively represent the odd harmonic amplitudes of noise sources v2, v4, v6 and v8; V 2even 、V 4even 、V 6even and V 8even They represent the even harmonic amplitudes of noise sources v2, v4, v6 and v8 respectively.

[0107] Furthermore, the phase angle relationship between the noise sources can be expressed as:

[0108]

[0109]

[0110] Formula (2) represents the phase relationship of the odd-order noise sources of the full-bridge circuit noise source, where and Respectively represent the odd harmonic phase angles of noise sources v2, v4, v6 and v8; is θ1, and The phase difference is λ1, and The phase difference is λ2, and The phase difference is λ3.

[0111] Equation (3) represents the phase relationship of the even-order noise source of the full-bridge circuit noise source, where and Respectively represent the even harmonic phase angles of noise sources v2, v4, v6 and v8. is θ2, and The phase difference is λ4, and Phase difference λ5, and The phase difference is λ6.

[0112] Combining the transformer ratio and the noise transmission path, the amplitude relationship between the primary and secondary noise sources can be obtained as follows:

[0113]

[0114]

[0115] According to the simplified noise model, combined with the noise source characteristics and transformer ratio, the KVL equation can be written to obtain the odd harmonic noise:

[0116]

[0117] In formula (6) Denotes the angular frequency as ω odd The total mode noise current, ω odd Indicates the angular frequency of odd harmonics, V p_odd Represents the amplitude of odd harmonics of the primary voltage of the planar transformer, n p and n s (Some positions are represented by Np and Ns) respectively represent the number of turns of the primary and secondary windings of the planar transformer.

[0118] When the power parameters of the circuit are determined, ω odd 、V p_odd 、n p and n s They are all uniquely determined, and the only things that can be changed are the sizes of C1 and C2.

[0119] Therefore, as long as we let As small as possible, the odd-order common-mode noise current can be reduced.

[0120] The even harmonic noise is:

[0121]

[0122] In formula (7) Represents the angular frequency as ω even The total mode noise current, ω even represents the angular frequency of even harmonics, represents the even harmonic phasor of the noise source v2, Represents the even harmonic phasors of the noise source v8.

[0123] When the power parameters of the circuit are determined, ω even , n p and n s They are all uniquely determined, and the only things that can be changed are the sizes of C1 and C2.

[0124] Therefore, it can also be seen that the smaller (C1+C2), the smaller the even-order common-mode noise current.

[0125] (D) Winding structure design

[0126] According to the above transmission mechanism of common-mode noise of planar transformer, the common-mode noise of planar transformer is mainly transmitted through the distributed capacitance between the primary winding and the secondary winding.

[0127] Among them, the single-layer coil in the winding of the planar transformer is actually the routing in the circuit board (PCB) (such as copper foil routing), so the spacing d between the turns of the primary and secondary windings is the distance between adjacent sub-layers of the PCB, that is, the thickness of the sub-board. For a planar transformer with only one single-layer coil in each sub-layer, considering the current flow factor, the wiring width w of the single-layer coil is generally much larger than d, so the distributed capacitance between the turns of the primary and secondary windings can be approximately regarded as a parallel plate capacitor, ignoring the edge effect, and its capacitance value C0 can be expressed as:

[0128]

[0129] In formula (8), ε r is the dielectric constant of the filling material between the sub-layers of the PCB (i.e. the material of the sub-board), ε0 is the dielectric constant in a vacuum, S is the area between turns, and d is the distance between turns (the distance between sub-layers, i.e. the thickness of the sub-board).

[0130] Assume that the planar transformer is in a certain working state, and the high potential of the primary winding is v ph , the primary winding low potential is v pl At the same time, due to the magnetic coupling between the primary and secondary windings of the planar transformer, an induced voltage will be generated on the secondary winding, forming a potential distribution on the secondary winding, so the high potential of the secondary winding is v sh , the secondary winding low potential is v sl .

[0131] As a result, there is a potential difference between the primary and secondary windings, thus forming an electric field distribution. At the same time, the overlapping area between the turns of the primary and secondary windings forms the above distributed capacitance C0. Therefore, when the potential on the primary and secondary windings of the planar transformer changes, the charge Q stored on the distributed capacitance C0 changes accordingly, and a common-mode noise current is generated.

[0132] According to the principle of electrostatic induction, the above charge Q satisfies:

[0133]

[0134] For example, assume that the turns ratio of the planar transformer is 6:2, that is, the primary winding is 6 turns (P1~P6), the secondary winding is 2 turns (S1~S2), and each turn is wound in 4 layers (that is, 4 single-layer coils in 4 sub-layers are connected in parallel).

[0135] Therefore, the charge stored between any adjacent turns of the primary and secondary windings can be expressed as:

[0136] Q p1s1 =C p1s1 (v p1m -v s1m ) (10);

[0137] In formula (10), Q p1s1 represents the charge stored between P1 and S1, C p1s1 represents the structural capacitance between P1 and S1, v p1m represents the midpoint voltage of P1, v s1m Indicates the midpoint voltage of S1.

[0138] Therefore, refer to Figure 5 When the primary and secondary windings adopt the "full interleaved" structure in the related technology, the charge Q stored between the primary and secondary windings of the entire planar transformer is all It can be expressed as:

[0139] Q all =Q p1s1 +Q p2s1 +Q p3s1 +Q p4s2 +Q p5s2 +Q p6s2 (11);

[0140] According to the above relationship between voltage ratio and turns ratio, the voltage drop per turn Δvp of the primary winding of the planar transformer is the same as the voltage drop per turn Δvs of the secondary winding. If the voltage drop per turn is Δv, then:

[0141]

[0142] Reference Fig.11 To distribute the voltage of a planar transformer winding, we only need to select the voltage at a certain point on the primary winding of the planar transformer as the voltage reference point. The potential at any other point can be expressed by the voltage reference point and the voltage drop per turn Δv.

[0143] If any point inside the winding is used as a voltage reference point, the model of the planar transformer needs to be split during modeling, which complicates the modeling. In order to simplify the model, the four endpoints A, B, C, and D of the planar transformer are used as alternative voltage reference points. For example, point B of the primary winding and point D of the secondary winding are selected as potential reference points.

[0144] According to the above equations (10) to (12), the relationship between the primary and secondary winding midpoint voltage and the reference point voltage is established, and the total induced charge Q can be obtained. all Another expression of is:

[0145] Q all =v BD (C p1s1 +C p2s1 +C p3s1 +C p4s2 +C p5s2 +C p6s2 )

[0146] +Δv(4C p1s1+3C p2s1 +2C p3s1 +2C p4s2 +C p5s2 )(13);

[0147] Cp in formula (13) 1s1 , Cp 2s1 , Cp 3s1 , Cp 4s2 , Cp 5s2 , Cp 6s2 After the structure and material of the planar transformer are determined, it is quantitative, so the relationship between the equivalent capacitance and the distributed capacitance can be established, and we can get:

[0148]

[0149] So the induced charge Q all The calculation is made to the port BD and port AD of the planar transformer, and then C BD , C AD The expression is:

[0150]

[0151]

[0152] Capacitance C between B and D BD , and the capacitance C between A and D AD is the equivalent common-mode capacitance of the planar transformer, capacitance C BD , C AD The sum of the induced charges at both ends is Q all The corresponding two-capacitor model of the planar transformer can be referred to Fig.12 .

[0153] According to the previous analysis, the odd common mode noise is minimum when the following equation is satisfied:

[0154]

[0155] Reference Figure 1 When the winding circuit adopts the "sandwich" structure of the embodiment of the present disclosure, its equivalent capacitance still needs to meet the odd harmonic cancellation condition, that is, equation (17).

[0156] Therefore, assuming that in a sandwich structure, the m1-th primary winding and the n1-th secondary winding are located in adjacent sublayers (one adjacent pair), and the m2-th primary winding and the n2-th secondary winding are located in adjacent sublayers (another adjacent pair), the total mode noise current can be obtained as:

[0157]

[0158] where vP0 is the potential of the low potential point of the primary side of the planar transformer, v S0 It is the potential of the low point of the secondary side of the planar transformer.

[0159] Then make the following definition:

[0160] ∑C PmSn =λ1 (19);

[0161]

[0162] According to the above Fig.12 The two-capacitor model can be set as:

[0163] C1=λ2 (21);

[0164] C2 = λ1-λ2 (22);

[0165] Among them, λ1 and λ2 need to satisfy a specific quantitative relationship. The simultaneous equations (18) to (22) can be obtained:

[0166] λ1=2C0 (23);

[0167]

[0168] Among them, by combining equation (17), equation (23) and equation (24), we can get:

[0169]

[0170] Further simplifying formula (25), we can obtain:

[0171] (m1-n1)+(m2-n2)=n p -n s (26);

[0172] That is to say, for the winding circuit of the "sandwich" structure of the embodiment of the present disclosure, if the "adjacent pairs" can satisfy the above formula (26), the common mode noise can be completely eliminated.

[0173] It can be seen that in the planar transformer of the embodiment of the present invention, by setting the specific adjacent manner of the turns of the primary and secondary windings, the odd-order common-mode noise and the even-order common-mode noise can be reduced at the same time without "adding" other structures, thereby achieving complete suppression of common-mode noise without increasing the number of PCB layers (without changing the volume of the planar transformer).

[0174] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A winding structure, comprising a circuit board having a plurality of sub-layers, and a winding circuit arranged in the circuit board; the winding circuit comprises a plurality of single-layer coils, different single-layer coils are arranged in different sub-layers, and all the single-layer coils are in the same relative position in their respective sub-layers; wherein: A plurality of the single-layer coils constitute a multi-turn primary winding and a multi-turn secondary winding; Two adjacent pairs are formed among the plurality of single-layer coils, and each of the adjacent pairs includes two single-layer coils respectively located in two adjacent sub-layers and belonging to the primary winding and the secondary winding respectively.

2. The winding structure according to claim 1, wherein: The distance between the sub-layers where the two single-layer coils of one adjacent pair are located is equal to the distance between the sub-layers where the two single-layer coils of another adjacent pair are located.

3. The winding structure according to claim 1, wherein: In two adjacent pairs, the sum of the number of turns of the two single-layer coils belonging to the primary winding in the primary winding is subtracted from the sum of the number of turns of the two single-layer coils belonging to the secondary winding in the secondary winding, and the difference obtained is equal to the difference between the total number of turns of the primary winding and the total number of turns of the secondary winding.

4. The winding structure according to claim 1, wherein: All the single-layer coils of the multiple turns of the primary winding are arranged in a plurality of consecutive sub-layers; The multiple turns of the secondary winding are divided into two groups, and the sub-layers where the single-layer coils of the two groups of secondary windings are located are respectively located on both sides of multiple continuous sub-layers where all the single-layer coils of the primary winding are located.

5. The winding structure according to claim 1, wherein: All the single-layer coils of the multiple turns of the secondary winding are arranged in a plurality of consecutive sub-layers; The multiple turns of the primary winding are divided into two groups, and the sub-layers where the single-layer coils of the two groups of primary windings are located are respectively located on both sides of multiple continuous sub-layers where all the single-layer coils of the secondary winding are located.

6. The winding structure according to any one of claims 1 to 5, wherein: Each turn of the primary winding comprises a single-layer coil; Each turn of the secondary winding includes a plurality of the single-layer coils connected in parallel.

7. The winding structure according to any one of claims 1 to 5, wherein: All of the single-layer coils are arranged in a plurality of consecutive sub-layers.

8. A power converter comprising: The winding structure according to any one of claims 1 to 7.

9. The power converter according to claim 8, wherein: The power converter is a planar power converter; The planar power converter comprises a power conversion circuit, which is arranged in the circuit board of the winding structure and is electrically connected to the winding circuit of the winding structure.

10. The power converter according to claim 8, wherein: The power converter comprises a transformer; The transformer includes a transformer without a potential static point or a transformer with a potential static point.

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