Silicon-based capacitor and preparation method thereof

Abstract

The present invention belongs to the field of thin film capacitors and provides a silicon-based capacitor and a preparation method thereof. The silicon-based capacitor includes a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an encapsulation layer. The silicon-based substrate is provided with an oblique groove. The first electrode layer is evenly laid on the silicon-based substrate. The dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer and the second electrode layer. The first electrode layer and the second electrode layer have different polarities. The encapsulation layer covers all of the first electrode layer, the dielectric layer, the second electrode layer, and the silicon-based substrate to encapsulate. By providing the oblique groove on the silicon-based substrate, the first electrode layer, the dielectric layer, and the second electrode layer, which are laid upward in sequence along the silicon-based substrate, are all in an inclined state. The silicon-based capacitor is flatter in space, achieving higher capacitance within the space, better heat dissipation performance, and better adaptability to application environments with thickness requirements.

Description

Technical Field

[0001] The present invention belongs to the field of thin film capacitors, and in particular relates to silicon-based capacitors and a preparation method thereof. Background Art

[0002] With the rapid development of new energy vehicles and communications technology, performance requirements for silicon-based capacitors are increasing. New energy vehicles require high-energy-density capacitors to support their battery systems, while automotive radio frequency systems rely on capacitors with excellent high-frequency performance to ensure stable signal transmission. Communications equipment also requires miniaturized, high-performance capacitors to fit into compact design spaces. Therefore, developing silicon-based capacitors that meet the performance requirements for capacitance, frequency response, and temperature stability while maintaining a compact size has become an industry trend.

[0003] Existing silicon-based capacitors are usually packaged as a whole from bottom to top, consisting of a lower electrode-silicon-based substrate-dielectric-upper electrode. This type of silicon-based capacitor using a smooth silicon-based substrate is usually thickened as a whole to adapt to high energy density and high-frequency scenarios. On the one hand, it is contrary to the trend of miniaturization, and on the other hand, it is difficult to dissipate heat and reduces temperature stability. The demand for miniaturization is also driving silicon-based capacitors to develop in the direction of smaller size and lighter weight, which is often contradictory to the goal of improving performance. Therefore, the development of a new type of silicon-based capacitor that can provide higher performance and adapt to increasingly compact equipment space has become an important research direction in this field. Summary of the Invention

[0004] In order to meet the performance requirements of silicon-based capacitors with high capacity, fast frequency response, good temperature stability and miniaturization, the present application provides silicon-based capacitors and their preparation methods.

[0005] The silicon-based capacitor and its preparation method provided in this application adopt the following technical solutions:

[0006] A silicon-based capacitor includes a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer, and an encapsulation layer. The silicon-based substrate is provided with an oblique groove. The first electrode layer is evenly laid on the silicon-based substrate. The dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer and the second electrode layer. The first electrode layer and the second electrode layer have different polarities. The encapsulation layer covers all of the first electrode layer, the dielectric layer, the second electrode layer, and the silicon-based substrate to encapsulate them.

[0007] Beneficial effects: In this case, an oblique groove is set on the silicon-based substrate, so that the first electrode layer, the dielectric layer, and the second electrode layer laid upward in sequence along the silicon-based substrate are all in an inclined state. The first electrode layer-the dielectric layer-the second electrode layer constitutes a capacitor energy storage unit, and all the capacitor energy storage units are in an inclined flat shape, so that in the same space, the first electrode layer and the second electrode layer can bear more charge, so that the same size of energy storage unit can have more charge, that is, have a higher capacitance. In addition, the silicon-based capacitor in this case is flatter in space, and it is easy to stack devices, which is suitable for circuit design solutions with requirements on thickness. In addition, due to the presence of the oblique groove, the contact area between the first electrode layer and the silicon-based substrate is increased, and the overall thickness of the silicon-based capacitor is reduced, so that the path during the heat dissipation of the device becomes shorter, so that the silicon-based capacitor has better heat dissipation performance, better heat dissipation uniformity, and more stable device performance.

[0008] Optionally, the inclination angle of the inclined slot is between 0° and 75°.

[0009] Beneficial Effects: The tilt angle of the skew groove in the silicon substrate is set by the designer. To be suitable for current directional etching processes such as electron beam lithography or semiconductor dry etching, the tilt angle is preferably set between 0° and 75°.

[0010] Optionally, the top of the chute is a flat top.

[0011] Beneficial Effects: The top shape of the chute is determined by the designer and can be flat, sloping, wavy, or other shapes. To facilitate the deposition of the first electrode layer, the second electrode layer, and the dielectric layer using atomic layer deposition technology, the top shape of the chute is preferably flat.

[0012] Optionally, the first electrode layer and the second electrode layer are laid apart through the dielectric layer, there are multiple first electrode layers, and there are one or more second electrode layers.

[0013] Beneficial Effects: The silicon-based substrate of this invention supports the laying of multiple first and second electrode layers with dielectric layers between them, forming a stacked structure. This increases the number of capacitor energy storage units consisting of "first electrode layer-dielectric layer-second electrode layer", ensuring the high capacity of the silicon-based capacitor.

[0014] The present invention also provides a method for preparing a silicon-based capacitor, which is used to prepare the above-mentioned silicon-based capacitor, and the method comprises:

[0015] Directional etching of the silicon wafer surface according to a specified depth, specified width, and specified tilt angle to generate a silicon-based substrate with an array of oblique grooves;

[0016] depositing a first electrode layer on the silicon-based substrate;

[0017] sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer;

[0018] The first electrode layer and the second electrode layer are sealed by a packaging layer, and the silicon-based substrate, the first electrode layer, the dielectric layer and the second electrode layer are packaged to obtain a silicon-based capacitor.

[0019] Beneficial effects: Silicon wafers are selected as the raw materials for silicon-based substrates, and the silicon wafers are directionally etched according to the specified inclination angle specified by the designer to generate an oblique groove of a specified depth and a specified width; multiple oblique grooves are etched on the surface of the same silicon wafer, and these oblique grooves constitute an oblique groove array to obtain a silicon-based substrate. Among them, the depth, width, inclination angle, the plane shape of the bottom of the oblique groove, and the type of the top of the oblique groove, whether it is a flat top or other type, can all be set before the silicon wafer is etched, and executed in the step of etching the silicon-based wafer, or can be directly read and decomposed from the oblique groove cross-section diagram manually set by the designer. The silicon-based substrate in this case supports various types and shapes of oblique grooves, which should be used to generate silicon-based capacitors with different performances. In addition, the first electrode layer, the dielectric layer, and the second electrode layer constitute the capacitive energy storage unit in the silicon-based capacitor, which ensures the traditional energy supply.

[0020] Optionally, before capping the first electrode layer and the second electrode layer, after sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer, the method further includes:

[0021] The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer.

[0022] Beneficial effect: The dielectric layer and the second electrode layer are laid in sequence on the first electrode layer, and the dielectric layer and the first electrode layer are laid in sequence on the second electrode layer, thereby realizing a stacked structure of "first electrode layer-dielectric layer-second electrode layer-dielectric layer-first electrode layer". The number of capacitor energy storage units composed of "first electrode layer-dielectric layer-second electrode layer" is increased, thereby ensuring the capacity of the silicon-based capacitor manufactured by this method.

[0023] Optionally, after depositing the dielectric layer and the second electrode layer in sequence on the first electrode layer, the process is cyclically performed to deposit the dielectric layer and the first electrode layer in sequence on the second electrode layer, and to deposit the dielectric layer and the second electrode layer in sequence on the first electrode layer.

[0024] Beneficial Effect: Multiple first electrode layers and multiple second electrode layers are laid out with dielectric layers between them, forming a cyclic stacked structure. This increases the number of capacitor energy storage units consisting of "first electrode layer-dielectric layer-second electrode layer," ensuring high capacity of the manufactured silicon-based capacitor.

[0025] Optionally, the designated depth is 50 μm, the designated width is 200 μm, the first electrode layer and the second electrode layer are Au or Pt layers with a thickness of 20 nm, and the dielectric layer is a HfZrO layer with a thickness of 20 nm.

[0026] Optionally, the designated depth is 8 μm, the designated width is 80 μm, the first electrode layer and the second electrode layer are Ni layers with a thickness of 20 nm, and the dielectric layer is an aluminum oxide layer with a thickness of 25 nm.

[0027] Optionally, the directionally etching the silicon wafer surface adopts electron beam lithography or semiconductor dry etching; the packaging layer is a ceramic-based packaging layer or a packaging layer for surface mount devices.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] (1) The silicon-based substrate is provided with an oblique groove, so that the first electrode layer, the dielectric layer, and the second electrode layer are laid upward in sequence along the silicon-based substrate, thereby achieving a higher capacitance under the same volume capacitor. In addition, due to the inclined setting of the oblique groove, the silicon-based capacitor in this case is flatter and thinner in space, making it easier to stack devices and suitable for thinner circuit design solutions.

[0030] (2) Due to the presence of the skew groove, the overall thickness of the device is reduced, and the heat dissipation path of the device is shortened. The silicon-based capacitor can have better heat dissipation energy, better heat dissipation uniformity, and more stable device performance.

[0031] (3) The first electrode layer and the second electrode layer can be cyclically stacked through the dielectric layer to form silicon-based capacitors of various specifications, ensuring the frequency response speed of the silicon-based capacitors, while meeting the requirements of high capacity and miniaturization while also supporting high-speed frequency response. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of a method for manufacturing a silicon-based capacitor in a first embodiment of the present invention;

[0033] Figure 2 for Figure 1 A schematic diagram of step 101;

[0034] Figure 3 for Figure 1 Another schematic diagram of step 101;

[0035] Figure 4 for Figure 1 Schematic diagram of a silicon-based substrate in which the designated top of the inclined groove in step 101 is an inclined top;

[0036] Figure 5 for Figure 1A first schematic diagram of laying the first electrode layer in step 102;

[0037] Figure 6 for Figure 1 A second schematic diagram of laying the first electrode layer in step 102;

[0038] Figure 7 for Figure 1 A first schematic diagram of laying the second electrode layer in step 103;

[0039] Figure 8 for Figure 1 A second schematic diagram of laying the second electrode layer in step 103;

[0040] Figure 9 This is a schematic diagram of the first structure of a silicon-based capacitor in the first embodiment of the present invention;

[0041] Figure 10 Schematic diagram of the second structure of the silicon-based capacitor in the first embodiment of the present invention;

[0042] Figure 11 is a flow chart of a method for preparing a silicon-based capacitor in a second embodiment of the present invention;

[0043] Figure 12 Schematic diagram of the structure of a silicon-based capacitor in the second embodiment of the present invention;

[0044] Figure 13 A schematic structural diagram of a silicon-based capacitor in a third embodiment of the present invention;

[0045] Figure 14 FIG. 4 is another structural schematic diagram of a silicon-based capacitor in the third embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0047] A first embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Figure 1 As shown, the method for manufacturing a silicon-based capacitor includes the following steps:

[0048] Step 101 : directionally etching the surface of a silicon wafer according to a specified depth, a specified width, and a specified tilt angle to generate a silicon-based substrate 11 with an array of oblique grooves.

[0049] Specifically, the desired tilt angle θ of the skew is set according to the desired requirements of the silicon-based capacitor. 期望 , the desired chute depth h 期望 , the desired chute width x 期望 The desired top type of the chute is combined with the directional etching method selected by the staff, and after fine-tuning, the specified depth h, specified width x, specified tilt angle θ and specified top type are obtained. Among them, the desired tilt angle θ of the chute is 期望 The inclination angle of the inclined slot planned by the designer when designing the silicon-based capacitor, and the expected depth of the inclined slot h 期望 The depth of the inclined groove planned by the designer when designing the silicon-based capacitor is x 期望 The width of the skew slot planned by the designer when designing the silicon-based capacitor. The desired top type of the skew slot is the top type of the skew slot specified by the designer when designing the silicon-based capacitor. The top of the skew slot can be horizontal, wavy, or unidirectionally inclined. The desired tilt angle of the skew slot is θ. 期望 , the desired chute depth h 期望 , the desired chute width x 期望 The difference between these desired values, the specified depth h, the specified width x, the specified tilt angle θ, and the specified tip type, and the specified values, such as the specified depth h, the specified width x, the specified tilt angle θ, and the specified tip type, is determined by the directional etching process. Directional etching processes, such as electron beam lithography or semiconductor dry etching, etch the surface of a silicon wafer to create the tilted grooves. The specified tilt angle θ is typically set between 0° and 75°, and as the process improves, this specified tilt angle θ can be set over a wider range.

[0050] In some examples, reference Figure 2 , the implementation of step 101 includes:

[0051] S1-1, directionally etching a preliminary groove on the surface of the silicon wafer according to a specified depth, a specified width and a specified tilt angle; the preliminary groove only needs to meet the specified width and the specified tilt angle, and there is no requirement for the depth.

[0052] S1-2, directionally deepen the grooves so that the grooves complete silicon etching in a specific direction, forming a silicon wafer with a nanoscale oblique groove array; the specific direction can be the depth direction or other directions, and the grooves of S1-1 are further etched. Taking the specific direction as the depth direction as an example, according to the specified depth, this step is continuously repeated to deepen the grooves multiple times so that the grooves reach the specified depth requirement, thereby completing the silicon etching action, and the silicon wafer with the nanoscale oblique groove array serves as the silicon-based substrate 11 with the oblique groove array. Among them, the specified depth can be a fixed value, so that the bottom of the cross section of all oblique grooves in the oblique groove array is horizontal; the specified depth can also be a data set, so as to achieve the shape change of the bottom of the grooves in the oblique groove array, such as the bottom of the groove is an inclined surface, a curved surface, a wavy surface, etc.

[0053] In other examples, reference Figure 3 The implementation of step 101 further includes executing step S1-3 after step S1-2:

[0054] The distance d between the nearest point at the bottom of the groove and the silicon wafer is calculated. When distance d is less than a preset value, to ensure the structural stability of the overall capacitor, the structure between the groove corresponding to d and the silicon wafer surface is etched into the silicon wafer plane. This silicon wafer is then used as the silicon-based substrate 11 with the skew groove array. In this example, the fragile and easily damaged portions of the silicon wafer that have undergone multiple steps S1-2 are etched away, thereby making the finished silicon-based substrate 11 more stable and less susceptible to damage.

[0055] In the first case, refer to Figure 4 , decomposed according to the cross-sectional shape of the chute designed by the user, the specified depth h of the chute is 8μm, the specified width x is 80μm, the specified inclination angle θ of the chute is 60°, the specified top type of the chute is an inclined top, and the shape of the bottom of the chute is horizontal. After this step 101, a silicon-based substrate A is generated.

[0056] In the second case, continue with reference 2 and Figure 3 , decomposed according to the cross-sectional shape of the chute designed by the user, the specified depth h of the chute is 50 μm, the specified width x is 200 μm, the specified inclination angle θ of the chute is 70°, the specified top type of the chute is flat top, and the shape of the bottom of the chute is horizontal. After this step 101, a B silicon-based substrate is generated.

[0057] Step 102 : depositing a first electrode layer 12 on the silicon-based substrate 11 .

[0058] Specifically, an electrode layer is deposited on the inclined groove of the silicon-based substrate 11 , preferably using atomic layer deposition technology in semiconductor deposition technology, and the thickness of the deposited layer is the same as the planned thickness of the first electrode layer 12 .

[0059] In the first case, step 102 is implemented by referring to Figure 5 On the silicon-based substrate A above, a base metal electrode nickel is deposited using atomic layer deposition technology to form a Ni layer with a thickness of 20 nm as the first electrode layer 12.

[0060] In the second case, step 102 is implemented as follows: Figure 6 On the silicon-based substrate B above, a noble metal electrode Au or Pt is deposited using atomic layer deposition technology to form an Au or Pt layer with a thickness of 20 nm as the first electrode layer 12.

[0061] Step 103 : depositing a dielectric layer 13 and a second electrode layer 14 in sequence on the first electrode layer 12 .

[0062] Specifically, the dielectric layer 13 is deposited on the first electrode layer 12 using atomic layer deposition technology, and the deposited thickness corresponds to the planned thickness of the dielectric layer 13. The dielectric layer 13 wraps the upper end surface of the first electrode layer 12, so that only the left and right ends of the first electrode layer 12 are exposed; the second electrode layer 14 is deposited on the dielectric layer 13 using atomic layer deposition technology, and the deposited thickness corresponds to the planned thickness of the second electrode layer 14. The second electrode layer 14 wraps the dielectric layer 13, so that the dielectric layer 13 is completely wrapped by the second electrode layer 14 and the first electrode layer 12, or only the left and right ends of the dielectric layer 13 are exposed, and the upper end surface is wrapped by the second electrode layer 14.

[0063] In the first case, refer to Figure 7 ,exist Figure 5 On the basis of the first electrode layer 12, aluminum oxide is deposited on the first electrode layer 12 using atomic layer deposition technology to a thickness of 25 nm to form a dielectric layer 13. Base metal electrode nickel is again deposited on the dielectric layer 13 to a thickness of 20 nm to form a second electrode layer 14.

[0064] In the second case, refer to Figure 8 ,exist Figure 6 On the basis of the above, a dielectric layer HfZrO is deposited on the first electrode layer 12 using atomic layer deposition technology to a thickness of 20 nm to form a dielectric layer 13. A noble metal electrode Au or Pu is again deposited on the dielectric layer 13 to a thickness of 20 nm to form a second electrode layer 14.

[0065] Step 104 , capping the first electrode layer 12 and the second electrode layer 14 through the encapsulation layer 15 , and encapsulating the silicon-based substrate 11 , the first electrode layer 12 , the dielectric layer 13 , and the second electrode layer 14 to obtain a silicon-based capacitor.

[0066] Specifically, since the first electrode layer 12 covers the silicon-based substrate 11, the dielectric layer 13 covers the first electrode layer 12, and the second electrode layer 14 covers the dielectric layer 13, the packaging layer 15 only needs to cover the outermost layers of the dielectric layer 13 and the second electrode layer 14. Usually, the second electrode layer 14 is the outermost layer, and the packaging layer 15 covers the second electrode layer 14. For terminal sealing, the packaging layer 15 needs to expose both ends of the first electrode layer 12 and the second electrode layer 14, and wrap the other positions to ensure the normal operation of the first electrode layer 12 and the second electrode layer 14 as different electrodes of the silicon-based capacitor. The packaging layer 15 adopts a ceramic-based packaging layer or a surface-mounted device packaging layer 15, refer to Figure 9 and Figure 10 The silicon-based substrate 11, first electrode layer 12, dielectric layer 13, and second electrode layer 14, which have already been assembled, are then encapsulated by the encapsulation layer 15, completing the entire silicon-based capacitor. To facilitate port identification during capping, the first electrode layer 12 and the second electrode layer 14 can also be partially offset to ensure that the positive and negative poles of the completed silicon-based capacitor can be determined.

[0067] The first embodiment of the present invention also provides a silicon-based capacitor obtained by the above-mentioned method for manufacturing a silicon-based capacitor. Figure 9 and Figure 10 shown.

[0068] A silicon-based capacitor includes a silicon-based substrate 11, a first electrode layer 12, a dielectric layer 13, a second electrode layer 14, and an encapsulation layer 15. The silicon-based substrate 11 is provided with an inclined groove. The first electrode layer 12 is evenly laid on the silicon-based substrate 11, the dielectric layer 13 is laid on the first electrode layer 12, and the second electrode layer 14 is laid on the dielectric layer 13. The dielectric layer 13 is located between the first electrode layer 12 and the second electrode layer 14 to isolate the first electrode layer 12 and the second electrode layer 14. The first electrode layer 12 and the second electrode layer 14 have different polarities. The encapsulation layer 15 covers all of the first electrode layer 12, the dielectric layer 13, the second electrode layer 14, and the silicon-based substrate 11 to encapsulate them.

[0069] Among them, the setting of the chute follows Figure 2 and Figure 3 As shown, the chute is set according to the specified depth h, specified width x, specified inclination angle θ and specified top type. The first electrode layer 12 and the second electrode layer 14 are both electrode layers, and the materials can be the same or different, and the thickness can be the same or different; when the first electrode layer 12 is the positive electrode, the second electrode layer 14 is the negative electrode; when the first electrode layer 12 is the negative electrode, the second electrode layer 14 is the positive electrode. The inclination angle of the chute, that is, the specified inclination angle is usually set between 0° and 75° to adapt to the overall manufacturing process. The top lines of different chute are parallel to each other, thereby ensuring the feasibility of mass production. The preferred specified top type of the chute is a flat top (same Figure 2 and Figure 3 shown).

[0070] The second embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Figure 11 As shown, the difference between the preparation method of the silicon-based capacitor and the preparation method of the first embodiment is:

[0071] After step 103 , step 105 is performed to sequentially deposit the dielectric layer 13 and the first electrode layer 12 on the second electrode layer 14 ; and after step 105 is completed, step 104 is performed to form a silicon-based capacitor.

[0072] refer to Figure 12 As shown, the silicon-based capacitor is composed of "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-packaging layer 15", wherein the layout and structure of the silicon-based substrate 11, first electrode layer 12, dielectric layer 13, second electrode layer 14 and packaging layer 15 are the same as those in the first embodiment mentioned above. In this embodiment, the adjacent first electrode layers 12 in the silicon-based capacitor form a capacitive energy storage unit through the dielectric layer 13 and the second electrode layer 14. The silicon-based capacitor has two electrical energy storage units, "first electrode layer 12-dielectric layer 13-second electrode layer 14" and "second electrode layer 14-dielectric layer 13-first electrode layer 12", to achieve higher energy storage of the silicon-based capacitor. It is worth mentioning that although the silicon-based capacitor has two first electrode layers 12, the thickness and material of the two first electrode layers 12 can be the same or different.

[0073] The third embodiment of the present invention provides a silicon-based capacitor and a method for manufacturing the same. Figure 12 and Figure 13 As shown, the difference between the preparation method of the silicon-based capacitor and the preparation method of the second embodiment is:

[0074] Step 103 and step 105 are executed cyclically, that is, the dielectric layer 13 and the second electrode layer 14 are sequentially laid on the first electrode layer 12, and the dielectric layer 13 and the first electrode layer 12 are sequentially laid on the second electrode layer 14. After the number of cycles reaches the target number, step 104 is executed to obtain Figure 13 and Figure 14 The silicon-based capacitor shown in FIG. The adjacent first electrode layer 12 - dielectric layer 13 - second electrode layer 14 in the silicon-based capacitor form a capacitance energy storage unit, that is, the silicon-based capacitor has multiple capacitance energy storage units to achieve higher energy storage.

[0075] refer to Figure 13As shown, a dielectric layer 13 and a second electrode layer 14 are sequentially laid on the first electrode layer 12, and vice versa, with the outermost layer being the first electrode layer 12. Subsequently, an encapsulation layer 15 is used to encapsulate the entire structure of "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13 ...-first electrode layer 12."

[0076] refer to Figure 14 As shown, a cycle is repeated, with the dielectric layer 13 and the second electrode layer 14 being laid sequentially on the first electrode layer 12, and the dielectric layer 13 and the first electrode layer 12 being laid sequentially on the second electrode layer 14, with the outermost layer being the second electrode layer 14. Subsequently, an encapsulation layer 15 is used to encapsulate the entire structure of "silicon-based substrate 11-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13-first electrode layer 12-dielectric layer 13-second electrode layer 14-dielectric layer 13 ... -second electrode layer 14".

[0077] The steps of the various methods described above are divided for clarity of description only. During implementation, they can be combined into one step, or some steps can be split and decomposed into multiple steps. As long as they contain the same logical relationship, they are all within the scope of protection of this patent. In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance. The term "plurality" refers to two or more, unless otherwise expressly defined.

[0078] The above description of the embodiments is intended to facilitate understanding and application of the present application by those skilled in the art. It will be apparent that those skilled in the art can readily make various modifications to these embodiments and apply the general principles described herein to other embodiments without expending any creative effort. Therefore, the present application is not limited to the embodiments described herein, and improvements and modifications made by those skilled in the art based on the disclosure of this application without departing from the scope and spirit of this application are within the scope of this application.

Claims

1. Silicon-based capacitor, characterized in that, The method comprises a silicon-based substrate, a first electrode layer, a dielectric layer, a second electrode layer and a packaging layer, wherein the silicon-based substrate is provided with an oblique groove, the first electrode layer is evenly laid on the silicon-based substrate, the dielectric layer is located between the first electrode layer and the second electrode layer to isolate the first electrode layer and the second electrode layer, the first electrode layer and the second electrode layer have different polarities, the packaging layer covers all the first electrode layer, the dielectric layer, the second electrode layer and the silicon-based substrate to encapsulate, and the first electrode layer and the second electrode layer are laid with intervals through the dielectric layer; according to a specified depth, a specified width and a specified tilt angle, the surface of the silicon wafer is directionally etched to obtain a preliminary groove, and the groove is directionally deepened to obtain the oblique groove, the tilt angle of the oblique groove is between 0° and 75°, the top lines of different oblique grooves are parallel to each other, the specified depth indicates the shape change of the bottom of the groove in the oblique groove array, and the packaging layer exposes both ends of the first electrode layer and the second electrode layer.

2. The silicon-based capacitor according to claim 1, wherein There are a plurality of the first electrode layers, and there are one or more the second electrode layers.

3. A method for preparing a silicon-based capacitor, characterized in that: For preparing the silicon-based capacitor according to claim 1, the method comprises: The silicon wafer surface is directionally etched to obtain preliminary grooves at a specified depth, width, and tilt angle. The grooves are directionally deepened so that the silicon is etched in a specific direction, forming a silicon wafer with a nanoscale skew groove array. The specified depth indicates the shape change of the bottom of the grooves in the skew groove array. The distance d between the nearest point of the groove bottom and the silicon wafer is calculated. When the distance d is lower than a preset value, the structure between the corresponding groove and the silicon wafer surface is etched into the silicon wafer plane to ensure the structural stability of the overall capacitor. The silicon wafer is then used as a silicon-based substrate with an array of skew grooves. The tilt angle of the skew grooves is between 0° and 75°, and the top lines of different skew grooves are parallel to each other. depositing a first electrode layer on the silicon-based substrate; sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer; The first electrode layer and the second electrode layer are sealed by a packaging layer to expose both ends of the first electrode layer and the second electrode layer, and the silicon-based substrate, the first electrode layer, the dielectric layer and the second electrode layer are packaged to obtain a silicon-based capacitor.

4. The method for preparing a silicon-based capacitor according to claim 3, wherein: Before capping the first electrode layer and the second electrode layer, after sequentially depositing a dielectric layer and a second electrode layer on the first electrode layer, the method further includes: The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer.

5. The method for preparing a silicon-based capacitor according to claim 3, wherein: After the dielectric layer and the second electrode layer are sequentially deposited on the first electrode layer, the steps are performed cyclically. The dielectric layer and the first electrode layer are sequentially deposited on the second electrode layer, and the dielectric layer and the second electrode layer are sequentially deposited on the first electrode layer.

6. The method for preparing a silicon-based capacitor according to claim 3, wherein: The designated depth is 50 μm, the designated width is 200 μm, the first electrode layer and the second electrode layer are Au or Pt layers with a thickness of 20 nm, and the dielectric layer is a HfZrO layer with a thickness of 20 nm.

7. The method for preparing a silicon-based capacitor according to claim 3, wherein: The designated depth is 8 μm, the designated width is 80 μm, the first electrode layer and the second electrode layer are Ni layers with a thickness of 20 nm, and the dielectric layer is an aluminum oxide layer with a thickness of 25 nm.

8. The method for preparing a silicon-based capacitor according to claim 3, wherein: The directionally etched silicon wafer surface is etched using electron beam lithography or semiconductor dry etching; the packaging layer is a ceramic-based packaging layer or a packaging layer for surface mounted devices.

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