Semiconductor package

Abstract

A semiconductor package includes a substrate including an insulating layer and a plurality of first pads on the insulating layer; a semiconductor chip including a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping the at least a portion of the plurality of first pads in the first direction; and a plurality of bumps on one surface of the substrate or one surface of the semiconductor chip, at least a portion of the plurality of bumps having a melting point lower than a melting point of each of the plurality of first pads and a melting point of each of the plurality of second pads, the plurality of bumps including a plurality of first bumps and at least one second bump having a melting point lower than a melting point of each of the plurality of first pads and a melting point of each of the plurality of second pads, the plurality of first bumps are electrically connected to at least a portion of the plurality of first pads or at least a portion of the plurality of second pads, and the magnetic permeability of the at least one second bump is higher than that of each of the plurality of first bumps.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package. Background Art

[0002] The semiconductor chip can be mounted on the substrate through various types of connection bumps. The semiconductor chip can receive power from the substrate or send signals to the substrate through multiple bumps. Specifically, as the semiconductor chip has higher performance and higher integration, the multiple bumps connected to the semiconductor chip can be arranged to have a finer pitch. Summary of the invention

[0003] An aspect of the inventive concept is to provide a semiconductor package that can efficiently improve bonding reliability of a substrate and / or a semiconductor chip in a vertical direction.

[0004] According to one aspect of the inventive concept, a semiconductor package includes: a substrate including an insulating layer and a plurality of first pads located on the insulating layer; a semiconductor chip including a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping with the at least a portion of the plurality of first pads in a first direction; and a plurality of bumps located on a surface of the substrate or a surface of the semiconductor chip, at least a portion of the plurality of bumps having a melting point lower than a melting point of each of the plurality of first pads and a melting point of each of the plurality of second pads, wherein the plurality of bumps include a plurality of first bumps and at least one second bump, the plurality of first bumps being electrically connected to at least a portion of the plurality of first pads or at least a portion of the plurality of second pads, and the at least one second bump having a magnetic permeability higher than a magnetic permeability of each of the plurality of first bumps.

[0005] According to one aspect of the inventive concept, a semiconductor package includes: a substrate, the substrate including an insulating layer and a plurality of first solder pads located on the insulating layer; a semiconductor chip, the semiconductor chip including a plurality of second solder pads electrically connected to at least a portion of the plurality of first solder pads, the plurality of second solder pads overlapping with the at least a portion of the plurality of first solder pads in a first direction; and a plurality of bumps, the plurality of bumps being located on a surface of the substrate or a surface of the semiconductor chip, the melting point of at least a portion of the plurality of bumps being lower than the melting point of each of the plurality of first solder pads and the melting point of each of the plurality of second solder pads, wherein at least one of the plurality of bumps includes: a first magnetic core; a second magnetic core, the second magnetic core being configured to apply a magnetic force to the first magnetic core; and a solder, the solder contacting the first magnetic core and the second magnetic core, at least partially surrounding the first magnetic core and the second magnetic core, and having a melting point lower than the melting point of the first magnetic core and the melting point of the second magnetic core.

[0006] According to one aspect of the inventive concept, a semiconductor package includes: a substrate including an insulating layer and a plurality of first pads located on the insulating layer; a semiconductor chip including a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping with the at least a portion of the plurality of first pads in a first direction; and a plurality of bumps located on a surface of the substrate or a surface of the semiconductor chip, the melting point of at least a portion of the bumps being lower than the melting point of each of the plurality of first pads and the melting point of each of the plurality of second pads, wherein the plurality of bumps include: a plurality of first bumps connected between at least a portion of the plurality of first pads and at least a portion of the plurality of second pads; and a plurality of second bumps including dummy bumps that are not connected to the plurality of first pads or are not connected to the plurality of second pads, wherein the plurality of second bumps each include a ferromagnetic material or a permanent magnetic material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a cross-sectional view showing an XZ cross-section of a semiconductor package according to an embodiment.

[0009] Figure 2A yes Figure 1An enlarged cross-sectional view of a portion “A” of a semiconductor package.

[0010] Figure 2B It shows Figure 2A A top view of an XY cross section of a semiconductor package.

[0011] FIG. 3A to FIG. 3C is an enlarged cross-sectional view of a semiconductor package according to an embodiment.

[0012] 4A to 4D is an enlarged cross-sectional view of a semiconductor package according to an embodiment.

[0013] FIG. 5A to FIG. 5G 1 and 2 are top views respectively showing arrangements of a plurality of bumps and a plurality of pads of a semiconductor package according to an embodiment.

[0014] Fig. 6A and Figure 6B is a cross-sectional view showing a semiconductor package according to an embodiment.

[0015] 7A to 7C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0016] The detailed description of the inventive concept described below refers to the accompanying drawings, which illustrate by way of example specific embodiments in which the inventive concept can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the inventive concept. It should be understood that the various embodiments of the inventive concept are different from each other, but are not necessarily mutually exclusive. For example, without departing from the spirit and scope of the inventive concept, an embodiment of a specific shape, structure and characteristic described herein can be implemented in another embodiment. In addition, it should be understood that the position or arrangement of each component within each disclosed embodiment can be changed without departing from the spirit and scope of the inventive concept. Therefore, the detailed description set forth below is not intended to be considered in a restrictive sense, and the scope of the inventive concept is limited only by the appended claims, and all equivalent forms are claimed by those claims. In the accompanying drawings, the same reference numerals indicate the same or similar functions throughout in various aspects. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Note that the aspects described with respect to one embodiment can be incorporated in different embodiments, although not specifically described with respect to it. That is, all embodiments and / or the features of any embodiment can be combined in any manner and / or combination.

[0017] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the inventive concept.

[0018] refer to Figures 1 to 2B , a semiconductor package 100 a according to an embodiment may include a substrate 110 , a semiconductor chip 120 , and a plurality of bumps, and the plurality of bumps may include a plurality of first bumps 130 and at least one second bump 130 mag.

[0019] The substrate 110 may be a support substrate on which the semiconductor chip 120 is mounted, and may be a package substrate for interconnecting pads of the semiconductor chip 120. The package substrate may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a substrate with interconnection, etc. The substrate 110 may include an insulating layer 111, an interconnection layer 112, an interconnection path 113, a first solder mask layer 115, and a second solder mask layer 116. In some embodiments, the number of the insulating layer 111 and the interconnection layer 112 forming the substrate 110 may be changed. In some embodiments, the substrate 110 may be a built-in layer substrate, such as an organic built-in layer. In some embodiments, the substrate 110 may be a module substrate, and in this case, the semiconductor chip 120 may be a semiconductor structure, such as a semiconductor package.

[0020] The insulating layer 111 may include an insulating material, and may include, for example, a thermosetting resin (such as an epoxy resin) or a thermoplastic resin (such as a polyimide). For example, the insulating layer 111 may include a photosensitive insulating material, such as a photoimageable dielectric (PID) resin. In other embodiments, the insulating layer 111 may include a resin mixed with an inorganic filler, such as an Ajinomoto stacked film (ABF). In other embodiments, the insulating layer 111 may include a prepreg, such as a flame retardant (FR-4) or bismaleimide triazine (BT). The insulating layer 111 may include the same or different materials, and the boundaries between the insulating layers 111 may not be distinguished depending on the materials, processes, etc., that form each layer. That is, the insulating layer 111 may be implemented as a single or monolithic structure.

[0021] The interconnection layer 112 and the interconnection path 113 can form an electrical path. The interconnection layer 112 and the interconnection path 113 can interconnect the semiconductor chip 120 to an area outside the semiconductor chip 120, for example, to a fan-out area that does not overlap with the semiconductor chip 120 in the Z direction. Therefore, the semiconductor package 100a of the present embodiment can be referred to as a fan-out semiconductor package. The form of the semiconductor package is not limited thereto, and in some embodiments, the semiconductor package 100a can form a fan-in semiconductor package. The interconnection layer 112 and the interconnection path 113 can include a ground pattern, a power pattern, and a signal pattern. The interconnection layer 112 can be arranged in a linear shape on the XY plane, and the interconnection path 113 can be a cylindrical shape with an inclined side surface, so that the width is reduced in an upward direction or a downward direction along the Z-direction axis on the XY plane. The interconnection path 113 is shown as a filling path structure in which the interior is completely filled with a conductive material, but the embodiment of the interconnection path 113 is not limited thereto. For example, the interconnection via 113 may have a conformal via shape in which a metal material is formed along an inner wall of a via hole.

[0022] The interconnection layer 112 and the interconnection via 113 may include a conductive material, and may include, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Depending on the width of the interconnection in the interconnection layer 112 or the spacing between the interconnections (e.g., 10 μm to 100 μm), the interconnection of the interconnection layer 112 may be implemented as a redistribution line.

[0023] The interconnection layer 112 may include a plurality of first pads 112P1, 112P2, and 112P3 exposed through the first solder mask layer 115 and the second solder mask layer 116. A portion of the uppermost interconnection layer 112 may form a plurality of first pads 112P1 and 112P2. A portion of the lowermost interconnection layer 112 may form a plurality of first pads 112P3. The plurality of first pads 112P1 and 112P2 may be disposed on the uppermost insulating layer among the insulating layers 111, and the plurality of first pads 112P3 may be disposed on the lowermost insulating layer among the insulating layers 111.

[0024] Figure 1 and Figure 2AA substrate 110 is shown, which is a protruded trace substrate (PTS) in which a plurality of first pads 112P1, 112P2, and 112P3 protrude upward and downward from the upper and lower surfaces of an insulating layer 111 along the Z-direction axis. The substrate 110 may be an embedded trace substrate (ETS). The ETS may have a structure in which the uppermost insulating layer among the insulating layers 111 is recessed upward and downward along the Z-direction axis in a region overlapping with the plurality of first pads 112P1 and 112P2, and the plurality of first pads 112P1 and 112P2 may be in direct contact with the uppermost insulating layer among the insulating layers 111 in the recessed space of the uppermost insulating layer among the insulating layers 111.

[0025] Each of the plurality of first pads 112P1 and 112P2 may include a surface treatment layer ST disposed on a surface exposed from the first solder mask layer 115. Depending on the design, the surface treatment layer ST may be omitted. The surface treatment layer ST may be disposed on the entire surface of the plurality of first pads 112P1, and may be disposed on a portion of the surface of the plurality of first pads 112P2 exposed by the opening OP. The surface treatment layer ST may include, for example, gold (Au), silver (Ag), nickel (Ni), and / or palladium (Pd). Although not shown, the plurality of first pads 112P3 may further include a surface treatment layer disposed on a surface exposed from the second solder mask layer 116.

[0026] The plurality of first pads 112P1 may be pads for mounting the semiconductor chip 120. The plurality of first pads 112P1 may be pads completely exposed through the first solder mask layer 115, and may be connected to the plurality of first bumps 130. Depending on the design, the first pad 112P2 among the plurality of first pads 112P1 and 112P2 may be omitted. The plurality of first pads 112P2 may be pads at least partially exposed through the first solder mask layer 115, and may not be connected to the plurality of first bumps 130. In the plurality of first pads 112P2, the upper surface and the side surface exposed from the first solder mask layer 115 may be at least partially covered by the non-conductive film layer 140, and may be in contact with the non-conductive film layer 140. The plurality of first pads 112P2 may be disposed on both sides of the plurality of first pads 112P1 in the group in at least one direction (e.g., the X direction). The plurality of first pads 112P3 may be pads connected to the package bumps 160.

[0027] The first solder mask layer 115 and the second solder mask layer 116 may be solder resist layers that may protect the interconnect layer 112 from external physical and chemical damage. The first solder mask layer 115 and the second solder mask layer 116 may include insulating materials such as prepreg, ABF, FR-4, BT and / or photo solder resist (PSR). The first solder mask layer 115 may form the upper surface of the substrate 110 and may have an opening OP that exposes at least a portion of the interconnect layer 112 (e.g., a plurality of first pads 112P1 and 112P2). The second solder mask layer 116 may have a plurality of openings that expose at least a portion of the interconnect layer 112 (e.g., a plurality of first pads 112P3).

[0028] The semiconductor chip 120 may be arranged on the substrate 110 to overlap in the vertical direction (ie, the Z direction), and may include a plurality of second pads 121 on its lower surface. The semiconductor chip 120 may be mounted on the upper surface of the substrate 110 using a flip chip bonding method. The semiconductor chip 120 may be located below the plurality of second pads 121, and may include a device layer or an active layer on which an integrated circuit (IC) is arranged. The semiconductor chip 120 may include a logic semiconductor chip and / or a memory semiconductor chip. The logic semiconductor chip may be a microprocessor, and may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a controller, and / or an application specific integrated circuit (ASIC). The memory semiconductor chip may be a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a non-volatile memory such as a flash memory.

[0029] The main body of the semiconductor chip 120 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and the plurality of second pads 121 may include a conductive material such as tungsten (W), aluminum (Al), copper (Cu), etc. The plurality of second pads 121 may be pads of a bare chip, such as pads of aluminum (Al), but may be pads of a packaged chip, such as pads of copper (Cu), according to an embodiment.

[0030] The plurality of second pads 121 may be electrically connected to the plurality of first pads 112P1 through the plurality of first bumps 130. Electrical connection may mean providing at least a portion of a path through which a signal is transmitted. In some embodiments, the plurality of second pads 121 may be disposed in the main body portion of the semiconductor chip 120 so that its lower surface forms the lower surface of the semiconductor chip 120. In some embodiments, a passivation layer exposing the plurality of second pads 121 may be further disposed on the lower surface of the semiconductor chip 120. The passivation layer may include a silicon oxide film and / or a silicon nitride film.

[0031] The plurality of first bumps 130 and the plurality of second bumps 130mag may be disposed on one surface (upper surface and / or lower surface) of the substrate 110 or one surface (upper surface and / or lower surface) of the semiconductor chip 120, and the melting point of at least a portion of the plurality of first bumps 130 and the plurality of second bumps 130mag may be lower than the melting point of each of the plurality of first pads 112P1 and the plurality of second pads 121. The plurality of first bumps 130 may physically and electrically connect at least a portion of the plurality of second pads 121 of the semiconductor chip 120 to at least a portion of the plurality of first pads 112P1 of the substrate 110. The plurality of first bumps 130 may not be connected to the first pads 112P2. The plurality of first bumps 130 and the plurality of second bumps 130mag may have a spherical shape or a columnar shape. The plurality of first bumps 130 and the plurality of second bumps 130mag may at least partially cover upper portions of upper surfaces and side surfaces of the plurality of first pads 112P1 .

[0032] The plurality of first bumps 130 and the plurality of second bumps 130mag may include a conductive material having a low melting point, such as lead (Pb), bismuth (Bi), tin (Sn) and / or tin alloy (Sn-Ag-Cu). At a temperature higher than the melting point, the plurality of first bumps 130 and the plurality of second bumps 130mag may be in a fluid state by a reflow process or a thermocompression bonding (TCB) process. Thereafter, as the temperature decreases, the plurality of first bumps 130 will be connected and fixed between at least a portion of the first pads 112P1 in the plurality of first pads 112P1 and at least a portion of the second pads 121 in the plurality of second pads 121. Therefore, the semiconductor chip 120 may be mounted on the substrate 110.

[0033] During a reflow process or a thermocompression bonding (TCB) process, a horizontal position difference (i.e., a position difference in the X direction) between at least a portion of the plurality of first pads 112P1 and at least a portion of the plurality of second pads 121 (which may be expressed as an offset) may be a cause of an incorrect electrical connection between at least a portion of the plurality of first pads 112P1 and at least a portion of the plurality of second pads 121. Therefore, the horizontal position difference (e.g., the offset) may be reduced to reduce the possibility of an incorrect connection between at least a portion of the plurality of first pads 112P1 and at least a portion of the plurality of second pads 121.

[0034] The permeability of at least one second bump 130mag may be higher than the permeability of each of the plurality of first bumps 130. Therefore, the at least one second bump 130mag may be magnetized and may thus become a source of magnetic force. When a horizontal position difference (e.g., offset) occurs between at least a portion of the plurality of first pads 112P1 and at least a portion of the second pads 121 among the plurality of second pads 121, since the magnetic force may include not only a vertical vector component but also a horizontal vector component, the horizontal position difference (e.g., offset) may vary due to the horizontal vector component.

[0035] At least one second bump 130mag may coexist with a plurality of first bumps 130. Because the magnetic permeability of each of the plurality of first bumps 130 may be lower than the magnetic permeability of the at least one second bump 130mag, the plurality of first bumps 130 may be substantially unaffected by the magnetic force of the at least one second bump 130mag. Therefore, the magnetic force of the at least one second bump 130mag does not further increase the horizontal position difference (e.g., offset), and the magnetic force may reliably reduce the horizontal position difference (e.g., offset) caused by the horizontal vector component. For example, the incorrect connection between at least a portion of the first pad 112P1 and at least a portion of the second pad 121 may be stably reduced or prevented. In addition, because the incorrect connection is stably reduced or prevented, the size and spacing of the plurality of first pads 112P1 and the plurality of second pads 121 may be stably reduced. For example, the semiconductor package 100a is advantageous in miniaturization while improving reliability.

[0036] For example, at least one second bump 130mag may be connected between different portions of the plurality of first pads 112P1 and different portions of the plurality of second pads 121. Because not only the plurality of first bumps 130 but also at least a portion of the at least one second bump 130mag may have a lower melting point than each of the plurality of first pads 112P1 and the plurality of second pads 121, the plurality of first bumps 130 and the at least one second bump 130mag may together provide an electrical connection path between the substrate 110 and the semiconductor chip 120 and may be formed simultaneously.

[0037] At least one second bump 130mag may include solder sol and magnetic material mag. The melting point of solder sol may be lower than the melting point of each of the plurality of first pads 112P1 and the plurality of second pads 121, and the plurality of first bumps 130 may be formed by solder. The magnetic material mag may include a magnetic material having a magnetic permeability higher than the magnetic permeability of the material included in each of the plurality of first pads 112P1 and the plurality of second pads 121. For example, the magnetic material mag may include a ferromagnetic material. The ferromagnetic material may include a ferromagnetic material, a ferrimagnetic material, and / or an anti-ferromagnetic material, and may form a magnetic force as the ferromagnetic material is magnetized. For example, the ferromagnetic material may include ferrite, iron (Fe), nickel (Ni), cobalt (Co), tungsten (W), molybdenum (Mo) or an alloy thereof. For example, the ferromagnetic material may be amorphous or crystalline, and may include one or more of a Fe-Si based alloy, a Fe-Si-Al based alloy, a Fe-Ni based alloy, a Fe-Ni-Mo based alloy, a Fe-Ni-Mo-Cu based alloy, a Fe-Co based alloy, a Fe-Ni-Co based alloy, a Fe-Cr based alloy, a Fe-Cr-Si based alloy, a Fe-Si-Cu-Nb based alloy, a Fe-Ni-Cr based alloy, a Fe-Cr-Al based alloy, or a Fe-Si-B-Cr based alloy. The ferrite may be, for example, at least one of the following: spinel ferrites, such as Mg-Zn-based ferrites, Mn-Zn-based ferrites, Mn-Mg-based ferrites, Cu-Zn-based ferrites, Mg-Mn-Sr-based ferrites, Ni-Zn-based ferrites, etc.; hexagonal ferrites, such as Ba-Zn-based ferrites, Ba-Mg-based ferrites, Ba-Ni-based ferrites, Ba-Co-based ferrites, Ba-Ni-Co-based ferrites, etc.; garnet-type ferrites, such as Y-based ferrites, etc.; and / or Li-based ferrites.

[0038] In other embodiments, the magnetic material mag of at least one second bump 130mag may include a permanent magnetic material. The permanent magnetic material may be a material that can maintain a strong magnetization state for a long time, and can therefore form a magnetic force without a separate magnetization process. For example, the permanent magnetic material may be a mixture of a ferromagnetic material (e.g., ferrite) and an additional material (e.g., neodymium (Nd), samarium (Sm), etc.).

[0039] refer to Figures 1 to 2B The semiconductor package 100 a according to the embodiment may further include a non-conductive film layer 140 , an encapsulant 150 and / or a package bump 160 .

[0040] The non-conductive film layer 140 may be disposed between the semiconductor chip 120 and the substrate 110 to at least partially surround the plurality of first bumps 130 and at least one second bump 130mag in a top view. The non-conductive film layer 140 may also be referred to as an underfill layer. The non-conductive film layer 140 may include a non-conductive polymer, and may include, for example, a non-conductive paste (NCP). The non-conductive film layer 140 may be formed on the lower surface of the semiconductor chip 120 or the upper surface of the substrate 110 during a reflow process or a TCB process, and may then at least partially fill the space between the semiconductor chip 120 and the substrate 110. Therefore, the non-conductive film layer 140 may be in a shape protruding from the end of the semiconductor chip 120 in an outward direction. Compared to the upper and lower surfaces of the non-conductive film layer 140, at the center of the non-conductive film layer 140 in the thickness direction, the length of the non-conductive film layer 140 horizontally protruding from the side surface of the semiconductor chip 120 may be greater.

[0041] The encapsulant 150 may seal and protect the semiconductor chip 120. The encapsulant 150 may be provided to at least partially cover the side surface and the upper surface of the semiconductor chip 120, but the embodiment is not limited thereto. The encapsulant 150 may include, but is not limited to, a molding material such as an epoxy molding compound (EMC). For example, the encapsulant 150 may include an insulating material, and may include, for example, a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), an inorganic filler and / or a prepreg containing glass fiber, ABF or FR-4, BT or PID.

[0042] The package bump 160 may be disposed in the opening of the second solder mask layer 116 on the lower surface of the substrate 110. The package bump 160 may physically connect and / or electrically connect the semiconductor package 100a to an external device such as a mainboard. The size and diameter of the package bump 160 may be greater than the size and diameter of each of the plurality of first bumps 130. The package bump 160 may include a low melting point metal, such as tin (Sn), an alloy (Sn-Ag-Cu) containing tin (Sn), etc., but is not limited thereto. The package bump 160 may be in a land shape, a ball shape, or a pin shape, and may be formed as a single layer or multiple layers. For example, the package bump 160 may be a solder ball.

[0043] refer to Figure 2A According to the embodiment, the at least one second bump 130mag of the semiconductor package 100a may include a magnetic material mag in a powder form dispersed in the solder sol. The average diameter of the magnetic material mag may be less than 10% of the average diameter of each of the at least one second bump 130mag, but the embodiment is not limited thereto.

[0044] refer to Figure 3A and Figure 3B According to the embodiment, at least one second bump 130mag of the semiconductor package (100b and 100c) may include solder sol, a first magnetic core mag1 and a second magnetic core mag2, respectively. The first magnetic core mag1 may be in direct contact with one of the plurality of first pads 112P1, and the second magnetic core mag2 may be in direct contact with one of the plurality of second pads 121.

[0045] The first magnetic core mag1 may be configured to apply a magnetic force to the second magnetic core mag2 by including a permanent magnetic material or being temporarily magnetized, and the second magnetic core mag2 may be configured to apply a magnetic force to the first magnetic core mag1 by including a permanent magnetic material or being temporarily magnetized. Each of the first magnetic core mag1 and the second magnetic core mag2 may be formed of a magnetic material (e.g., a ferromagnetic material and / or a permanent magnetic material) having a higher magnetic permeability than each of the plurality of first pads 112P1 and the plurality of second pads 121. As the volume of each of the first magnetic core mag1 and the second magnetic core mag2 increases, the magnetic force between the first magnetic core mag1 and the second magnetic core mag2 may increase. The volume of each of the first magnetic core mag1 and the second magnetic core mag2 may be 10% or more of the volume of each of the second bumps 130mag in the at least one second bump 130mag, but the embodiment is not limited thereto.

[0046] For example, before the semiconductor chip 120 is disposed on the substrate 110, the first magnetic core mag1 may be disposed on at least a portion of the plurality of first pads 112P1 of the substrate 110, and the second magnetic core mag2 may be disposed on at least a portion of the plurality of second pads 121 of the semiconductor chip 120. Thereafter, when the semiconductor chip 120 is disposed on the substrate 110, the first magnetic core mag1 and the second magnetic core mag2 may be attracted to each other by magnetic force.

[0047] Because the solder sol is in contact with each of the first magnetic core mag1 and the second magnetic core mag2, and as Figure 3AAs shown, the first magnetic core mag1 and the second magnetic core mag2 are at least partially surrounded respectively, so the vertical distance between the first magnetic core mag1 and the second magnetic core mag2 (i.e., the distance along the Z axis) can be shortened. As the vertical distance decreases, the influence of the magnetic force between the first magnetic core mag1 and the second magnetic core mag2 on each other can increase. In addition, the horizontal position of the first magnetic core mag1 on the substrate 110 (i.e., the position along the X axis) and the horizontal position of the second magnetic core mag2 on the semiconductor chip 120 can be substantially unchanged. Therefore, the horizontal position difference (e.g., offset) along the X axis between at least a portion of the first pad 112P1 and at least a portion of the second pad 121 can be efficiently offset. In addition, even when the number of at least one second bump 130mag is relatively small compared to the plurality of first bumps 130, the horizontal position difference (e.g., offset) can be stably offset.

[0048] refer to Figure 3A , the first magnetic core mag1 may be formed as a layer on the upper surface of the plurality of first pads 112P1, and the second magnetic core mag2 may be formed as a layer on the lower surface of the plurality of second pads 121. Each of the first magnetic core mag1 and the second magnetic core mag2 may be implemented in a manner of applying or coating a magnetic material, but the embodiment is not limited thereto.

[0049] refer to Figure 3B , the first magnetic core mag1 and the second magnetic core mag2 may protrude from one of the plurality of first pads 112P1 and the plurality of second pads 121, and may contact each other. For example, when the semiconductor chip 120 may be disposed on the substrate 110, the vertical dimensions (e.g., the length along the Z axis) of the first magnetic core mag1 and the second magnetic core mag2 may be longer by the magnetic force between the first magnetic core mag1 and the second magnetic core mag2. In other embodiments, before the semiconductor chip 120 is disposed on the substrate 110, each of the first magnetic core mag1 and the second magnetic core mag2 may be formed to be thick.

[0050] refer to Figure 3C , at least one second bump 130mag of the semiconductor package 100d according to the embodiment may respectively have a structure in which a magnetic material mag in a powder form dispersed in a solder sol is combined with a first magnetic core mag1. In other embodiments, at least one second bump 130mag may have a structure in which Figure 3A and Figure 3B The second magnetic core mag2 has a structure mixed with a magnetic material mag having a powder form.

[0051] refer to Figure 4A and Figure 4B, at least one second bump 130mag of the semiconductor package (100e and 100f) according to the embodiment may include a dummy bump that is not connected to the plurality of first pads 112P1 or is not connected to the plurality of second pads 121. Therefore, the at least one second bump 130mag may not form an electrical connection path between the substrate 110 and the semiconductor chip 120, and may therefore be designed without considering the reliability of the electrical connection path (e.g., according to the influence of crack occurrence, energy loss due to an increase in specific resistance, signal integrity, power integrity, etc.). Therefore, the design freedom related to the magnetic permeability or magnetic properties of the at least one second bump 130mag may be further improved, and the at least one second bump 130mag may form a magnetic force more efficiently. In addition, even if the number of the at least one second bump 130mag may be relatively small compared to the plurality of first bumps 130, the horizontal position difference (e.g., offset) (e.g., position difference along the X-axis) may be stably offset. In addition, since the degree of freedom in arrangement of the at least one second bump 130mag can be further improved, the at least one second bump 130mag can be advantageously disposed at a desired position (eg, at a position adjacent to a corner of the semiconductor chip 120 ).

[0052] The volume of the at least one second bump 130mag may be greater than the volume of each of the plurality of first bumps 130. Therefore, since the at least one second bump 130mag may stably at least partially fill the space increased by not being connected to the plurality of first pads 121P1 or the plurality of second pads 121, the size imbalance between the at least one second bump 130mag and the plurality of first bumps 130 may be suppressed, and the warpage factor of the substrate 110 or the semiconductor chip 120 may be reduced. In other embodiments, since the horizontal dimension (e.g., the length in the X direction) of each of the at least one second bump 130mag may be greater than the horizontal dimension of each of the plurality of first bumps 130, and the at least one second bump 130mag may have a larger space for accommodating magnetic materials, the magnetic force may be further enhanced.

[0053] refer to Figure 4C and Figure 4D , the semiconductor package (100g and 100h) according to the embodiment may include a plurality of second bumps 130mag, and may not include a plurality of first bumps having relatively low magnetic permeability. Figure 4C , the magnetic structure of the dummy bump among the plurality of second bumps 130mag may be different from the magnetic structure of the second bump connected between the plurality of first pads 112P1 and the plurality of second pads 121. Figure 4D , the plurality of second bumps 130mag may be substantially equal to one another.

[0054] FIG. 5A to FIG. 5G The upper portion of each of the first and second bumps 130 and 130mag represents an arrangement of the plurality of first bumps 130 and the plurality of second bumps 130, and FIG. 5A to FIG. 5G The lower portion of each of represents the arrangement of the plurality of first pads 112P. The specific size, number, shape, and arrangement of the plurality of first bumps 130 and the plurality of second bumps 130mag and the plurality of pads 112P may vary depending on the design.

[0055] refer to FIG. 5A to FIG. 5G , among the plurality of bumps of the semiconductor package (100i, 100j, 100k, 100l, 100m, 100o, and 100p) according to the embodiment, the two bumps that are most adjacent to the two corners of the semiconductor chip 120 that are not adjacent to each other may be at least a portion of the second bumps 130mag among the plurality of second bumps 130mag. The two corners of the semiconductor chip 120 that are not adjacent to each other may be the upper right corner and the lower left corner or the upper left corner and the lower right corner of the semiconductor chip 120. In other embodiments, among the plurality of bumps, the four bumps that are most adjacent to each corner of the semiconductor chip 120 may be at least a portion of the second bumps 130mag among the plurality of second bumps 130mag. Reference Figure 5A , the spacing distance L1 between the corner of the semiconductor chip 120 and the second bump 130mag adjacent to the corner of the semiconductor chip 120 among the plurality of second bumps 130mag may be shorter than the spacing distance L2 between the corner of the semiconductor chip 120 and the first bump 130 most adjacent to the corner of the semiconductor chip 120 among the plurality of first bumps 130. Therefore, since the positional freedom or structural freedom of the plurality of second bumps 130mag may be further improved, the plurality of second bumps 130mag may form magnetic force more efficiently.

[0056] refer to Figure 5B , the spacing distance L3 between the two most adjacent second bumps among the plurality of second bumps 130mag can be longer than the spacing distance L4 between the two most adjacent first bumps among the plurality of first bumps 130. Therefore, the influence of the magnetic force of at least one second bump 130mag can be reduced or prevented from further increasing the horizontal position difference (e.g., offset) of the pad, and the magnetic force can stably reduce the horizontal position difference (e.g., offset) caused by the horizontal vector component of the magnetic force. FIG. 5A to FIG. 5E , the number of the at least one second bump 130mag may be less than the number of the plurality of first bumps 130 .

[0057] refer to Figure 5A , Figure 5B , Figure 5D and Figure 5G, the plurality of second bumps 130mag may be connected to a portion of the plurality of first pads 112P. Figure 5C , the plurality of second bumps 130mag may not be connected to the plurality of first pads 112P, and may overlap vertically (ie, along the Z axis) in the dummy region. Figure 5E and Fig. 5F , only a portion of the plurality of second bumps 130mag may be connected to a portion of the plurality of first pads 112P, and different portions of the plurality of second bumps 130mag may overlap vertically (ie, along the Z axis) in the dummy region.

[0058] refer to FIG. 5A to FIG. 5G , the arrangement of the plurality of first pads 112P may have a vacant area GP. FIG. 5A to FIG. 5E , the arrangement of the plurality of first bumps 130 may also have a structure in which the plurality of first bumps 130 are not arranged in a region vertically overlapping the empty region GP (ie, along the Z axis). Figure 5D and Fig. 5F At least a portion of the plurality of second bumps 130mag may be disposed in a region vertically overlapping the empty region GP (ie, along the Z axis). Fig. 5F and Figure 5G , the semiconductor package ( 100o and 100p ) according to the embodiment may include a plurality of second bumps 130mag, and may not include a plurality of first bumps having relatively low magnetic permeability.

[0059] refer to Fig. 6A ,and Figure 1 The semiconductor package 1000 may further include a second semiconductor package 200 disposed on the first semiconductor package 100q. For example, the semiconductor package 1000 may be a package-on-package (POP) type in which the second semiconductor package 200 is stacked on the first semiconductor package 100q, and may be a system-in-package (SIP) type in function.

[0060] With reference above Figures 1 to 2B Compared with the semiconductor package 100 a described above, the first semiconductor package 100 q may further include a conductive pillar 170 extending into or penetrating the encapsulant 150 and a substrate 180 located on the conductive pillar 170 .

[0061] The conductive pillar 170 may be disposed between the substrate 110 and the substrate 180 to electrically connect the substrate 110 and the substrate 180. The conductive pillar 170 may extend between the substrate 110 and the substrate 180 in a vertical direction (e.g., the Z direction) to provide a vertical connection path that electrically connects the interconnect layer 112 and the upper interconnect layer 182. The conductive pillar 170 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or an alloy containing these, and may be in a spherical shape or a ball shape extending in the Z direction.

[0062] The substrate 180 may be a substrate that provides an interconnection layer on the upper surface of the first semiconductor package 100q, and may be disposed between the lower package and the upper package in the POP structure. The substrate 180 may include an upper insulating layer 181, an upper interconnection layer 182, and an interconnection path 183. Since the upper insulating layer 181, the upper interconnection layer 182, and the interconnection path 183 may have the same or similar properties as the insulating layer 111, the interconnection layer 112, and the interconnection path 113 of the substrate 110 described above, respectively, overlapping descriptions will be omitted. The uppermost upper insulating layer 181 and the lowermost upper insulating layer 181 among the upper insulating layers 181 may be solder mask layers that may protect the upper interconnection layer 182, and may include an opening that exposes at least a portion of the upper interconnection layer 182.

[0063] The first semiconductor package 100q is shown having a Figures 1 to 2B The embodiment of the present invention includes a structure of the first pads 112P1 and 112P2 and the first solder mask layer 115, but the embodiment is not limited thereto. In example embodiments, the above reference 112P1 and 112P2 may be used in the first semiconductor package 100q. Figures 1 to 5G Any of the described embodiments.

[0064] The second semiconductor package 200 may include a substrate 210, an upper semiconductor chip 220, an upper encapsulant 230, and a plurality of first bumps 260. The structure of the second semiconductor package 200 is illustrative, and semiconductor packages having various structures may be stacked on the first semiconductor package 100q.

[0065] The substrate 210 may include an upper pad 212 and a lower pad 211 exposed through the upper surface and the lower surface. The substrate 210 may include, for example, silicon (Si), glass, ceramic, or plastic. The substrate 210 may include an electrical path 213 formed by an interconnection pattern therein, and the interconnection pattern may have a multilayer structure.

[0066] The upper semiconductor chip 220 may include a logic semiconductor chip and / or a memory semiconductor chip. The upper semiconductor chip 220 may have an active surface on the lower surface of the upper semiconductor chip 220 with a device layer disposed therebelow, but in various embodiments, the arrangement of the active surface may be changed. The upper semiconductor chip 220 may be mounted on the substrate 210 using a wire bonding method or a flip chip bonding method. For example, a plurality of upper semiconductor chips 220 may be vertically stacked on the substrate 210 and electrically connected to the upper pad 212 of the substrate 210 by bonding wires WB. For example, the upper semiconductor chip 220 may include a memory chip, and the semiconductor chip 120 of the first semiconductor package 100q may include an AP chip.

[0067] The upper encapsulant 230 may be disposed to at least partially surround the upper semiconductor chip 220, and may serve to protect the upper semiconductor chip 220. The upper encapsulant 230 may be formed of, for example, a silicone-based material, a thermosetting material, a thermoplastic material, a UV treatment material, or the like.

[0068] A plurality of first bumps 260 may be disposed on the lower surface of the substrate 210 and may be connected to at least a portion of the lower pads 211. The plurality of first bumps 260 may connect the second semiconductor package 200 to the first semiconductor package 100q thereunder, thereby enabling electrical connection between the first semiconductor package 100q and the second semiconductor package 200. The plurality of first bumps 260 may be implemented in a similar manner to the plurality of first bumps 130, and may therefore have a lower melting point than that of each lower pad 211, but the embodiment is not limited thereto.

[0069] At least one second bump 260mag may be disposed on the lower surface of the substrate 210, and may have a higher magnetic permeability than each of the plurality of first bumps 260. Therefore, since the at least one second bump 260mag may provide a magnetic force for offsetting a horizontal position (i.e., along the X-axis) difference (e.g., offset) when the first semiconductor package 100q and the second semiconductor package 200 are vertically bonded to each other, the bonding reliability of the POP structure of the first semiconductor package 100q and the second semiconductor package 200 may be improved. The at least one second bump 260mag may be implemented in a manner similar to the at least one second bump 130mag, but the embodiment may not be limited thereto.

[0070] refer to Figure 6B ,and Figure 1Different from the embodiment of the present invention, the semiconductor package 2000 may further include a plurality of upper semiconductor chips 220a stacked on the semiconductor chip 120a located on the substrate 110. For example, the semiconductor package 2000 may be a SIP, the semiconductor chip 120a may be a logic semiconductor chip, and the upper semiconductor chip 220a may be a memory semiconductor chip.

[0071] The semiconductor chip 120a of the present embodiment may have a first region CR1 located at a lower portion and a second region CR2 located at an upper portion, and may further include a device layer 122 and a through-via 125. The first region CR1 may be a device region, and may be a region where devices (such as transistors and / or memory cells) constituting the semiconductor chip are formed based on the second region CR2. The second region CR2 may be a substrate region, and may be, for example, a region containing a semiconductor material such as silicon (Si).

[0072] The device layer 122 may be disposed in the first region CR1 to configure the device. The through via 125 may pass through the second region CR2 of the semiconductor chip 120a. In some embodiments, the through via 125 may further pass through at least a portion of the first region CR1. The through via 125 may be electrically connected to the device layer 122 of the first region CR1, and may provide an electrical connection between the upper semiconductor chip 220a and the substrate 110. The through via 125 may be formed of a conductive material, and may include, for example, tungsten (W), aluminum (Al) and / or copper (Cu).

[0073] In addition to the above description, the above reference Figures 1 to 2B The description of the semiconductor package 100 a described above may also be equally applicable to the substrate 110 and the semiconductor chip 120 a .

[0074] The upper semiconductor chip 220a may be stacked along the Z direction and disposed on the semiconductor chip 120a. In addition to the uppermost upper semiconductor chip 220a, the upper semiconductor chip 220a may further include a through-via 125. The first connection region BS1 may be formed between the semiconductor chip 120a and the upper semiconductor chip 220a, and the second connection region BS2, the third connection region BS3, and the fourth connection region BS4 may be located between the upper semiconductor chips 220a, respectively. Although not specifically shown, at least a portion of the first connection region BS1, the second connection region BS2, the third connection region BS3, and the fourth connection region BS4 structure may be substantially the same as the connection region between the substrate 110 and the semiconductor chip 120a.

[0075] For example, in each of the first connection region BS1, the second connection region BS2, the third connection region BS3, and the fourth connection region BS4, the plurality of first bumps 260 may be connected to the plurality of second pads 221 of each upper semiconductor chip 220a. The plurality of first bumps 260 may be implemented similarly to the plurality of first bumps 130, and may therefore have a lower melting point than each of the plurality of second pads 221, but is not limited thereto.

[0076] For example, in each of the first connection area BS1, the second connection area BS2, the third connection area BS3, and the fourth connection area BS4, at least one second bump 260mag may be disposed on the upper surface or the lower surface of each upper semiconductor chip 220a, and may have a higher magnetic permeability than the magnetic permeability of each of the plurality of first bumps 260. Therefore, since the at least one second bump 260mag can provide a magnetic force for offsetting the horizontal position difference (i.e., along the X axis) between the upper semiconductor chips 220 when bonded to the upper semiconductor chip 220a in the vertical direction (i.e., along the Z axis), the bonding reliability of the upper semiconductor chip 220a can be improved. The at least one second bump 260mag may be implemented in a manner similar to the at least one second bump 130mag, but the embodiment is not limited thereto.

[0077] refer to Fig. 7A , a substrate 110 may be prepared on a carrier substrate 10. The substrate 110 may have a first solder mask layer 115 formed on an upper surface thereof. Through the opening OP of the first solder mask layer 115, a plurality of first pads 112P1 may be formed to be completely exposed, and a plurality of first pads 112P2 may be formed to be at least partially exposed.

[0078] According to design, a surface treatment layer ST may be selectively formed on surfaces of the plurality of first pads 112P1 and 112P2 exposed through the openings OP of the first solder mask layer 115. The surface treatment layer ST may be formed by, for example, a plating process, and may include gold (Au), silver (Ag), nickel (Ni), and / or palladium (Pd).

[0079] The solder sol and the first magnetic cores mag1 may be disposed on at least a portion of the upper surface of the plurality of first pads 112P1, and the number of the first magnetic cores mag1 may be less than the number of the solder sol.

[0080] refer to Figure 7B, the semiconductor chip 120 can be mounted on the substrate 110. A non-conductive film layer 140 can be formed on the lower surface of the semiconductor chip 120, and the semiconductor chip 120 can be prepared in a state where the solder sol and the second magnetic core mag2 are arranged on the lower surface of the plurality of second pads 121. The number of the second magnetic cores mag2 can be less than the number of the solder sol. In some embodiments, the non-conductive film layer 140 can be formed on the upper surface of the substrate 110. The semiconductor chip 120 can be bonded to the substrate 110 by, for example, a reflow process or a TCB process. In this case, the semiconductor chip 120 can be aligned on the substrate 110 using a separate bonding tool, and can be bonded to the substrate 110 by receiving heat and pressure from the bonding tool.

[0081] In this case, the first magnetic core mag1 located on the upper surface of the substrate 110 and the second magnetic core mag2 located on the lower surface of the semiconductor chip 120 can be attracted to each other by the magnetic force (FX). Therefore, the horizontal position difference (i.e., along the X-axis line) between the plurality of first pads 112P2 and the plurality of second pads 121 (e.g., offset) can be offset. Depending on the design, one of the first magnetic core mag1 or the second magnetic core mag2 can be omitted. For example, the first magnetic core mag1 may not be disposed on the upper surface of the substrate 110, the second magnetic core mag2 may be configured to apply an attractive force due to the magnetic force to the surface treatment layer ST, and the second magnetic core mag2 may be replaced by Figure 2A The magnetic material mag.

[0082] refer to Figure 7C , the substrate 110p can be arranged on the carrier substrate 10 as a semiconductor wafer in a combined state. In this case, the carrier substrate 10 can be implemented as an electrostatic chuck or the like, but the embodiment is not limited thereto. A plurality of semiconductor chips 120 can be arranged one by one on the upper surface of the substrate 110p by a pick-and-place device 40. The semiconductor wafer can be cut along the scribe line SL' and can be divided into a plurality of semiconductor packages 100p. The semiconductor package 100p according to the embodiment can further improve the alignment accuracy between the substrate 110p and the semiconductor chip 120 to help control the accuracy of the pick-and-place device 40.

[0083] refer to Figure 7C, the pick-and-place device 40 may include at least one coil 30 and / or a circuit 50. The at least one coil 30 may be configured to magnetize at least one second bump disposed on the lower surface of the semiconductor chip 120. In this case, the circuit 50 may output a large amount of current to the at least one coil 30 through the lead 41. In other embodiments, the circuit 50 may be configured to sense the magnetic force generated by the magnetic material or the first magnetic core on the upper surface of the substrate 110. For example, the circuit 50 may be configured to detect the resonant frequency of the LC resonance through a combination of at least one coil 30 and a capacitor, and the resonant frequency may be used as input information for controlling the pick-and-place device 40.

[0084] The semiconductor package according to the embodiment can effectively improve the bonding reliability of the substrate and / or the semiconductor chip in the vertical direction (i.e., along the Z axis). For example, even if the semiconductor chip and / or the pad are miniaturized, it is possible to effectively suppress the occurrence of incorrect electrical connection when bonding the substrate and / or the semiconductor chip in the vertical direction (i.e., along the Z axis).

[0085] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A substrate, the substrate comprising an insulating layer and a plurality of first pads located on the insulating layer; a semiconductor chip comprising a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping the at least a portion of the plurality of first pads in a first direction; as well as a plurality of bumps, the plurality of bumps being located on one surface of the substrate or one surface of the semiconductor chip, the melting point of at least a portion of the plurality of bumps being lower than the melting point of each of the plurality of first pads and the melting point of each of the plurality of second pads, Wherein, the plurality of bumps include a plurality of first bumps and at least one second bump, the plurality of first bumps are electrically connected to at least a portion of the plurality of first pads or at least a portion of the plurality of second pads, and the magnetic permeability of the at least one second bump is higher than the magnetic permeability of each first bump in the plurality of first bumps.

2. The semiconductor package according to claim 1, wherein: The at least one second bump comprises a plurality of second bumps, The spacing distance between two second bumps that are most adjacent to each other among the plurality of second bumps is greater than the spacing distance between two first bumps that are most adjacent to each other among the plurality of first bumps.

3. The semiconductor package according to claim 1, wherein: The number of the at least one second bump is less than the number of the plurality of first bumps.

4. The semiconductor package according to claim 3, wherein: The at least one second bump comprises a plurality of second bumps, The plurality of second bumps include two bumps among the plurality of bumps that are most adjacent to two non-adjacent corners of the semiconductor chip.

5. The semiconductor package according to claim 3, wherein: The at least one second bump comprises a plurality of second bumps, The plurality of second bumps include four bumps among the plurality of bumps that are most adjacent to each corner of the semiconductor chip.

6. The semiconductor package according to claim 1, wherein: The plurality of first bumps are connected between a first portion of the plurality of first pads and a first portion of the second pads among the plurality of second pads, and The at least one second bump is connected between a second portion of first pads among the plurality of first pads and a second portion of second pads among the plurality of second pads.

7. The semiconductor package according to claim 1, wherein: The at least one second bump includes a dummy bump that is not connected to the plurality of second pads.

8. The semiconductor package according to claim 1, wherein: The plurality of first bumps are connected between at least a portion of the plurality of first pads and at least a portion of the second pads. The at least one second bump includes a dummy bump that is not connected to the plurality of first pads or is not connected to the plurality of second pads.

9. The semiconductor package according to claim 1, wherein: A volume of each of the at least one second bump is greater than a volume of each of the plurality of first bumps.

10. The semiconductor package according to claim 1, wherein Each of the plurality of first bumps is in a spherical shape, and Wherein, each of the at least one second bump is in a spherical shape.

11. The semiconductor package according to claim 1, wherein: The at least one second bump includes a magnetic material having a higher magnetic permeability than a magnetic permeability of a material included in each of the plurality of first pads and a magnetic permeability of a material included in each of the plurality of second pads.

12. The semiconductor package according to claim 1, wherein The at least one second bump includes a ferromagnetic material.

13. The semiconductor package according to claim 1, wherein: The at least one second bump includes a permanent magnetic material.

14. The semiconductor package according to claim 1, wherein Each of the at least one second bump comprises: a first magnetic core; a second magnetic core configured to apply a magnetic force to the first magnetic core; and A solder contacts the first magnetic core and the second magnetic core, at least partially surrounds the first magnetic core and the second magnetic core, and has a melting point lower than that of the first magnetic core and the second magnetic core.

15. A semiconductor package, comprising: A substrate, the substrate comprising an insulating layer and a plurality of first pads located on the insulating layer; a semiconductor chip comprising a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping the at least a portion of the plurality of first pads in a first direction; as well as a plurality of bumps, the plurality of bumps being located on one surface of the substrate or one surface of the semiconductor chip, the melting point of at least a portion of the plurality of bumps being lower than the melting point of each of the plurality of first pads and the melting point of each of the plurality of second pads, Wherein, at least one of the plurality of convex blocks comprises: a first magnetic core; a second magnetic core configured to apply a magnetic force to the first magnetic core; and A solder contacts the first magnetic core and the second magnetic core, at least partially surrounds the first magnetic core and the second magnetic core, and has a melting point lower than that of the first magnetic core and the second magnetic core.

16. The semiconductor package according to claim 15, wherein: The first magnetic core contacts a first pad among the plurality of first pads, and The second magnetic core is in contact with a second soldering pad among the plurality of second soldering pads.

17. The semiconductor package according to claim 16, wherein: The first magnetic core and the second magnetic core protrude from the one first pad and the one second pad, respectively, and contact each other.

18. The semiconductor package according to claim 15, wherein: The first magnetic core and the second magnetic core each include ferromagnetic material or permanent magnetic material.

19. A semiconductor package, comprising: A substrate, the substrate comprising an insulating layer and a plurality of first pads located on the insulating layer; a semiconductor chip comprising a plurality of second pads electrically connected to at least a portion of the plurality of first pads, the plurality of second pads overlapping the at least a portion of the plurality of first pads in a first direction; as well as a plurality of bumps, the plurality of bumps being located on one surface of the substrate or one surface of the semiconductor chip, the melting point of at least a portion of the plurality of bumps being lower than the melting point of each of the plurality of first pads and the melting point of each of the plurality of second pads, Wherein, the plurality of bumps include: a plurality of first bumps connected between at least a portion of the plurality of first pads and at least a portion of the second pads; and a plurality of second bumps, the plurality of second bumps including dummy bumps that are not connected to the plurality of first pads or not connected to the plurality of second pads, Wherein, each of the plurality of second bumps comprises a ferromagnetic material or a permanent magnetic material.

20. The semiconductor package according to claim 19, wherein The plurality of second bumps include four bumps most adjacent to each corner of the semiconductor chip among the plurality of bumps.

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