Semiconductor device

Abstract

The invention provides a semiconductor device which can be miniaturized. A semiconductor device is provided with: a source electrode (12) provided on a substrate (10); a gate electrode (14) provided in a ring shape on the substrate and surrounding the source electrode; a drain electrode (16) provided on the substrate and surrounding the gate electrode from a first direction, a direction opposite the first direction, and a second direction orthogonal to the first direction; and a gate wiring (23) provided on the substrate, the first end of the gate wiring being connected to only one portion of the gate electrode, and the second end of the gate wiring being connected to the first gate bus bar.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known that in a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes are arranged along the direction in which the electrodes are arranged (eg, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] When a plurality of unit FETs are arranged, it is difficult to miniaturize the semiconductor device. If a semiconductor device is to be miniaturized, the design may become difficult. Summary of the invention

[0007] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to achieve miniaturization.

[0008] One embodiment of the present disclosure is a semiconductor device comprising: a source electrode disposed on a substrate; a gate electrode disposed on the substrate and surrounding a portion of the source electrode; a drain electrode disposed on the substrate and surrounding the gate electrode; and a gate wiring disposed on the substrate, a first end of which is connected only to one portion of the gate electrode and a second end of which is connected to a first gate bus.

[0009] Effects of the Invention

[0010] According to the present disclosure, miniaturization can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0012] Figure 2 yes Figure 1 A-A section view.

[0013] Figure 3 3 is a top view of the semiconductor device of Comparative Example 1.

[0014] Figure 4 3 is a top view of a semiconductor device according to Comparative Example 2.

[0015] Figure 5 It is a top view of a semiconductor device according to Modification 1 of Embodiment 1.

[0016] Figure 6 It is a top view of a semiconductor device according to a second variation of the first embodiment.

[0017] Figure 7 It is a top view of the semiconductor device of Example 2.

[0018] Figure 8 It is a top view of a semiconductor device according to a first variation of the second embodiment.

[0019] Fig. 9 This is a top view of a semiconductor device according to a second variation of the second embodiment.

[0020] Fig.10 It is a top view of a semiconductor device according to a third variation of the second embodiment.

[0021] Fig.11 It is a top view of the semiconductor device of Example 3.

[0022] Description of Reference Numerals

[0023] 10, 10a: substrate; 10b: semiconductor layer; 11: active region; 12: source electrode; 13: inactive region; 14, 14a, 14b, 14c, 14d: gate electrode; 16, 16a, 16b, 16c, 16d: drain electrode; 20: via; 23: gate wiring; 24, 24a, 24b: gate busbar; 25: gate pad; 26: drain busbar; 27: drain pad; 28, 28a: metal layer; 32: region; 34: unit; 35, 35a, 35b, 35c, 35d: unit FET; 36a, 36b: FET group; 37: ohmic contact layer; 38: low resistance layer; 39: gate metal layer; 40, 44: chip; 41, 45: dielectric layer; 42, 46: conductor pattern; 48: semiconductor chip; 50a, 50b, 50c: arrows; 51, 52: parts; 53: center point; 54: part; 55: range; 60: base; 61: frame; 62: input terminal; 63: output terminal; 65, 66, 67, 68: bonding wires; 100, 101, 102, 103, 104, 105, 106, 107, 110, 112: semiconductor device. DETAILED DESCRIPTION

[0024] [Description of Embodiments of the Present Disclosure]

[0025] First, the contents of the embodiments of the present disclosure will be listed and described.

[0026] (1) One embodiment of the present disclosure is a semiconductor device comprising: a source electrode provided on a substrate; a gate electrode provided on the substrate and surrounding a portion of the source electrode; a drain electrode provided on the substrate and surrounding the gate electrode; and a gate wiring provided on the substrate, a first end of which is connected to only one portion of the gate electrode and a second end of which is connected to a first gate bus bar. Thus, the semiconductor device can be miniaturized with easy design.

[0027] (2) In the above (1), the gate electrode may be provided on the substrate in a ring shape. This can achieve miniaturization.

[0028] (3) In the above (1), the drain electrode may be provided on the substrate so as to surround the gate electrode from a first direction, a direction opposite to the first direction, and a second direction intersecting the first direction. This can achieve miniaturization.

[0029] (4) In the above (3), the drain electrode may surround the gate electrode only from the first direction, the direction opposite to the first direction, and the second direction. This can achieve miniaturization.

[0030] (5) In the above (3), the first end of the gate wiring may be connected to a portion of the gate electrode that is not surrounded by the drain electrode in the opposite direction from the second direction, within a range having a width of 1 / 2 of the width of the portion in the first direction centered at a center point in the first direction. This allows the gate widths of the two FETs connected in parallel to be made close in practice, thereby making the design easier.

[0031] (6) In the above (3), the drain electrode may surround the gate electrode from the direction opposite to the second direction. This can increase the actual gate width, thereby achieving miniaturization.

[0032] (7) In the above (3), the width of the source electrode in the second direction may be less than 3 times and not less than 1 / 3 times the width of the source electrode in the first direction. This can improve heat dissipation.

[0033] (8) In any one of the above (1) to (7), the semiconductor device may include a metal layer, the metal layer being provided under the substrate and electrically connected to the source electrode via a via hole penetrating the substrate. This can achieve miniaturization.

[0034] (9) In the above (3), the substrate may have an active region where the semiconductor layer in the substrate is activated, and a region of the drain electrode surrounding the gate electrode from the first direction, the direction opposite to the first direction, and the second direction may be provided on the active region. Thus, miniaturization can be achieved.

[0035] (10) In the above (3), the semiconductor device may include: a FET group, the FET group includes a plurality of unit FETs arranged in the first direction, the plurality of unit FETs each including the source electrode, the gate electrode, and the drain electrode, and the adjacent unit FETs share the drain electrode; and a drain bus bar connected to the drain electrodes of the plurality of unit FETs in a first FET group in the FET group, so that the first FET group is arranged between the drain bus bar and the first gate bus bar, and the first gate bus bar is connected to the gate wiring of the plurality of unit FETs in the first FET group. Thus, it is easy to design a semiconductor device with a large gate width.

[0036] (11) In the above (10), the semiconductor device may include: a second FET group included in the FET group, the drain bus bar being arranged between the second FET group and the first FET group; and a second gate bus bar connected to gate wirings of a plurality of unit FETs in the second FET group, the second FET group being arranged between the second gate bus bar and the drain bus bar. Thus, it is easy to design a semiconductor device with a large gate width.

[0037] (12) In the above (11), the width of the drain busbar in the second direction may be greater than the width of the drain electrode in the first direction shared by the unit FETs adjacent in the first direction. This allows the current density of the drain busbar to be close to the current density of the drain electrode, thereby achieving miniaturization.

[0038] (13) In the above (11) or (12), the semiconductor device may include: a gate pad electrically connected to the first gate bus bar and the second gate bus bar; and a drain pad electrically connected to the drain bus bar, so that the first FET group and the second FET group are arranged between the drain pad and the gate pad. In this way, the gate pad and the drain pad can be efficiently arranged, thereby achieving miniaturization.

[0039] (14) In any one of the above (11) to (13), the semiconductor device may include a plurality of units arranged in the second direction, each of the plurality of units including the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar. Thus, the unit FETs can be efficiently arranged, thereby achieving miniaturization.

[0040] [Details of the embodiments of the present disclosure]

[0041] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0042] [Example 1]

[0043] Figure 1 This is a top view of the semiconductor device of Example 1. Figure 2 yes Figure 1 The thickness direction of the substrate 10 is defined as the Z direction, the direction between the drain electrode 16c and the gate bus bar 24 with the source electrode 12 interposed therebetween is defined as the X direction, and the direction between the drain electrode 16a and the drain electrode 16b with the source electrode 12 interposed therebetween is defined as the Y direction.

[0044] like Figure 1 and Figure 2 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region where the semiconductor layer 10b is deactivated by ion implantation or the like is the inactive region 13. The region where the semiconductor layer 10b is activated without being deactivated is the active region 11.

[0045] A source electrode 12, a gate electrode 14, a drain electrode 16, a gate wiring 23, a gate bus bar 24, and a drain bus bar 26 are provided on the substrate 10. The unit FET 35 includes the source electrode 12, the gate electrode 14, and the drain electrode 16.

[0046] The planar shape of the source electrode 12 is a substantially rectangular shape having sides extending in the X direction and the Y direction. The gate electrode 14 is provided in a ring shape so as to surround the source electrode 12. The gate electrode 14 includes gate electrodes 14a to 14d. The gate electrode 14a and the gate electrode 14b extend in the X direction, and the source electrode 12 is arranged between the gate electrode 14a and the gate electrode 14b in the Y direction. The gate electrode 14c and the gate electrode 14d extend in the Y direction, and the source electrode 12 is arranged between the gate electrode 14c and the gate electrode 14d in the X direction.

[0047] The drain electrode 16 surrounds the gate electrode 14 from the + direction (first direction) in the Y direction, the - direction (the opposite direction to the first direction) in the Y direction, and the - direction (the second direction orthogonal to the first direction) in the X direction. The drain electrode 16 includes drain electrodes 16a to 16c. The gate electrodes 14a to 14c are respectively arranged between the drain electrodes 16a to 16c and the source electrode 12. The source electrode 12, the gate electrodes 14a to 14c, and the drain electrodes 16a to 16c are provided on the active region 11 of the substrate 10.

[0048] The unit FET 35 includes unit FETs 35a to 35c. The unit FET 35a includes a source electrode 12, a gate electrode 14a, and a drain electrode 16a. The unit FET 35b includes a source electrode 12, a gate electrode 14b, and a drain electrode 16b. The unit FET 35c includes a source electrode 12, a gate electrode 14c, and a drain electrode 16c.

[0049] The gate electrode 14d is provided on the inactive region 13 of the substrate 10. The gate bus bar 24 is provided in a region on the inactive region 13 of the substrate 10 provided along the + direction in the X direction of the gate electrode 14d, and extends in the Y direction. The gate wiring 23 is provided on the inactive region 13, and electrically connects the gate electrode 14d and the gate bus bar 24 to short-circuit them.

[0050] The drain bus bar 26 includes the drain electrode 16c and the drain electrode 16 provided on the inactive region 13, and extends in the Y direction. In the X direction, the unit FET 35 is arranged between the gate bus bar 24 and the drain bus bar 26.

[0051] The via hole 20 penetrates the substrate 10 and is connected to the source electrode 12. A metal layer 28 is provided on the lower surface of the substrate 10. A metal layer 28a is provided on the inner surface of the via hole 20. Thus, the metal layer 28 is electrically connected to the source electrode 12 via the via hole 20 to form a short circuit. A reference potential such as a ground potential is provided to the metal layer 28.

[0052] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the unit FET 35 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the gallium nitride channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs) semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0053] The source electrode 12 and the drain electrode 16 include an ohmic contact layer 37 and a low resistance layer 38. The gate wiring 23 and the gate bus 24 include a gate metal layer 39 and a low resistance layer 38. The ohmic contact layer 37 is a metal layer in ohmic contact with the semiconductor layer 10b, for example, a titanium film and an aluminum film from the substrate 10 side. The low resistance layer 38 is a metal layer having a lower resistivity than an ohmic contact layer such as a gold layer. The gate electrode 14 and the gate metal layer 39 are metal films, for example, a nickel film and a gold film from the substrate 10 side. An insulating layer may be provided in a manner covering the source electrode 12, the gate electrode 14, the drain electrode 16, the gate wiring 23, and the gate bus 24. The insulating layer is, for example, an inorganic insulating film such as a silicon nitride layer or an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer. Figure 2 In the embodiment, the width of the ohmic contact layer 37 and the gate metal layer 39 is greater than the width of the low resistance layer 38, but the width of the ohmic contact layer 37 and the gate metal layer 39 may be the same as the width of the low resistance layer 38. In addition, the low resistance layer 38 may not be provided.

[0054] [Comparative Example 1]

[0055] Figure 3 is a top view of the semiconductor device of Comparative Example 1. Figure 3 As shown, in the semiconductor device 110 of Comparative Example 1, the gate electrodes 14c, 14d and the drain electrode 16c are not provided. The gate electrodes 14a and 14b are directly connected to the gate bus 24. The drain electrodes 16a and 16b are directly connected to the drain bus 26. The drain bus 26 is provided on the inactive region 13. In Comparative Example 1, two unit FETs 35a and 35b are provided for one source electrode 12. The other structures are the same as those of Example 1.

[0056] [Comparative Example 2]

[0057] Figure 4 is a top view of the semiconductor device of Comparative Example 2. Figure 4 As shown, in the semiconductor device 112 of Comparative Example 2, a gate electrode 14c is provided to connect the - end of the gate electrode 14a in the X direction with the - end of the gate electrode 14b in the X direction. A drain electrode 16c is provided to connect the - end of the drain electrode 16a in the X direction with the - end of the drain electrode 16b in the X direction. The drain electrode 16c is provided on the active region 11. Thus, three unit FETs 35a to 35c are provided for one source electrode 12. Thus, compared with Comparative Example 1, the gate width of the unit FET 35 can be increased. The output of one source electrode 12 can be increased, and high output can be achieved. If the same output power is considered, the miniaturization of the semiconductor device can be achieved. The other structures are the same as those in Example 1, and the description is omitted.

[0058] When a high-frequency signal is supplied from the - end in the Y direction of the gate bus 24 as indicated by arrow 50c, one of the signals after branching flows through the gate bus 24 as indicated by arrow 50a and then flows through the gate electrode 14a. The other signal after branching flows through the gate electrodes 14b and 14c as indicated by arrow 50b. The signal flowing through arrow 50a and the signal flowing through arrow 50b merge at a portion 52 where the electrical lengths of arrows 50a and 50b are the same, i.e., a portion where the gate electrode 14a and the gate electrode 14c are connected. Therefore, the unit FET 35 can actually be regarded as a FET in which two FETs, a first FET having unit FET 35a and a second FET having unit FETs 35b and 35c, are connected in parallel. The actual gate widths of the first FET and the second FET up to the portion 52 are different. In this case, when designing a transistor for high frequency by arranging a plurality of unit FETs 35, it is necessary to actually consider FETs with different gate widths, and the design becomes difficult.

[0059] [Description of Example 1]

[0060] According to Example 1, Figure 1 As shown, the first end of the gate wiring 23 is connected only to the portion 51 (one portion) in the gate electrode 14, and the second end of the gate wiring 23 is connected to the gate bus 24. Thus, one of the high-frequency signals that has passed through the gate wiring 23 and has been branched at the portion 51 reaches the portion 52 in the gate electrode 14c as shown by the arrow 50a. The other branched signal reaches the portion 52 in the gate electrode 14c as shown by the arrow 50b through the portion of the gate electrode 14d and the gate electrode 14b. The portion 52 where the electrical length of the arrow 50a is the same as the electrical length of the arrow 50b is approximately the center of the gate electrode 14c. Thus, the unit FET 35 can actually be regarded as a FET formed by connecting the first FET having the unit FET 35a and a portion of the unit FET 35c and the second FET having the unit FET 35b and a portion of the unit FET 35c in parallel. Compared with Comparative Example 2, the actual gate widths of the first FET and the second FET can be made close. Therefore, when designing a high-frequency transistor by arranging a plurality of unit FETs 35, the design becomes easy. Thus, in the first embodiment, the semiconductor device 100 which is easy to design can be miniaturized.

[0061] In the first embodiment, the drain electrode 16 does not surround the gate electrode 14 from the + direction in the X direction (the opposite direction to the second direction). That is, the drain electrode 16 surrounds the gate electrode 14 only from the + direction in the Y direction, the - direction in the Y direction, and the - direction in the X direction. In this way, the drain electrode 16 does not need to be provided between the source electrode 12 and the gate bus bar 24. Thus, miniaturization can be achieved.

[0062] exist Figure 1In the figure, portion 54 is a portion of the gate electrode 14 that is not surrounded by the drain electrode 16 in the + direction in the X direction. The width of portion 54 in the Y direction is W1. The center point in the Y direction of portion 54 is set as center point 53. Range 55 is a range with a width W2 centered at center point 53, and the width W2 is 1 / 2 of the width W1 of portion 54 in the Y direction. At this time, the first end of the gate wiring 23 is connected to the range 55. As a result, the actual gate widths of the two FETs actually connected in parallel in the unit FET 35 can be made closer. As a result, it is easier to design when arranging multiple unit FETs 35 to design a transistor for high frequency. The width W2 of range 55 can be set to 1 / 3 of the width W1, or can be set to 1 / 4 of the width W1.

[0063] The metal layer 28 is provided under the substrate 10 and is electrically connected to the source electrode 12 via the via hole 20 penetrating the substrate 10. Thus, a reference potential can be provided to the source electrode 12. In the case where the source electrode 12 has one via hole 20, the actual gate width of the unit FET 35 per via hole 20 can be increased. Thus, miniaturization can be achieved.

[0064] The region of the drain electrode 16 surrounding the gate electrode 14 in the + and - directions in the Y direction and the - direction in the X direction is provided on the active region 11. Thus, the drain electrode 16c can function as the drain electrode of the unit FET 35c. Thus, miniaturization can be achieved.

[0065] [Variation 1 of Example 1]

[0066] Figure 5 FIG. 1 is a top view of a semiconductor device according to a first variation of the first embodiment. Figure 5 As shown, in the semiconductor device 101 of the modification 1 of the embodiment 1, the FET groups 36a and 36b are arranged in the X direction. The FET groups 36a and 36b have a plurality of unit FETs 35 arranged in the Y direction. The unit FETs 35 adjacent in the Y direction share a drain electrode 16. The FET groups 36a and 36b share a drain bus 26 and are arranged mirror-symmetrically with respect to the drain bus 26 in the X direction. The gate electrodes 14 of the plurality of unit FETs 35 of the FET group 36a are electrically connected to the gate bus 24a to be short-circuited. The gate electrodes 14 of the plurality of unit FETs 35 of the FET group 36b are electrically connected to the gate bus 24b to be short-circuited. In the X direction, the FET group 36a is arranged between the gate bus 24a and the drain bus 26, and in the X direction, the FET group 36b is arranged between the gate bus 24b and the drain bus 26.

[0067] The gate busbars 24a, 24b and the drain busbar 26 extend in the Y direction. The gate pad 25 and the drain pad 27 are arranged so that the FET groups 36a and 36b are arranged therebetween in the Y direction. The - ends of the gate busbars 24a and 24b in the Y direction are electrically connected to the gate pad 25 to form a short circuit. The + end of the drain busbar 26 in the Y direction is electrically connected to the drain pad 27 to form a short circuit. The number of unit FETs 35 in each of the FET groups 36a and 36b may be two, three or more than five. The other structures are the same as those in Example 1 and the description is omitted.

[0068] As shown in the first variation of the first embodiment, the FET group 36a (first FET group) has a plurality of unit FETs 35 arranged in the Y direction, and the drain electrodes 16 of the adjacent unit FETs 35 are shared. The gate bus 24a (first gate bus) is electrically connected to the gate electrodes 14 of the plurality of unit FETs 35 of the FET group 36a. The drain bus 26 is connected to the drain electrodes 16 of the unit FETs 35 of the FET group 36a. The FET group 36a is arranged between the drain bus 26 and the gate bus 24a. With such a structure, the unit FETs 35 can be arranged in the Y direction, and the gate width of the semiconductor device 101 can be increased. Since the unit FETs 35 having substantially the same characteristics are arranged, it is easy to design the semiconductor device 101 with a large gate width.

[0069] The drain bus 26 is arranged between the FET group 36a and the FET group 36b (second FET group). The FET group 36b is arranged between the drain bus 26 and the gate bus 24b (second gate bus). Thus, the unit FETs 35 can be arranged in the Y direction, and the gate width of the semiconductor device 101 can be increased. Since the unit FETs 35 with substantially the same characteristics are arranged, it is easy to design the semiconductor device 101 with a large gate width.

[0070] The gate pad 25 connected to the gate bus bars 24a and 24b and the drain pad 27 connected to the drain bus bar 26 are provided so that the FET groups 36a and 36b are arranged therebetween. Thus, a gate potential can be supplied from the gate pad 25 to the gate electrodes 14 of the FET groups 36a and 36b via the gate bus bars 24a and 24b. A drain potential can be supplied from the drain pad 27 to the drain electrodes 16 of the FET groups 36a and 36b via the drain bus bar 26. In this way, the gate pad 25 and the drain pad 27 can be efficiently arranged, thereby achieving miniaturization.

[0071] A larger current flows through the drain bus 26 than through the drain electrode 16 shared by the adjacent unit FETs 35 in the Y direction. By making the current density of the drain bus 26 and the current density of the drain electrode 16 shared by the adjacent unit FETs 35 in the Y direction equal, miniaturization can be achieved. Figure 5As shown, the width W3 of the drain bus 26 in the X direction is made larger than the width W4 of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction in the Y direction. As a result, the current density of the drain bus 26 can be made close to the current density of the drain electrode 16 shared by the unit FETs 35 adjacent in the Y direction. As a result, the semiconductor device 101 can be miniaturized. The width W3 can be set to be 1.5 times or more of the width W4, and can be set to be 2 times or more of the width W4. From the viewpoint of not making the current density of the drain bus 26 too small, the width W3 can be set to be 10 times or less of the width W4.

[0072] The width of the source electrode 12 in the X direction is, for example, greater than 0.1 μm and less than 200 μm, and is 50 μm as an example. The width of the source electrode 12 in the Y direction is, for example, greater than 0.1 μm and less than 200 μm, and is 50 μm as an example. The gate length of the gate electrode 14 is, for example, greater than 0.05 μm and less than 5 μm. The width W3 of the drain bus 26 in the X direction is, for example, greater than 10 μm and less than 200 μm, and is 50 μm as an example. The width W4 of the drain electrode 16 in the Y direction shared by the unit FETs 35 adjacent in the Y direction is, for example, greater than 10 μm and less than 100 μm, and is 25 μm as an example. The width of the drain electrode 16c in the X direction is, for example, greater than 5 μm and less than 50 μm, and is 12 μm as an example. The distance between the gate electrode 14d and the gate bus bars 24a and 24b in the X direction is, for example, 0.1 μm or more and 100 μm or less, and is 5 μm as an example. The width of the gate bus bars 24a and 24b in the X direction is, for example, 0.05 μm or more and 500 μm or less, and is 30 μm as an example. The width of the gate wiring 23 in the Y direction is, for example, 0.05 μm or more and 500 μm or less, and is 1.0 μm as an example.

[0073] [Variation 2 of Example 1]

[0074] Figure 6 FIG. 1 is a top view of a semiconductor device according to a second variation of the first embodiment. Figure 6 As shown, in the semiconductor device 102 of the second variation of the first embodiment, a plurality of units 34 having FET groups 36a, 36b, gate busbars 24a, 24b, and drain busbars 26 are arranged in the X direction. A gate pad 25 is provided in each unit 34, and a drain pad 27 is provided in each unit 34. The gate pads 25 of the plurality of units 34 may also be provided in connection. The drain pads 27 of the plurality of units 34 may also be provided in connection. The number of units 34 may be two, three, or more than five. The other structures are the same as those of the first variation of the first embodiment, and the description thereof is omitted.

[0075] As shown in the second modification of the first embodiment, by arranging the cells 34 in the X direction, a plurality of unit FETs 35 can be efficiently arranged. This enables miniaturization.

[0076] [Example 2]

[0077] Figure 7 FIG. 2 is a top view of the semiconductor device of Example 2. Figure 7 As shown, in the semiconductor device 103 of Example 2, the drain electrode 16 includes not only the drain electrodes 16a to 16c but also the drain electrode 16d. The drain electrode 16d is provided between the gate electrode 14d and the gate bus 24. The drain electrode 16d is provided on the active region 11. The unit FET 35d includes the source electrode 12, the gate electrode 14d and the drain electrode 16d. The drain electrode 16d is divided into two in the Y direction. A region 32 in which the drain electrode 16d is not provided is provided between the divided drain electrodes 16d. The region 32 extends in the X direction. The gate wiring 23 is provided in the region 32 and does not overlap with the drain electrode 16d. In addition, the gate wiring 23 is provided on the inactive region 13. The other structures are the same as those in Example 1 and the description is omitted.

[0078] According to the second embodiment, the drain electrode 16 surrounds the gate electrode 14 from the + direction in the X direction. Figure 1 In contrast, the actual gate width of the unit FET 35 sharing one source electrode 12 can be increased. Thus, the semiconductor device 103 can be further miniaturized. For miniaturization, the width of the region 32 in the Y direction can be set to be less than 1 / 2 of the width of the gate electrode 14d in the Y direction.

[0079] As in Example 1, the first end of the gate wiring 23 is connected to only one portion of the gate electrode 14. Thus, the unit FET 35 can be regarded as a FET in which the first FET and the second FET having substantially the same actual gate width are connected in parallel. Thus, when a plurality of unit FETs 35 are arranged to design a transistor for high frequency, the design is easy. Furthermore, compared with Comparative Example 2, the actual gate width can be increased, so that miniaturization is possible.

[0080] In the second embodiment, regardless of the position of the portion 51 where the gate wiring 23 is connected to the gate electrode 14, the actual gate width of the FET from the portion 51 via the gate electrode 14a to the portion 52 and the actual gate width of the FET from the portion 51 via the gate electrode 14b to the portion 52 are substantially the same. This makes design easier.

[0081] [Variation 1 of Example 2]

[0082] Figure 8 FIG. 1 is a top view of a semiconductor device according to a first variation of the second embodiment. Figure 8As shown, in the semiconductor device 104 of the modification 1 of the second embodiment, the width Wx of the source electrode 12 in the X direction is substantially the same as the width Wy in the Y direction. The planar shape of the source electrode 12 is substantially square. Thus, the actual gate width of the unit FET 35 can be maximized while making the planar shape area of ​​the source electrode 12 the same. In addition, the heat can be diffused in all directions. Thus, the heat dissipation can be improved. The other structures are the same as those of the second embodiment, and the description is omitted.

[0083] From the perspective of increasing the actual gate width and heat dissipation, the width Wx can be set to be less than 3 times and more than 1 / 3 times the width Wy, can be set to be less than 2 times and more than 1 / 2 times the width Wy, and can be set to be less than 1.5 times and more than 1 / 1.5 times the width Wy. Similarly, in Embodiment 1 and its modified examples, the width Wx can be set to be less than 3 times and more than 1 / 3 times the width Wy, can be set to be less than 2 times and more than 1 / 2 times the width Wy, and can be set to be less than 1.5 times and more than 1 / 1.5 times the width Wy.

[0084] [Variation 2 of Example 2]

[0085] Fig. 9 FIG. 2 is a top view of a semiconductor device according to a second variation of the second embodiment. Fig. 9 As shown, in the semiconductor device 105 of the second modification of the second embodiment, the unit FET 35 is the unit FET 35 of the second embodiment. The number of unit FETs 35 in each of the FET groups 36a and 36b can be two, three, or five or more. The other structures are the same as those of the first modification of the first embodiment, and the description thereof is omitted.

[0086] As shown in the second modification of the second embodiment, the unit FETs 35 having the drain electrodes 16d may be arranged in the Y direction. Thus, the gate width of the semiconductor device 105 can be increased. The width W3 of the drain bus 26 in the X direction is larger than the width W4 of the drain electrode 16 in the Y direction shared by the unit FETs 35 adjacent in the Y direction. Thus, a larger current can flow through the drain bus 26 than through the drain electrode 16 of the unit FET 35.

[0087] [Variation 3 of Example 2]

[0088] Fig.10 FIG. 2 is a top view of a semiconductor device according to a third variation of the second embodiment. Fig.10 As shown, in the semiconductor device 106 of the modification example 3 of the embodiment 2, the unit FET 35 is the unit FET 35 of the embodiment 2. The number of units 34 can be two, three, or five or more. The other structures are the same as the modification example 2 of the embodiment 1, and the description is omitted. As shown in the modification example 3 of the embodiment 2, the units 34 can also be arranged in the X direction.

[0089] [Example 3]

[0090] Fig.11 FIG. 1 is a top view of the semiconductor device of Example 3. Fig.11 As shown in FIG. 1 , in the semiconductor device 107, an insulating frame 61 of ceramic or the like is mounted on a base 60 of metal such as copper. An input terminal 62 and an output terminal 63 are provided on the frame 61. The chips 40 and 44 and the semiconductor chip 48 are mounted on the base 60. The semiconductor chip 48 is, for example, a semiconductor chip of the second modification of the first embodiment. Figure 6 The semiconductor device 102 of the embodiment 2 or the modification 3 of the embodiment 2 Fig.10 Semiconductor device 106. Chip 40 includes dielectric layer 41, conductor pattern 42 provided on dielectric layer 41, and conductor pattern (not shown) provided under dielectric layer 41. Chip 44 includes dielectric layer 45, conductor pattern 46 provided on dielectric layer 45, and conductor pattern (not shown) provided under dielectric layer 45. Conductor pattern 42, conductor pattern 46, input terminal 62, and output terminal 63 are metal layers such as gold layer. Gate pad 25 and drain pad 27 are provided on semiconductor chip 48. Fig.11 In the figure, the unit 34 and the like are omitted.

[0091] The bonding wire 65 electrically connects the input terminal 62 and the conductor pattern 42. The bonding wire 66 electrically connects the conductor pattern 42 and the gate pad 25. The bonding wire 67 electrically connects the drain pad 27 and the conductor pattern 46. The bonding wire 68 electrically connects the conductor pattern 46 and the output terminal 63.

[0092] The conductor pattern 42 sandwiching the dielectric layer 41 and the conductor pattern under the dielectric layer 41 function as a capacitor connected in a shunt. The bonding wire 65, the bonding wire 66, and the chip 40 form an input matching circuit. The conductor pattern 46 sandwiching the dielectric layer 45 and the conductor pattern under the dielectric layer 45 function as a capacitor connected in a shunt. The bonding wire 67, the bonding wire 68, and the chip 44 form an output matching circuit.

[0093] The high-frequency signal input from the input terminal 62 is input to the semiconductor chip 48 via the chip 40. The high-frequency signal amplified in the semiconductor chip 48 is output from the output terminal 63 via the chip 44. Figure 6 and the modification 3 of the embodiment 2 Fig.10 As shown in FIG. 1 , the gate pad 25 and the drain pad 27 are provided on the long sides of the substrate 10. Therefore, the bonding wires 66 and 67 can be easily bonded to the gate pad 25 and the drain pad 27. As shown in Example 3, the semiconductor devices of Examples 1 and 2 and their modified examples may also adopt a structure in which a semiconductor chip is mounted in a package.

[0094] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A source electrode is disposed on the substrate; a gate electrode, disposed on the substrate and surrounding a portion of the source electrode; a drain electrode, disposed on the substrate and surrounding the gate electrode; and The gate wiring is arranged on the substrate, a first end of which is connected to only one part of the gate electrode, and a second end of which is connected to the first gate bus bar.

2. The semiconductor device according to claim 1, wherein The gate electrode is arranged on the substrate in a ring shape.

3. The semiconductor device according to claim 1 or 2, wherein: The drain electrode is disposed on the substrate, and surrounds the gate electrode from a first direction, a direction opposite to the first direction, and a second direction intersecting the first direction.

4. The semiconductor device according to claim 3, wherein: The drain electrode surrounds the gate electrode only from the first direction, the direction opposite to the first direction, and the second direction.

5. The semiconductor device according to claim 3, wherein: The first end of the gate wiring is connected to a portion of the gate electrode that is not surrounded by the drain electrode in the direction opposite to the second direction, within a range having a width that is 1 / 2 of the width of the portion in the first direction centered at a center point in the first direction.

6. The semiconductor device according to claim 3, wherein: The drain electrode surrounds the gate electrode from a direction opposite to the second direction.

7. The semiconductor device according to claim 3, wherein: The width of the source electrode in the second direction is less than or equal to 3 times and more than or equal to 1 / 3 times the width of the source electrode in the first direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein: A metal layer is provided, wherein the metal layer is provided under the substrate and is electrically connected to the source electrode via a via hole penetrating the substrate.

9. The semiconductor device according to claim 3, wherein: The substrate has an active region where a semiconductor layer within the substrate is activated, A region of the drain electrode that surrounds the gate electrode from the first direction, the direction opposite to the first direction, and the second direction is provided on the active region.

10. The semiconductor device according to claim 3, wherein The semiconductor device comprises: an FET group including a plurality of unit FETs arranged in the first direction, each of the plurality of unit FETs including the source electrode, the gate electrode, and the drain electrode, and adjacent unit FETs sharing the drain electrode; and a drain bus bar connected to the drain electrodes of a plurality of unit FETs in a first FET group in the FET group, so that the first FET group is arranged between the drain bus bar and the first gate bus bar, The first gate bus bar is connected to gate wirings of a plurality of unit FETs in the first FET group.

11. The semiconductor device according to claim 10, comprising: A second FET group included in the FET group, with the drain bus bar arranged between the second FET group and the first FET group; and The second gate bus is connected to gate wirings of a plurality of unit FETs in the second FET group, so that the second FET group is arranged between the second gate bus and the drain bus.

12. The semiconductor device according to claim 11, wherein The width of the drain bus bar in the second direction is greater than the width of the drain electrode in the first direction shared by the unit FETs adjacent to each other in the first direction.

13. The semiconductor device according to claim 11 or 12, comprising: a gate pad electrically connected to the first gate bus bar and the second gate bus bar; and The drain pad is electrically connected to the drain bus bar, so that the first FET group and the second FET group are arranged between the drain pad and the gate pad.

14. The semiconductor device according to any one of claims 11 to 13, wherein: A plurality of units are provided which are arranged in the second direction, and each of the plurality of units includes the first FET group, the second FET group, the drain bus bar, the first gate bus bar, and the second gate bus bar.

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