Low electromagnetic radiation on-board charger control circuit

Abstract

The present invention relates to a low electromagnetic radiation on-board charger control circuit, comprising K high-voltage surge voltage signal sampling circuits, M current signal sampling circuits, N slowly varying voltage signal sampling circuits, R temperature detection circuits, a digital quantization and control processing module, and a gate drive circuit. The present invention first obtains a high-voltage surge voltage error code and a large current error code through sampling circuit detection, and multiplies K groups of high-voltage surge voltage error codes and K groups of large current error codes at the same time and then sums them to obtain an EMI total radiation energy value, which is compared with the reference radiation value under each working mode of the charger system, and the clock frequency control code, waveform duty cycle control code, and waveform category control code are adjusted, and then the gate control signal is adjusted to adjust the EMI total radiation energy value. The present invention adopts a high-voltage surge voltage sampling circuit to more directly judge the EMI radiation energy generated by each surge voltage, and the total EMI radiation detection and control method can quickly achieve EMI index control.

Description

Technical Field

[0001] The present invention relates to a low electromagnetic radiation on-board charger control circuit, belonging to the technical field of new energy vehicles. Background Art

[0002] The onboard charger is a core functional module required for electric vehicles. It converts AC mains power into DC power to charge the vehicle's power battery. As consumer demand for EV mileage increases, battery capacity continues to rise. However, electric vehicles have limited space and heat dissipation capabilities, leading to higher market demands for the power density and efficiency of onboard chargers. To achieve this, the most direct technical approach is to increase the switching frequency of the power devices in the charger's power conversion system. However, this increased switching frequency inevitably leads to serious electromagnetic interference (EMI), a core technical specification for automotive-grade products.

[0003] On-board chargers generally adopt a two-level architecture, such as Figure 1 As shown, the front-stage AC / DC converter converts AC power into a constant DC voltage and also performs power factor correction. The rear-stage DC / DC converter draws power from the busbar of the front-stage circuit, providing isolation and voltage regulation. The operating states of both the front-stage AC / DC converter and the rear-stage DC / DC converter are controlled by a separate charger control circuit. This control circuit detects the voltage signals Vx and Ix of the front-stage AC / DC converter and provides feedback, which controls the switching states of the power devices within the front-stage AC / DC converter and the rear-stage DC / DC converter, respectively, to charge the load battery. Because the DC / DC converter is connected to a battery, it requires a wide voltage regulation range. Furthermore, the battery charging process requires precise feedback control. Choosing an appropriate charging strategy significantly improves the charging performance of the on-board charger and is an essential element of on-board charger design.

[0004] Therefore, the function and performance composition of the on-board charger control circuit have a crucial impact on the overall performance of the charger. Summary of the Invention

[0005] The present invention addresses the electromagnetic interference problem encountered in the implementation of a high-power density on-board charger and proposes an on-board charger control circuit with low electromagnetic interference characteristics, which has important practical significance for improving the safety and stability of the overall electric vehicle power supply system.

[0006] For the above-mentioned two-stage on-board charger, the low electromagnetic radiation on-board charger control circuit provided by the present invention includes: K high-voltage rapid voltage signal sampling circuits, M current signal sampling circuits, N slowly varying voltage signal sampling circuits, R temperature detection circuits, J high-side power device gate drive circuits, J low-side power device gate drive circuits, and a digital quantization and control processing module;

[0007] The input ends of the K high-voltage surge voltage signal sampling circuits are respectively connected to the high-voltage surge signal generating nodes inside the front-stage AC / DC converter and the back-stage DC / DC converter in the on-board charger, specifically the power output nodes of the K half-bridge arms, and the node voltage is V X1 ~V XK , output K high voltage sudden change voltage detection signals V Xt1 ~V XtK ;

[0008] The input ends of the M current signal sampling circuits are respectively connected to the large current signal output nodes inside the front-stage AC / DC converter and the back-stage DC / DC converter in the on-board charger, and the current I of the power output nodes of the K half-bridge arms is collected. L1 ~I LK And MK charger output current I L(K+1) ~I LM , output M large current detection signals I Lt1 ~I LtM ;

[0009] The N slowly varying voltage signal sampling circuits sample the status of the AC input voltage Vin, the output DC charging voltage Vout, the DC bus voltage Vbus and other slowly varying voltage signals of the on-board charger in real time, and output N slowly varying voltage detection signals V t1 ~V tN ;

[0010] The R temperature detection circuits detect the temperature of each physical space in the on-board charger respectively and output R temperature detection signals V Tt1 ~V TtR ;

[0011] The K high-voltage surge voltage detection signals V Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM , N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtR All are connected to the digital quantization and control processing module for processing and obtain J high-side gate control signals DS1H ~DS JH and J low-side gate control signals DS 1L ~DS JL ; Among them, J high-side gate control signals DS 1H ~DS JH They are connected to J high-side power device gate drive circuits and output J high-side power device gate drive signals S 1H ~S JH ; J low-side gate control signals DS 1L ~DS JL They are connected to J low-side power device gate drive circuits and output J low-side power device gate drive signals S 1L ~S JL ; Gate drive signal S 1H ~S JH and S 1L ~S JL The gates of the power switching devices in the K half-bridge arms are controlled respectively, thereby achieving modulation control of the states of the preceding AC / DC converter and the subsequent DC / DC converter;

[0012] Wherein, K is a positive integer greater than 2, M is a positive integer greater than K, N is a positive integer greater than 3, R is any positive integer, and J is a positive integer greater than or equal to K.

[0013] Specifically, the high-voltage surge voltage signal sampling circuit includes: an optocoupler device U1, a detection resistor Rt1, a detection resistor Rt2, a diode D2, a differential capacitor C1, a differential resistor Rd1, a differential resistor Rd2 and an operational amplifier A1; wherein, the optocoupler U1, the detection resistor Rt1, the detection resistor Rt2, and the diode D2 complete the high-voltage surge voltage isolation and voltage division detection functions, and the differential capacitor C1, the differential resistor Rd1, the differential resistor Rd2 and the operational amplifier A1 constitute a differential conduction circuit; the rapid change process of the voltage signal input at the power output node of the half-bridge arm will be converted into a corresponding differential derivative signal output, and the voltage amplitude of the differential derivative signal is proportional to the switching slope of the voltage signal of the half-bridge arm power output node, and is proportional to the energy of the EMI interference source.

[0014] Specifically, the digital quantization and control processing module includes: an analog input selection circuit, a high-precision analog-to-digital converter, a FIFO register group, a first MUX selector, a reference data memory, a second MUX selector, a data error calculation circuit and a comprehensive control processing circuit;

[0015] The K high-voltage surge voltage detection signals V Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM, N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtR All are input to the input end of the analog input selection circuit, and are output to the analog signal input port of the high-precision analog-to-digital converter in sequence under the control of the analog selection control signal CK1. The selection switch input port of the analog input selection circuit must be greater than K+M+N+R; under the control of the control signal CK2, the high-precision analog-to-digital converter converts each input analog voltage signal in sequence and outputs the corresponding K+M+N+R digital codes Dx; the clock frequency of the control signal CK2 is equal to that of the analog selection control signal CK1; the K+M+N+R digital codes Dx will enter the FIFO register group in a first-in-first-out manner, and obtain K high-voltage induced voltage quantization codes DV through data serial-to-parallel conversion. Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR ;

[0016] The above K high voltage quantization codes DV Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR Connected to the data input terminal of the first MUX selector, and output to the sampled data input port of the data error calculation circuit in sequence under the control of the data selection control signal CK3;

[0017] Reference data memory outputs reference voltage data DRV X , refer to high current data DRI L , reference ramp voltage data DRV and reference temperature data DRT, connected to the data input terminal of the second MUX selector, and also output to the reference data input port of the data error calculation circuit in sequence under the control of the data selection control signal CK3;

[0018] The data error calculation circuit calculates the difference between the data of the sampling data input port and the reference data input port, performs serial-to-parallel conversion and data synchronization on the difference data, and finally outputs K high-voltage voltage error codes DeV X1 ~DeV XK, M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT R All error codes are synchronously input to the integrated control processing circuit, and J high-side gate control signals DS are obtained after processing. 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL .

[0019] Specifically, the integrated control processing circuit includes: an error reference data memory, a sudden voltage average calculation circuit, a current average calculation circuit, a slowly changing voltage average calculation circuit, a temperature average calculation circuit, a multimodal signal fusion processing circuit, a clock frequency control circuit, a waveform duty cycle control circuit, a waveform type control circuit and an output drive waveform synthesizer;

[0020] The error reference data memory is configured to store the error reference data according to the mode control code D provided by the multi-modal signal fusion processing circuit. mod Output surge voltage reference error data DRV Xe , High current reference error data DRI Le , slowly changing voltage reference error data DRV e and temperature reference error data DRT e , respectively connected to the reference error data input ports of the surge voltage average calculation circuit, current average calculation circuit, slow voltage average calculation circuit and temperature average calculation circuit; K high-voltage surge voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT RThe error code data input terminals of the surge voltage average calculation circuit, the current average calculation circuit, the slowly varying voltage average calculation circuit and the temperature average calculation circuit are input synchronously respectively; the surge voltage average calculation circuit, the current average calculation circuit, the slowly varying voltage average calculation circuit and the temperature average calculation circuit respectively perform error average calculation according to the data of their respective reference error data input ports and the error code data input terminals, and respectively generate surge voltage average signal Des, current average signal Dei, slowly varying voltage average signal Dev and temperature average signal Det; the surge voltage average signal Des, current average signal Dei, slowly varying voltage average signal Dev and temperature average signal Det et synchronously enters the multimodal signal fusion processing circuit for comprehensive calculation processing, and the obtained mode control code Dmod is connected to the error reference data memory, and the obtained clock frequency control code Dcfr, waveform duty cycle control code Dcpw, and waveform type control code Dctyp are respectively generated by the clock frequency control circuit, waveform duty cycle control circuit, and waveform type control circuit to generate frequency control word freq, duty cycle control word pwd, and waveform type control word type, and connected to the output drive waveform synthesizer; finally, the output drive waveform synthesizer outputs J high-side gate control signals DS according to the frequency control word freq, duty cycle control word pwd, and waveform type control word type 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL .

[0021] The multimodal signal fusion processing circuit realizes detection and control of EMI electromagnetic radiation of the on-board charger according to the EMI intensity calculation method;

[0022] The EMI intensity calculation method first detects the high voltage sudden change voltage error code DeV at the same time. X1 ~DeV XK , large current error code DeI L1 ~DeI LM , multiply the K groups of high-voltage sudden voltage error codes and K groups of high-current error codes corresponding to the power output nodes of the K half-bridge arms at the same time in pairs and then sum them to obtain the EMI total radiation energy value; then compare the EMI total radiation energy value with the reference radiation value under each working mode of the on-board charger system; if the intensity of the EMI total radiation energy value exceeds the reference radiation value, the multimodal signal fusion processing circuit will adjust the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp, thereby changing the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type; finally, by adjusting the J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS1L ~DS JL The pulse width, frequency and waveform mode are used to adjust the total EMI radiation energy value.

[0023] In addition to controlling the basic operating mode of the on-board charger, the multimodal signal fusion processing circuit also needs to control the startup process of the on-board charger;

[0024] The startup sequence of the on-board charger is as follows: First, turn off J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL ; After the on-board charger is connected to AC power, the front-stage AC / DC converter performs a soft start process, and the DC bus voltage slowly increases. After the soft start, the AC input current is close to 0; when the DC bus voltage stabilizes, the front-stage AC / DC converter enters normal closed-loop control, and the multimodal signal fusion processing circuit controls all high-side and low-side gate drive signals in the front-stage AC / DC converter to turn on; the rear-stage DC / DC converter starts, and the multimodal signal fusion processing circuit controls all high-side and low-side gate drive signals in the rear-stage DC / DC converter to turn on. When the output voltage or current of the on-board charger reaches a given value, the startup process ends, and the on-board charger starts to work normally and performs normal power transmission and charging.

[0025] After the on-board charger completes the normal startup process, it normally detects the key current and voltage signals in the front-stage AC / DC converter and the back-stage DC / DC converter, and digitally quantizes the detection signals. The quantization code and the reference data are calculated in the error calculation circuit to obtain the state error, namely: the sudden change voltage mean signal Des, the current mean signal Dei, the slow change voltage mean signal Dev and the temperature mean signal Det; the multimodal signal fusion processing circuit reads the error mean calculation result and performs comprehensive calculation to determine whether the function and performance indicators of the on-board charger are normal; if the system state is abnormal, it enters the interrupt protection measure; if the system state is normal, the multimodal signal fusion processing circuit will adjust the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp according to the error mean calculation result, and then change the frequency control word freq, the duty cycle control word pwd and the waveform type control word type, and finally adjust the J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL The pulse width, frequency and waveform mode are used to control the status mode of the on-board charger.

[0026] The advantages of the present invention are as follows: the present invention first obtains a high-voltage surge voltage error code and a high-current error code through sampling circuit detection, and multiplies K groups of high-voltage surge voltage error codes and K groups of high-current error codes at the same time and then sums them to obtain the EMI total radiation energy value; the EMI total radiation energy value is compared with the reference radiation value under each operating mode of the charger system, and then the multimodal signal fusion processing circuit adjusts the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp. Finally, by adjusting the pulse width and frequency and waveform mode of J high-side gate control signals and J low-side gate control signals, the operating mode of the main power conversion circuit of the on-board charger is controlled and the EMI total radiation energy value is adjusted. The present invention adds a high-voltage surge voltage sampling circuit to the existing technology, which can more directly determine the EMI radiation energy generated by each surge voltage. The present invention proposes a total EMI radiation detection and control method, which can quickly achieve EMI index control. The solution of the present invention can be widely used in various types of charger power supply systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a typical two-stage on-board charger circuit diagram.

[0028] Figure 2 This is a structural block diagram of the control circuit of the low electromagnetic radiation on-board charger of the present invention.

[0029] Figure 3 Schematic diagram of sampling voltage and current signals of a power converter according to the present invention.

[0030] Figure 4 This is an embodiment of the high-voltage surge voltage signal sampling circuit of the present invention.

[0031] Figure 5 This is a structural block diagram of the digital quantization and control processing module of the present invention.

[0032] Figure 6 It is a structural block diagram of the comprehensive control processing circuit of the present invention.

[0033] Figure 7 This is a flow chart of the charger startup control of the present invention.

[0034] Figure 8 This is a flow chart of the normal working mode of the charger of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0036] like Figure 2As shown, the low-electromagnetic radiation on-board charger control circuit of the present invention includes: K high-voltage, rapidly changing voltage signal sampling circuits, M current signal sampling circuits, N slowly changing voltage signal sampling circuits, R temperature detection circuits, a digital quantization and control processing module, J high-side power device gate drive circuits, and J low-side power device gate drive circuits. Based on the main power conversion circuit of the on-board charger being controlled, K is a positive integer greater than 2, M is a positive integer greater than K, N is a positive integer greater than 3, R is any positive integer, and J is a positive integer greater than or equal to K.

[0037] The input ends of the K high-voltage surge voltage signal sampling circuits are respectively connected to the high-voltage surge signal generating nodes inside the front-stage AC / DC converter and the rear-stage DC / DC converter in the two-stage on-board charger, which are usually the voltage V of the power output nodes of the K half-bridge arms. X1 ~V XK , get K high voltage sudden change voltage detection signals V Xt1 ~V XtK .

[0038] The input ends of the M current signal sampling circuits are respectively connected to the large current signal output nodes inside the front-stage AC / DC converter and the rear-stage DC / DC converter in the two-stage on-board charger, usually the current I of the power output nodes of the K half-bridge arms. L1 ~I LK And the output current I of other sampling points of the charger K+1 ~I LM , get M large current detection signals I Kt1 ~I LtM .

[0039] The N slowly varying voltage signal sampling circuits sample the states of the AC input voltage Vin, the output DC charging voltage Vout, the DC bus voltage Vbus and other slowly varying voltage signals in real time to obtain N slowly varying voltage detection signals V t1 ~V tN .

[0040] The R temperature detection circuits respectively detect the temperature of each physical space in the front-stage AC / DC converter and the rear-stage DC / DC converter in the two-stage on-board charger, and obtain R temperature detection signals V Tt1 ~V TtR .

[0041] The high voltage surge voltage detection signal V Xt1 ~V XtK , large current detection signal I Kt1 ~I LtM , slowly changing voltage detection signal V t1 ~V tN, Temperature detection signal V Tt1 ~V TtR All are input to the digital quantization and control processing module to process and obtain J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL . High side gate control signal DS 1H ~DS JH Output to J high-side power device gate drive circuits to obtain J high-side power device gate drive signals S 1H ~S JH ; Low side gate control signal DS 1L ~DS JL Output to J low-side power device gate drive circuits to obtain J low-side power device gate drive signals S 1L ~S JL .

[0042] Figure 2 The low electromagnetic radiation on-board charger control circuit of the present invention adopts a slowly varying voltage signal sampling circuit to sample the voltages Vin, Vbus, Vout and other important voltage signals in the two-stage on-board charger respectively, adopts a high-voltage sudden change voltage signal sampling circuit to sample the power output nodes of the K half-bridge arms in the two-stage on-board charger respectively, and adopts a current signal sampling circuit to sample the current of the large current signal output nodes in the two-stage on-board charger in real time; adopts a temperature detection circuit to detect the temperature of each physical space in the two-stage on-board charger respectively; and obtains K high-voltage sudden change voltage detection signals V through the above detection. Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM , N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtR , and all are input into the digital quantization and control processing module for processing, and J high-side gate control signals and J low-side gate control signals are obtained; J high-side gate control signals are passed through the high-side power device gate drive circuit to obtain J high-side power device gate drive signals S 1H ~S JH ; J low-side gate control signals pass through the low-side power device gate drive circuit to obtain J low-side power device gate drive signals S 1L ~S JL ;S 1H ~S JH and S 1L ~S JLIt is used to control the gates of the power switching devices in the K half-bridge arms of the two-stage on-board charger, thereby realizing modulation control of the states of the front-stage AC / DC converter and the rear-stage DC / DC converter.

[0043] In existing on-board charger implementations, signal sampling and control circuits typically only sample the voltages Vin, Vbus, and Vout, as well as the output current and bus current. Based on the states of these voltage and current signals, the states of the front-stage AC / DC converter and the back-stage DC / DC converter in the two-stage on-board charger are controlled. This control approach can control the charger's output charging voltage and current, but it struggles to detect and control the charger's electromagnetic interference characteristics. The present invention, based on this traditional control approach, employs a high-voltage, induced voltage signal sampling circuit to sample the power output nodes of the K half-bridge arms within the front-stage AC / DC converter and the back-stage DC / DC converter, respectively. A current signal sampling circuit samples the current of all high-current signal output nodes within the front-stage AC / DC converter and the back-stage DC / DC converter in real time. Furthermore, a temperature detection circuit is employed to monitor the temperature of various physical spaces within the front-stage AC / DC converter and the back-stage DC / DC converter. By detecting the voltage, current, and temperature states of more nodes within the charger, the operating state of the two-stage charger can be more accurately controlled.

[0044] Figure 3 Schematic diagram of sampling voltage and current signals of a power converter according to the present invention. Figure 3 The left side shows a typical full-bridge output drive circuit, which includes two half-bridge arm output circuits. The left half-bridge arm output node Vx drives an inductive or capacitive load. X The driving current of the inductive or capacitive load is I L The high-voltage bus voltage that powers the two half-bridge arms is Vbus. The two half-bridge arms are controlled by four power semiconductor switching devices, and the working states of the four power semiconductor switching devices are controlled by gate drive signals S1, S2, S3, and S4. Among the above signals, the high-voltage bus voltage is Vbus, which is usually a slowly varying voltage signal. In a charger with a 400V voltage platform, Vbus is in the range of 200-500V; the gate drive signals S1, S2, S3, and S4 are usually 20KHz to 1MHz pulse waveform signals. Therefore, the output node Vx of the half-bridge arm is usually a high-voltage, large-amplitude, rapid-change signal with the same frequency as the gate drive signal and a maximum voltage of Vbus. The load current I L This is usually a fluctuating signal with the same frequency as the gate drive signal. Typically, the main source of EMI interference in power conversion systems is rapidly changing high-power voltage and current node signals. Figure 3 The EMI interference source of the circuit is the output node V of the half-bridge arm. XTherefore, the present invention detects the main source of electromagnetic interference of the charger by detecting the output node V X At the moment of rapid voltage change, it is used to comprehensively judge whether the EMI interference of the charger exceeds the set value, and the charger working state control circuit adjusts the gate output drive signal S1, S2, S3, and S4 to control the four power switching devices respectively, thereby achieving Figure 3 The EMI interference state of the power converter is controlled.

[0045] The solution of the present invention simultaneously controls the high voltage bus voltage Vbus, the half bridge arm output node Vx and the load current I L The high voltage bus voltage is Vbus and the load current is I L The rate of change is relatively slow, and the existing voltage and current sampling technology can be used. Figure 3 The right side shows the present invention for the half-bridge arm output node V X Schematic diagram of the principle of high-voltage surge voltage signal sampling. As mentioned above, the steeper the voltage and current change slopes of the high-current power device switching signals in the power converter, the greater the EMI interference generated. The slope of the voltage signal can be detected by differential derivation. The half-bridge arm output node V X When the signal is stable, the differential derivative signal V xt Output is 0; when the half-bridge arm output node V X The signal has a step-up process, and is processed by the differential conduction circuit. The differential derivative signal V xt Will become a voltage of magnitude dV / dt; the half-bridge arm output node V X The signal remains stable again, and the differential derivative signal V xt The output is 0; similarly, when the half-bridge arm output node V X The signal shows a step-down process, and the differential derivative signal V xt It will become a voltage of -dV / dt. It can be seen that after using the differential conduction circuit, the half-bridge arm output node V X The rapid change of the voltage signal will be converted into the corresponding differential derivative signal V xt , and the differential derivative signal V xt The voltage amplitude of the half-bridge arm output node V X The switching slope is proportional to the switching voltage, and therefore proportional to the energy of the EMI interference source.

[0046] Figure 4This is an embodiment of the high-voltage surge voltage signal sampling circuit of the present invention. The circuit includes: the positive electrode of the input end of the optocoupler U1 is connected to the cathode of the diode D2 and is connected to the input end of the high-voltage surge voltage signal sampling circuit through the detection resistor Rt1; the negative electrode of the input end of the optocoupler U1 is connected to the anode of the diode D2 and is connected to the ground signal GNDH through the detection resistor Rt2; the positive electrode of the output end of the optocoupler U1 is connected to the inverting input end of the operational amplifier A1 through the differential capacitor C1; the output end of the operational amplifier A1 is connected to the inverting input end of the amplifier A1 through the differential resistor Rd1 and serves as the output end of the high-voltage surge voltage signal sampling circuit; the non-inverting input end of the operational amplifier A1 is connected to the upper end of the differential resistor Rd2; the lower end of the differential resistor Rd2 and the negative electrode of the output end of the optocoupler U1 are connected to the ground signal GND.

[0047] Among them, the optocoupler device U1, the detection resistor Rt1, the detection resistor Rt2, and the diode D2 complete the high-voltage surge voltage isolation and voltage division detection functions, and the differential capacitor C1, the differential resistor Rd1, the differential resistor Rd2 and the operational amplifier A1 constitute a differential conduction circuit. Since the half-bridge arm output node Vx is usually a high-voltage large-amplitude surge signal with the same frequency as the gate drive signal and a maximum voltage of Vbus, it is necessary to first perform voltage division and isolation. The present invention uses the optocoupler device U1, the detection resistor Rt1, the detection resistor Rt2, and the diode D2 to complete this function, and obtain a low-voltage surge voltage signal IN with a maximum amplitude of 5V, and then passes through the differential capacitor C1, the differential resistor Rd1, the differential resistor Rd2 and the operational amplifier A1 to form a differential conduction circuit to obtain the final high-voltage surge voltage detection signal V xt In practical applications, different resistance values ​​of Rt1 are needed to achieve different derivative amplification factors for signal sampling, so that the high voltage voltage detection signal V xt It does not exceed the range of the subsequent high-precision quantization ADC circuit.

[0048] Figure 5 for Figure 2 The digital quantization and control processing module includes an analog input selection circuit 1, a high-precision ADC 2, a FIFO register group 3, a first MUX selector 4, a reference data memory 5, a second MUX selector 6, a data error calculation circuit 7, and an integrated control processing circuit 8.

[0049] K high-voltage surge voltage detection signals V Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM , N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtRAll are input to the input end of the analog input selection circuit 1, and are output to the analog signal input port of the high-precision ADC 2 in sequence under the control of the analog selection control signal CK1 (the selection switch input port of the analog input selection circuit 1 must be greater than K+M+N+R); the high-precision ADC 2 will convert each input analog voltage signal in sequence under the control of the control signal CK2 to obtain K+M+N+R digital codes Dx corresponding to each, wherein the clock frequency of the control signal CK2 and the analog selection control signal CK1 must be equal; the K+M+N+R digital codes Dx converted by the high-precision ADC 2 will enter the FIFO register group 3 in a first-in-first-out manner, and obtain K high-voltage induced voltage quantization codes DV through data serial-to-parallel conversion. Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR .

[0050] The above K high voltage quantization codes DV Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR Then it enters the data input end of the first MUX selector 4 and is sequentially output to the sampling data input port of the data error calculation circuit 7 under the control of the data selection control signal CK3.

[0051] The reference data memory 5 will output the reference voltage data DRV X , refer to high current data DRI L , reference ramp voltage data DRV and reference temperature data DRT are input to the data input terminal of the second MUX selector 6, and are also output to the reference data input port of the data error calculation circuit 7 in sequence under the control of the data selection control signal CK3.

[0052] The data error calculation circuit 7 calculates the difference between the data of the sampling data input port and the reference data input port, and performs serial-to-parallel conversion and data synchronization on the difference data, and finally obtains K high-voltage sudden voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM, N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT R .

[0053] Finally, K high voltage voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT R Synchronously input to the integrated control processing circuit 8 and process to obtain J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL .

[0054] Figure 5 The digital quantization and control processing module shown needs to be set according to different application scenarios when it is implemented in the actual charger circuit. Taking the commonly used 6KW charger as an example, the front-stage AC / DC converter of the two-stage on-board charger usually adopts a PFC converter, and the rear-stage DC / DC converter adopts an LLC converter to further convert the output DC charging voltage Vout, and the Vout output charging current is Iout. In order to achieve a power output of 6KW, the front-stage PFC converter needs to adopt a full-bridge structure converter, and the rear-stage LLC converter also needs to adopt a full-bridge structure. Therefore, a total of 6 half-bridge arm drive structures are required for the two-stage converter. Therefore, the input end of the analog input selection circuit 1 needs to be connected to 6 high-voltage surge voltage detection signals V Xt1 ~V Xt6 and 7 high current detection signals I Lt1 ~I Lt7 In addition, the slow-changing voltage detection signal can be set to 4 V t1 ~V t4 , the temperature detection signal can be set to 2 V Tt1 ~V Tt2 , then the input end of the analog input selection circuit 1 needs to be connected to 25 analog input ports. The high-precision ADC 2 will convert the 25 input analog voltage signals in sequence to obtain 25 corresponding digital codes Dx, and enter the FIFO register group 3 in a first-in-first-out manner. After the data is serial-to-parallel converted, 6 high-voltage voltage quantization codes DV are obtained. Xt1 ~DV Xt6 , 7 large current quantization codes DI Lt1 ~DI Lt7 , 4 slowly changing voltage quantization codes DV t1 ~DVt4 , 4 temperature quantization codes DT t1 ~DT t4 The data error calculation circuit 7 processes the above data and finally obtains 6 high voltage voltage error codes DeV X1 ~DeV X6 , 7 large current error codes DeI L1 ~DeI L7 , 4 slowly varying voltage error codes DeV1~DeV4, 2 temperature error codes DeT1~DeT2, and then input to the integrated control processing circuit 8 to process and obtain 6 high-side gate control signals DS 1H ~DS 6H and 6 low-side gate control signals DS 1L ~DS 6L .

[0055] Figure 6 for Figure 5 The block diagram of the integrated control processing circuit 8 is shown in FIG. The integrated control processing circuit 8 includes an error reference data memory 81, a surge voltage average calculation circuit 82, a current average calculation circuit 83, a slow voltage average calculation circuit 84, a temperature average calculation circuit 85, a multimodal signal fusion processing circuit 86, a clock frequency control circuit 87, a waveform duty cycle control circuit 88, a waveform type control circuit 89, and an output drive waveform synthesizer 90.

[0056] The error reference data memory 81 will be based on the mode control code D provided by the multi-modal signal fusion processing circuit 86. mod Output surge voltage reference error data DRV Xe , High current reference error data DRI Le , slowly changing voltage reference error data DRV e and temperature reference error data DRT e , respectively enter the reference error data input port of the surge voltage average calculation circuit 82, the current average calculation circuit 83, the slow voltage average calculation circuit 84 and the temperature average calculation circuit 85. K high-voltage surge voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT RThe error code data input terminals of the sudden voltage average calculation circuit 82, the current average calculation circuit 83, the slowly varying voltage average calculation circuit 84 and the temperature average calculation circuit 85 are input synchronously; the sudden voltage average calculation circuit 82, the current average calculation circuit 83, the slowly varying voltage average calculation circuit 84 and the temperature average calculation circuit 85 respectively perform error average calculation based on the data of their respective reference error data input ports and the error code data input terminals, and generate a sudden voltage average signal Des, a current average signal Dei, a slowly varying voltage average signal Dev and a temperature average signal Det respectively. The rapidly varying voltage mean signal Des, the current mean signal Dei, the slowly varying voltage mean signal Dev, and the temperature mean signal Det are synchronously fed into a multimodal signal fusion processing circuit 86 for comprehensive computational processing, generating a clock frequency control code Dcfr, a waveform duty cycle control code Dcpw, and a waveform type control code Dctyp. These signals are then fed into a clock frequency control circuit 87, a waveform duty cycle control circuit 88, and a waveform type control circuit 89, respectively, to generate a frequency control word freq, a duty cycle control word pwd, and a waveform type control word type. Finally, an output drive waveform synthesizer 90 generates J high-side gate control signals and J low-side gate control signals based on the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type.

[0057] Taking the 6KW two-stage charger as an example, the six high-voltage voltage error codes DeV are usually obtained by testing the front-stage AC / DC converter and the back-stage DC / DC converter of the on-board charger. X1 ~DeV X6 , 7 large current error codes DeI L1 ~DeI L7 , four slowly varying voltage error codes DeV1-DeV4, and two temperature error codes DeT1-DeT2, which respectively enter the surge voltage average calculation circuit 82, current average calculation circuit 83, slowly varying voltage average calculation circuit 84, and temperature average calculation circuit 85. Assuming the data bandwidth of the multimodal signal fusion processing circuit 86 is 16 bits, after data error calculation, a 16-bit clock frequency control code Dcfr, a 16-bit waveform duty cycle control code Dcpw, and a 16-bit waveform type control code Dctyp are obtained. These codes enter the clock frequency control circuit 87, the waveform duty cycle control circuit 88, and the waveform type control circuit 89, respectively, to generate a 16-bit frequency control word freq, a 16-bit duty cycle control word pwd, and a 16-bit waveform type control word type. Finally, the output drive waveform synthesizer 90 generates six high-side gate control signals and six low-side gate control signals based on the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type.

[0058] The above process achieves precise control of the on-board charger's performance. A key step is the output of the error reference data memory 81, which stores the sudden voltage reference error data DRVXe, high current reference error data DRILe, slowly varying voltage reference error data DRVe, and temperature reference error data DRTe. These values ​​should be centered around the typical operating conditions of the on-board charger while also covering the extreme conditions that may occur during the charger's operation. The error reference data memory 81 should also contain corresponding error data for different operating modes. During lithium battery charging, the battery experiences varying degrees of temperature rise and polarization. Therefore, the charging current should be limited to a reasonable range, and the charging current should change with temperature rise and polarization. This requires a combination of constant current or constant voltage charging, two-stage charging, pulse charging, and multi-stage constant current charging strategies. In the present invention, the charger's operating mode is determined by the mode control code Dmod, which is obtained by the multimodal signal fusion processing circuit 86 through comprehensive processing of the sudden voltage mean signal Des, the current mean signal Dei, the slowly varying voltage mean signal Dev, and the temperature mean signal Det. Therefore, the various reference error data stored in error reference data memory 81 require modeling of the charger circuit operating parameters and actual parameter testing. By sampling a large amount of experimental data and then performing statistical analysis, the distribution range and central value of the reference data can be determined. The aforementioned surge voltage average calculation circuit 82, current average calculation circuit 83, slow voltage average calculation circuit 84, and temperature average calculation circuit 85 utilize the same digital summation and averaging circuit, primarily consisting of a data shift register, a cumulative adder circuit, and a multiplication unit. This section is prior art and will not be further elaborated.

[0059] The main function of the multimodal signal fusion processing circuit 86 is to perform comprehensive discrimination processing on the mean value of the voltage and current state error of the two-stage on-board charger. Therefore, a more complex discrimination processing model algorithm is required. Various existing PID algorithms, artificial intelligence neural network algorithms and other algorithm models can be used as implementation means. The detection and control of the EMI electromagnetic radiation of the charger by the present invention is mainly realized by the multimodal signal fusion processing circuit 86 based on the EMI intensity calculation method. The EMI intensity calculation method first detects K high-voltage sudden voltage error codes DeV at the same time. X1 ~DeV XK , M large current error codes DeI L1 ~DeI LMThe K groups of high-voltage sudden voltage error codes and K groups of high-current error codes corresponding to the power output nodes of the K half-bridge arms at the same time are multiplied in pairs and then summed to obtain the EMI total radiation energy value; the EMI total radiation energy value is then compared with the reference radiation value under each working mode of the on-board charger system; if the intensity of the EMI total radiation energy value exceeds the reference radiation value, the multimodal signal fusion processing circuit 86 will adjust the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp, thereby changing the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type; finally, by adjusting the J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL The pulse width, frequency and waveform mode are used to adjust the total EMI radiation energy value.

[0060] In addition to controlling the basic charger operation mode, the multimodal signal fusion processing circuit 86 also needs to control the charger startup process. Figure 7 This is the charger startup control flow chart of the present invention. Since the charger uses two-stage power conversion circuits to perform power conversion simultaneously, when the charger is started, the operating modes of the front and rear power converters need to be properly set. The startup sequence of the charger of the present invention is as follows: First, turn off the J high-side gate control signals DS used by the half-bridge arms of the front and rear converters. 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL After AC power is supplied to the charger, the front-stage AC / DC converter performs a soft start process, and the DC bus voltage Vbus slowly increases. After the soft start, the AC input current is almost 0. When the DC bus voltage Vbus stabilizes, the front-stage AC / DC converter enters normal closed-loop control, and the multimodal signal fusion processing circuit 86 controls the high-side and low-side gate drive signals in all front-stage AC / DC converters to turn on. The rear-stage DC / DC converter starts, and the multimodal signal fusion processing circuit 86 controls the high-side and low-side gate drive signals in all rear-stage DC / DC converters to turn on. When the output voltage or current of the entire machine reaches a given value, the startup process ends, and the charger starts to work normally and performs normal power transmission and charging.

[0061] For the front-stage AC / DC converter, when the converter starts up, the DC bus Vbus is equivalent to a short circuit, resulting in a large inrush current at the moment of startup. The peak inrush current will increase with the increase in power level and needs to be limited by software and hardware. At this time, the back-stage DC / DC converter circuit does not work. When AC voltage is applied to the AC side, the multimodal signal fusion processing circuit 86 first controls the shutdown of all half-bridge arm power switches. At this time, the DC bus Vbus capacitor voltage will rise to the peak of the AC input voltage. The multimodal signal fusion processing circuit 86 then controls the activation of the corresponding gate drive signal of the half-bridge arm power switch of the preceding AC / DC converter, causing the power switch control of the preceding power half-bridge to switch to the normal operating circuit, allowing the bus voltage to continue to rise to the set value. Since the circuit operates consistently in a no-load state during this process, the DC bus voltage will continue to rise, requiring a hiccup mode to control the output voltage. That is, when the voltage exceeds the set value, the multimodal signal fusion processing circuit 86 shuts off the corresponding gate drive signal of the preceding AC / DC converter. At this time, the preceding AC / DC converter circuit is in a no-load state, and the input current is almost zero, thereby achieving soft start of the preceding AC / DC converter. After completing the startup of the preceding AC / DC converter circuit, the system begins the soft start of the subsequent DC / DC converter. On the one hand, by adjusting the operating frequency of the switching device, soft start is achieved with high frequency and low gain at startup. On the other hand, when working in constant current or constant voltage mode, the given reference voltage and current values ​​are given as a ramp function, that is, they slowly increase from 0 to the reference value.

[0062] Figure 8 This is a flow chart of the normal working mode of the charger of the present invention. When the on-board charger completes the normal startup process, the control circuit normally detects the key current and voltage signals in the front-stage AC / DC converter and the back-stage DC / DC converter, and digitally quantizes the detection signals. The quantization code and the reference data are calculated in the error calculation circuit 7 to obtain the state error, namely: the sudden change voltage average signal Des, the current average signal Dei, the slowly change voltage average signal Dev and the temperature average signal Det; the multimodal signal fusion processing circuit 86 will read the sudden change voltage average calculation circuit 82, the current average calculation circuit 83, the slowly change voltage average calculation circuit 84 and the temperature average signal Det. The error mean calculation result output by the calculation circuit 85 is used for comprehensive calculation to determine whether the function and performance indicators of the on-board charger are normal; if the system status is abnormal, the interrupt protection measures such as short circuit protection and over-temperature protection are implemented; if the system status is normal, the multimodal signal fusion processing circuit 86 will adjust the clock frequency control code Dcfr, waveform duty cycle control code Dcpw, and waveform type control code Dctyp according to the error mean calculation result, and then change the frequency control word freq, duty cycle control word pwd and waveform type control word type, and finally adjust the J high-side gate control signals DS 1H ~DSJH and J low-side gate control signals DS 1L ~DS JL The pulse width, frequency and waveform mode are used to control the status mode of the on-board charger.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. Low electromagnetic radiation on-board charger control circuit, the on-board charger includes a front-stage AC / DC converter and a rear-stage DC / DC converter, which is characterized by: It includes K high-voltage rapid voltage signal sampling circuits, M current signal sampling circuits, N slowly changing voltage signal sampling circuits, R temperature detection circuits, J high-side power device gate drive circuits, J low-side power device gate drive circuits, and a digital quantization and control processing module; The input ends of the K high-voltage surge voltage signal sampling circuits are respectively connected to the high-voltage surge signal generating nodes inside the front-stage AC / DC converter and the back-stage DC / DC converter in the on-board charger, specifically the power output nodes of the K half-bridge arms, and the node voltage is V X1 ~V XK , output K high voltage sudden change voltage detection signals V Xt1 ~V XtK ; The input ends of the M current signal sampling circuits are respectively connected to the large current signal output nodes inside the front-stage AC / DC converter and the back-stage DC / DC converter in the on-board charger, and the current I of the power output nodes of the K half-bridge arms is collected. L1 ~I LK And MK charger output current I L(K+1) ~I LM , output M large current detection signals I Lt1 ~I LtM ; The N slowly varying voltage signal sampling circuits sample the status of the AC input voltage Vin, the output DC charging voltage Vout, the DC bus voltage Vbus and other slowly varying voltage signals of the on-board charger in real time, and output N slowly varying voltage detection signals V t1 ~V tN ; The R temperature detection circuits detect the temperature of each physical space in the on-board charger respectively and output R temperature detection signals V Tt1 ~V TtR ; The K high-voltage surge voltage detection signals V Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM , N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtR All are connected to the digital quantization and control processing module for processing and obtain J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL ; Among them, J high-side gate control signals DS 1H ~DS JH They are connected to J high-side power device gate drive circuits and output J high-side power device gate drive signals S 1H ~S JH ; J low-side gate control signals DS 1L ~DS JL They are connected to J low-side power device gate drive circuits and output J low-side power device gate drive signals S 1L ~S JL ; Gate drive signal S 1H ~S JH and S 1L ~S JL The gates of the power switching devices in the K half-bridge arms are controlled respectively, thereby achieving modulation control of the states of the preceding AC / DC converter and the subsequent DC / DC converter; Wherein, K is a positive integer greater than 2, M is a positive integer greater than K, N is a positive integer greater than 3, R is any positive integer, and J is a positive integer greater than or equal to K.

2. The low electromagnetic radiation on-board charger control circuit according to claim 1 is characterized in that: The high-voltage surge voltage signal sampling circuit includes: the positive electrode of the input end of the optocoupler U1 is connected to the cathode of the diode D2 and is connected to the input end of the high-voltage surge voltage signal sampling circuit through the detection resistor Rt1, the negative electrode of the input end of the optocoupler U1 is connected to the anode of the diode D2 and is connected to the ground signal GNDH through the detection resistor Rt2; the positive electrode of the output end of the optocoupler U1 is connected to the inverting input end of the operational amplifier A1 through the differential capacitor C1, the output end of the operational amplifier A1 is connected to the inverting input end of the amplifier A1 through the differential resistor Rd1 and serves as the output end of the high-voltage surge voltage signal sampling circuit, the non-inverting input end of the operational amplifier A1 is connected to the upper end of the differential resistor Rd2, and the lower end of the differential resistor Rd2 and the negative electrode of the output end of the optocoupler U1 are connected to the ground signal GND; Among them, the optocoupler U1, the detection resistor Rt1, the detection resistor Rt2, and the diode D2 complete the high-voltage surge voltage isolation and voltage division detection functions, and the differential capacitor C1, the differential resistor Rd1, the differential resistor Rd2 and the operational amplifier A1 constitute the differential conduction circuit; the rapid change process of the voltage signal input at the power output node of the half-bridge arm will be converted into the corresponding differential derivative signal output, and the voltage amplitude of the differential derivative signal is proportional to the switching slope of the voltage signal of the half-bridge arm power output node and is proportional to the energy of the EMI interference source.

3. The low electromagnetic radiation on-board charger control circuit according to claim 1 is characterized in that: The digital quantization and control processing module comprises: an analog input selection circuit (1), a high-precision analog-to-digital converter (2), a FIFO register group (3), a first MUX selector (4), a reference data memory (5), a second MUX selector (6), a data error calculation circuit (7) and a comprehensive control processing circuit (8); The K high-voltage surge voltage detection signals V Xt1 ~V XtK , M large current detection signals I Lt1 ~I LtM , N slowly changing voltage detection signals V t1 ~V tN , R temperature detection signals V Tt1 ~V TtR All are input to the input end of the analog input selection circuit (1), and are output to the analog signal input port of the high-precision analog-to-digital converter (2) in sequence under the control of the analog selection control signal CK1. The selection switch input port of the analog input selection circuit (1) must be greater than K+M+N+R. Under the control of the control signal CK2, the high-precision analog-to-digital converter (2) converts each input analog voltage signal in sequence and outputs K+M+N+R digital codes Dx corresponding to each. The clock frequency of the control signal CK2 is equal to that of the analog selection control signal CK1. The K+M+N+R digital codes Dx will enter the FIFO register group (3) in a first-in-first-out manner, and obtain K high-voltage quantization codes DV after data serial-to-parallel conversion. Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR ; The above K high voltage quantization codes DV Xt1 ~DV XtK , M large current quantization codes DI Lt1 ~DI LtM , N slowly varying voltage quantization codes DV t1 ~DV tN , R temperature quantization codes DT t1 ~DT tR Connected to the data input terminal of the first MUX selector (4), and output to the sampling data input port of the data error calculation circuit (7) in sequence under the control of the data selection control signal CK3; The reference data memory (5) outputs the reference voltage data DRV X , refer to high current data DRI L , reference ramp voltage data DRV and reference temperature data DRT, connected to the data input terminal of the second MUX selector (6), and also output to the reference data input port of the data error calculation circuit (7) in sequence under the control of the data selection control signal CK3; The data error calculation circuit (7) calculates the difference between the data of the sampling data input port and the reference data input port, performs serial-to-parallel conversion and data synchronization on the difference data, and finally outputs K high-voltage voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT R All error codes are synchronously input to the integrated control processing circuit (8), and J high-side gate control signals DS are obtained after processing 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL .

4. The low electromagnetic radiation on-board charger control circuit according to claim 3 is characterized in that: The integrated control processing circuit (8) includes: an error reference data memory (81), a sudden voltage average value calculation circuit (82), a current average value calculation circuit (83), a slowly voltage average value calculation circuit (84), a temperature average value calculation circuit (85), a multi-modal signal fusion processing circuit (86), a clock frequency control circuit (87), a waveform duty cycle control circuit (88), a waveform type control circuit (89), and an output drive waveform synthesizer (90); The error reference data memory (81) is configured to generate a mode control code D provided by the multi-modal signal fusion processing circuit (86). mod Output surge voltage reference error data DRV Xe , High current reference error data DRI Le , slowly changing voltage reference error data DRV e and temperature reference error data DRT e , respectively connected to the reference error data input ports of the surge voltage average value calculation circuit (82), the current average value calculation circuit (83), the slow voltage average value calculation circuit (84) and the temperature average value calculation circuit (85); K high-voltage surge voltage error codes DeV X1 ~DeV XK , M large current error codes DeI L1 ~DeI LM , N slowly changing voltage error codes DeV1~DeV N , R temperature error codes DeT1~DeT R The error code data input terminals of the surge voltage mean value calculation circuit (82), the current mean value calculation circuit (83), the slow-changing voltage mean value calculation circuit (84) and the temperature mean value calculation circuit (85) are synchronously inputted respectively; the surge voltage mean value calculation circuit (82), the current mean value calculation circuit (83), the slow-changing voltage mean value calculation circuit (84) and the temperature mean value calculation circuit (85) respectively perform error mean value calculation according to the data of their respective reference error data input ports and the error code data input terminals, and respectively generate surge voltage mean value signal Des, current mean value signal Dei, slow-changing voltage mean value signal Dev and temperature mean value signal Det; the surge voltage mean value signal Des, the current mean value signal Dei, the slow-changing voltage mean value signal Dev and the temperature mean value signal Det Signal Det synchronously enters the multimodal signal fusion processing circuit (86) and is processed by comprehensive operation. The obtained mode control code Dmod is connected to the error reference data memory (81). The obtained clock frequency control code Dcfr, waveform duty cycle control code Dcpw, and waveform type control code Dctyp are respectively generated by the clock frequency control circuit (87), the waveform duty cycle control circuit (88), and the waveform type control circuit (89) to generate frequency control word freq, duty cycle control word pwd, and waveform type control word type, which are then connected to the output drive waveform synthesizer (90). Finally, the output drive waveform synthesizer (90) outputs J high-side gate control signals DS according to the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type. 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL .

5. The low electromagnetic radiation on-board charger control circuit according to claim 4 is characterized in that: The multimodal signal fusion processing circuit (86) realizes detection and control of EMI electromagnetic radiation of the on-board charger according to the EMI intensity calculation method; The EMI intensity calculation method first detects the high voltage sudden change voltage error code DeV at the same time. X1 ~DeV XK , large current error code DeI L1 ~DeI LM , multiply the K groups of high-voltage sudden voltage error codes and K groups of high-current error codes corresponding to the power output nodes of the K half-bridge arms at the same time in pairs and then sum them to obtain the total EMI radiation energy value; The total EMI radiation energy value is then compared with the reference radiation value under each working mode of the on-board charger system; If the total EMI radiation energy value exceeds the reference radiation value, the multimodal signal fusion processing circuit (86) will adjust the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp, thereby changing the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type; finally, by adjusting the J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL The pulse width, frequency and waveform mode are used to adjust the total EMI radiation energy value.

6. The low electromagnetic radiation on-board charger control circuit according to claim 4 is characterized in that: The multimodal signal fusion processing circuit (86) not only needs to control the basic vehicle charger operating mode, but also needs to control the startup process of the vehicle charger; The startup sequence of the on-board charger is as follows: First, turn off J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL After the on-board charger is supplied with AC power, the front-stage AC / DC converter performs a soft start process, and the DC bus voltage slowly increases. After the soft start is completed, the AC input current is close to 0. When the DC bus voltage is stable, the front-stage AC / DC converter enters normal closed-loop control, and the multimodal signal fusion processing circuit (86) controls all high-side and low-side gate drive signals in the front-stage AC / DC converter to turn on. The rear-stage DC / DC converter starts, and the multimodal signal fusion processing circuit (86) controls all high-side and low-side gate drive signals in the rear-stage DC / DC converter to turn on. When the output voltage or current of the on-board charger reaches a given value, the startup process ends, and the on-board charger starts to work normally and performs normal power transmission charging.

7. The low electromagnetic radiation on-board charger control circuit according to claim 6, characterized in that: After the on-board charger completes the normal startup process, it normally detects the key current and voltage signals in the front-stage AC / DC converter and the back-stage DC / DC converter, and digitally quantizes the detection signals. The quantization code and the reference data are calculated in the error calculation circuit (7) to obtain the state error, namely: the sudden change voltage mean signal Des, the current mean signal Dei, the slow change voltage mean signal Dev and the temperature mean signal Det; the multi-modal signal fusion processing circuit (86) reads the error mean calculation result and performs comprehensive calculation to determine whether the function and performance indicators of the on-board charger are normal; If the system status is abnormal, it will enter the interrupt protection measure; If the system is in normal state, the multimodal signal fusion processing circuit (86) will adjust the clock frequency control code Dcfr, the waveform duty cycle control code Dcpw, and the waveform type control code Dctyp according to the error mean calculation result, and then change the frequency control word freq, the duty cycle control word pwd, and the waveform type control word type, and finally adjust the J high-side gate control signals DS 1H ~DS JH and J low-side gate control signals DS 1L ~DS JL The pulse width, frequency and waveform mode are used to control the status mode of the on-board charger.

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