Multi-level inverter and dead zone modulation method thereof

Abstract

The invention discloses a multi-level inverter and a dead zone modulation method thereof. The multi-level inverter comprises a first bridge circuit, a second bridge circuit, at least one flying capacitor branch, a third bridge circuit and a follow current branch, the first end of the first bridge circuit is connected with the first input power supply end, and the second end of the first bridge circuit is connected with the neutral input power supply end; the first end of the second bridge circuit is connected with the second input power supply end, the second end of the second bridge circuit is connected with the neutral input power supply end, and the third end of the first bridge circuit and the third end of the second bridge circuit are connected with the third bridge circuit through a flying capacitor branch; the follow current branch is connected between the neutral input power supply end and the output end of the multi-level inverter, and the follow current branch is used for communicating the neutral input power supply end and the output end of the multi-level inverter when the output level of the multi-level inverter crosses zero. And the abnormal phenomenon of the output level of the multi-level inverter during zero-crossing switching is avoided.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of voltage conversion, and in particular to a multi-level inverter and a dead-zone modulation method thereof. Background Art

[0002] During the operation of the multi-level inverter, there is an abnormal output level phenomenon when zero-crossing switching occurs between two adjacent half-cycles. In the prior art, when improving the abnormal output level phenomenon during zero-crossing switching, it is easy to increase the loss of the multi-level inverter and reduce the efficiency of the multi-level inverter. Or it is necessary to accurately detect the moment of zero-crossing switching, and update the switching logic within this time range, and then return to the original switching logic, which requires high detection accuracy at the zero-crossing moment, and needs to adjust the switching strategy within a very short time, which increases the calculation speed and memory resource requirements of the multi-level inverter control system. Or it is necessary to add multiple groups of transition modes, which makes the modulation strategy of the multi-level inverter complex, increases the design complexity of the multi-level inverter control system, and affects the control accuracy of the control system. Summary of the invention

[0003] The present invention provides a multi-level inverter and a dead zone modulation method thereof, so as to improve the abnormal output level phenomenon when the multi-level inverter switches through zero, ensure the efficiency of the multi-level inverter, reduce the electromagnetic interference phenomenon of the multi-level inverter, and eliminate the need to detect the zero-crossing moment of the multi-level inverter, thereby improving the calculation speed and control accuracy of the multi-level inverter control system.

[0004] In a first aspect, an embodiment of the present invention provides a multi-level inverter, comprising a first bridge circuit, a second bridge circuit, at least one flying capacitor branch, a third bridge circuit and a freewheeling branch;

[0005] The first end of the first bridge circuit is connected to the first input power supply terminal, the second end of the first bridge circuit is connected to the neutral input power supply terminal, and the third end of the first bridge circuit is connected to the first end of the first flying capacitor branch; the first end of the second bridge circuit is connected to the second input power supply terminal, the second end of the second bridge circuit is connected to the neutral input power supply terminal, the third end of the second bridge circuit is connected to the second end of the first flying capacitor branch, and at least one flying capacitor branch is connected in series; the third end of the last flying capacitor branch is connected to the first end of the third bridge circuit, the fourth end of the last flying capacitor branch is connected to the second end of the third bridge circuit, and the third end of the third bridge circuit serves as the output end of the multi-level inverter; the freewheeling branch is connected between the neutral input power supply terminal and the output end of the multi-level inverter, and the freewheeling branch is used to connect the neutral input power supply terminal and the output end of the multi-level inverter when the output level of the multi-level inverter passes through zero.

[0006] Optionally, the freewheeling branch includes a first unidirectional conduction unit and a second unidirectional conduction unit; the first unidirectional conduction unit and the second unidirectional conduction unit are connected between the neutral input power supply terminal and the output terminal of the multi-level inverter, and the first unidirectional conduction unit and the second unidirectional conduction unit are used to provide a freewheeling circuit when the output level passes through zero.

[0007] Optionally, the first unidirectional conducting unit includes a first unidirectional conducting transistor, and the second unidirectional conducting unit includes a second unidirectional conducting transistor;

[0008] The emitter of the first unidirectional conducting transistor and the collector of the second unidirectional conducting transistor are connected to the neutral input power supply terminal, and the emitter of the second unidirectional conducting transistor and the collector of the first unidirectional conducting transistor are connected to the output terminal of the multilevel inverter.

[0009] Optionally, the first unidirectional conducting unit includes a first unidirectional conducting transistor and a first diode, and the second unidirectional conducting unit includes a second unidirectional conducting transistor and a second diode;

[0010] The collector of the first unidirectional conducting transistor and the cathode of the first diode are connected to the neutral input power supply terminal, the emitter of the first unidirectional conducting transistor is connected to the anode of the first diode, and is connected to the emitter of the second unidirectional conducting transistor and the anode of the second diode, the collector of the second unidirectional conducting transistor is connected to the cathode of the second diode, and is connected to the output terminal of the multilevel inverter.

[0011] Optionally, the first unidirectional conducting unit includes a first bidirectional conducting transistor and a third diode, and the second unidirectional conducting unit includes a second bidirectional conducting transistor and a fourth diode;

[0012] The first electrode of the first bidirectional pass transistor and the anode of the third diode are connected to the neutral input power supply terminal, the second electrode of the first bidirectional pass transistor and the cathode of the third diode are connected to the second electrode of the second bidirectional pass transistor and the cathode of the fourth diode, and the first electrode of the second bidirectional pass transistor and the anode of the fourth diode are connected to the output terminal of the multilevel inverter.

[0013] Optionally, the first bridge circuit includes a first transistor, a second transistor, a fifth diode and a sixth diode, and the second bridge circuit includes a third transistor, a fourth transistor, a seventh diode and an eighth diode;

[0014] The first electrode of the first transistor is connected to the cathode of the fifth diode and serves as the first end of the first bridge circuit; the second electrode of the first transistor and the anode of the fifth diode are connected to the first electrode of the second transistor and the cathode of the sixth diode and serve as the third end of the first bridge circuit; the second electrode of the second transistor is connected to the anode of the sixth diode and serves as the second end of the first bridge circuit;

[0015] The first electrode of the third transistor is connected to the cathode of the seventh diode and serves as the second end of the second bridge circuit. The second electrode of the third transistor and the anode of the seventh diode are connected to the first electrode of the fourth transistor and the cathode of the eighth diode and serve as the third end of the second bridge circuit. The second electrode of the fourth transistor is connected to the anode of the eighth diode and serves as the first end of the second bridge circuit.

[0016] Optionally, the flying capacitor branch includes a fifth transistor, a sixth transistor, a ninth diode, a tenth diode and a flying capacitor, and the third bridge circuit includes a seventh transistor, an eighth transistor, an eleventh diode and a twelfth diode;

[0017] The first electrode of the fifth transistor is connected to the cathode of the ninth diode and serves as the first end of the flying capacitor branch; the second electrode of the fifth transistor and the anode of the ninth diode are connected to the first electrode of the flying capacitor and serve as the third end of the flying capacitor branch; the second electrode of the flying capacitor is connected to the first electrode of the sixth transistor and the cathode of the tenth diode and serves as the fourth end of the flying capacitor branch; the second electrode of the sixth transistor is connected to the anode of the tenth diode and serves as the second end of the flying capacitor branch;

[0018] The first electrode of the seventh transistor is connected to the cathode of the eleventh diode and serves as the first end of the third bridge circuit. The second electrode of the seventh transistor and the anode of the eleventh diode are connected to the first electrode of the eighth transistor and the cathode of the twelfth diode and serve as the third end of the third bridge circuit. The second electrode of the eighth transistor is connected to the anode of the twelfth diode and serves as the second end of the third bridge circuit.

[0019] In a second aspect, an embodiment of the present invention further provides a dead zone modulation method of a multi-level inverter, which is used to modulate the multi-level inverter described in the first aspect, comprising:

[0020] In the first step, the freewheeling branch is controlled to open the freewheeling loop according to the freewheeling control signal;

[0021] In the second step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and the third bridge circuit are respectively controlled to at least partially shut down the current loop of the current mode;

[0022] In the third step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, at least a portion of the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and the third bridge circuit are controlled to open the current loop of the next mode respectively;

[0023] In the fourth step, the freewheeling branch is controlled to shut down the freewheeling loop according to the freewheeling control signal.

[0024] Optionally, the first bridge control signal includes a first drive signal and a second drive signal, and the second bridge control signal includes a third drive signal and a fourth drive signal; the method further includes:

[0025] Delaying the falling edge of the first pulse width modulation signal by a first preset time to form a first driving signal;

[0026] Delaying the falling edge of the second pulse width modulation signal by the first preset time, and delaying the rising edge by the second preset time, to form a second driving signal;

[0027] Delaying the falling edge of the third pulse width modulation signal by the first preset time, and delaying the rising edge by the second preset time, to form a third driving signal;

[0028] Delaying the falling edge of the fourth pulse width modulation signal by the first preset time to form a fourth driving signal; the first pulse width modulation signal has the same timing as the third pulse width modulation signal, the first pulse width modulation signal has an opposite timing to the second pulse width modulation signal, and the third pulse width modulation signal has an opposite timing to the fourth pulse width modulation signal;

[0029] The first drive signal, the second drive signal, the third drive signal and the fourth drive signal are subjected to a logic operation to form the freewheeling control signal.

[0030] Optionally, performing a logic operation on the first drive signal, the second drive signal, the third drive signal and the fourth drive signal to form the freewheeling control signal includes:

[0031] Perform a non-logical operation on the first driving signal and a logical operation on the second driving signal to form a first control signal;

[0032] Perform a non-logical operation and an AND logic operation on the third driving signal and the fourth driving signal to form a second control signal;

[0033] Performing an OR logic operation on the first control signal and the second control signal, and delaying the rising edge of the signal after the OR logic operation by the second preset time to form the freewheeling control signal.

[0034] The technical solution of the embodiment of the present invention is connected between the neutral input power supply terminal and the output terminal of the multilevel inverter by setting a freewheeling branch. When the output level of the multilevel inverter passes through zero, the freewheeling branch can connect the neutral input power supply terminal and the output terminal of the multilevel inverter, so that the current can pass through two parallel branches at the same time, so that the potential of the output terminal of the multilevel inverter is maintained at 0V by transmitting the 0V provided by the neutral input power supply terminal through the freewheeling branch, avoiding the abnormal phenomenon of the output level of the multilevel inverter during zero-crossing switching, and reducing the electromagnetic interference phenomenon of the multilevel inverter. In other modes of the multilevel inverter, the freewheeling branch can be controlled to be in a disconnected state, thereby avoiding the conduction loss of the freewheeling branch in other modes, reducing the loss of the multilevel inverter, and improving the efficiency of the multilevel inverter. Moreover, there is no need to detect the zero-crossing moment of the multilevel inverter, and there is no need to add a complex modulation strategy, so that the accuracy requirements of the multilevel inverter control system can be reduced, which is conducive to improving the control accuracy and reducing the cost of the multilevel inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A structural schematic diagram of a five-level inverter provided for related technology;

[0036] Figure 2 A waveform simulation diagram of the output level of a five-level inverter provided in the related art;

[0037] Figure 3 A schematic diagram of the structure of a multi-level inverter provided by an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of waveform simulation of output levels of a multi-level inverter provided by an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention; Figure 8 A schematic diagram of the structure of another multi-level inverter provided by an embodiment of the present invention;

[0042] Fig. 9 A timing diagram of a control signal for switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention;

[0043] Fig.10 A current schematic diagram of a multi-level inverter in OP state provided by an embodiment of the present invention;

[0044] Fig.11 A current schematic diagram of the first step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention;

[0045] Fig.12 A current schematic diagram of the second step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention;

[0046] Fig.13 A current schematic diagram of the third step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention;

[0047] Fig.14 A current schematic diagram of the fourth step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention;

[0048] Fig.15 A schematic diagram of a voltage waveform simulation between a collector and an emitter of a first unidirectional conducting transistor provided in an embodiment of the present invention;

[0049] Fig.16 for Figure 8 A schematic diagram of voltage waveform simulation under a non-unity power factor corresponding to a multi-level inverter provided;

[0050] Fig.17 A timing diagram of a control signal for switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention;

[0051] Fig.18 A current diagram of a multi-level inverter in the ON state provided by an embodiment of the present invention. Fig.18 As shown;

[0052] Fig.19 A current schematic diagram of the first step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention;

[0053] Fig. 20 A current schematic diagram of the second step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention;

[0054] Fig.21 A current schematic diagram of the third step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention;

[0055] Fig. 22 A current schematic diagram of the fourth step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention;

[0056] Fig.23 A schematic flow chart of a dead zone modulation method for a multi-level inverter provided by an embodiment of the present invention;

[0057] Fig.24 A logic diagram of forming a dead zone modulation signal provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0059] Figure 1 A structural diagram of a five-level inverter provided in the related art. Figure 1As shown, the five-level inverter includes a first half-bridge composed of a first insulated gate bipolar transistor S1 and a second insulated gate bipolar transistor S2, a second half-bridge composed of a third insulated gate bipolar transistor S3 and a fourth insulated gate bipolar transistor S4, a flying capacitor branch composed of a fifth insulated gate bipolar transistor S5, a sixth insulated gate bipolar transistor S6 and a flying capacitor C1, and a third half-bridge composed of a seventh insulated gate bipolar transistor S7 and an eighth insulated gate bipolar transistor S8. Table 1 is a modal schematic table of a five-level inverter provided by the related art. Among them, the 1 state is used to represent that the transistor is turned on, and the 0 state is used to represent that the transistor is turned off. The N state is used to represent that the output level of the five-level inverter is -U dc / 2, N1 state and N2 state are used to characterize the output level of the five-level inverter as -U dc / 4, the ON state and OP state are used to indicate that the output level of the five-level inverter is 0, and the P1 state and P2 state are used to indicate that the output level of the five-level inverter is U dc / 4, the P state is used to indicate that the output level of the five-level inverter is U dc / 2,U dc is the voltage between the first input power supply terminal and the second input power supply terminal. It can be seen from the above process that the zero-crossing switching of the five-level inverter includes two mode switchings, one of which is switching from the ON state to the OP state. The other is switching from the OP state to the ON state. During the dead time of the switching, all transistors are turned off. When the current is flowing out, the current automatically flows through the reverse parallel diodes of the fourth insulated gate bipolar transistor S4, the seventh insulated gate bipolar transistor S7 and the eighth insulated gate bipolar transistor S8, so that the output end of the five-level inverter generates -U dc When the current is flowing in, the current automatically flows in the reverse parallel diodes of the first insulated gate bipolar transistor S1, the fifth insulated gate bipolar transistor S5 and the sixth insulated gate bipolar transistor S6, so that the output end of the five-level inverter generates U dc / 2 abnormal level jump. For example, Figure 2 A waveform simulation diagram of the output level of a five-level inverter provided in the related art. The horizontal axis is time and the vertical axis is voltage. Figure 2 As shown in the figure, at the two zero-crossing switching moments in one power frequency cycle, the output level of the five-level inverter jumps from 0V to -U dc / 2 and U dc / 2, causing abnormal level jump in the five-level inverter.

[0060] Table 1

[0061]

[0062] In view of the above technical problems, an embodiment of the present invention provides a multi-level inverter. Figure 3 A schematic diagram of the structure of a multi-level inverter provided by an embodiment of the present invention. Figure 3 As shown, the multi-level inverter includes a first bridge circuit 110, a second bridge circuit 120, at least one flying capacitor branch 130, a third bridge circuit 140 and a freewheeling branch 150; a first end of the first bridge circuit 110 is connected to a first input power terminal V+, a second end of the first bridge circuit 110 is connected to a neutral input power terminal V0, and a third end of the first bridge circuit 110 is connected to a first end of the first flying capacitor branch 130; a first end of the second bridge circuit 120 is connected to a second input power terminal V-, a second end of the second bridge circuit 120 is connected to a neutral input power terminal V0, and a third end of the second bridge circuit 120 is connected to a first flying capacitor branch 130. The second end of the flying capacitor branch 130 is connected, and at least one flying capacitor branch 130 is connected in series; the third end of the last flying capacitor branch 130 is connected to the first end of the third bridge circuit 140, and the fourth end of the last flying capacitor branch 130 is connected to the second end of the third bridge circuit 140, and the third end of the third bridge circuit 140 serves as the output end VOUT of the multi-level inverter; the freewheeling branch 150 is connected between the neutral input power supply end V0 and the output end VOUT of the multi-level inverter, and the freewheeling branch 150 is used to connect the neutral input power supply end V0 and the output end VOUT of the multi-level inverter when the output level of the multi-level inverter passes through zero.

[0063] Specifically, the first bridge circuit 110 and the second bridge circuit 120 can be half-bridge circuits, both of which include controllable transistors with low frequency and high withstand voltage. The flying capacitor branch 130 and the third bridge circuit 140 both include controllable transistors with high frequency and low withstand voltage. At the same time, the flying capacitor branch 130 also includes a flying capacitor. During the normal operation of the multi-level inverter, the output terminal VOUT of the multi-level inverter can be controlled by controlling the connection path between the output terminal VOUT of the multi-level inverter and the first input power terminal V+, the neutral input power terminal V0 and the second input power terminal V-, so as to control the output terminal VOUT of the multi-level inverter to output multi-level alternating current, and realize zero-crossing switching at the half cycle. Exemplarily, the multi-level inverter is switched from a positive level to a negative level current output as an example for explanation. Before the zero-crossing switching, the first bridge circuit 110 connects the first end and the third end, the second bridge circuit 120 connects the second end and the third end, the flying capacitor branch 130 connects the second end and the fourth end, and the third bridge circuit 140 connects the second end and the third end, so that the 0V provided by the neutral input power supply terminal V0 is output to the output terminal VOUT of the multi-level inverter through the second bridge circuit 120, the flying capacitor branch 130 and the third bridge circuit 140, so that the multi-level inverter outputs 0V. After the zero-crossing switching, the first bridge circuit 110 connects the second end and the third end, the second bridge circuit 120 connects the first end and the third end, the flying capacitor branch 130 connects the first end and the third end, and the third bridge circuit 140 connects the first end and the third end, so that the 0V provided by the neutral input power supply terminal V0 is output to the output terminal VOUT of the multi-level inverter through the first bridge circuit 110, the flying capacitor branch 130 and the third bridge circuit 140, so that the multi-level inverter outputs 0V. During the dead time of the zero-crossing switching process, the freewheeling branch 150 can be controlled to connect the neutral input power supply terminal V0 and the output terminal VOUT of the multi-level inverter. At this time, the freewheeling branch 150 is equivalent to being connected in parallel with the current branch formed by the second bridge circuit 120, the flying capacitor branch 130 and the third bridge circuit 140, so that the current can pass through the two parallel branches at the same time, so that the potential of the output terminal VOUT of the multi-level inverter is maintained at 0V by transmitting the 0V provided by the neutral input power supply terminal V0 through the freewheeling branch 150, avoiding the abnormal phenomenon of the output level of the multi-level inverter during zero-crossing switching, and reducing the electromagnetic interference phenomenon of the multi-level inverter. At the same time, the first bridge circuit 110, the second bridge circuit 120, the flying capacitor branch 130 and the third bridge circuit 140 are controlled to complete the zero-crossing switching. In other modes of the multilevel inverter, the freewheeling branch 150 can be controlled to be in a disconnected state, thereby avoiding the conduction loss of the freewheeling branch 150 in other modes, reducing the loss of the multilevel inverter, and improving the efficiency of the multilevel inverter. In addition, there is no need to detect the zero-crossing moment of the multilevel inverter, and there is no need to add a complex modulation strategy, thereby reducing the accuracy requirements of the multilevel inverter control system, which is conducive to improving the control accuracy and reducing the cost of the multilevel inverter.

[0064] For example, Figure 4 FIG. 1 is a waveform simulation diagram of the output level of a multi-level inverter provided by an embodiment of the present invention. The horizontal axis is time and the vertical axis is voltage. Figure 4 As shown, at two zero-crossing switching moments within one power frequency cycle, the output level of the multi-level inverter has no abnormal level jump phenomenon, thereby reducing the electromagnetic interference phenomenon of the multi-level inverter.

[0065] The technical solution of this embodiment is to connect the neutral input power supply terminal and the output terminal of the multilevel inverter by setting the freewheeling branch. When the output level of the multilevel inverter passes through zero, the freewheeling branch can connect the neutral input power supply terminal and the output terminal of the multilevel inverter, so that the current can pass through two parallel branches at the same time, so that the potential of the output terminal of the multilevel inverter is maintained at 0V by transmitting the 0V provided by the neutral input power supply terminal through the freewheeling branch, avoiding the abnormal phenomenon of the output level of the multilevel inverter during zero-crossing switching, and reducing the electromagnetic interference phenomenon of the multilevel inverter. In other modes of the multilevel inverter, the freewheeling branch can be controlled to be in a disconnected state, so that the conduction loss of the freewheeling branch in other modes can be avoided, the loss of the multilevel inverter is reduced, and the efficiency of the multilevel inverter is improved. Moreover, there is no need to detect the zero-crossing moment of the multilevel inverter, and there is no need to add a complex modulation strategy, so that the accuracy requirements of the multilevel inverter control system can be reduced, which is conducive to improving the control accuracy and reducing the cost of the multilevel inverter.

[0066] Figure 5 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 5 As shown, the freewheeling branch 150 includes a first unidirectional conduction unit 151 and a second unidirectional conduction unit 152; the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 are connected between the neutral input power supply terminal V0 and the output terminal VOUT of the multi-level inverter, and the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 are used to provide a freewheeling loop when the output level passes through zero.

[0067] Specifically, Figure 5exemplarily shows that the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 are connected in parallel between the neutral input power supply terminal V0 and the output terminal VOUT of the multilevel inverter. When the first unidirectional conduction unit 151 is turned on, the conduction direction can be from the neutral input power supply terminal V0 to the output terminal VOUT of the multilevel inverter, and when the second unidirectional conduction unit 151 is turned on, the conduction direction can be from the output terminal VOUT of the multilevel inverter to the neutral input power supply terminal V0. During the dead time of zero-crossing switching, when the current direction is the outflow direction from the neutral input power supply terminal V0 to the output terminal VOUT of the multilevel inverter, the first unidirectional conduction unit 151 can be controlled to be turned on, so that the freewheeling branch 150 can provide a current branch. When the current direction is the inflow direction from the output terminal VOUT of the multi-level inverter to the neutral input power terminal V0, the second unidirectional conduction unit 152 can be controlled to be turned on, and the freewheeling branch 150 can also provide a current branch, so that the level of the output terminal VOUT of the multi-level inverter can be maintained at 0V through the current branch provided by the freewheeling branch 150, avoiding the abnormal phenomenon of the output level of the multi-level inverter during zero-crossing switching. In other modes of the multi-level, the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 can be controlled to be turned off, and the conduction loss of the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 can be avoided, reducing the loss of the multi-level inverter and improving the efficiency of the multi-level inverter. Moreover, it can be used under both unity power factor and non-unity power factor, which increases the scope of use of the multi-level inverter. For example, in this embodiment, the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 can be controlled to be turned on or off at the same time by the same freewheeling control signal, which can not only provide a freewheeling loop for the multi-level inverter, but also reduce the number of control signals and reduce the control complexity, which is beneficial to improving the control accuracy and reducing the cost of the multi-level inverter.

[0068] Continue to refer Figure 5 The first unidirectional conduction unit 151 includes a first unidirectional conduction transistor S fx1 The second unidirectional conduction unit 150 includes a second unidirectional conduction transistor S fx2 ; The first unidirectional conduction transistor S fx1 The emitter of the second unidirectional conducting transistor S fx2 The collector of is connected to the neutral input power supply terminal V0, and the second unidirectional conduction transistor S fx2 The emitter of the first unidirectional conducting transistor S fx1 The collector of is connected to the output terminal VOUT of the multi-level inverter.

[0069] Specifically, Figure 5 The first unidirectional conducting transistor S is shown as an example. fx1 and the second unidirectional conducting transistor Sfx2 The first unidirectional conducting transistor S fx1 and the second unidirectional conducting transistor S fx2 It has unidirectional conductivity, and its conduction direction is that the collector of the IGBT points to the emitter. fx1 When the second unidirectional conducting transistor S fx2 When turned on, it can provide a current loop with a current direction from the neutral input power supply terminal V0 to the output terminal VOUT of the multi-level inverter. Thus, when the current direction is the outflow direction, the second unidirectional conduction transistor S fx2 The first unidirectional conduction transistor S is turned on to provide a current loop for the output current and control the level of the output terminal VOUT of the multi-level inverter to be 0V. When the current direction is the inflow direction, the first unidirectional conduction transistor S is controlled fx1 The first unidirectional conduction transistor S can also be controlled to conduct to provide a current loop for the inflow current, and the level of the output terminal VOUT of the multi-level inverter is controlled to be 0V. fx1 and the second unidirectional conducting transistor S fx2 At the same time, when the current direction is outflow, the current passes through the second unidirectional conduction transistor S fx2 When the current direction is the inflow direction, the current flows through the first unidirectional conduction transistor S fx1 Flows into the neutral input power supply terminal V0.

[0070] Figure 6 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 6 As shown, the first unidirectional conduction unit 151 includes a first unidirectional conduction transistor S fx1 and a first diode D1, the second unidirectional conduction unit 152 includes a second unidirectional conduction transistor S fx2 and a second diode D2; a first unidirectional conducting transistor S fx1 The collector of the first diode D1 and the cathode of the first diode D1 are connected to the neutral input power supply terminal V0, and the first unidirectional conduction transistor S fx1 The emitter of the first diode D1 is connected to the anode of the first diode D1 and to the second unidirectional conducting transistor S fx2 The emitter of the second diode D2 is connected to the anode of the second unidirectional conduction transistor S fx2 The collector of is connected to the cathode of the second diode D2 and to the output terminal VOUT of the multi-level inverter.

[0071] Specifically, Figure 6 exemplarily shows that the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 are connected in series between the neutral input power supply terminal V0 and the output terminal VOUT of the multi-level inverter. fx1 and the second unidirectional conducting transistor S fx2 is an insulated gate bipolar transistor (IGBT). fx1 When the second unidirectional conducting transistor S fx2 When it is turned on, it can provide a current loop with a current direction from the neutral input power supply terminal V0 to the output terminal VOUT of the multi-level inverter. When the current direction is the outflow direction, the first unidirectional conduction transistor S can be controlled fx1 The second unidirectional conducting transistor S fx2 At this time, the first unidirectional conducting transistor S fx1 The second diode D2 provides a current loop for the output current, and controls the level of the output terminal VOUT of the multi-level inverter to be 0V. When the current direction is the inflow direction, the first unidirectional conduction transistor S fx1 The second unidirectional conducting transistor S fx2 At this time, the second unidirectional conducting transistor S fx2 The first diode D1 and the first unidirectional conduction transistor S1 can provide a current loop for the input current, and control the level of the output terminal VOUT of the multi-level inverter to be 0V. In some embodiments, the first unidirectional conduction transistor S2 can also be controlled to be 0V during the dead time of the zero-crossing switching. fx1 and the second unidirectional conducting transistor S fx2 Conducting at the same time can also provide a current loop for the input current and the output current, and at the same time can reduce the number of control signals, reduce the control complexity, and help improve the control accuracy and reduce the cost of the multi-level inverter.

[0072] Figure 7 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 7 As shown, the first unidirectional conduction unit 151 includes a first bidirectional conduction transistor S fx3 and a third diode D3, the second unidirectional conduction unit 152 includes a second bidirectional conduction transistor S fx4 and a fourth diode D4; a first bidirectional conducting transistor S fx3 The first electrode of the third diode D3 and the anode of the third diode D3 are connected to the neutral input power supply terminal V0, and the first bidirectional conduction transistor S fx3 The second electrode of the third diode D3 and the cathode of the second bidirectional conducting transistor Sfx4 The second electrode of the second bidirectional conducting transistor S is connected to the cathode of the fourth diode D4. fx4 The first electrode of the fourth diode D4 and the anode of the fourth diode D4 are connected to the output terminal VOUT of the multi-level inverter.

[0073] Specifically, Figure 7 exemplarily shows that the first unidirectional conduction unit 151 and the second unidirectional conduction unit 152 are connected in series between the neutral input power supply terminal V0 and the output terminal VOUT of the multi-level inverter. fx3 and the second bidirectional conducting transistor S fx4 It can be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). When the current direction is outflow, the first bidirectional conducting transistor S can be controlled fx3 The second bidirectional conducting transistor S fx4 At this time, the third diode D3 and the second bidirectional conducting transistor S fx4 A current loop for outputting the current is provided to control the level of the output terminal VOUT of the multi-level inverter to be 0V. When the current direction is the inflow direction, the first bidirectional conducting transistor S fx3 The second bidirectional conducting transistor S fx4 At this time, the fourth diode D4 and the first bidirectional conducting transistor S fx3 A current loop for input current is provided to control the level of the output terminal VOUT of the multi-level inverter to be 0V.

[0074] Figure 8 FIG. 1 is a schematic diagram of another structure of a multi-level inverter provided by an embodiment of the present invention. Figure 8 As shown, the first bridge circuit 110 includes a first transistor S x1 , the second transistor S x2 , a fifth diode D5 and a sixth diode D6, the second bridge circuit 120 includes a third transistor S x3 , the fourth transistor S x4 , a seventh diode D7 and an eighth diode D8; a first transistor S x1 The first electrode of the first transistor S is connected to the cathode of the fifth diode D5 and serves as the first end of the first bridge circuit 110. x1 The second electrode and the anode of the fifth diode D5 are connected to the second transistor S x2 The first electrode of the second transistor S is connected to the cathode of the sixth diode D6 and serves as the third end of the first bridge circuit 110. x2The second electrode of the third transistor S is connected to the anode of the sixth diode D6 and serves as the second end of the first bridge circuit 110; x3 The first electrode of the third transistor S is connected to the cathode of the seventh diode D7 and serves as the second end of the second bridge circuit 120. x3 The second electrode and the anode of the seventh diode D7 are connected to the fourth transistor S x4 The first electrode of the fourth transistor S is connected to the cathode of the eighth diode D8 and serves as the third end of the second bridge circuit 120. x4 The second electrode of is connected to the anode of the eighth diode D8 and serves as the first end of the second bridge circuit 120.

[0075] Specifically, Figure 8 The first transistor S is shown as an example. x1 To the fourth transistor S x4 The first transistor S is an IGBT, and each transistor is connected in reverse parallel with a diode. In the first half cycle of the multi-level inverter, the first transistor S x1 and the third transistor S x3 The second transistor S can be turned on to make the output level of the multi-level inverter greater than 0. In the second half cycle of the multi-level inverter, the second transistor S x2 and the fourth transistor S x4 When the MOSFET is turned on, the output level of the multi-level inverter can be made less than 0, thereby realizing the inversion of DC power.

[0076] Continue to refer Figure 8 The flying capacitor branch 130 includes a fifth transistor S x5 , the sixth transistor S x6 , the ninth diode D9, the tenth diode D10 and the flying capacitor C fx The third bridge circuit 140 includes a seventh transistor S x7 , the eighth transistor S x8 , an eleventh diode D11 and a twelfth diode D12; a fifth transistor S x5 The first electrode of the fifth transistor S is connected to the cathode of the ninth diode D9 and serves as the first end of the flying capacitor branch 130. x5 The second electrode and the anode of the ninth diode D9 and the flying capacitor C fx The first electrode of the flying capacitor C is connected to the third end of the flying capacitor branch 130. fx The second electrode and the sixth transistor S x6 The first electrode of the sixth transistor S is connected to the cathode of the tenth diode D10 and serves as the fourth end of the flying capacitor branch 130. x6 The second electrode of the seventh transistor S is connected to the anode of the tenth diode D10 and serves as the second end of the flying capacitor branch 130; x7The first electrode of the seventh transistor S is connected to the cathode of the eleventh diode D11 and serves as the first end of the third bridge circuit 140. x7 The second electrode and the anode of the eleventh diode D11 are connected to the eighth transistor S x8 The first electrode of the eighth transistor S is connected to the cathode of the twelfth diode D12 and serves as the third end of the third bridge circuit 140. x8 The second electrode of is connected to the anode of the twelfth diode D12 and serves as the second end of the third bridge circuit 140.

[0077] Specifically, during the operation of the multilevel inverter, when the flying capacitor C fx The transistors on one side are all in the on state, and the current can be directly output to the output terminal VOUT of the multi-level inverter through the transistor on the flying capacitor side. The output level is the voltage provided by the input power supply terminal. fx When the transistor on one side is partially turned on, at least one flying capacitor C fx The current flows through the flying capacitor C fx The voltage provided by the input power supply terminal is divided to reduce the absolute value of the output level and realize multi-level inversion. Figure 8 FIG. 1 shows an exemplary multilevel inverter including a flying capacitor branch 130. When the fifth transistor S x5 and the seventh transistor S x7 When the output level can be U dc / 2 or 0V, when the sixth transistor S x6 and the eighth transistor S x8 When turned on, the output level can be -U dc / 2 or 0V. When the fifth transistor S x5 and the eighth transistor S x8 When the output level can be ±U dc / 4, when the sixth transistor S x6 and the seventh transistor S x7 When conducting, the output level can be ±U dc / 4.

[0078] Continue to refer Figure 8 The multilevel inverter further includes a first bus capacitor C1 and a second bus capacitor C2. The first bus capacitor C1 is connected between the first input power terminal V+ and the neutral input power terminal V0, and the second bus capacitor C2 is connected between the second input power terminal V- and the neutral input power terminal V0. By setting the first bus capacitor C1 and the second bus capacitor C2, the potential of the neutral input power terminal V0 can be stabilized to 0V, which is used to provide a 0V voltage for the output terminal VOUT of the multilevel inverter.

[0079] Table 2 is a schematic diagram of zero-crossing switching modes of a multi-level inverter provided by an embodiment of the present invention. Fig. 9 A timing diagram of a control signal for switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention. a1 is the timing of the first pulse width modulation signal, G a2 is the timing of the second pulse width modulation signal, G a3 is the timing of the third pulse width modulation signal, G a4 is the timing of the fourth pulse width modulation signal, G x1 The first transistor S x1 The timing of the driving signal, G x2 The second transistor S x2 The timing of the driving signal, G x3 The third transistor S x3 The timing of the driving signal, G x4 The fourth transistor S x4 The timing of the driving signal, G fx1 is a first unidirectional conducting transistor S fx1 The timing of the driving signal, G fx2 is the second unidirectional conducting transistor S fx2 At the same time, the driving signal G x5 ( Fig. 9 ) is used to drive the fifth transistor S x5 , driving signal G x6 ( Fig. 9 ) is used to drive the sixth transistor S x6 , driving signal G x7 ( Fig. 9 ) is used to drive the seventh transistor S x7 , driving signal G x8 ( Fig. 9 ) is used to drive the eighth transistor S x8 The following is based on Figure 8 and Fig. 9 The specific process of switching from the OP state to the ON state when the current of the multilevel inverter is flowing out is described.

[0080] Fig.10 A current diagram of a multi-level inverter in OP state provided by an embodiment of the present invention. Fig.10 As shown, in the OP state before zero-crossing switching, G x1 , G x3 , G x6 and G x8 is high level, G x2 , G x4 , G x5 , Gx7 , G fx1 and G fx2 The first transistor S x1 , the third transistor S x3 , the sixth transistor S x6 and the eighth transistor S x8 The current flows from the neutral input power supply terminal V0 through the third transistor S x3 , the sixth transistor S x6 The tenth diode D10 and the eighth transistor S are connected in reverse parallel. x8 The twelfth diode D12 connected in reverse parallel flows out to the output terminal VOUT of the multi-level inverter, and the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0081] Fig.11 A current diagram of the first step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention. Fig.11 As shown, the first step of switching from OP state to ON state, G x3 , G x6 , G x8 , G fx1 and G fx2 is high level, G x1 , G x2 , G x4 , G x5 and G x7 is low level. Turn off the first transistor S x1 , turn on the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 At this time, the current flows out to the output terminal VOUT of the multi-level inverter through two current branches, one of which is still from the neutral input power supply terminal V0 through the third transistor S x3 , the sixth transistor S x6 The tenth diode D10 and the eighth transistor S are connected in reverse parallel. x8 The twelfth diode D12 connected in reverse parallel flows out to the output terminal VOUT of the multi-level inverter, and another current branch flows from the neutral input power supply terminal V0 through the second unidirectional conduction transistor S fx2 The output voltage flows out to the output terminal VOUT of the level inverter, and the output level of the output terminal VOUT of the multi-level inverter is 0V. fx1 and the second unidirectional conducting transistor S fx2 When turned on, the first unidirectional conducting transistor S fx1 and the second unidirectional conducting transistor S fx2 The voltage between the collector and emitter of is kept at 0V, so that the first unidirectional conduction transistor S fx1and the second unidirectional conducting transistor S fx2 The soft switch conduction improves the efficiency of the multi-level inverter.

[0082] Fig.12 A current diagram of the second step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention. Fig.12 As shown, in the second step of switching from OP state to ON state, G fx1 and G fx2 is high level, G x1 , G x2 , G x3 , G x4 , G x5 , G x6 , G x7 and G x8 is low level. Turn off the third transistor S x3 , the sixth transistor S x6 and the eighth transistor S x8 , the current branch from the third transistor S x3 , the sixth transistor S x6 The tenth diode D10 and the eighth transistor S are connected in reverse parallel. x8 The twelfth diode D12 connected in reverse parallel is switched to the second unidirectional conducting transistor S fx2 , the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0083] Fig.13 A current diagram of the third step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention. Fig.13 As shown, the third step of switching from OP state to ON state, G x2 , G x4 , G x5 , G x7 , G fx1 and G fx2 is high level, G x1 , G x3 , G x6 and G x8 is low level. Turn on the second transistor S x2 , the fourth transistor S x4 , the fifth transistor S x5 and the seventh transistor S x7 At this time, the current flows out to the output terminal VOUT of the multi-level inverter through two current branches, one of which is still from the neutral input power supply terminal V0 through the second unidirectional conduction transistor S fx2 The current flows out to the output terminal VOUT of the level inverter, and the other current branch flows from the neutral input power supply terminal V0 through the second transistor S x2The second diode D2 and the fifth transistor S are connected in reverse parallel. x5 and the seventh transistor S x7 Flows out to the output terminal VOUT of the multilevel inverter, and the output level of the output terminal VOUT of the multilevel inverter is 0V.

[0084] Fig.14 A current diagram of the fourth step of switching a multi-level inverter from an OP state to an ON state provided by an embodiment of the present invention. Fig.14 As shown, the fourth step of switching from OP state to ON state, G x2 , G x4 , G x5 and G x7 is high level, G x1 , G x3 , G x6 , G x8 , G fx1 and G fx2 The first unidirectional conducting transistor S is turned off. fx1 and the second unidirectional conducting transistor S fx2 , at this time, it is the ON state after zero-crossing switching, and the current branch flows from the second unidirectional conduction transistor S fx2 The second transistor S is switched naturally x2 The second diode D2 and the fifth transistor S are connected in reverse parallel. x5 and the seventh transistor S x7 , the output level of the output terminal VOUT of the multi-level inverter is 0V. fx1 and the second unidirectional conducting transistor S fx2 When turned off, the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 The voltage between the collector and emitter of is kept at 0V, so that the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 The soft switch is turned off to improve the efficiency of the multi-level inverter. Fig.15 A schematic diagram of a voltage waveform simulation between the collector and emitter of a first unidirectional conducting transistor provided in an embodiment of the present invention. Curve 1 is a voltage waveform simulation diagram of a first unidirectional conducting transistor S fx1 The voltage curve between the collector and emitter of the first unidirectional conducting transistor S fx1 The driving signal G fx1 The curve of Fig.15As shown, at the turn-on and turn-off moments of the first unidirectional conduction transistor, the voltage between the collector and the emitter of the first unidirectional conduction transistor is maintained at 0V, thereby achieving soft switching of the first unidirectional conduction transistor and improving the efficiency of the multi-level inverter.

[0085] It can be seen from the above process that during the zero-crossing switching process, the output level of the multi-level inverter is maintained at 0V, thereby avoiding the abnormal phenomenon of the output level during the zero-crossing switching.

[0086] Fig.16 for Figure 8 A schematic diagram of a voltage waveform simulation under a non-unity power factor corresponding to a multi-level inverter is provided. Curve 3 is a waveform curve of a single-phase voltage of a power grid, curve 4 is a waveform curve of a single-phase current of a power grid, curve 5 is a waveform curve of a single-phase output level of a multi-level inverter, and curve 6 is a waveform curve of a single-phase current of a power grid through a first unidirectional conduction transistor S fx1 The current waveform curve 7 is the current waveform curve through the second unidirectional conduction transistor S fx2 The current waveform curve. Fig.16 As shown, under non-unity power factor, the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 The freewheeling is performed so that the output level of the multi-level inverter is maintained at 0V, thus avoiding the abnormal phenomenon of the output level during zero-crossing switching.

[0087] Table 2

[0088]

[0089] In some embodiments, the zero-crossing switching process of the multilevel inverter may also switch from the ON state to the OP state. Fig.17 A timing diagram of a control signal for switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention. a1 is the timing of the first pulse width modulation signal, G a2 is the timing of the second pulse width modulation signal, G a3 is the timing of the third pulse width modulation signal, G a4 is the timing of the fourth pulse width modulation signal, G x1 The first transistor S x1 The timing of the driving signal, G x2 The second transistor S x2 The timing of the driving signal, G x3 The third transistor S x3 The timing of the driving signal, G x4 The fourth transistor S x4 The timing of the driving signal, G fx1is a first unidirectional conducting transistor S fx1 The timing of the driving signal, G fx2 is the second unidirectional conducting transistor S fx2 At the same time, the driving signal G x5 ( Fig.17 ) is used to drive the fifth transistor S x5 , driving signal G x6 ( Fig.17 ) is used to drive the sixth transistor S x6 , driving signal G x7 ( Fig.17 ) is used to drive the seventh transistor S x7 , driving signal G x8 ( Fig.17 ) is used to drive the eighth transistor S x8 The following describes the specific process of switching from the ON state to the OP state when the current of the multilevel inverter is flowing.

[0090] Fig.18 A current diagram of a multi-level inverter in the ON state provided by an embodiment of the present invention. Fig.18 As shown, in the ON state before zero-crossing switching, G x2 , G x4 , G x5 and G x7 is high level, G x1 , G x3 , G x6 , G x8 , G fx1 and G fx2 The second transistor S x2 , the fourth transistor S x4 , the fifth transistor S x5 and the seventh transistor S x7 The current flows from the output terminal VOUT of the multi-level inverter through the fifth transistor S x5 The ninth diode D9 and the seventh transistor S connected in reverse parallel x7 The eleventh diode D11 and the second transistor S are connected in reverse parallel x2 Flows to the neutral input power supply terminal V0, and the output level of the output terminal VOUT of the multilevel inverter is 0V.

[0091] Fig.19 A current diagram of the first step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention. Fig.19 As shown, the first step from the ON state to the OP state, G x2 , G x5 , G x7 , Gfx1 and G fx2 is high level, G x1 , G x3 , G x4 , G x6 and G x8 The fourth transistor S is turned off. x4 , turn on the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 At this time, the current flows into the neutral input power supply terminal V0 through two current branches, one of which is still from the output terminal VOUT of the multi-level inverter through the fifth transistor S x5 The ninth diode D9 and the seventh transistor S connected in reverse parallel x7 The eleventh diode D11 and the second transistor S are connected in reverse parallel x2 The other current branch flows from the output terminal VOUT of the multilevel inverter through the first unidirectional conduction transistor S fx1 Flowing into the neutral input power supply terminal V0, the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0092] Fig. 20 A current diagram of the second step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention. Fig. 20 As shown, the second step from the ON state to the OP state, G fx1 and G fx2 is high level, G x1 , G x2 , G x3 , G x4 , G x5 , G x6 , G x7 and G x8 is low level. Turn off the second transistor S x2 , the fifth transistor S x5 and the seventh transistor S x7 , the current branch from the fifth transistor S x5 The ninth diode D9 and the seventh transistor S connected in reverse parallel x7 The eleventh diode D11 and the second transistor S are connected in reverse parallel x2 Switch to the first unidirectional conduction transistor S fx1 , the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0093] Fig.21 A current diagram of the third step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention. Fig. 20 As shown, the third step from the ON state to the OP state, Gx1 , G x3 , G x6 , G x8 , G fx1 and G fx2 is high level, G x2 , G x4 , G x5 and G x7 is low level. Turn on the first transistor S x1 , the third transistor S x3 , the sixth transistor S x6 and the eighth transistor S x8 At this time, the current flows into the neutral input power supply terminal V0 through two current branches, one of which is from the output terminal VOUT of the multi-level inverter through the first unidirectional conduction transistor S fx1 Flows into the neutral input power supply terminal V0, and the other current branch passes through the sixth transistor S x6 and the eighth transistor S x8 and the third transistor S x3 The third diode D3 connected in reverse parallel flows into the neutral input power supply terminal V0, and the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0094] Fig. 22 A current diagram of the fourth step of switching a multi-level inverter from an ON state to an OP state provided by an embodiment of the present invention. Fig. 22 As shown, the fourth step of switching from the ON state to the OP state, G x1 , G x3 , G x6 and G x8 is high level, G x2 , G x4 , G x5 , G x7 , G fx1 and G fx2 The first unidirectional conducting transistor S is turned off. fx1 and the second unidirectional conducting transistor S fx2 , at this time, it is the OP state after zero-crossing switching, and the current branch is from the first unidirectional conduction transistor S fx1 Naturally switch to the sixth transistor S x6 and the eighth transistor S x8 and the third transistor S x3 The third diode D3 is connected in reverse parallel, and the output level of the output terminal VOUT of the multi-level inverter is 0V.

[0095] It can be seen from the above process that during the zero-crossing switching process, the output level of the multi-level inverter is maintained at 0V, thereby avoiding the abnormal phenomenon of the output level during the zero-crossing switching.

[0096] It should be noted that Table 2 exemplarily provides a schematic diagram of a zero-crossing switching mode of a multi-level inverter. In other embodiments, the first transistor S x1 and the fourth transistor S x4 The state switching step can also avoid the abnormal phenomenon of the output level during zero-crossing switching. For example, Table 3 is a schematic diagram of the mode of zero-crossing switching of another multi-level inverter provided by an embodiment of the present invention. As shown in Table 3, relative to Table 2, the first transistor S can be controlled x1 The second step of switching from the OP state to the ON state is turned off. Similarly, the fourth transistor S x4 The second step of switching from the ON state to the OP state is turned off. Table 4 is a schematic diagram of the mode of zero-crossing switching of another multi-level inverter provided by an embodiment of the present invention. As shown in Table 4, relative to Table 3, the fourth transistor S x4 The fourth step is to switch from the OP state to the ON state. Similarly, the first transistor S can be controlled x1 The fourth step of switching from the ON state to the OP state is turned on. Table 5 is a schematic diagram of the mode of zero-crossing switching of another multi-level inverter provided by an embodiment of the present invention. As shown in Table 5, relative to Table 2, the fourth transistor S x4 The fourth step is to switch from the OP state to the ON state. Similarly, the first transistor S can be controlled x1 The fourth step to switch from ON state to OP state is open. No limitation is made here.

[0097] Table 3

[0098]

[0099] Table 4

[0100]

[0101] Table 5

[0102]

[0103] An embodiment of the present invention further provides a dead zone modulation method for a multi-level inverter, which is used to modulate the multi-level inverter provided by any embodiment of the present invention. Fig.23 A schematic diagram of a dead zone modulation method for a multi-level inverter provided by an embodiment of the present invention. Fig.23 As shown, the method includes:

[0104] S10, in the first step, controlling the freewheeling branch to open the freewheeling loop according to the freewheeling control signal;

[0105] Specifically, when the freewheeling branch includes a first unidirectional conducting transistor S connected in parallel fx1and the second unidirectional conducting transistor S fx2 When the first freewheeling control signal can simultaneously control the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 In the first step of zero-crossing switching, the first unidirectional conducting transistor S can be controlled by the freewheeling branch. fx1 and the second unidirectional conducting transistor S fx2 Open to control the freewheeling branch to provide a freewheeling loop.

[0106] S20, in the second step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, respectively control the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and the third bridge circuit to at least partially shut down the current loop of the current mode;

[0107] Specifically, the first bridge control signal is used to control the first bridge circuit, the second bridge control signal is used to control the second bridge circuit, the branch control signal is used to control the flying capacitor branch, and the third bridge control signal is used to control the third bridge circuit. When the first bridge circuit includes a first transistor and a second transistor, the first bridge control signal includes a first drive signal and a second drive signal, which respectively control the conduction or shutoff of the first transistor and the second transistor. Similarly, when the second bridge circuit includes a third transistor and a fourth transistor, the second bridge control signal includes a third drive signal and a fourth drive signal, which respectively control the conduction or shutoff of the third transistor and the fourth transistor. The number of branch control signals is the same as the number of flying capacitor branches. When each flying capacitor branch includes a fifth transistor and a sixth transistor, each branch control signal includes a fifth drive signal and a sixth drive signal, which respectively control the conduction or shutoff of the fifth transistor and the sixth transistor. When the third bridge circuit includes a seventh transistor and an eighth transistor, the third bridge control signal includes a seventh drive signal and an eighth drive signal, which respectively control the conduction or shutoff of the seventh transistor and the eighth transistor. In the first step, the freewheeling branch can provide a freewheeling loop. In the second step, the current branch before the zero-crossing switching can be controlled to be turned off, and a freewheeling loop is provided by the freewheeling branch to maintain the output level at 0V, thereby avoiding abnormal output level.

[0108] S30, in the third step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, respectively control the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and at least part of the third bridge circuit to open the current loop of the next mode;

[0109] Specifically, after the current branch before the zero-crossing switching is turned off, the continuous current branch provides a freewheeling loop to maintain the output level at 0V, and at the same time controls the current branch after the zero-crossing switching to open, thereby achieving zero-crossing switching.

[0110] S40. In the fourth step, the freewheeling branch is controlled to shut down the freewheeling loop according to the freewheeling control signal.

[0111] Specifically, after the zero-crossing switching, the freewheeling branch is controlled to be turned off, so that the multi-level inverter can output the multi-level voltage normally.

[0112] The technical solution of this embodiment, by controlling the freewheeling branch to open during zero-crossing switching, provides a freewheeling loop, so that the output level of the multilevel inverter is maintained at 0V, avoiding the abnormal phenomenon of the output level of the multilevel inverter during zero-crossing switching. In the fourth step, the freewheeling branch can be controlled to be in a disconnected state, thereby avoiding the conduction loss of the freewheeling branch in other modes, reducing the loss of the multilevel inverter, and improving the efficiency of the multilevel inverter. Moreover, there is no need to detect the zero-crossing moment of the multilevel inverter, and there is no need to add a complex modulation strategy, so that the accuracy requirements of the multilevel inverter control system can be reduced, which is conducive to improving the control accuracy and reducing the cost of the multilevel inverter.

[0113] In some embodiments, the first bridge control signal includes a first drive signal and a second drive signal, and the second bridge control signal includes a third drive signal and a fourth drive signal; Fig.24 A logic diagram of forming a dead zone modulation signal provided by an embodiment of the present invention. Fig.24 As shown, the dead zone modulation method of the multi-level inverter also includes:

[0114] The falling edge of the first pulse width modulation signal is delayed by a first preset time to form a first driving signal.

[0115] Specifically, Fig.24 As shown, the first pulse width modulation signal G a1 The falling edge can be delayed by a first preset time by the conduction delay module 101 to form a first driving signal G x1 , used to drive the first transistor. The delay time of the conduction delay module 101 is a first preset time, which can be set according to the dead time of the multi-level inverter. The first pulse width modulation signal G a1 It can be a conventional driving signal of a multi-level inverter. For example, when the first pulse width modulation signal G a1 When the pulse width modulation signal is a 2s period and a 50% duty cycle, its high level time is 1s and its low level time is 1s. When the first preset time is 0.1s, the first drive signal G x1 The falling edge is at 1.1s and the rising edge is at 2s.

[0116] The falling edge of the second pulse width modulation signal is delayed by a first preset time, and the rising edge is delayed by a second preset time to form a second driving signal.

[0117] Specifically, the second preset time may be different from the first preset time. The second pulse width modulation signal G a2 The first pulse width modulation signal G a1 It is a pulse width modulation signal with opposite timing but the same period and duty cycle. Fig.24 As shown, the second pulse width modulation signal G a2 The falling edge can be delayed by a first preset time through the on-delay module 101, and the rising edge can be delayed by a second preset time through the off-delay module 102 to form the second driving signal G x2 , used to drive the second transistor. The delay time of the turn-off delay module 102 is a second preset time, which can be set according to the dead time of the multi-level inverter. Exemplarily, when the second pulse width modulation signal G a2 When the pulse width modulation signal has a period of 2s and a duty cycle of 50%, its high level time is 1s and its low level time is 1s. When the first preset time is 0.1s and the second preset time is 0.1s, the second driving signal G x2 The falling edge is at 1.1s and the rising edge is at 2.1s.

[0118] The falling edge of the third pulse width modulation signal is delayed by a first preset time, and the rising edge is delayed by a second preset time to form a third driving signal.

[0119] Specifically, the third pulse width modulation signal G a3 The first pulse width modulation signal G a1 It is a pulse width modulation signal with the same timing, period and duty cycle. Fig.24 As shown, the third pulse width modulation signal G a3 The falling edge can be delayed by a first preset time through the on-delay module 101, and the rising edge can be delayed by a second preset time through the off-delay module 102 to form a third driving signal G x3 , used to drive the third transistor. Exemplarily, when the third pulse width modulation signal G a3 When the pulse width modulation signal is a period of 2s and the duty cycle is 50%, the high level time is 1s and the low level time is 1s. When the first preset time is 0.1s and the second preset time is 0.1s, the third driving signal G x3 The falling edge is at 1.1s and the rising edge is at 2.1s.

[0120] The falling edge of the fourth pulse width modulation signal is delayed by the first preset time to form a fourth driving signal; the timing of the first pulse width modulation signal is the same as that of the third pulse width modulation signal, the timing of the first pulse width modulation signal is opposite to that of the second pulse width modulation signal, and the timing of the third pulse width modulation signal is opposite to that of the fourth pulse width modulation signal.

[0121] Specifically, the fourth pulse width modulation signal G a4 and the third pulse width modulation signal G a3 It is a pulse width modulation signal with opposite timing but the same period and duty cycle. Fig.24 As shown, the fourth pulse width modulation signal G a4 The delay module 101 can delay the falling edge by a first preset time to form a fourth driving signal G x4 , used to drive the fourth transistor. Exemplarily, when the fourth pulse width modulation signal G a4 When the pulse width modulation signal is a 2s period and a 50% duty cycle, its high level time is 1s and its low level time is 1s. When the first preset time is 0.1s, the fourth driving signal G x4 The falling edge is at 1.1s and the rising edge is at 2s.

[0122] The first drive signal, the second drive signal, the third drive signal and the fourth drive signal are subjected to a logic operation to form a freewheeling control signal.

[0123] Specifically, when forming the first driving signal G x1 , the second driving signal G x2 , the third driving signal G x3 and the fourth driving signal G x4 After that, it is logically operated to form the freewheeling control signal G fx , to control the first unidirectional conduction transistor S fx1 and the second unidirectional conducting transistor S fx2 It is turned on during zero-crossing switching and turned off in other modes.

[0124] In some embodiments, continue to refer to Fig.24 , performing a logic operation on the first drive signal, the second drive signal, the third drive signal and the fourth drive signal to form a freewheeling control signal, including:

[0125] The first driving signal and the second driving signal are respectively subjected to a non-logical operation and then to an AND logic operation to form a first control signal.

[0126] Specifically, Fig.24 , the first driving signal G x1 Perform a NOT logic operation, and at the same time the second drive signal G x2After performing a NOT logic operation, the two are further performed with a NOT logic operation to form a first control signal.

[0127] The third driving signal and the fourth driving signal are respectively subjected to a non-logical operation and then to an AND logical operation to form a second control signal.

[0128] Specifically, Fig.23 , the third driving signal G x3 Perform a NOT logic operation, and at the same time the fourth drive signal G x4 After performing a NOT logic operation, the two are further performed with a NOT logic operation to form a second control signal.

[0129] An OR logic operation is performed on the first control signal and the second control signal, and the rising edge of the signal after the OR logic operation is delayed by a second preset time to form a freewheeling control signal.

[0130] Specifically, Fig.24 As shown, the first control signal and the second control signal are subjected to an OR logic operation, and then the rising edge of the signal output by the OR logic operation is delayed by a second preset time through the shutdown delay module 102 to form a freewheeling control signal G fx .

[0131] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-level inverter, characterized in that: It includes a first bridge circuit, a second bridge circuit, at least one flying capacitor branch, a third bridge circuit and a freewheeling branch; The first end of the first bridge circuit is connected to the first input power supply terminal, the second end of the first bridge circuit is connected to the neutral input power supply terminal, and the third end of the first bridge circuit is connected to the first end of the first flying capacitor branch; the first end of the second bridge circuit is connected to the second input power supply terminal, the second end of the second bridge circuit is connected to the neutral input power supply terminal, the third end of the second bridge circuit is connected to the second end of the first flying capacitor branch, and at least one flying capacitor branch is connected in series; the third end of the last flying capacitor branch is connected to the first end of the third bridge circuit, the fourth end of the last flying capacitor branch is connected to the second end of the third bridge circuit, and the third end of the third bridge circuit serves as the output end of the multi-level inverter; the freewheeling branch is connected between the neutral input power supply terminal and the output end of the multi-level inverter, and the freewheeling branch is used to connect the neutral input power supply terminal and the output end of the multi-level inverter when the output level of the multi-level inverter passes through zero.

2. The multilevel inverter according to claim 1, characterized in that: The freewheeling branch includes a first unidirectional conduction unit and a second unidirectional conduction unit; the first unidirectional conduction unit and the second unidirectional conduction unit are connected between the neutral input power supply terminal and the output terminal of the multi-level inverter, and the first unidirectional conduction unit and the second unidirectional conduction unit are used to provide a freewheeling loop when the output level passes through zero.

3. The multilevel inverter according to claim 2, characterized in that: The first unidirectional conducting unit includes a first unidirectional conducting transistor, and the second unidirectional conducting unit includes a second unidirectional conducting transistor; The emitter of the first unidirectional conducting transistor and the collector of the second unidirectional conducting transistor are connected to the neutral input power supply terminal, and the emitter of the second unidirectional conducting transistor and the collector of the first unidirectional conducting transistor are connected to the output terminal of the multilevel inverter.

4. The multilevel inverter according to claim 2, characterized in that: The first unidirectional conducting unit includes a first unidirectional conducting transistor and a first diode, and the second unidirectional conducting unit includes a second unidirectional conducting transistor and a second diode; The collector of the first unidirectional conducting transistor and the cathode of the first diode are connected to the neutral input power supply terminal, the emitter of the first unidirectional conducting transistor is connected to the anode of the first diode, and is connected to the emitter of the second unidirectional conducting transistor and the anode of the second diode, the collector of the second unidirectional conducting transistor is connected to the cathode of the second diode, and is connected to the output terminal of the multilevel inverter.

5. The multilevel inverter according to claim 2, characterized in that: The first unidirectional conducting unit includes a first bidirectional conducting transistor and a third diode, and the second unidirectional conducting unit includes a second bidirectional conducting transistor and a fourth diode; The first electrode of the first bidirectional pass transistor and the anode of the third diode are connected to the neutral input power supply terminal, the second electrode of the first bidirectional pass transistor and the cathode of the third diode are connected to the second electrode of the second bidirectional pass transistor and the cathode of the fourth diode, and the first electrode of the second bidirectional pass transistor and the anode of the fourth diode are connected to the output terminal of the multilevel inverter.

6. The multilevel inverter according to any one of claims 1 to 5, characterized in that: The first bridge circuit includes a first transistor, a second transistor, a fifth diode and a sixth diode, and the second bridge circuit includes a third transistor, a fourth transistor, a seventh diode and an eighth diode; The first electrode of the first transistor is connected to the cathode of the fifth diode and serves as the first end of the first bridge circuit; the second electrode of the first transistor and the anode of the fifth diode are connected to the first electrode of the second transistor and the cathode of the sixth diode and serve as the third end of the first bridge circuit; the second electrode of the second transistor is connected to the anode of the sixth diode and serves as the second end of the first bridge circuit; The first electrode of the third transistor is connected to the cathode of the seventh diode and serves as the second end of the second bridge circuit. The second electrode of the third transistor and the anode of the seventh diode are connected to the first electrode of the fourth transistor and the cathode of the eighth diode and serve as the third end of the second bridge circuit. The second electrode of the fourth transistor is connected to the anode of the eighth diode and serves as the first end of the second bridge circuit.

7. The multilevel inverter according to claim 6, characterized in that: The flying capacitor branch includes a fifth transistor, a sixth transistor, a ninth diode, a tenth diode and a flying capacitor, and the third bridge circuit includes a seventh transistor, an eighth transistor, an eleventh diode and a twelfth diode; The first electrode of the fifth transistor is connected to the cathode of the ninth diode and serves as the first end of the flying capacitor branch; the second electrode of the fifth transistor and the anode of the ninth diode are connected to the first electrode of the flying capacitor and serve as the third end of the flying capacitor branch; the second electrode of the flying capacitor is connected to the first electrode of the sixth transistor and the cathode of the tenth diode and serves as the fourth end of the flying capacitor branch; the second electrode of the sixth transistor is connected to the anode of the tenth diode and serves as the second end of the flying capacitor branch; The first electrode of the seventh transistor is connected to the cathode of the eleventh diode and serves as the first end of the third bridge circuit. The second electrode of the seventh transistor and the anode of the eleventh diode are connected to the first electrode of the eighth transistor and the cathode of the twelfth diode and serve as the third end of the third bridge circuit. The second electrode of the eighth transistor is connected to the anode of the twelfth diode and serves as the second end of the third bridge circuit.

8. A dead zone modulation method for a multi-level inverter, used for modulating the multi-level inverter according to any one of claims 1 to 7, characterized in that: include: In the first step, the freewheeling branch is controlled to open the freewheeling loop according to the freewheeling control signal; In the second step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and the third bridge circuit are respectively controlled to at least partially shut down the current loop of the current mode; In the third step, according to the first bridge control signal, the second bridge control signal, the branch control signal and the third bridge control signal, at least a portion of the first bridge circuit, the second bridge circuit, at least one flying capacitor branch and the third bridge circuit are controlled to open the current loop of the next mode respectively; In the fourth step, the freewheeling branch is controlled to shut down the freewheeling loop according to the freewheeling control signal.

9. The dead zone modulation method of a multi-level inverter according to claim 8, characterized in that: The first bridge control signal includes a first drive signal and a second drive signal, and the second bridge control signal includes a third drive signal and a fourth drive signal; the method further includes: Delaying the falling edge of the first pulse width modulation signal by a first preset time to form a first driving signal; Delaying the falling edge of the second pulse width modulation signal by the first preset time, and delaying the rising edge by the second preset time, to form a second driving signal; Delaying the falling edge of the third pulse width modulation signal by the first preset time, and delaying the rising edge by the second preset time, to form a third driving signal; Delaying the falling edge of the fourth pulse width modulation signal by the first preset time to form a fourth driving signal; the first pulse width modulation signal has the same timing as the third pulse width modulation signal, the first pulse width modulation signal has an opposite timing to the second pulse width modulation signal, and the third pulse width modulation signal has an opposite timing to the fourth pulse width modulation signal; The first drive signal, the second drive signal, the third drive signal and the fourth drive signal are subjected to a logic operation to form the freewheeling control signal.

10. The dead zone modulation method of a multi-level inverter according to claim 9, characterized in that: Performing a logic operation on the first drive signal, the second drive signal, the third drive signal, and the fourth drive signal to form the freewheeling control signal includes: Perform a non-logical operation on the first driving signal and a logical operation on the second driving signal to form a first control signal; Perform a non-logical operation and an AND logic operation on the third driving signal and the fourth driving signal to form a second control signal; Performing an OR logic operation on the first control signal and the second control signal, and delaying the rising edge of the signal after the OR logic operation by the second preset time to form the freewheeling control signal.

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