Circuit for actively simulating capacitor at two ends and implementation method

Abstract

The embodiment of the invention provides a circuit for actively simulating capacitors at two ends and an implementation method. The circuit for actively simulating capacitors at two ends comprises a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1, R2, R3, R4, R5, R7 and R8 with different resistance values, and four same operational amplifiers A1, A2, A3 and A4, according to the capacitance value of a user simulation capacitor, a standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of a variable resistor R6 in the circuit is adjusted to obtain an active equivalent simulation capacitor. And carrying out calibration processing on the target capacitance tester based on the active equivalent simulation capacitor.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of power systems, and in particular to a circuit and implementation method for actively simulating a two-terminal capacitor. Background Art

[0002] The capacitors used in the current power system are very large, with a capacitance of up to 100mF. The corresponding capacitance tester has a very large range. In order to ensure the accuracy of the capacitance, it is necessary to calibrate it with a standard capacitor. However, it is very difficult to make a large-capacity standard capacitor, which requires increasing the size of the capacitor and affects its technical characteristics. Summary of the invention

[0003] In view of this, the embodiments of this specification provide a circuit and implementation method for actively simulating a two-terminal capacitor to solve the technical defects existing in the prior art.

[0004] According to a first aspect of an embodiment of the present specification, there is provided a circuit for actively simulating a two-terminal capacitance, comprising: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values, namely, R1, R2, R3, R4, R5, R7, R8, and four identical operational amplifiers A1, A2, A3, and A4;

[0005] Among them, according to the capacitance value of the user simulated capacitor, a standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent simulated capacitor, thereby calibrating the target capacitance tester based on the active equivalent simulated capacitor.

[0006] Preferably, the left end of the standard capacitor C1 is connected to the input end of the circuit, and the right end thereof is connected to the inverting input end of the operational amplifier A1;

[0007] The inverting input terminal of the operational amplifier A1 is simultaneously connected to the left end of the resistor R1 , the output terminal thereof is connected to the right end of the resistor R1 , and the non-inverting input terminal thereof is connected to the ground signal.

[0008] Preferably, the left end of the inductor L1 is connected to the output end of the operational amplifier A1, and the right end thereof is connected to the inverting input end of the operational amplifier A2;

[0009] The inverting input terminal of the operational amplifier A2 is simultaneously connected to the left end of the resistor R3, the output terminal thereof is connected to the right end of the resistor R3, and the non-inverting input terminal thereof is connected to the ground signal.

[0010] Preferably, the right end of the resistor R2 is connected to the output end of the operational amplifier A4, and the left end thereof is connected to the input end of the circuit; the right end of the resistor R4 is connected to the output end of the operational amplifier A2, and the left end thereof is connected to the input end of the circuit.

[0011] Preferably, the right end of the resistor R5 is connected to the output end of the operational amplifier A1, and the left end thereof is connected to the inverting input end of the operational amplifier A3;

[0012] The inverting input terminal of the operational amplifier A3 is simultaneously connected to the right end of the variable resistor R6, the output terminal thereof is connected to the left end of the variable resistor R6, and the non-inverting input terminal thereof is connected to the ground signal.

[0013] Preferably, the right end of the resistor R7 is connected to the output end of the operational amplifier A3, and the left end thereof is connected to the inverting input end of the operational amplifier A4;

[0014] The inverting input terminal of the operational amplifier A4 is connected to the right end of the resistor R8, the output terminal thereof is connected to the left end and the left end of the resistor R8, and the non-inverting input terminal thereof is connected to the ground signal.

[0015] Preferably, the analog impedance Z at the circuit input is:

[0016]

[0017] Among them, when R 1 =R 2 =R 4 , R 1 C 1 R 3 =2L 1 , and R 7 =R 8 When , the simulated impedance Z at the circuit input is:

[0018]

[0019] Among them, V in is the input voltage at the input end of the circuit;

[0020] Among them, the active equivalent simulated capacitance C simulated by the simulated impedance Z at the input end of the circuit is:

[0021]

[0022] According to a second aspect of an embodiment of this specification, a method for implementing an active simulated two-terminal capacitor is provided, comprising:

[0023] According to the capacitance value of the user simulated capacitor, select a standard capacitor C1 corresponding to the capacitance value;

[0024] Based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the active simulated two-terminal capacitance circuit is adjusted to obtain an active equivalent simulated capacitance, thereby performing calibration processing on the target capacitance tester based on the active equivalent simulated capacitance;

[0025] The active analog two-terminal capacitor circuit includes: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values: R1, R2, R3, R4, R5, R7, R8, and four identical operational amplifiers: A1, A2, A3, and A4.

[0026] Preferably, the analog impedance Z at the circuit input is:

[0027]

[0028] Among them, when R 1 =R 2 =R 4 , R 1 C 1 R 3 =2L 1 , and R 7 =R 8 When , the simulated impedance Z at the circuit input is:

[0029]

[0030] Among them, V in is the input voltage at the input end of the circuit.

[0031] Preferably, the active equivalent simulated capacitance C simulated by the simulated impedance Z at the circuit input end is:

[0032]

[0033] The embodiment of this specification obtains an active equivalent simulated capacitor by selecting a standard capacitor C1 corresponding to the capacitance value of the user simulated capacitor according to the capacitance value, and adjusting the resistance value of the variable resistor R6 in the circuit based on the capacitance value and the standard capacitor C1, thereby calibrating the target capacitance tester based on the active equivalent simulated capacitor, and also manufacturing a small-volume standard capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of an active analog two-terminal capacitor circuit provided by an embodiment of the present specification;

[0035] Figure 2This is a flow chart of a method for implementing an active simulated two-terminal capacitor provided by an embodiment of this specification. DETAILED DESCRIPTION

[0036] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0037] Figure 1 is a schematic diagram of an active analog two-terminal capacitor circuit provided by an embodiment of this specification, such as Figure 1 As shown, it includes: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values ​​R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8 and four identical operational amplifiers A1, an operational amplifier A2, an operational amplifier A3, and an operational amplifier A4;

[0038] Among them, according to the capacitance value of the user simulated capacitor, a standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent simulated capacitor, thereby calibrating the target capacitance tester based on the active equivalent simulated capacitor.

[0039] In one embodiment of the present invention, the left end of the standard capacitor C1 is connected to the input end of the circuit, and the right end thereof is connected to the inverting input end of the operational amplifier A1;

[0040] The inverting input terminal of the operational amplifier A1 is simultaneously connected to the left end of the resistor R1 , the output terminal thereof is connected to the right end of the resistor R1 , and the non-inverting input terminal thereof is connected to the ground signal.

[0041] In one embodiment of the present invention, the left end of the inductor L1 is connected to the output end of the operational amplifier A1, and the right end thereof is connected to the inverting input end of the operational amplifier A2;

[0042] The inverting input terminal of the operational amplifier A2 is simultaneously connected to the left end of the resistor R3, the output terminal thereof is connected to the right end of the resistor R3, and the non-inverting input terminal thereof is connected to the ground signal.

[0043] In one embodiment of the present invention, the right end of the resistor R2 is connected to the output end of the operational amplifier A4, and the left end thereof is connected to the input end of the circuit; the right end of the resistor R4 is connected to the output end of the operational amplifier A2, and the left end thereof is connected to the input end of the circuit.

[0044] In one embodiment of the present invention, the right end of the resistor R5 is connected to the output end of the operational amplifier A1, and the left end thereof is connected to the inverting input end of the operational amplifier A3;

[0045] The inverting input terminal of the operational amplifier A3 is simultaneously connected to the right end of the variable resistor R6, the output terminal thereof is connected to the left end of the variable resistor R6, and the non-inverting input terminal thereof is connected to the ground signal.

[0046] In one embodiment of the present invention, the right end of the resistor R7 is connected to the output end of the operational amplifier A3, and the left end thereof is connected to the inverting input end of the operational amplifier A4;

[0047] The inverting input terminal of the operational amplifier A4 is connected to the right end of the resistor R8, the output terminal thereof is connected to the left end and the left end of the resistor R8, and the non-inverting input terminal thereof is connected to the ground signal.

[0048] In one embodiment of the present invention, the simulated impedance Z at the circuit input is:

[0049]

[0050] Among them, when R 1 =R 2 =R 4 , R 1 C 1 R 3 =2L 1 , and R 7 =R 8 When , the simulated impedance Z at the circuit input is:

[0051]

[0052] Among them, V in is the input voltage at the input end of the circuit;

[0053] Among them, the active equivalent simulated capacitance C simulated by the simulated impedance Z at the input end of the circuit is:

[0054]

[0055] Figure 2 is a flow chart of a method for implementing an active simulated two-terminal capacitor provided by an embodiment of this specification, such as Figure 2 As shown, including:

[0056] Step S101: According to the capacitance value of the user simulated capacitance, a standard capacitor C1 corresponding to the capacitance value is selected;

[0057] Step S102: Based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the active simulated two-terminal capacitance circuit is adjusted to obtain an active equivalent simulated capacitance, thereby calibrating the target capacitance tester based on the active equivalent simulated capacitance;

[0058] The active analog two-terminal capacitor circuit includes: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values: R1, R2, R3, R4, R5, R7, R8, and four identical operational amplifiers: A1, A2, A3, and A4.

[0059] In one embodiment of the present invention, the simulated impedance Z at the circuit input is:

[0060]

[0061] Among them, when R 1 =R 2 =R 4 , R 1 C 1 R 3 =2L 1 , and R 7 =R 8 When , the simulated impedance Z at the circuit input is:

[0062]

[0063] Among them, V in is the input voltage at the input end of the circuit.

[0064] In the embodiment of the present invention, the active equivalent simulated capacitance C simulated by the simulated impedance Z at the input end of the circuit is:

[0065]

[0066] like Figure 1As shown, the input end of the circuit is connected to the left end of C1, the right end of C1 is connected to the inverting input end of the operational amplifier A1, the inverting input end of A1 is also connected to the left end of R1, the right end of R1 is connected to the output end of the operational amplifier, and the non-inverting input end of the operational amplifier A1 is connected to the ground signal; the output end of the operational amplifier A1 is connected to the left end of the inductor L1, the right end of the inductor L1 is connected to the inverting input end of the operational amplifier A2, the inverting input end of the operational amplifier A2 is also connected to the left end of the resistor R3, the right end of the resistor R3 is connected to the output end of the operational amplifier A2, and the non-inverting input end of the operational amplifier A2 is connected to the ground signal; the output end of the operational amplifier A2 is connected to the right end of the resistor R4, and the left end of R4 is connected to the input end of the circuit; the output end of the operational amplifier A1 is connected to The right end of the resistor R5 is connected, the left end of the resistor R5 is connected to the inverting input end of the operational amplifier A3, the inverting input end of the operational amplifier A3 is also connected to the right end of the variable resistor R6, the left end of the variable resistor R6 is connected to the output end of the operational amplifier A3, and the non-inverting input end of the operational amplifier A3 is connected to the ground signal; the output end of the operational amplifier A3 is connected to the right end of the resistor R7, the left end of the resistor R7 is connected to the inverting input end of the operational amplifier A4, the inverting input end of the operational amplifier A4 is also connected to the right end of the resistor R8, the left end of the resistor R8 is connected to the output end of the operational amplifier A4, the non-inverting input end of the operational amplifier A4 is connected to the ground signal, the output end of the operational amplifier A4 is connected to the right end of the resistor R2, and the left end of the resistor R2 is connected to the input end of the circuit.

[0067] The four operational amplifiers used in the present invention are all of the same model, namely LM3886; other types of power operational amplifiers may also be used.

[0068] The working principle of the active circuit simulating the two-terminal capacitor is as follows:

[0069] According to the virtual short and virtual open of operational amplifier A1:

[0070]

[0071] V O1 =-V in ·jωC 1 R 1 (2)

[0072] According to Kirchhoff's voltage law:

[0073] V in =I 2 R 2 +V O4 =I 3 R 4 +V O2 (3)

[0074] According to the virtual short and virtual open of operational amplifier A2:

[0075]

[0076] Substituting formula (2) into formula (4)

[0077]

[0078] From formula (1), we can know that:

[0079] I 1 =V in JωC 1 (6)

[0080] According to the virtual short and virtual open of operational amplifier A3:

[0081] According to the virtual short and virtual open of operational amplifier A4:

[0082] Substituting formula (7) into formula (8), we can get:

[0083]

[0084] Substituting formula (2) into formula (9)

[0085]

[0086] From formula (3), we can know that:

[0087]

[0088] Substituting formula (10) into formula (11)

[0089]

[0090] From formula (3), we can know that:

[0091]

[0092] Substituting formula (5) into formula (13)

[0093]

[0094] According to Kirchhoff's current law:

[0095] I=I 1 +I 2 +I 3 (15)

[0096] Substituting formulas (6), (12), and (14) into formula (15), we can obtain:

[0097]

[0098] The impedance of the entire circuit input is:

[0099]

[0100] Substituting formula (16) into formula (17), we can get:

[0101]

[0102] From formula (18), we can see that the analog impedance of the circuit has nothing to do with the size of the input signal, but only with the parameters of the circuit design.

[0103] When R 1 =R 2 =R 4 , and R 1 C 1 R 3 =2L 1 , and R 7 =R 8 hour,

[0104]

[0105] From formula (19), we can see that the simulated impedance of the circuit has no real part, which is equivalent to the equivalent resistance of the circuit being 0, indicating that the simulated impedance is a pure capacitor. At the same time, the capacitance simulated by the simulated impedance is equivalent to:

[0106]

[0107] From formula (20), we can see that by selecting a suitable standard capacitor C1, we can simulate the size of the capacitor by simply changing the size of the variable resistor R6. For example, to simulate a 100mF standard capacitor, the standard capacitor C1 can be a 100μF standard capacitor, R5 can be 100Ω, R6 can be 100kΩ, and R 1 =R 2 =R 4 =100Ω, R 7 =R 8 =1kΩ,R 3 =100Ω, inductance L 1 =1H, under this condition, a standard capacitance of 100mF can be achieved.

[0108] The design of the entire circuit realizes the simulation of large capacitance. By precisely changing the size of the variable resistor R6, accurate simulation of large capacitance is achieved, and the simulated capacitance loss value is zero. The simulated large capacitance can be used to calibrate a large capacitance tester, ensuring the accuracy of the capacitance tester.

[0109] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the present invention is not limited thereby. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the present invention shall be within the scope of the present invention.

Claims

1. A circuit for actively simulating a two-terminal capacitor, characterized in that: include: A standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values ​​R1, R2, R3, R4, R5, R7, R8 and four identical operational amplifiers A1, A2, A3 and A4; Among them, according to the capacitance value of the user simulated capacitor, a standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent simulated capacitor, thereby calibrating the target capacitance tester based on the active equivalent simulated capacitor.

2. The circuit for active simulation of two-terminal capacitance according to claim 1, characterized in that: The left end of the standard capacitor C1 is connected to the input end of the circuit, and the right end is connected to the inverting input end of the operational amplifier A1; The inverting input terminal of the operational amplifier A1 is simultaneously connected to the left end of the resistor R1 , the output terminal thereof is connected to the right end of the resistor R1 , and the non-inverting input terminal thereof is connected to the ground signal.

3. The circuit for active simulation of two-terminal capacitance according to claim 2, characterized in that: The left end of the inductor L1 is connected to the output end of the operational amplifier A1, and the right end thereof is connected to the inverting input end of the operational amplifier A2; The inverting input terminal of the operational amplifier A2 is simultaneously connected to the left end of the resistor R3, the output terminal thereof is connected to the right end of the resistor R3, and the non-inverting input terminal thereof is connected to the ground signal.

4. The circuit for active simulation of two-terminal capacitance according to claim 3, characterized in that: The right end of the resistor R2 is connected to the output end of the operational amplifier A4, and the left end thereof is connected to the input end of the circuit; the right end of the resistor R4 is connected to the output end of the operational amplifier A2, and the left end thereof is connected to the input end of the circuit.

5. The circuit for active simulation of two-terminal capacitance according to claim 4, characterized in that: The right end of the resistor R5 is connected to the output end of the operational amplifier A1, and the left end thereof is connected to the inverting input end of the operational amplifier A3; The inverting input terminal of the operational amplifier A3 is simultaneously connected to the right end of the variable resistor R6, the output terminal thereof is connected to the left end of the variable resistor R6, and the non-inverting input terminal thereof is connected to the ground signal.

6. The circuit for active simulation of two-terminal capacitance according to claim 5, characterized in that: The right end of the resistor R7 is connected to the output end of the operational amplifier A3, and the left end thereof is connected to the inverting input end of the operational amplifier A4; The inverting input terminal of the operational amplifier A4 is connected to the right end of the resistor R8, the output terminal thereof is connected to the left end and the left end of the resistor R8, and the non-inverting input terminal thereof is connected to the ground signal.

7. The circuit for active simulation of two-terminal capacitance according to claim 6, characterized in that: The simulated impedance Z at the input of the circuit is: Among them, when R1=R2=R4, R1C1R3=2L1, and R7=R8, the simulated impedance Z at the input end of the circuit is: Among them, V in is the input voltage at the input end of the circuit; Among them, the active equivalent simulated capacitance C simulated by the simulated impedance Z at the input end of the circuit is:

8. A method for realizing active simulation of two-terminal capacitance, characterized in that: include: According to the capacitance value of the user simulated capacitor, select a standard capacitor C1 corresponding to the capacitance value; Based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the active simulated two-terminal capacitance circuit is adjusted to obtain an active equivalent simulated capacitance, thereby performing calibration processing on the target capacitance tester based on the active equivalent simulated capacitance; The active analog two-terminal capacitor circuit includes: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors with different resistance values: R1, R2, R3, R4, R5, R7, R8, and four identical operational amplifiers: A1, A2, A3, and A4.

9. The implementation method according to claim 8, characterized in that: The simulated impedance Z at the input of the circuit is: Among them, when R1=R2=R4, R1C1R3=2L1, and R7=R8, the simulated impedance Z at the input end of the circuit is: Among them, V in is the input voltage at the input end of the circuit.

10. The implementation method according to claim 9, characterized in that: The simulated impedance Z at the input of the circuit simulates the active equivalent simulated capacitance C as follows:

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