Circuit and implementation method of active analog two-terminal capacitor

Abstract

The embodiment of the present specification provides a circuit and implementation method of active analog two-terminal capacitor, wherein the circuit of active analog two-terminal capacitor comprises: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1 with different resistance values, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, and four same operational amplifiers A1, A2, A3 and A4; wherein according to a capacitance value of a user analog capacitor, a standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent analog capacitor, so that calibration processing of a target capacitance tester is carried out based on the active equivalent analog capacitor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present specification relate to the technical field of power systems, in particular to a circuit for simulating a two-terminal capacitor and a method for implementing the same. BACKGROUND

[0002] Now the capacitor used in power system is very large, the capacitance can reach 100mF, the corresponding range of the capacitor tester is also very large, in order to ensure the accuracy of the capacitor, it is necessary to use standard capacitor to calibrate it, but it is very difficult to make large-capacity standard capacitor, it is necessary to increase the volume of the capacitor, and its technical characteristics will be affected. SUMMARY

[0003] Therefore, the embodiments of the present specification provide a circuit for simulating a two-terminal capacitor and a method for implementing the same to solve the technical defects in the prior art.

[0004] According to a first aspect of the embodiments of the present specification, a circuit for simulating a two-terminal capacitor is provided, comprising: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1 with different resistance values, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, and four identical operational amplifiers A1, A2, A3, and A4.

[0005] Among them, according to the capacitance value of the user simulated capacitor, the standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent simulated capacitor, so as to perform calibration processing of the target capacitor tester based on the active equivalent simulated capacitor.

[0006] Preferably, the left end of the standard capacitor C1 is connected with the input end of the circuit, and the right end thereof is connected with the inverting input end of the operational amplifier A1.

[0007] The inverting input end of the operational amplifier A1 is connected with the left end of the resistor R1 at the same time, the output end thereof is connected with the right end of the resistor R1, and the non-inverting input end thereof is connected with the ground signal.

[0008] Preferably, the left end of the inductor L1 is connected with the output end of the operational amplifier A1, and the right end thereof is connected with the inverting input end of the operational amplifier A2.

[0009] The inverting input end of the operational amplifier A2 is connected with the left end of the resistor R3 at the same time, the output end thereof is connected with the right end of the resistor R3, and the non-inverting input end thereof is connected with the ground signal.

[0010] Preferably, the right end of the resistor R2 is connected with the output end of the operational amplifier A4, and the left end is connected with the input end of the circuit; the right end of the resistor R4 is connected with the output end of the operational amplifier A2, and the left end is connected with the input end of the circuit.

[0011] Preferably, the right end of the resistor R5 is connected with the output end of the operational amplifier A1, and the left end is connected with the inverting input end of the operational amplifier A3.

[0012] The inverting input end of the operational amplifier A3 is connected with the right end of the variable resistor R6, the output end is connected with the left end of the variable resistor R6, and the non-inverting input end is connected with the ground signal.

[0013] Preferably, the right end of the resistor R7 is connected with the output end of the operational amplifier A3, and the left end is connected with the inverting input end of the operational amplifier A4.

[0014] The inverting input end of the operational amplifier A4 is connected with the right end of the resistor R8, the output end is connected with the left end of the resistor R8, and the non-inverting input end is connected with the ground signal.

[0015] Preferably, the analog impedance Z of the input end of the circuit is:

[0016]

[0017] When R1=R2=R4, R1C1R3=2L1, and R7=R8, the analog impedance Z of the input end of the circuit is:

[0018]

[0019] Wherein, V in is the input voltage of the input end of the circuit;

[0020] Wherein, the active equivalent analog capacitance C simulated by the analog impedance Z of the input end of the circuit is:

[0021]

[0022] According to the second aspect of the embodiment of the present specification, an implementation method of an active analog two-terminal capacitance is provided, comprising:

[0023] According to the capacitance value of the user analog capacitance, a standard capacitor C1 corresponding to the capacitance value is selected;

[0024] Based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the active analog two-terminal capacitance circuit is adjusted to obtain an active equivalent analog capacitance, so that the calibration processing of the target capacitance tester is carried out based on the active equivalent analog capacitance;

[0025] The active analog two-terminal capacitance circuit comprises: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1 of different resistance values, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R7, a resistor R8, and four identical operational amplifiers A1, A2, A3, and A4.

[0026] Preferably, the analog impedance Z of the circuit input end is:

[0027]

[0028] When R1 = R2 = R4, R1C1R3 = 2L1, and R7 = R8, the analog impedance Z of the circuit input end is:

[0029]

[0030] V in is the input voltage of the circuit input end.

[0031] Preferably, the active equivalent analog capacitance C simulated by the analog impedance Z of the circuit input end is:

[0032]

[0033] The embodiment of the present specification selects a standard capacitor C1 corresponding to the capacitance value of the user analog capacitor according to the capacitance value of the user analog capacitor, and adjusts the resistance value of the variable resistor R6 in the circuit based on the capacitance value and the standard capacitor C1, to obtain an active equivalent analog capacitor, so as to perform calibration processing of the target capacitance tester based on the active equivalent analog capacitor, and also manufacture a small-size standard capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a schematic diagram of an active analog two-terminal capacitance circuit provided by an embodiment of the present specification;

[0035] Figure 2 is a flow chart of an implementation method of an active analog two-terminal capacitance provided by an embodiment of the present specification. DETAILED DESCRIPTION

[0036] In the following description, many specific details are set forth in order to provide a thorough understanding of the present specification. However, the present specification can be practiced in many different ways beyond the specific details disclosed herein, and the skilled in the art can make similar substitutions without departing from the scope of the present specification, so the present specification is not limited to the specific implementations disclosed below.

[0037] Figure 1is a schematic diagram of an active analog two-terminal capacitance circuit provided by an embodiment of the present specification, as shown in Figure 1 includes a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1 of different resistance values, resistors R2, R3, R4, R5, R7, R8, and four identical operational amplifiers A1, A2, A3, and A4.

[0038] Among them, according to the capacitance value of the user analog capacitor, the standard capacitor C1 corresponding to the capacitance value is selected, and based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the circuit is adjusted to obtain an active equivalent analog capacitor, so as to perform calibration processing of the target capacitance tester based on the active equivalent analog capacitor.

[0039] In an embodiment of the present application, the left end of the standard capacitor C1 is connected to the input end of the circuit, and the right end is connected to the inverting input end of the operational amplifier A1.

[0040] The inverting input end of the operational amplifier A1 is connected to the left end of the resistor R1 at the same time, the output end is connected to the right end of the resistor R1, and the non-inverting input end is connected to the ground signal.

[0041] In an embodiment of the present application, the left end of the inductor L1 is connected to the output end of the operational amplifier A1, and the right end is connected to the inverting input end of the operational amplifier A2.

[0042] The inverting input end of the operational amplifier A2 is connected to the left end of the resistor R3 at the same time, the output end is connected to the right end of the resistor R3, and the non-inverting input end is connected to the ground signal.

[0043] In an embodiment of the present application, the right end of the resistor R2 is connected to the output end of the operational amplifier A4, and the left end is connected to the input end of the circuit; the right end of the resistor R4 is connected to the output end of the operational amplifier A2, and the left end is connected to the input end of the circuit.

[0044] In an embodiment of the present application, the right end of the resistor R5 is connected to the output end of the operational amplifier A1, and the left end is connected to the inverting input end of the operational amplifier A3.

[0045] The inverting input end of the operational amplifier A3 is connected to the right end of the variable resistor R6 at the same time, the output end is connected to the left end of the variable resistor R6, and the non-inverting input end is connected to the ground signal.

[0046] In one embodiment of the present application, the right end of the resistor R7 is connected to the output end of the operational amplifier A3, and the left end is connected to the inverting input end of the operational amplifier A4.

[0047] The inverting input end of the operational amplifier A4 is connected to the right end of the resistor R8, the output end is connected to the left end of the resistor R8, and the non-inverting input end is connected to the ground signal.

[0048] In one embodiment of the present application, the analog impedance Z of the circuit input end is:

[0049]

[0050] When R1=R2=R4, R1C1R3=2L1, and R7=R8, the analog impedance Z of the circuit input end is:

[0051]

[0052] Wherein, V in is the input voltage of the circuit input end;

[0053] Wherein, the active equivalent analog capacitor C simulated by the analog impedance Z of the circuit input end is:

[0054]

[0055] Figure 2 is a flow chart of an implementation method of an active analog two-terminal capacitor provided by one embodiment of the present application, as Figure 2 shown, comprising:

[0056] Step S101: according to the capacitance value of the user analog capacitor, selecting a standard capacitor C1 corresponding to the capacitance value;

[0057] Step S102: based on the capacitance value and the standard capacitor C1, adjusting the resistance value of the variable resistor R6 in the active analog two-terminal capacitor circuit to obtain an active equivalent analog capacitor, and then performing calibration processing of the target capacitor tester based on the active equivalent analog capacitor;

[0058] Wherein, the active analog two-terminal capacitor circuit comprises: a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1, R2, R3, R4, R5, R7, and R8 of different resistance values, and four identical operational amplifiers A1, A2, A3, and A4.

[0059] In one embodiment of the present application, the analog impedance Z of the circuit input end is:

[0060]

[0061] Wherein, when R1=R2=R4, R1C1R3=2L1, and R7=R8, the analog impedance Z of the input end of the circuit is:

[0062]

[0063] Wherein, V in is the input voltage of the input end of the circuit.

[0064] In the embodiment of the present application, the analog impedance Z of the input end of the circuit is:

[0065]

[0066] As shown in Figure 1 , the input end of the circuit is connected with the left end of C1, the right end of C1 is connected with the inverting input end of operational amplifier A1, the inverting input end of A1 is simultaneously connected with the left end of R1, the right end of R1 is connected with the output end of the operational amplifier, the non-inverting input end of operational amplifier A1 is connected with the ground signal; the output end of A1 is connected with the left end of inductor L1, the right end of L1 is connected with the inverting input end of operational amplifier A2, the inverting input end of A2 is simultaneously connected with the left end of resistor R3, the right end of R3 is connected with the output end of operational amplifier A2, the non-inverting input end of A2 is connected with the ground signal; the output end of A2 is connected with the right end of resistor R4, the left end of R4 is connected with the input end of the circuit; the output end of A1 is connected with the right end of resistor R5, the left end of R5 is connected with the inverting input end of operational amplifier A3, the inverting input end of A3 is simultaneously connected with the right end of variable resistor R6, the left end of R6 is connected with the output end of A3, the non-inverting input end of A3 is connected with the ground signal; the output end of A3 is connected with the right end of resistor R7, the left end of R7 is connected with the inverting input end of operational amplifier A4, the inverting input end of A4 is simultaneously connected with the right end of resistor R8, the left end of R8 is connected with the output end of A4, the non-inverting input end of A4 is connected with the ground signal, the output end of A4 is connected with the right end of resistor R2, and the left end of R2 is connected with the input end of the circuit.

[0067] The four operational amplifiers used in the present application are all of the same model, which is LM3886; other types of power operational amplifiers can also be used.

[0068] The working principle of the active analog two-terminal capacitor circuit is as follows:

[0069] According to the virtual short and virtual open of operational amplifier A1:

[0070]

[0071] V O1 = -V in • jωC1R1 (2)

[0072] According to Kirchhoff's voltage law:

[0073] V in = I2R2 + V O4 = I3R4 + V O2 (3)

[0074] According to the virtual short and virtual open of operational amplifier A2:

[0075]

[0076] Substitute equation (2) into equation (4)

[0077]

[0078] According to equation (1):

[0079] I1= V in jωC1 (6)

[0080] According to the virtual short and virtual open of operational amplifier A3:

[0081] According to the virtual short and virtual open of operational amplifier A4:

[0082] Substitute equation (7) into equation (8):

[0083]

[0084] Substitute equation (2) into equation (9)

[0085]

[0086] According to equation (3):

[0087]

[0088] Substitute equation (10) into equation (11)

[0089]

[0090] According to equation (3):

[0091]

[0092] Substitute equation (5) into equation (13)

[0093]

[0094] According to Kirchhoff's current law:

[0095] I = I1 + I2 + I3 (15)

[0096] Substitute equation (6), (12), (14) into equation (15), we can get:

[0097]

[0098] The impedance of the whole circuit input end is:

[0099]

[0100] Substitute equation (16) into equation (17), we can get:

[0101]

[0102] From equation (18), the analog impedance of the circuit is irrelevant to the size of the input signal, only related to the parameters of the circuit design,

[0103] When R1 = R2 = R4, and R1C1R3 = 2L1, and R7 = R8,

[0104]

[0105] From equation (19), the analog impedance of the circuit has no real part, which is equivalent to the equivalent resistance of the circuit being 0, indicating that the analog impedance is a pure capacitor, and the size of the equivalent capacitor simulated by the analog impedance is:

[0106]

[0107] From equation (20), by selecting a suitable standard capacitor C1, the size of the capacitor can be simulated by changing the size of the variable resistor R6. For example: to simulate a 100mF standard capacitor, a 100μF standard capacitor can be used for the standard capacitor C1, R5 is 100Ω, R6 is 100kΩ, R1 = R2 = R4 = 100Ω, R7 = R8 = 1kΩ, R3 = 100Ω, and inductance L1 = 1H, under the condition of meeting the conditions, 100mF standard capacitor can be realized.

[0108] The design of the whole circuit realizes the simulation of large capacitors, accurate simulation of large capacitors is realized by accurately changing the size of the variable resistor R6, and the loss value of the simulated capacitor is zero. The simulated large capacitor can be used for calibration of large capacitor tester calibration, ensuring the accuracy of the capacitor tester.

[0109] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, and are not intended to limit the scope of the present application. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and spirit of the present application shall fall within the scope of the present application.

Claims

1. A circuit for an active analog two-terminal capacitance, characterized by Comprise: Standard capacitor C1, variable resistor R6, inductor L1, seven different resistance resistors R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R7, resistor R8 and four identical operational amplifier A1, operational amplifier A2, operational amplifier A3, operational amplifier A4; Wherein, according to the capacitance value of the user analog capacitor, the standard capacitor C1 corresponding to the capacitance value is selected, and the resistance value of the variable resistor R6 in the circuit is adjusted based on the capacitance value and the standard capacitor C1, to obtain an active equivalent analog capacitor, so that the calibration process of the target capacitance tester is carried out based on the active equivalent analog capacitor; The left end of the standard capacitor C1 is connected with the input end of the circuit, and the right end thereof is connected with the reverse input end of the operational amplifier A1; The reverse input end of the operational amplifier A1 is connected with the left end of the resistor R1 at the same time, the output end thereof is connected with the right end of the resistor R1, and the same direction input end thereof is connected with the ground signal; The left end of the inductor L1 is connected with the output end of the operational amplifier A1, and the right end thereof is connected with the reverse input end of the operational amplifier A2; The reverse input end of the operational amplifier A2 is connected with the left end of the resistor R3 at the same time, the output end thereof is connected with the right end of the resistor R3, and the same direction input end thereof is connected with the ground signal; The right end of the resistor R2 is connected with the output end of the operational amplifier A4, and the left end thereof is connected with the input end of the circuit; the right end of the resistor R4 is connected with the output end of the operational amplifier A2, and the left end thereof is connected with the input end of the circuit; The right end of the resistor R5 is connected with the output end of the operational amplifier A1, and the left end thereof is connected with the reverse input end of the operational amplifier A3; The reverse input end of the operational amplifier A3 is connected with the right end of the variable resistor R6 at the same time, the output end thereof is connected with the left end of the variable resistor R6, and the same direction input end thereof is connected with the ground signal; The right end of the resistor R7 is connected with the output end of the operational amplifier A3, and the left end thereof is connected with the reverse input end of the operational amplifier A4; The reverse input end of the operational amplifier A4 is connected with the right end of the resistor R8 at the same time, the output end thereof is connected with the left end of the resistor R8, and the same direction input end thereof is connected with the ground signal.

2. The active analog two-terminal capacitance circuit of claim 1, wherein, The analog impedance Z of the circuit input end is: Wherein, when R1=R2=R4, R1C1R3=2L1, and R7=R8, the analog impedance Z of the circuit input end is: wherein V in is the input voltage at the input of the circuit; Wherein, the active equivalent analog capacitor C simulated by the analog impedance Z of the circuit input end is:

3. A method of implementing an active analog two-terminal capacitance, characterized by, Comprise: According to the capacitance value of the user analog capacitor, the standard capacitor C1 corresponding to the capacitance value is selected; Based on the capacitance value and the standard capacitor C1, the resistance value of the variable resistor R6 in the active analog two-terminal capacitor circuit is adjusted to obtain an active equivalent analog capacitor, so that the calibration process of the target capacitance tester is carried out based on the active equivalent analog capacitor; The active analog two-terminal capacitor circuit comprises a standard capacitor C1, a variable resistor R6, an inductor L1, seven resistors R1 of different resistance values, resistors R2, R3, R4, R5, R7 and R8, and four identical operational amplifiers A1, A2, A3 and A4. The left end of the standard capacitor C1 is connected to the input end of the circuit, and the right end thereof is connected to the inverting input end of the operational amplifier A1. The inverting input end of the operational amplifier A1 is connected to the left end of the resistor R1, the output end thereof is connected to the right end of the resistor R1, and the non-inverting input end thereof is connected to a ground signal. The left end of the inductor L1 is connected to the output end of the operational amplifier A1, and the right end thereof is connected to the inverting input end of the operational amplifier A2. The inverting input end of the operational amplifier A2 is connected to the left end of the resistor R3, the output end thereof is connected to the right end of the resistor R3, and the non-inverting input end thereof is connected to a ground signal. The right end of the resistor R2 is connected to the output end of the operational amplifier A4, and the left end thereof is connected to the input end of the circuit; the right end of the resistor R4 is connected to the output end of the operational amplifier A2, and the left end thereof is connected to the input end of the circuit. The right end of the resistor R5 is connected to the output end of the operational amplifier A1, and the left end thereof is connected to the inverting input end of the operational amplifier A3. The inverting input end of the operational amplifier A3 is connected to the right end of the variable resistor R6, the output end thereof is connected to the left end of the variable resistor R6, and the non-inverting input end thereof is connected to a ground signal. The right end of the resistor R7 is connected to the output end of the operational amplifier A3, and the left end thereof is connected to the inverting input end of the operational amplifier A4. The inverting input end of the operational amplifier A4 is connected to the right end of the resistor R8, the output end thereof is connected to the left end of the resistor R8, and the non-inverting input end thereof is connected to a ground signal.

4. The implementation method of claim 3, wherein, The analog impedance Z of the input end of the circuit is: When R1=R2=R4, R1C1R3=2L1, and R7=R8, the analog impedance Z of the input end of the circuit is: V in is the input voltage of the circuit input terminal; The active equivalent analog capacitor C simulated by the analog impedance Z of the input end of the circuit is:

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