Timer circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a timer circuit, a chip and an electronic device, the timer circuit comprises a main timer and an auxiliary timer, the main timer and the auxiliary timer can both output pulse signals representing the overflow condition by overturning the output level when the count value of the timer overflows, and the overflow condition of the main timer and the overflow condition of the auxiliary timer is improved. Therefore, the situation that the auxiliary timer needs to observe the overflow condition of the auxiliary timer by means of the main timer is avoided, the time needed for observing the overflow condition of the auxiliary timer is shortened, and the correctness of the overflow observation result of the auxiliary timer is improved.

Description

Technical Field

[0001] The present application relates to the field of counting technology, and in particular to a timer circuit, a chip and an electronic device. Background Art

[0002] In a combined design with a main timer and an auxiliary timer, usually only the main timer is configured with an output pin that can output a pulse signal, while the auxiliary timer is not configured with an output pin that can output a pulse signal.

[0003] When the overflow of the auxiliary timer needs to be observed, the overflow interrupt signal output by the auxiliary timer is usually used to flip the pulse signal output by the main timer to observe the overflow of the auxiliary timer.

[0004] However, the overflow interrupt signal output by the auxiliary timer needs to be processed through a longer path, which causes delay and increases the risk of errors. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application provide a timer circuit, a chip and an electronic device to solve the above technical problems.

[0006] In a first aspect, an embodiment of the present application provides a timer circuit, which includes a main timer and an auxiliary timer. The main timer is used to flip the output level when its own count value overflows; the auxiliary timer is used to flip the output level when its own count value overflows.

[0007] In a second aspect, an embodiment of the present application further provides a chip, which includes the above-mentioned timer circuit.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned timer circuit or chip arranged in the device body.

[0009] The timer circuit, chip and electronic device provided in the embodiments of the present application enable both the main timer and the auxiliary timer to output a pulse signal representing the overflow situation by flipping the output level when their own count value overflows, thereby avoiding the need for the auxiliary timer to rely on the main timer to observe its own overflow situation, reducing the time required to observe the overflow situation of the auxiliary timer, and improving the accuracy of the overflow observation results of the auxiliary timer.

[0010] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A first principle block diagram of a timer circuit provided in an embodiment of the present application is shown.

[0013] Figure 2 A second principle block diagram of the timer circuit provided in an embodiment of the present application is shown.

[0014] Figure 3 A third principle block diagram of a timer circuit is shown.

[0015] Figure 4 A fourth principle block diagram of a timer circuit is shown.

[0016] Figure 5 A fifth principle block diagram of a timer circuit is shown.

[0017] Figure 6 A sixth principle block diagram of a timer circuit is shown.

[0018] Figure 7 A seventh principle block diagram of a timer circuit is shown.

[0019] Figure 8 A first circuit schematic diagram of a counting direction control module is shown.

[0020] Fig. 9 A second circuit schematic diagram of the counting direction control module is shown.

[0021] Fig.10 A third circuit schematic diagram of the counting direction control module is shown.

[0022] Fig.11 A fourth circuit schematic diagram of the counting direction control module is shown.

[0023] Fig.12 An eighth principle block diagram of a timer circuit is shown.

[0024] Fig.13 A ninth principle block diagram of a timer circuit is shown.

[0025] Fig.14 A tenth principle block diagram of a timer circuit is shown.

[0026] Fig.15 An eleventh principle block diagram of a timer circuit is shown.

[0027] Fig.16 A twelfth principle block diagram of a timer circuit is shown.

[0028] Fig.17 A working schematic diagram of the storage module is shown.

[0029] Fig.18 A schematic diagram showing the operation of the first timer to the third timer is shown.

[0030] Fig.19 A schematic diagram showing the operation of the fourth timer, the fifth timer and the reload capture register is shown.

[0031] Fig. 20 A first timing schematic diagram of a timer circuit is shown.

[0032] Fig.21 A second timing schematic diagram of the timer circuit is shown.

[0033] Fig. 22 An illustrative schematic diagram of an incremental encoder is shown.

[0034] Fig.23 A third timing schematic diagram of the timer circuit is shown.

[0035] Fig.24 A fourth timing schematic diagram of a timer circuit is shown.

[0036] Fig.25 A schematic diagram of the structure of a chip provided in an embodiment of the present application is shown.

[0037] Fig.26 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0038] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0039] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0040] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0041] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0042] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0043] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0044] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0045] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0046] An encoder is installed on the output shaft of the motor to obtain information such as the direction, speed and angle of the motor. At the same time, closed-loop control can be performed through the feedback signal of the encoder to achieve the effect of automatic control and feedback adjustment. The encoder is an electronic component that can convert mechanical angle signals into digital signals for transmission to achieve accurate measurement and control of position, speed and angle.

[0047] Incremental encoding mode can be implemented in the timer, combined with the characteristics of the timer to obtain dynamic information, such as speed, acceleration or deceleration, to obtain its own current position from the timer register. Among them, the time information that determines the dynamic parameters is generated by capturing the idle timer. There are two trigger sources for this capture event: capture trigger caused by sensor signal level jump and capture trigger caused by position reading operation.

[0048] Motors with encoders can achieve closed-loop control and feedback adjustment through feedback signals, making parameters such as the torque and speed output by the motor more stable. They are suitable for application scenarios that require high control accuracy and stability.

[0049] In a combined design with a main timer and an auxiliary timer, usually only the main timer is configured with an output pin that can output a pulse signal, while the auxiliary timer is not configured with an output pin that can output a pulse signal.

[0050] When the overflow of the auxiliary timer needs to be observed, the overflow interrupt signal output by the auxiliary timer is usually used to flip the pulse signal output by the main timer to observe the overflow of the auxiliary timer.

[0051] However, the overflow interrupt signal output by the auxiliary timer needs to be processed through a longer path, which causes delay and increases the risk of errors.

[0052] The embodiment of the present application provides a timer circuit 100, such as Figure 1 As shown, the timer circuit 100 includes a main timer 13 and an auxiliary timer 14. When the count value of the timer overflows, the output level is reversed, so that the main timer 13 and the auxiliary timer 14 can output a pulse signal representing the overflow situation, thereby avoiding the auxiliary timer 14 from relying on the main timer 13 to observe its own overflow situation, reducing the time required to observe the overflow situation of the auxiliary timer 14, and improving the accuracy of the overflow observation result of the auxiliary timer 14.

[0053] The present application embodiment provides a timer circuit 100. Figures 1 to 24 ,like Figure 1As shown, the timer circuit 100 includes a main timer 13 and an auxiliary timer 14. The main timer 13 is used to flip the output level when its own count value overflows; the auxiliary timer 14 is used to flip the output level when its own count value overflows.

[0054] It can be understood that the timer circuit 100 provided in the embodiment of the present application, by flipping the output level when its own count value overflows, allows the main timer 13 and the auxiliary timer 14 to output a pulse signal (PWM wave) representing the overflow situation, thereby avoiding the need for the auxiliary timer 14 to rely on the main timer 13 to observe its own overflow situation, reducing the time required to observe the overflow situation of the auxiliary timer 14, and improving the accuracy of the overflow observation result of the auxiliary timer 14.

[0055] Alternatively, if Figure 2 As shown, when the count value of one of the main timer 13 and the auxiliary timer 14 overflows, an overflow interrupt signal is output, and the overflow interrupt signal controls the other one of the main timer 13 and the auxiliary timer 14 to output a pulse signal, and the pulse signal is used to represent the overflow state.

[0056] It should be noted that one of the multiple timers 10 can be an auxiliary timer 14, and another of the multiple timers 10 can be a main timer 13. When the count value of the auxiliary timer 14 overflows, an interrupt overflow signal is output, the software detects the interrupt function, and enters the interrupt. The interrupt controls the PWM (pulse width modulation) pin output by the main timer 13 by flipping the control signal of the main timer 13. The main timer 13 outputs a pulse signal (PWM signal), and the overflow of the auxiliary timer 14 is indirectly observed through the pulse signal, i.e., the PWM wave. In this way, not only can each timer 10 output a pulse signal for observing the overflow, but the auxiliary timer 14 can also observe its own overflow with the help of the main timer 13. Both the main timer 13 and the auxiliary timer 14 can be called timer 10.

[0057] Alternatively, if Figure 3 As shown, the timer circuit 100 includes a frequency division control module 20, which is used to generate a first clock signal clk1 and a second clock signal clk2 according to an input clock signal clk_gptim, wherein the frequency of the first clock signal clk1 is greater than the frequency of the second clock signal clk2; the working mode of the timer 10 includes a timer mode, in which the count value of the timer 10 changes according to the number of edges of the second clock signal clk2.

[0058] It should be noted that, in the timer mode, counting according to the second clock signal clk2 with a lower frequency can increase the pulse width of the pulse signal. The count value of the timer 10 can change according to the number of rising edges of the second clock signal clk2, or according to the number of falling edges of the second clock signal clk2. For example, the count value can increase by 1 or decrease by 1 for each rising edge or falling edge.

[0059] The timer 10 may include a counting circuit 11 for increasing or decreasing a count value.

[0060] Alternatively, if Figure 4 As shown, the timer circuit 100 includes a frequency division control module 20, which is used to generate a first clock signal clk1 and a second clock signal clk2 according to an input clock signal clk_gptim, wherein the frequency of the first clock signal clk1 is greater than the frequency of the second clock signal clk2; the working mode of the timer 10 includes a counter mode, in which, under the control of the first clock signal clk1, the count value of the timer 10 changes according to the number of external trigger signals received.

[0061] It should be noted that, in the counter mode, the count value is increased or decreased according to the number of times the external trigger signal is received. The external trigger signal can have one or more. The external trigger signal is the external trigger source signal.

[0062] Alternatively, if Figure 5 As shown, the timer circuit 100 includes a frequency division control module 20, which is used to generate a first clock signal clk1 and a second clock signal clk2 according to an input clock signal clk_gptim, wherein the frequency of the first clock signal clk1 is greater than the frequency of the second clock signal clk2; the working mode of the timer 10 includes an incremental interface mode, in which, under the control of the first clock signal clk1, the count value of the timer 10 changes according to the number of edges and / or the number of levels of two connected external trigger signals, for frequency multiplication counting.

[0063] It should be noted that, in the incremental interface mode, the number of external trigger signals may be two, so that the count value can be increased or decreased according to the two external trigger signals, which can be applicable to more application scenarios.

[0064] Alternatively, if Figure 6 As shown, the two external trigger signals include a first channel signal A and a second channel signal B output by an incremental encoder, and the first channel signal A and the second channel signal B are orthogonally encoded.

[0065] It should be noted that the present embodiment can apply the incremental interface mode to the motor control scenario to count the output information of the encoder. In the field of motor speed measurement, the frequency multiplication counting technology can improve the resolution and measurement accuracy of the encoder. For example, by counting both the rising and falling edges of the two channels (A and B) of the encoder, the counting frequency can be increased to 4 times that of the original square wave signal, thereby achieving 4 times the frequency. This technology can expand the speed application range of the speed measurement method and improve the accuracy of low-speed measurement.

[0066] Alternatively, if Figure 7 As shown, the timer circuit 100 further includes a counting direction control module 30 , and the counting direction control module 30 is used to configure the counting direction of the timer 10 according to an external trigger signal.

[0067] It should be noted that, in this embodiment, the counting direction of the timer 10 can be determined by itself according to the external trigger signal (external trigger source signal).

[0068] Alternatively, if Figures 8 to 11 As shown, the external trigger signal includes a first external trigger signal and a second external trigger signal, and the counting direction control module 30 includes a first counting selection unit 31, a second counting selection unit 32 and a counting direction control unit 33. The first counting selection unit 31 is used to generate at least one of the first intermediate signal and the second intermediate signal according to one of the first external trigger signal and the second external trigger signal under the control of the first clock signal clk1; the second counting selection unit 32 is used to generate at least one of the third intermediate signal and the fourth intermediate signal according to the other of the first external trigger signal and the second external trigger signal under the control of the first clock signal clk1; the counting direction control unit 33 is used to generate at least one of the up counting signal up_cnt_en and the down counting signal down_cnt_en according to at least one of the first intermediate signal and the second intermediate signal and at least one of the third intermediate signal and the fourth intermediate signal.

[0069] It should be noted that the external trigger source 1 can provide a first external trigger signal, and the external trigger source 2 can provide a second external trigger signal. The input terminals of the counting direction control unit 33 are respectively connected to the output terminals of the first counting selection unit 31 and the second counting selection unit 32. The up counting signal up_cnt_en can control the count value of the timer 10 to increase in the positive direction, and the down counting signal down_cnt_en can control the count value of the timer 10 to decrease in the reverse direction.

[0070] In one embodiment, if Figure 8As shown, the first counting selection unit 31 includes a first trigger D1, a second trigger D2, a first NOT gate NOT1 and a first AND gate AND1. The input end of the first trigger D1 is connected to the first external trigger signal, and the clock end of the first trigger D1 is connected to the first clock signal clk1; the input end of the second trigger D2 is connected to the output end of the first trigger D1, and the clock end of the second trigger D2 is connected to the clock end of the first trigger D1; the input end of the first NOT gate NOT1 is connected to the output end of the second trigger D2; the first input end of the first AND gate AND1 is connected to the output end of the first NOT gate NOT1, the second input end of the first AND gate AND1 is connected to the output end of the first trigger D1, and the output end of the first AND gate AND1 outputs the first intermediate signal.

[0071] It should be noted that the first intermediate signal Figure 8 It is represented as pos_edge1. The first trigger D1 and the second trigger D2 can be but are not limited to D triggers, and can also be other applicable triggers.

[0072] Alternatively, if Figure 8 As shown, the first counting selection unit 31 also includes a second NOT gate NOT2 and a second AND gate AND2, the input end of the second NOT gate NOT2 is connected to the output end of the first trigger D1; the first input end of the second AND gate AND2 is connected to the output end of the second NOT gate NOT2, the second input end of the second AND gate AND2 is connected to the output end of the second trigger D2, and the output end of the second AND gate AND2 outputs the second intermediate signal.

[0073] It should be noted that the second intermediate signal Figure 8 The second NOT gate NOT2 inverts the output signal of the first flip-flop D1 and then performs an AND logic operation with the output signal of the second flip-flop D2 to generate a second intermediate signal.

[0074] Alternatively, if Figure 8 As shown, the second counting selection unit 32 includes a third trigger D3 and a third NOT gate NOT3, the input end of the third trigger D3 is connected to the second external trigger signal, and the clock end of the third trigger D3 is connected to the first clock signal clk1; the output end of the third trigger D3 outputs a third intermediate signal; the input end of the third NOT gate NOT3 is connected to the output end of the third trigger D3, and the output end of the third NOT gate NOT3 outputs a fourth intermediate signal.

[0075] It should be noted that the second external trigger signal is generated as a third intermediate signal after passing through the third trigger D3 , and the third NOT gate NOT3 inverts the third intermediate signal to generate a fourth intermediate signal.

[0076] Alternatively, if Figure 8As shown, the second counting selection unit 32 also includes a fourth trigger D4, a fourth NOT gate NOT4 and a third AND gate AND3, the input end of the fourth trigger D4 is connected to the output end of the third trigger D3, and the clock end of the fourth trigger D4 is connected to the clock end of the third trigger D3; the input end of the fourth NOT gate NOT4 is connected to the output end of the fourth trigger D4; the first input end of the third AND gate AND3 is connected to the output end of the fourth NOT gate NOT4, the second input end of the third AND gate AND3 is connected to the output end of the third trigger D3, and the output end of the third AND gate AND3 outputs pos_edge2.

[0077] It should be noted that the output signal of the third flip-flop D3 is processed by the fourth flip-flop D4 and the fourth NOT gate NOT4 in sequence, and then performs an AND logic operation with the output signal of the third flip-flop D3 to generate pos_edge2.

[0078] Alternatively, if Figure 8 As shown, the second counting selection unit 32 also includes a fifth NOT gate NOT5 and a fourth AND gate AND4, the input end of the fifth NOT gate NOT5 is connected to the output end of the third trigger D3; the first input end of the fourth AND gate AND4 is connected to the output end of the fifth NOT gate NOT5, the second input end of the fourth AND gate AND4 is connected to the output end of the fourth trigger D4, and the output end of the fourth AND gate AND4 outputs neg_edge2.

[0079] It should be noted that, after the fifth NOT gate NOT5 inverts the output signal of the third flip-flop D3 , it performs an AND logic operation with the output signal of the fourth flip-flop D4 to generate neg_edge2 .

[0080] Alternatively, if Figure 8 As shown, the counting direction control unit 33 includes a fifth AND gate AND5 and a first selector MUX1, the first input end of the fifth AND gate AND5 is connected to pos_edge1, and the second input end of the fifth AND gate AND5 is connected to the fourth intermediate signal; the control end of the first selector MUX1 is connected to the output end of the fifth AND gate AND5, the first input end of the first selector MUX1 is connected to the first constant, the second input end of the first selector MUX1 is connected to the second constant, and the output end of the first selector MUX1 outputs an upward counting signal up_cnt_en.

[0081] It should be noted that the first constant can be 0 represented by 1 bit binary, and the second constant can be 1 represented by 1 bit binary. When the output level of the fifth AND gate AND5 is low level (0), the first selector MUX1 selects to output the first constant as the low level of the up-counting signal up_cnt_en; when the output level of the fifth AND gate AND5 is high level (1), the first selector MUX1 selects to output the second constant as the high level of the up-counting signal up_cnt_en.

[0082] Alternatively, if Figure 8 As shown, the counting direction control unit 33 also includes a sixth AND gate AND6 and a second selector MUX2, the first input end of the sixth AND gate AND6 is connected to pos_edge1, and the second input end of the sixth AND gate AND6 is connected to the third intermediate signal; the control end of the second selector MUX2 is connected to the output end of the sixth AND gate AND6, the first input end of the second selector MUX2 is connected to the first constant, the second input end of the second selector MUX2 is connected to the second constant, and the output end of the second selector MUX2 outputs a down counting signal down_cnt_en.

[0083] It should be noted that when the output level of the sixth AND gate AND6 is a low level (0), the second selector MUX2 selects to output the first constant as the low level of the down counting signal down_cnt_en; when the output level of the sixth AND gate AND6 is a high level (1), the second selector MUX2 selects to output the second constant as the high level of the down counting signal down_cnt_en.

[0084] Figure 8 Counting is performed with the rising edge of external trigger source 1, and according to the high and low levels of external trigger source 2, the corresponding up-counting signal up_cnt_en and / or down-counting signal down_cnt_en are output.

[0085] Fig. 9 The second circuit schematic diagram of the counting direction control module is shown in FIG. Figure 8 The difference is that the fifth and sixth AND gates AND5 and AND6 are connected to neg_edge1 instead of pos_edge1. The first selector MUX1 outputs a down counting signal down_cnt_en. The second selector MUX2 outputs an up counting signal up_cnt_en. Fig. 9 Count with the falling edge of external trigger source 1. When external trigger source 2 is at a high level, count up. When external trigger source 2 is at a low level, count down.

[0086] Fig.10 The third circuit schematic diagram of the counting direction control module is shown. Figure 8The difference is that the input terminal of the first trigger D1 is connected to the second external trigger signal, and the input terminal of the third trigger D3 is connected to the first external trigger signal. The fifth AND gate AND5 and the sixth AND gate AND6 are connected to neg_edge1 instead of pos_edge1. Fig.10 Count with the falling edge of external trigger source 2. When external trigger source 1 is at a high level, count down; when external trigger source 1 is at a low level, count up.

[0087] Fig.11 The fourth circuit schematic diagram of the counting direction control module is shown. Fig.10 The difference is that the fifth AND gate AND5 and the sixth AND gate AND6 are connected to pos_edge1 instead of neg_edge1. Fig.11 Counting is performed with the rising edge of external trigger source 2. When external trigger source 1 is at a high level, counting is performed upwards; when external trigger source 1 is at a low level, counting is performed downwards.

[0088] Alternatively, if Fig.12 As shown, multiple timers 10 include a first timer Timer T1, a second timer Timer T2 and a third timer Timer T3. The first timer Timer T1 counts the external trigger signal connected according to the configuration data of the timer 10 to output an overflow interrupt signal, a count overflow signal and a pulse signal; the second timer Timer T2 counts the external trigger signal connected according to the configuration data of the timer 10 to output an overflow interrupt signal, a count overflow signal and a pulse signal; the third timer Timer T3 counts the external trigger signal connected according to the configuration data of the timer 10 to output an overflow interrupt signal, a count overflow signal and a pulse signal; wherein, any two timers 10 among the first timer Timer T1, the second timer Timer T2 and the third timer Timer T3 capture and / or reload the count value; each of the first timer Timer T1, the second timer Timer T2 and the third timer Timer T3 outputs a pulse signal according to the count overflow signal.

[0089] It should be noted that the external trigger signal can be exemplarily represented as at least one of T1_IN1, T1_IN2, T2_IN1, T2_IN2, T3_IN1 and T3_IN2, and the interrupt routing (IR) can output the external trigger signal. The count overflow signal can be exemplarily represented as at least one of t1ovr, t2ovr and t3ovr. The overflow interrupt signal can be exemplarily represented as at least one of IR1, IR2 and IR3, and the overflow interrupt signal can be output to the interrupt routing (IR). The pulse signal can be exemplarily represented as t1OUT, t2OUT and t3OUT, and the external input / output (I / O) can be used to transmit the pulse signal or the external trigger signal.

[0090] It is understandable that the coordinated use of multiple timers 10 can achieve count spread spectrum, thereby meeting the requirement of a larger count cycle.

[0091] Alternatively, if Fig.13 As shown, the timer circuit 100 also includes a reload capture register RE_CA_reg, and the multiple timers 10 also include a fourth timer Timer T4 and a fifth timer Timer T5. The fourth timer Timer T4 counts the connected external trigger signal and / or count overflow signal according to the configuration data of the timer 10 to output an overflow interrupt signal, a count overflow signal and a pulse signal; the fifth timer Timer T5 counts the connected external trigger signal according to the configuration data of the timer 10 to output an overflow interrupt signal, a count overflow signal and a pulse signal; wherein the reload capture register RE_CA_reg is connected between the fourth timer Timer T4 and the fifth timer Timer T5, the reload capture register RE_CA_reg is used to capture the count value of the fourth timer Timer T4, and the fifth timer Timer T5 is used to reload the value of the reload capture register RE_CA_reg.

[0092] It should be noted that the external trigger signal can be exemplarily represented as at least one of T4_IN1, T4_IN2, T5_IN1 and T5_IN2, and the interrupt routing (IR) can output the external trigger signal. The count overflow signal can be exemplarily represented as at least one of t4ovr and t5ovr. The overflow interrupt signal can be exemplarily represented as at least one of IR4 and IR5, and the overflow interrupt signal can be output to the interrupt routing (IR). The pulse signal can be exemplarily represented as t4OUT and t5OUT.

[0093] In this embodiment, the count value of the fourth timer Timer T4 can be captured by the reload capture register RE_CA_reg, and the count value of the fifth timer Timer T5 can be reloaded (reloaded). Thus, one of the timers 10 is replaced by the reload capture register RE_CA_reg, which can simplify the combination design and configuration of the timer 10.

[0094] Alternatively, if Fig.14 As shown, the timer circuit 100 further includes a storage module 40, and the storage module 40 is used to store the frequency division coefficient, the timer 10 configuration data and the reset configuration data.

[0095] It should be noted that the frequency division coefficient is used in the timer 10. By setting the frequency division coefficient, the clock frequency of the timer 10 can be controlled. The timer 10 configuration data includes the prescaler settings, counting mode, automatic reload value, etc. of the timer 10. These configuration data determine the working mode and behavior of the timer 10. The reset configuration data is used to control the reset behavior of the system.

[0096] Alternatively, if Fig.15 As shown, the storage module 40 includes a clock configuration register group 41, a timer configuration register group 42 and a reset configuration register group 43. The clock configuration register group 41 is used to store a division coefficient to divide the input clock signal clk_gptim; the timer configuration register group 42 is used to store timer 10 configuration data to configure at least one of the working mode, counting direction and initial value of the timer 10; the reset configuration register group 43 is used to store reset configuration data to control the reset of the timer circuit 100 according to the AND logic operation result of multiple signals in the reset configuration data.

[0097] It should be noted that the AND logic operation result of the multiple signals in the reset configuration data, such as at least two of rgf_MRSTCLR, rgf_MRST1 and rgf_MRST0, can be represented by rst_gptim_n. The bus is represented by bus.

[0098] Fig.16 A twelfth principle block diagram of the timer circuit 100 is shown. Fig.17 FIG. 4 shows a schematic diagram of the operation of the storage module 40. Fig.16 , Fig.17As shown, sys_rst_n is used to represent the system reset signal, which can control the reset of the frequency division control module 20, the storage module 40, each timer 10 and the reload capture register RE_CA_reg. dbg_rst_n is used to represent the test reset signal, which can control at least part of the timer circuit 100 to reset in response to a trigger event. api_rst_n is used to represent the dedicated reset signal, which can control at least part of the timer 10 to reset.

[0099] Wherein, clk_gptim can also be used to control the opening or closing of the clock configuration register group 41, and the reset of the clock configuration register group 41 is not affected by api_rst_n. The first clock signal clk1 and the second clock signal clk2 are affected by api_rst_n.

[0100] The clock configuration register group 41 and the reset configuration register group 43 can both transmit relevant data to the timer configuration register group 42 when needed. The timer configuration register group 42 can determine the working configuration of the timer 10 by means of the generated frequency division configuration.

[0101] Fig.18 The working diagram of the first timer Timer T1 to the third timer Timer T3 is shown. At least two of the first timer Timer T1, the second timer Timer T2 and the third timer Timer T3 can constitute a first group of timer 10 units, and data can be captured and reloaded between any two timers 10.

[0102] Among them, each of the first timer Timer T1, the second timer Timer T2 and the third timer Timer T3 can select the external trigger source edge trigger (upper and lower edges) according to the register configuration, and perform corresponding capture or reload. The timers 10 can be cascaded through the overflow signal according to the configuration. When the conditions are met, the first timer Timer T1, the second timer Timer T2 and the third timer Timer T3 will be triggered to count, and when the count overflows, a PWM wave is generated.

[0103] Fig.19The working diagram of the fourth timer Timer T4, the fifth timer Timer T5 and the reload capture register RE_CA_reg is shown. The fourth timer Timer T4, the fifth timer Timer T5 and the reload capture register RE_CA_reg can constitute the second group of timer 10 units. Compared with the first group of timer 10 units, the design and configuration of the second group of timer 10 units are simpler. The difference is that the capture and reload functions can only exist in one direction, that is, the reload capture register RE_CA_reg captures the value of the fourth timer Timer T4, and the fifth timer Timer T5 can load the value of the reload capture register RE_CA_reg. At this time, the reload capture register RE_CA_reg is only used as a register. The purpose of doing this is to simplify the first group of timer 10 combination units, thereby avoiding complex design and configuration.

[0104] Among them, the fourth timer Timer T4 can select the external trigger source edge trigger (upper and lower edges) according to the register configuration, and perform corresponding capture. The fifth timer Timer T5 can select the external trigger source edge trigger (upper and lower edges) according to the register configuration, and perform corresponding reload. Timers 10 can be cascaded through overflow signals according to the configuration. When the conditions are met, the fourth timer Timer T4 and the fifth timer Timer T5 will be triggered to count, and when the count overflows, a PWM wave is generated.

[0105] Fig. 20 FIG. 1 shows a first timing diagram of the timer circuit 100. The initial value of the timer 10 is configurable, and the maximum count is described by taking 65535 as an example. Fig. 20 Shown is the timing diagram in timer mode.

[0106] The first-level frequency division indicates that the input clock signal clk_gptim is divided to generate the first clock signal clk1 (in the basic clock domain). The timer 10 count indicates that the first-level frequency division counts once for each rising edge. When the count value reaches 65535, the level of the pulse signal (PWM) output by the timer 10 is reversed.

[0107] The two-level frequency division indicates that the second clock signal clk2 is generated by dividing the input clock signal clk_gptim. The two-level frequency division of timer 10 indicates that the two-level frequency division counts once every rising edge. When the count value reaches 65535, the level of the pulse signal (PWM two-level frequency division) output by timer 10 is reversed.

[0108] It can be seen that since the frequency of the clock signal corresponding to the second-level frequency division is smaller than the frequency of the clock signal corresponding to the first-level frequency division, the pulse width corresponding to the PWM second-level frequency division will be larger than the pulse width corresponding to the PWM.

[0109] Fig.21 A second timing diagram of the timer circuit 100 is shown. Fig.21 The timing diagram in the counter mode is shown. According to the external trigger signal provided by the external trigger source, each timer 10 is connected to two external trigger signals (IN1, IN2), so that a single or multiple external trigger signals can be used in conjunction, and each external trigger signal is counted in the basic clock domain (first-level frequency division) (exemplarily adding 1 until overflow, and then restarting counting). The external trigger signal can represent the external trigger event. After the initial value of the timer 10 is set, the output PWM wave can be obtained by comprehensive judgment based on the trigger event of the external input.

[0110] Fig. 22 The following is a schematic diagram of an incremental encoder. The detector is used to read the optical grooves or marks on the encoder disk, usually through the photoelectric effect. When the encoder disk rotates, the light source shines on the optical grooves on the disk, and the detector can sense the interruption of light, thereby generating A and B signals.

[0111] The A and B signals are encoded in quadrature, meaning they are 90 degrees out of phase. This encoding allows the system to distinguish between clockwise and counterclockwise rotation and more accurately calculate position changes.

[0112] Each time the encoder disk rotates past a specific mark or slot, the detector generates a pulse. These pulses can be used to count the position of the rotation, thereby tracking position or speed.

[0113] Detectors are usually designed to detect the edges of the light slot as it passes by, which ensures accurate pulse generation even at high rotation speeds.

[0114] In addition to the A and B signals, some incremental encoders have an additional detector for reading the Z signal. The Z signal is often used to indicate that a full rotation cycle has been completed, or to mark a specific reference position.

[0115] When the encoder moves at a constant speed, each pulse has a 50% duty cycle. An index mark may be used to indicate a specific reference position.

[0116] Incremental encoders report position changes through changes in the A and B signals. Due to their high response speed, incremental encoders are often used in high-speed motion applications that require real-time monitoring and control.

[0117] Incremental encoders can report position changes almost instantly, making them suitable for motion control systems that require fast feedback.

[0118] Fig.23 The third timing diagram of the timer circuit 100 is shown. Each timer 10 has a PWM wave output function (such as the PWM output of Timer T1 and the PWM output of Timer T2), and when a count overflows (for example, the count value reaches 65535) of a timer 10 (such as Timer T1) under the first-level frequency division, the level of the PWM output of Timer T1 is reversed.

[0119] Multiple timers 10 can also be combined to output PWM waves, such as the use of two timers 10 (for example, a combination of Timer T1 and Timer T2). When a timer 10 is configured in timer mode, when the count overflows, the count overflow signal can be fed back to other timers 10. Other timers 10 count once according to the trigger signal to trigger multiple timers 10 or a single timer 10 to count. In this way, two timers 10 can be combined to achieve count spread spectrum. For example, a 32-bit timer 10 can achieve a 64-bit count width by connecting two of them, thereby meeting the requirements of a larger count cycle.

[0120] Among them, under the counting clock of Timer T2, the two-level frequency division of Timer T2 counts and adds 1 every time Timer T1 overflows, so that the PWM output of Timer T2 realizes count spread spectrum.

[0121] Fig.24 The fourth timing diagram of the timer circuit 100 is shown. Multiple timers 10 are used in cooperation with each other. Through reasonable configuration of registers, such as capturing or reloading the value in the timer 10, the first timer 10 is set to the basic three modes (timer mode, counter mode and incremental interface mode), and the other timers 10 are set to the capture mode. Whether the first timer 10 is triggered by external count or internal clock frequency, the timer 10 will count changes. The value in the first timer 10 can be captured by another timer 10, so that the purpose of storing the value of the timer 10 can be achieved. The capture trigger signal can be an external input trigger signal or an overflow signal of the first timer 10. According to the configuration of the software, different combinations of functions and scene requirements can be realized. At the same time, the principle of reloading is the same. The values ​​in other timers 10 can be reloaded into the first timer 10 to realize the counting of timer 10 between timers 10, which can meet the counting of multiple events at the same time.

[0122] Among them, under the first-level frequency division, the count value of Timer T4 increases by 1 for each rising edge until the overflow, and the PWM output of Timer T4 flips the level. Under the counting clock of Timer T5, the count value of Timer T5 increases by 1 for each rising edge until the overflow, and the PWM output of Timer T5 flips the level. Each level of the external reload trigger source triggers the reload between Timer T4 and Timer T5 through the reload capture register RE_CA_reg, for example, the count value in Timer T4 (exemplarily 20) is reloaded as the count value of Timer T5, the count value 4000 in Timer T4 is reloaded as the count value of Timer T5, and the count value in Timer T4 (exemplarily 65500) is reloaded as the count value of Timer T5.

[0123] In summary, multiple timers 10 can be used in combination to generate PWM wave output, which can meet various application scenarios. Each timer 10 has an independent PWM wave output pin and can be used alone. The problem of a long path and the need for a certain timer 10 to work can be observed independently without the need to rely on other timers 10. At the same time, two combination units are added to achieve different ways of reloading and capturing, and a clock reset control module is added to control the clock and reset count of the timer 10, which can effectively control the operation of the timer 10.

[0124] The present application embodiment also provides a chip 200, such as Fig.25 As shown, the chip 200 includes the above-mentioned timer circuit 100. The chip 200 is also called an integrated circuit (IC), and the chip 200 can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip.

[0125] It can be understood that since the chip 200 provided in the embodiment of the present application includes the above-mentioned timer circuit 100, it can also reverse the output level when its own count value overflows, so that the main timer 13 and the auxiliary timer 14 can both output a pulse signal representing the overflow situation, thereby avoiding the need for the auxiliary timer 14 to rely on the main timer 13 to observe its own overflow situation, reducing the time required to observe the overflow situation of the auxiliary timer 14, and improving the accuracy of the overflow observation result of the auxiliary timer 14.

[0126] The present application embodiment also provides an electronic device 300, such as Fig.26As shown, the electronic device 300 includes a device body and the above-mentioned chip 200 or timer circuit 100 provided in the device body. The electronic device 300 may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0127] It can be understood that since the electronic device 300 provided in the embodiment of the present application includes the above-mentioned timer circuit 100 or chip 200, it can also reverse the output level when its own count value overflows, so that the main timer 13 and the auxiliary timer 14 can both output a pulse signal representing the overflow situation, thereby avoiding the need for the auxiliary timer 14 to rely on the main timer 13 to observe its own overflow situation, reducing the time required to observe the overflow situation of the auxiliary timer 14, and improving the correctness of the overflow observation result of the auxiliary timer 14.

[0128] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as a preferred embodiment as above, it is not intended to limit the present application. Any technical personnel in this field can use the technical contents disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes without departing from the scope of the technical solution of the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A timer circuit, characterized in that: The timer circuit comprises: A master timer, wherein the master timer is used to flip the output level when its count value overflows; The auxiliary timer is used to flip the output level when the count value of the auxiliary timer overflows.

2. The timer circuit according to claim 1, characterized in that When the count value of one of the main timer and the auxiliary timer overflows, an overflow interrupt signal is output, and the overflow interrupt signal controls the other one of the main timer and the auxiliary timer to output a pulse signal, and the pulse signal is used to indicate the overflow state.

3. The timer circuit according to claim 1, wherein: The timer circuit comprises a frequency division control module, the frequency division control module is used to generate a first clock signal and a second clock signal according to an input clock signal, the frequency of the first clock signal is greater than the frequency of the second clock signal; The operation mode of the timer includes a timer mode, in which a count value of the timer changes according to the number of edges of the second clock signal.

4. The timer circuit according to claim 1, wherein: The timer circuit comprises a frequency division control module, the frequency division control module is used to generate a first clock signal and a second clock signal according to an input clock signal, the frequency of the first clock signal is greater than the frequency of the second clock signal; The working mode of the timer includes a counter mode. In the counter mode, under the control of the first clock signal, the count value of the timer changes according to the number of times the external trigger signal is received.

5. The timer circuit according to claim 1, wherein: The timer circuit comprises a frequency division control module, the frequency division control module is used to generate a first clock signal and a second clock signal according to an input clock signal, the frequency of the first clock signal is greater than the frequency of the second clock signal; The working mode of the timer includes an incremental interface mode. In the incremental interface mode, under the control of the first clock signal, the count value of the timer changes according to the number of edges and / or the number of levels of two connected external trigger signals for frequency multiplication counting.

6. The timer circuit according to claim 5, characterized in that: The two external trigger signals include a first channel signal and a second channel signal output by an incremental encoder, and the first channel signal and the second channel signal are orthogonally encoded.

7. The timer circuit according to any one of claims 3 to 5, characterized in that: The timer circuit further comprises a counting direction control module, and the counting direction control module is used to configure the counting direction of the timer according to the external trigger signal.

8. The timer circuit according to claim 7, characterized in that: The external trigger signal includes a first external trigger signal and a second external trigger signal, and the counting direction control module includes: a first counting selection unit, configured to generate at least one of a first intermediate signal and a second intermediate signal according to one of the first external trigger signal and the second external trigger signal under the control of the first clock signal; a second counting selection unit, the second counting selection unit being configured to generate at least one of a third intermediate signal and a fourth intermediate signal according to the other of the first external trigger signal and the second external trigger signal under the control of the first clock signal; A counting direction control unit is used to generate at least one of an up-counting signal and a down-counting signal according to at least one of the first intermediate signal and the second intermediate signal and at least one of the third intermediate signal and the fourth intermediate signal.

9. The timer circuit according to claim 1, wherein: The timer circuit further comprises a storage module, and the storage module is used to store a frequency division coefficient, timer configuration data and reset configuration data.

10. The timer circuit according to claim 9, characterized in that The storage module comprises: A clock configuration register group, the clock configuration register group is used to store the frequency division coefficient to divide the input clock signal; A timer configuration register group, the timer configuration register group is used to store timer configuration data to configure at least one of the working mode, counting direction and initial value of the timer; A reset configuration register group is used to store the reset configuration data to control the reset of the timer circuit according to the AND logic operation result of multiple signals in the reset configuration data.

11. A chip, characterized in that: The chip comprises the timer circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device comprises a device body and the chip according to claim 11 disposed in the device body.

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