Phase-locked loop rapid frequency automatic calibration system

Abstract

The invention discloses a phase-locked loop rapid frequency automatic calibration system, which relates to the technical field of digital circuits and comprises an input signal selector, a voltage-controlled oscillator, an eight-frequency-division eight-phase circuit and an automatic frequency calibration circuit. According to the invention, the eight-frequency-division eight-phase output clock is used as the VCO output calibration clock, so that the AFC calibration time can be shortened to 1 / 7 of the traditional AFC time under the same calibration precision under the condition that a low-speed clock meeting the constraint condition of a digital circuit is used.

Description

Technical Field

[0001] The invention relates to the technical field of digital circuits, and in particular to a phase-locked loop fast frequency automatic calibration system. Background Art

[0002] A phase-locked loop (PLL) is a circuit widely used in modern electronic systems. It locks the phase and frequency of a voltage-controlled oscillator (VCO) to a reference signal through a closed-loop control system. The automatic frequency calibration (AFC) technology of the phase-locked loop is one of the key technologies to ensure that the phase-locked loop quickly locks to the target frequency.

[0003] Some application scenarios have strict requirements on the AFC time. For example, a long AFC time of the phase-locked loop in a low-power system will seriously increase the system wake-up working time. The long wake-up working time seriously increases the power consumption and reduces the battery life of portable electronic devices. In addition, some radio frequency communications use time division multiplexing, and the phase-locked loop frequently switches channels. If the AFC time of the phase-locked loop is too long, it will not meet the channel switching time required by the protocol, causing communication interruption of the communication equipment.

[0004] In high-performance phase-locked loop (PLL) applications, inductor-capacitor VCO is usually used. In order to ensure that the VCO frequency adjustment range is wide and the gain is small, multi-bit sub-band control is usually used, and each sub-band interval is relatively narrow, which puts higher requirements on the accuracy and time of AFC. In order to meet the AFC calibration frequency error less than 1 / 2 of the sub-band frequency interval, more stringent requirements are put forward for the calibration accuracy of AFC. Ways to improve AFC accuracy include increasing the counting cycle of the reference frequency or using a high-frequency VCO clock. However, increasing the counting cycle of the reference frequency will increase the AFC time, and using a high-frequency VCO clock will increase the difficulty of the digital circuit clock constraint of the calibration algorithm. Summary of the invention

[0005] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a phase-locked loop fast frequency automatic calibration system, which uses the eight-divided eight-phase output clock as the VCO output calibration clock, and can shorten the AFC calibration time to 1 / 7 of the traditional AFC time under the same calibration accuracy while using a low-speed clock that meets the constraints of the digital circuit.

[0006] One aspect of the present invention provides a phase-locked loop fast frequency automatic calibration system, comprising: Input signal selector, voltage controlled oscillator, divide-by-eight eight-phase circuit and automatic frequency calibration circuit; The eight-frequency-divider eight-phase circuit is used to receive the positive output signal and the negative output signal of the voltage-controlled oscillator, and convert the positive output signal and the negative output signal into eight clock signals with a phase difference of 45 degrees, and then output them to the automatic frequency calibration circuit; The automatic frequency calibration circuit is used to count the input reference clock signal, and to group and count and sum the eight input clock signals with a phase difference of 45 degrees, and to adjust the output of the optimal sub-band control signal to the voltage-controlled oscillator by comparing the summation result of the eight clock signals with a phase difference of 45 degrees with the counting result of the reference clock signal, and to send a phase-locked loop opening and closing control signal to the input signal selector after the frequency calibration is completed; The input signal selector is used to use one of the voltage-controlled oscillator fixed control voltage signal and the phase-locked loop closed-loop control voltage signal as the input control signal of the voltage-controlled oscillator according to the phase-locked loop opening and closing control signal.

[0007] Furthermore, the eight-frequency-divide-eight-phase circuit includes a cascaded four-frequency-divide-circuit and a two-frequency-divide-eight-phase clock generator.

[0008] Furthermore, the four-frequency divider circuit includes two cascaded two-frequency divider circuits.

[0009] Furthermore, the automatic frequency calibration circuit includes a reference clock signal counting circuit, a feedback calibration clock counting circuit, an adder and a state machine circuit.

[0010] Further, the reference clock signal counting circuit includes a first AND gate logic circuit and a first counter; The first input end of the first AND gate logic circuit is connected to the activation signal output end of the state machine circuit, the second input end of the first AND gate logic circuit is used to receive the input reference clock signal, and the output end of the first AND gate logic circuit is connected to the first input end of the first counter; The second input terminal of the first counter is used to receive an input counting control signal, the third input terminal of the first counter is connected to the reset signal output terminal of the state machine circuit, and the output terminal of the first counter is connected to the counting overflow signal input terminal of the state machine circuit.

[0011] Further, the feedback calibration clock counting circuit includes eight AND gate logic circuits, eight OR gate logic circuits and eight second counters; Among them, the first input ends of the eight AND gate logic circuits are used to respectively receive the eight clock signals with a phase difference of 45 degrees, the second input ends of the eight AND gate logic circuits are respectively connected to the activation signal output end of the state machine circuit, the output ends of the eight AND gate logic circuits are respectively connected to the first input ends of the eight OR gate logic circuits, the second input ends of the eight OR gate logic circuits are respectively connected to the output ends of the first counters, the output ends of the eight OR gate logic circuits are respectively connected to the first input ends of eight second counters, the second input ends of the eight second counters are connected to the clear signal output end of the state machine circuit, and the output ends of the eight second counters are connected to the input ends of the adder.

[0012] Furthermore, the adder is used to sum the output count values ​​of the eight second counters and output the summation result to the state machine circuit.

[0013] Furthermore, the state machine circuit is used for: The difference between the summed result of the adder input and the voltage-controlled oscillator count target value is calculated by a data comparator, and the size of the summed result of the adder input and the voltage-controlled oscillator count target value is determined according to the difference; If the sum of the adder inputs is less than the voltage-controlled oscillator count target value, the binary code of the sub-band control signal is increased; if the sum of the adder inputs is greater than the voltage-controlled oscillator count target value, the binary code of the sub-band control signal is decreased; The adjusted sub-band control signal is output to the voltage controlled oscillator.

[0014] Furthermore, the state machine circuit is also used to determine whether the difference between the summation result of the adder input and the voltage-controlled oscillator count target value is less than a preset threshold value. If it is less than the preset threshold value, a prompt signal indicating that the frequency calibration is successful is output; if it is greater than the preset threshold value, a prompt signal indicating that the frequency calibration has failed is output.

[0015] Furthermore, the state machine circuit is also used to output a reset signal to the first counter and the second counter, and output a phase-locked loop on / off control signal to the input signal selector after the frequency calibration is completed.

[0016] The present invention provides a phase-locked loop fast frequency automatic calibration system, which generates an eight-phase low-frequency clock by dividing the VCO output clock by eight, then counts the groups, and then adds the counting results, thereby achieving the effect of AFC counting the low-frequency clock but not increasing the number of counts, and greatly shortening the calibration time while ensuring the calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 The system circuit principle of the phase-locked loop fast frequency automatic calibration system provided by an embodiment of the present application is Figure 1 ; Figure 2 The system circuit principle of the phase-locked loop fast frequency automatic calibration system provided by an embodiment of the present application is Figure 2 . DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0020] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0021] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0022] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0023] In order to solve the defects of traditional phase-locked loop AFC, such as long calibration time, low precision, and constraints of high-frequency clock on the digital circuit clock of the calibration algorithm, the present invention realizes a solution of using eight-divided eight-phase output clock as VCO output calibration clock. When using a low-speed clock that meets the constraints of the digital circuit, the AFC calibration time can be shortened to 1 / 7 of the traditional AFC calibration time under the same calibration accuracy.

[0024] In order to facilitate understanding of the embodiments of the present application, technical terms that frequently appear in the present application are explained below.

[0025] (1) AFC (Auto Frequency Control) Automatic Frequency Control / Automatic Frequency Calibration. AFC outputs the sub-band control signal of the VCO (Voltage Controlled Oscillator). For example, in the GSM mobile phone circuit, the main function of AFC is to keep the mobile phone clock synchronized with the system clock. When the mobile phone detects that the clock is out of sync, AFC will adjust the control voltage of the oscillation circuit, thereby changing the output frequency of the VCO to ensure that the mobile phone is synchronized with the system.

[0026] (2) VCO (voltage-controlled oscillator) Voltage-controlled oscillator. Refers to an oscillation circuit in which the output frequency corresponds to the input control voltage. The working state of the oscillator or the component parameters of the oscillation circuit are controlled by the input control voltage, which can constitute a voltage-controlled oscillator.

[0027] The basic principle of multi-bit sub-band control of VCO is to divide the frequency into multiple sub-bands, each sub-band corresponds to a specific frequency range, and by using multi-bit digital signals, such as binary coding, different sub-bands can be accurately selected to control the output frequency of the VCO. Multi-bit sub-band control can improve the resolution and accuracy of frequency control and is suitable for application scenarios that require high-precision frequency synthesis.

[0028] See also Figure 1 In one embodiment of the present application, a phase-locked loop fast frequency automatic calibration system includes an input signal selector 101, a voltage-controlled oscillator 102, an eight-divide-by-eight eight-phase circuit 103 and an automatic frequency calibration circuit 104.

[0029] Further, the eight-frequency-divide-by-eight-phase circuit 103 is used to receive the positive output signal VOC_P and the negative output signal VOC_N of the voltage-controlled oscillator 102, and convert the positive output signal VOC_P and the negative output signal VOC_N into eight clock signals CK0, CK45, CK90, CK135, CK180, CK225, CK270, and CK315 with a phase difference of 45 degrees, and then output them to the automatic frequency calibration circuit 104. Exemplarily, the eight-frequency-divide-by-eight-phase circuit 103 may include a cascaded four-frequency-divide-by-four circuit DIV4 and a two-frequency-divide-by-two eight-phase clock generator 8 phase clock generator DIV2, wherein the four-frequency-divide-by-four circuit DIV4 includes two cascaded two-frequency-divide-by-two circuits DIV2.

[0030] Furthermore, the automatic frequency calibration circuit 104 is used to count the input reference clock signal Ref_ck, and to group count and sum the eight input clock signals CK0, CK45, CK90, CK135, CK180, CK225, CK270, and CK315 with a phase difference of 45 degrees, and to adjust the output of the optimal sub-band control signal VCO_band<7:0> to the voltage-controlled oscillator 102 by comparing the sum result of the eight clock signals with a phase difference of 45 degrees with the counting result of the reference clock signal Ref_ck, and to send the phase-locked loop opening and closing control signal switch_ pll_open / closed_loop to the input signal selector 101 after the frequency calibration is completed.

[0031] Further, the input signal selector 101 uses one of the voltage controlled oscillator fixed control voltage signal Fix_vc and the phase-locked loop closed-loop control voltage signal closed_loop_vc as the input control signal of the voltage controlled oscillator 102 according to the phase-locked loop opening and closing control signal switch_pll_open / closed_loop.

[0032] See also Figure 2 The automatic frequency calibration circuit 104 includes a reference clock signal counting circuit 1041 , a feedback calibration clock counting circuit 1042 , an adder 1043 and a state machine circuit 1044 .

[0033] Specifically, the reference clock signal counting circuit 1041 includes a first AND gate logic circuit ADN and a first counter counter_A, the first input end of the first AND gate logic circuit ADN is connected to the activation signal output end active of the state machine circuit 1044, the second input end of the first AND gate logic circuit ADN is used to receive the input reference clock signal Ref_ck, the output end of the first AND gate logic circuit ADN is connected to the first input end of the first counter counter_A, the second input end of the first counter counter_A is used to receive the input counting control signal count_num_ctrl<3:0>, the third input end of the first counter counter_A is connected to the clear signal output end clear of the state machine circuit 1044, and the output end of the first counter counter_A is connected to the counting overflow signal input end cal_stop of the state machine circuit 1044.

[0034] Specifically, the feedback calibration clock counting circuit 1042 includes eight AND gate logic circuits 8X ADN, eight OR gate logic circuits 8X OR, and eight second counters 8X counter_B. The first input ends of the eight AND gate logic circuits 8X ADN are used to respectively receive eight clock signals CK0, CK45, CK90, CK135, CK180, CK225, CK270, and CK315 with a phase difference of 45 degrees. The second input ends of the eight AND gate logic circuits 8X ADN are respectively connected to the activation signal output end active of the state machine circuit 1044. The output ends of the eight AND gate logic circuits 8X ADN are respectively connected to the first input ends of the eight OR gate logic circuits 8X OR. The second input ends of the eight OR gate logic circuits 8X OR are respectively connected to the output ends of the first counters counter_A. The output ends of the eight OR gate logic circuits 8X OR are respectively connected to the first input ends of the eight second counters 8Xcounter_B. The second input ends of the eight second counters 8X counter_B are connected to the clear signal output end clear of the state machine circuit 1044. The output ends of the eight second counters 8X counter_B are connected to the input end of the adder 1043. The adder 1043 is used to add the eight second counters 8X The output count values ​​of counter_B are summed, and the sum result CSUM<13:0> is output to the state machine circuit 1044 .

[0035] Specifically, the state machine circuit 1044 is used to calculate the difference between the summation result CSUM<13:0> input by the adder 1043 and the voltage controlled oscillator count target value aim_num through the data comparator, and determine the size of the summation result CSUM<13:0> input by the adder 1043 and the voltage controlled oscillator count target value aim_num according to the difference. If the summation result CSUM<13:0> input by the adder 1043 is less than the voltage controlled oscillator count target value aim_num, then increase the binary code of the sub-band control signal VCO_band<7:0>; if the summation result CSUM<13:0> input by the adder 1043 is greater than the voltage controlled oscillator count target value aim_num, then reduce the binary code of the sub-band control signal VCO_band<7:0>; and output the adjusted sub-band control signal VCO_band<7:0> to the voltage controlled oscillator 102.

[0036] Furthermore, the state machine circuit 1044 is also used to determine whether the difference between the summation result CSUM<13:0> input by the adder 1043 and the voltage-controlled oscillator count target value aim_num is less than a preset threshold Error. If it is less than the preset threshold Error, a prompt signal indicating that the frequency calibration is successful is output; if it is greater than the preset threshold, a prompt signal indicating that the frequency calibration has failed is output.

[0037] Furthermore, the state machine circuit 1044 is further configured to output a clear signal clear to the first counter counter_A and the second counter counter_B, and output a phase-locked loop opening and closing control signal switch_pll_open / closed_loop to the input signal selector 101 after the frequency calibration is completed.

[0038] In this embodiment, the sum of the count values ​​obtained by the eight low-frequency clocks with a phase difference of 45 degrees after passing through the eight groups of second counters and the final adder is equal to the clock cycle count value output by the VCO, but the operating frequency of each counter is reduced to 1 / 8 of the VCO operating frequency. Under the same frequency calibration accuracy and the same AFC input clock frequency, the count value of the reference frequency can be reduced to 1 / 8 of that of the traditional AFC. Since the state interval of the state machine remains consistent with that of the traditional AFC, the calibration time of the AFC in this embodiment is 1 / 7 of that of the traditional AFC.

[0039] The following is a practical example to introduce the frequency calibration process of the phase-locked loop fast frequency automatic calibration system: See also Figure 1 , 2 The voltage controlled oscillator 102 generates an eight-phase clock through eight-frequency division to provide the automatic frequency calibration circuit 104 with a feedback calibration clock, and at the same time inputs a reference clock signal Ref_ck to the automatic frequency calibration circuit 104 .

[0040] Select the phase-locked loop AFC mode to open-loop calibration, open_loop_en = 1, and configure the count value of the first counter counter_A to 16. Taking the calibration accuracy at a frequency of ±1.562 MHz as an example, configure the counter comparison error Error<3:0> = 3. Configure the PLL loop feedback division ratio FB_divider_value, which is the target value of VCO frequency calibration. For example: FB_divider_value = 80. The calculation method of the VCO frequency calibration target value is VCO_fre = FB_divider_value × ref_ck = 80 × 50 MHz = 4000 MHz.

[0041] After the input settings are configured, the AFC enable signal is pulled high, i.e., AFC_enable = 1, the internal active signal of AFC is pulled high, the first counter counter A starts to count the input reference clock signal Ref_ck, and eight groups of second counters counter B start to count the eight-phase clocks after the eighth division of the VCO respectively. The adder sums the outputs of the eight groups of counter B and outputs the sum result CSUM<13:0>.

[0042] When the count of the first counter counter A reaches the set value of 16, the overflow signal cal_stop = 1 and the active signal active = 0 are output. At this time, the two input clocks are turned off, and the data comparator of the state machine circuit 1044 starts to compare the set count value of the first counter counter A, which is 16, with the product of the value of the PLL loop feedback division ratio FB_divider_value, which is 80, that is, the VCO count target value aim_num = 1280, with the VCO clock count value CSUM<13:0>. If CSUM < aim_num, the sub-band control signal VCO_band<7:0> changes from the initial value 10000000 to 11000000. If CSUM > aim_num, the sub-band control signal VCO_band<7:0> changes from the initial value 10000000 to 01000000. After changing the sub-band control signal VCO_band, the clear signal clear is pulled high and waits for 100 ns, then active = 1 and clear = 0 are output, and a new state counting cycle restarts.

[0043] When the difference between CSUM and aim_num is less than the configured preset threshold Error, it indicates that the AFC process is successfully completed, the adjusted sub-band control signal VCO_band<7:0> is output, and a prompt signal AFC_done = 1 and AFC_fail = 0 indicating successful frequency calibration are output.

[0044] When the difference between CSUM and aim_num is greater than the preset threshold Error, it indicates that the AFC process is not successfully completed, and the adjusted sub-band control signal VCO_band<7:0> is also output, and the prompt signals AFC_done=1 and AFC_fail=1 indicating the failure of frequency calibration are output.

[0045] A comparison of the calibration time and accuracy of the conventional phase-locked loop AFC and the phase-locked loop AFC in this embodiment is shown in Table 1. For a conventional AFC structure with 8-bit output and using a binary algorithm, it takes 21.8us to achieve a frequency calibration accuracy of ±1.562MHz, while the present invention only takes 3.36us to achieve the same frequency calibration accuracy, which can meet almost all fast-locking phase-locked loop application scenarios.

[0046] Table 1

[0047] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.

Claims

1. A phase-locked loop fast frequency automatic calibration system, characterized in that: include: Input signal selector, voltage controlled oscillator, divide-by-eight eight-phase circuit and automatic frequency calibration circuit; The eight-frequency-divider eight-phase circuit is used to receive the positive output signal and the negative output signal of the voltage-controlled oscillator, and convert the positive output signal and the negative output signal into eight clock signals with a phase difference of 45 degrees, and then output them to the automatic frequency calibration circuit; The automatic frequency calibration circuit is used to count the input reference clock signal, and to group and count and sum the eight input clock signals with a phase difference of 45 degrees, and to adjust the output of the optimal sub-band control signal to the voltage-controlled oscillator by comparing the summation result of the eight clock signals with a phase difference of 45 degrees with the counting result of the reference clock signal, and to send a phase-locked loop opening and closing control signal to the input signal selector after the frequency calibration is completed; The input signal selector is used to use one of the voltage-controlled oscillator fixed control voltage signal and the phase-locked loop closed-loop control voltage signal as the input control signal of the voltage-controlled oscillator according to the phase-locked loop opening and closing control signal.

2. A phase-locked loop fast frequency automatic calibration system according to claim 1, characterized in that: The eight-frequency-divide-eight-phase circuit comprises a cascaded four-frequency-divide-circuit and a two-frequency-divide-eight-phase clock generator.

3. A phase-locked loop fast frequency automatic calibration system according to claim 2, characterized in that: The four-frequency divider circuit includes two cascaded two-frequency divider circuits.

4. The phase-locked loop fast frequency automatic calibration system according to claim 1, characterized in that: The automatic frequency calibration circuit includes a reference clock signal counting circuit, a feedback calibration clock counting circuit, an adder and a state machine circuit.

5. The phase-locked loop fast frequency automatic calibration system according to claim 4, characterized in that: The reference clock signal counting circuit includes a first AND gate logic circuit and a first counter; The first input end of the first AND gate logic circuit is connected to the activation signal output end of the state machine circuit, the second input end of the first AND gate logic circuit is used to receive the input reference clock signal, and the output end of the first AND gate logic circuit is connected to the first input end of the first counter; The second input terminal of the first counter is used to receive an input counting control signal, the third input terminal of the first counter is connected to the reset signal output terminal of the state machine circuit, and the output terminal of the first counter is connected to the counting overflow signal input terminal of the state machine circuit.

6. A phase-locked loop fast frequency automatic calibration system according to claim 5, characterized in that: The feedback calibration clock counting circuit includes eight AND gate logic circuits, eight OR gate logic circuits and eight second counters; Among them, the first input ends of the eight AND gate logic circuits are used to respectively receive the eight clock signals with a phase difference of 45 degrees, the second input ends of the eight AND gate logic circuits are respectively connected to the activation signal output end of the state machine circuit, the output ends of the eight AND gate logic circuits are respectively connected to the first input ends of the eight OR gate logic circuits, the second input ends of the eight OR gate logic circuits are respectively connected to the output ends of the first counters, the output ends of the eight OR gate logic circuits are respectively connected to the first input ends of eight second counters, the second input ends of the eight second counters are connected to the clear signal output end of the state machine circuit, and the output ends of the eight second counters are connected to the input ends of the adder.

7. A phase-locked loop fast frequency automatic calibration system according to claim 6, characterized in that: The adder is used for summing the output count values ​​of the eight second counters and outputting the summation result to the state machine circuit.

8. A phase-locked loop fast frequency automatic calibration system according to claim 7, characterized in that: The state machine circuit is used to: The difference between the summed result of the adder input and the voltage-controlled oscillator count target value is calculated by a data comparator, and the size of the summed result of the adder input and the voltage-controlled oscillator count target value is determined according to the difference; If the sum of the adder inputs is less than the voltage-controlled oscillator count target value, the binary code of the sub-band control signal is increased; if the sum of the adder inputs is greater than the voltage-controlled oscillator count target value, the binary code of the sub-band control signal is decreased; The adjusted sub-band control signal is output to the voltage controlled oscillator.

9. A phase-locked loop fast frequency automatic calibration system according to claim 8, characterized in that: The state machine circuit is also used to determine whether the difference between the summation result of the adder input and the voltage-controlled oscillator count target value is less than a preset threshold value. If it is less than the preset threshold value, a prompt signal indicating that the frequency calibration is successful is output; if it is greater than the preset threshold value, a prompt signal indicating that the frequency calibration has failed is output.

10. The phase-locked loop fast frequency automatic calibration system according to claim 9, characterized in that: The state machine circuit is also used to output a reset signal to the first counter and the second counter, and output a phase-locked loop on / off control signal to the input signal selector after the frequency calibration is completed.

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