Memory block and manufacturing method thereof

Abstract

The invention provides a memory block and a manufacturing method thereof. According to the storage block, each storage sub-array layer in a storage array comprises a drain region semiconductor layer, a channel semiconductor layer and a source region semiconductor layer which are stacked; the drain region semiconductor layer, the channel semiconductor layer and the source region semiconductor layer respectively comprise a plurality of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips which are distributed along the row direction and extend along the column direction; a row of drain region, channel and source region semiconductor strips in the multi-layer storage sub-array layer are of a row of semiconductor strip-shaped structures; the drain / source leading-out area is provided with a plurality of drain / source connecting end units which are arranged at intervals in the row direction and the column direction, and the drain / source connecting end in each drain / source connecting end unit is connected with one layer of drain region / source region semiconductor strips in the semiconductor strip-shaped structure in the corresponding column. The storage block can avoid the bridging condition of two adjacent drain / source connecting ends in the same drain / source connecting end unit along the column direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a further improvement based on Chinese patent application 2022113607924 filed on November 1, 2022. This application introduces all the records of Chinese patent application 2022113607924 filed on November 1, 2022 by reference. Technical Field

[0003] The present invention relates to the technical field of semiconductor devices, and in particular to a storage block and a manufacturing method thereof. Background Art

[0004] Two dimensional (2D) memory blocks are ubiquitous in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random-access memory (DRAM) arrays, etc. However, 2D memory arrays have reached their scaling limits and storage density cannot be further increased.

[0005] In addition, in a NOR flash memory block, the source region as a bitline (BL) and the drain region as a senseline (SL) are usually led out through connection lines and then respectively connected to the connection pads of the memory block for signal transmission. However, two adjacent connection lines in the existing memory block are prone to bridge connection, resulting in a short circuit of the connection lines. Summary of the invention

[0006] The storage block and its manufacturing method provided in the present application are intended to solve the problem that the existing 2D storage array has reached its scaling limit and the storage density cannot be further improved, and two adjacent connection lines are prone to bridging, resulting in a short circuit of the connection line.

[0007] In order to solve the above technical problems, a technical solution adopted by the present application is to provide a storage block. The storage block includes:

[0008] substrate;

[0009] A memory array is provided on the substrate and comprises a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory sub-array layers stacked in sequence along a height direction, each of the memory sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each of the memory sub-array layers respectively comprise a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips distributed along a row direction, each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips respectively extending along a column direction; a column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips in the plurality of memory sub-array layers is defined as a column of semiconductor strip structures;

[0010] At least one drain / source lead-out region, wherein the drain / source lead-out region is provided with a plurality of drain / source connection terminal units, and the plurality of drain / source connection terminal units are respectively arranged at intervals along the row direction and the column direction; wherein the drain / source connection terminal in each of the drain / source connection terminal units is connected to a layer of drain / source semiconductor strips in the semiconductor strip structure of the corresponding column.

[0011] Among them, in the drain / source lead-out area, the drain / source connection ends in several of the drain / source connection end units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structures, and the drain / source connection ends in several of the drain / source connection end units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structures.

[0012] Wherein, each of the drain / source connection terminal units includes a first drain / source connection terminal and a second drain / source connection terminal distributed along the row direction; the first drain / source connection terminal and the second drain / source connection terminal are respectively connected to the drain / source semiconductor strips of the same layer of two adjacent columns of the semiconductor strip structures.

[0013] Wherein, in the drain / source lead-out region, each non-edge column of the semiconductor strip structure corresponds to two columns of the drain / source connection terminal units respectively; wherein, the second drain / source connection terminal in one column of the drain / source connection terminal units is connected to the drain / source region semiconductor strips of odd-numbered layers in the non-edge semiconductor strip structure, and the first drain / source connection terminal in another column of the drain / source connection terminal units is connected to the drain / source region semiconductor strips of even-numbered layers in the non-edge semiconductor strip structure.

[0014] Wherein, the two columns of drain / source connection terminal units corresponding to each non-edge column of the semiconductor strip structures are staggered with each other.

[0015] The first drain / source connection terminal and the second drain / source connection terminal in each of the drain / source connection terminal units share the same drain / source isolation hole; the drain / source isolation hole is used to remove the portion of the channel semiconductor strips in the two adjacent columns of the semiconductor strip structures close to the drain / source isolation hole; the drain / source isolation hole and the removed region of the channel semiconductor strips are filled with a first insulating material;

[0016] Two adjacent drain / source semiconductor strips of different layers in each column of the semiconductor strip structure in the area where each drain / source connection terminal unit is located are isolated from each other by the first insulating material.

[0017] Wherein, in the area where each of the drain / source connection terminal units is located, lead holes are respectively opened on both sides of the drain / source isolation hole, and each of the lead holes corresponds to exposing one of the drain / source semiconductor strips in a column of the semiconductor strip structures;

[0018] The lead-out holes in the same row corresponding to the drain / source connection terminal units in the same row respectively expose the drain / source semiconductor strips in the same layer in multiple columns of the semiconductor strip structures;

[0019] The lead-out holes in the same column corresponding to the drain / source connection terminal units in the same column respectively expose the drain / source semiconductor strips of different layers in the semiconductor strip structures in the same column.

[0020] Wherein, a drain / source lead-out structure is arranged in the lead-out hole, and the drain / source connection end is connected to the drain region / source region semiconductor strip in the semiconductor strip structure through the drain / source lead-out structure.

[0021] Part of the sidewalls and bottom wall of the lead-out hole is covered with an insulating isolation layer to expose only one corresponding drain / source semiconductor strip in the semiconductor strip structure.

[0022] Wherein, the drain / source lead-out structure includes a semiconductor connection layer and a connection improvement layer extending along the height direction; wherein, the semiconductor connection layer is in contact with the corresponding exposed drain / source semiconductor strip, and the connection improvement layer is arranged on the semiconductor connection layer and in contact with the corresponding drain / source connection terminal.

[0023] Wherein, the semiconductor connection layer comprises a polysilicon connection layer, and the connection improvement layer comprises a metal silicide connection improvement layer.

[0024] Wherein, the drain / source lead-out structure includes a connection improvement layer and a metal connection layer extending along the height direction; wherein, the connection improvement layer is in contact with the corresponding exposed drain / source semiconductor strip, and the metal connection layer is arranged on the connection improvement layer and in contact with the corresponding drain / source connection terminal.

[0025] Wherein, the connection improving layer comprises a metal silicide connection improving layer; and / or

[0026] The metal connection layer and the drain / source connection terminal are made of the same metal.

[0027] The drain / source lead-out region includes a drain / source high lead-out sub-region and a drain / source low lead-out sub-region, wherein the drain / source connection terminal in the drain / source high lead-out sub-region is used to connect the drain / source semiconductor strip in the high region of the semiconductor strip structure; the drain / source connection terminal in the drain / source low lead-out sub-region is used to connect the drain / source semiconductor strip in the low region of the semiconductor strip structure;

[0028] The drain / source connection terminals corresponding to the drain / source semiconductor strips in each upper layer and the drain / source connection terminals corresponding to the drain / source semiconductor strips in the matching layer of the drain / source semiconductor strips in the lower layer are formed in the same process.

[0029] The storage block includes a plurality of drain / source lead-out regions, and the plurality of drain / source lead-out regions are arranged at intervals in the column direction.

[0030] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a process method for manufacturing a storage block. The method comprises: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and a plurality of storage sub-array layers arranged on the substrate and stacked in sequence along the height direction, each of the storage sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each of the storage sub-array layers respectively comprise a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips distributed along the row direction; each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips respectively extends in the column direction; a column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips in the plurality of storage sub-array layers is defined as a column of semiconductor strip structures;

[0031] A plurality of drain / source connection terminal units are arranged in at least one drain / source lead-out region of the semiconductor substrate, and the plurality of drain / source connection terminal units are arranged at intervals along the row direction and the column direction, respectively; wherein the drain / source connection terminal in each of the drain / source connection terminal units is connected to a layer of drain / source semiconductor strips in the semiconductor strip structure of the corresponding column.

[0032] Among them, in the drain / source lead-out area, the drain / source connection ends in several of the drain / source connection end units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structures, and the drain / source connection ends in several of the drain / source connection end units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structures.

[0033] Wherein, a plurality of drain / source connection terminal units are arranged in at least one drain / source lead-out region of the semiconductor substrate, including:

[0034] In the drain / source lead-out region, a plurality of drain / source isolation holes are provided;

[0035] Removing portions of the channel semiconductor strips close to the drain / source lead-out regions in two adjacent columns of the semiconductor strip structures through the drain / source isolation holes, and filling a first insulating material in the removed regions of the drain / source isolation holes and the channel semiconductor strips;

[0036] Lead holes of a preset depth are respectively opened on both sides of the drain / source isolation hole, and each of the lead holes corresponds to exposing a layer of the drain / source semiconductor strip in a column of the semiconductor strip structure;

[0037] A drain / source lead-out structure is formed in the lead-out hole, and the drain / source connection terminal is formed on the drain / source lead-out structure.

[0038] The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises:

[0039] By means of a first removal operation, a-th lead-out holes are respectively opened on both sides of part of the drain / source isolation holes; each of the a-th lead-out holes exposes the drain / source semiconductor strip of the a-th layer in each column of the semiconductor strip structure;

[0040] Through the second removal operation, bth lead-out holes are respectively opened on both sides of part of the drain / source isolation holes; each of the bth lead-out holes exposes the bth layer of the drain / source semiconductor strip in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed; wherein a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

[0041] The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises:

[0042] A row of lead holes of corresponding depth is opened on both sides of the drain / source isolation holes in each row, row by row, wherein the mth lead hole opened on both sides of the drain / source isolation holes in the mth row exposes the drain / source semiconductor strip of the mth layer in each column of the semiconductor strip structure, and m is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

[0043] The step of sequentially opening a row of lead-out holes of corresponding depth on both sides of each row of drain / source isolation holes row by row comprises:

[0044] First lead-out holes are respectively opened on both sides of the drain / source isolation holes in the first row, and each of the first lead-out holes exposes the drain / source semiconductor strip of the first layer in each column of the semiconductor strip structure;

[0045] Second lead-out holes are respectively opened on both sides of the drain / source isolation holes in the second row, and each of the second lead-out holes exposes the drain / source semiconductor strip of the second layer in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed.

[0046] The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises:

[0047] Lead holes of a preset depth are respectively opened on both sides of each of the drain / source isolation holes, and each of the lead holes of the preset depth is respectively subjected to at least one removal operation, wherein the lead holes of the preset depth after n removal operations expose the drain / source semiconductor strip of the nth layer in a corresponding column of the semiconductor strip structure, where n is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

[0048] The steps of opening the lead-out holes of the preset depth on both sides of each drain / source isolation hole, and each lead-out hole of the preset depth undergoing at least one removal operation, include:

[0049] First lead holes are respectively opened on both sides of each drain / source isolation hole by a first removal operation, wherein the lead holes processed by the first removal operation respectively expose the drain / source semiconductor strip of the first layer in each column of the semiconductor strip structure;

[0050] Except for the first lead-out holes having a preset depth of the first depth, a second removal operation is performed on the other first lead-out holes to form second lead-out holes, wherein the second lead-out holes respectively expose the drain / source semiconductor strips of the second layer in each column of the semiconductor strip structure;

[0051] Except for the second lead-out holes having a preset depth of the second depth, a third removal operation is performed on the other second lead-out holes to form third lead-out holes, wherein the third lead-out holes respectively expose the drain / source semiconductor strips of the third layer in each column of the semiconductor strip structures; and so on, until the drain / source semiconductor strips of the last layer in each column of the semiconductor strip structures are exposed.

[0052] The steps of opening the lead-out holes of the preset depth on both sides of each drain / source isolation hole, and each lead-out hole of the preset depth undergoing at least one removal operation, include:

[0053] First lead holes are respectively opened on both sides of part of the drain / source isolation holes by a first removal operation; (K / 2+1)th lead holes are respectively opened on both sides of the remaining drain / source isolation holes by a second removal operation; wherein each of the first lead holes exposes the drain / source semiconductor strip of the first layer in the semiconductor strip structure of the corresponding column; each of the (K / 2+1)th lead holes exposes the drain / source semiconductor strip of the (K / 2+1)th layer in the semiconductor strip structure of the corresponding column; K is the total number of layers of the drain / source semiconductor strips in a column of the semiconductor strip structure;

[0054] Except for the lead-out holes with a preset depth of the first depth and the (K / 2+1)th depth, a third removal operation is performed on the other first lead-out holes and the (K / 2+1)th lead-out holes to form a second lead-out hole and a (K / 2+2)th lead-out hole respectively;

[0055] Except for the lead-out holes with a preset depth of the second depth and the (K / 2+2)th depth, the fourth removal operation is performed on the other second lead-out holes and the (K / 2+2)th lead-out holes to form a third lead-out hole and a (K / 2+3)th lead-out hole, respectively; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed.

[0056] Wherein, the step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection terminal on the drain / source lead-out structure comprises:

[0057] Depositing an insulating isolation layer on the sidewalls and bottom wall of the lead-out hole;

[0058] Removing at least a portion of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in a column of semiconductor strip structures corresponding to the lead-out hole;

[0059] forming a semiconductor connection layer extending in a height direction in the lead-out hole having the insulating isolation layer deposited on the sidewall;

[0060] forming a connection improving layer on the semiconductor connection layer;

[0061] The drain / source connection terminal is formed on a side of the connection improving layer facing away from the semiconductor connection layer.

[0062] Wherein, the semiconductor connection layer comprises a polysilicon connection layer, and the connection improvement layer comprises a metal silicide connection improvement layer.

[0063] Wherein, the step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection terminal on the drain / source lead-out structure comprises:

[0064] Depositing an insulating isolation layer on the sidewalls and bottom wall of the lead-out hole;

[0065] Removing at least a portion of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in a column of semiconductor strip structures corresponding to the lead-out hole;

[0066] forming a connection improving layer in the lead-out hole having the insulating isolation layer deposited on the sidewall;

[0067] forming a metal connection layer extending in a height direction on the connection improving layer;

[0068] The drain / source connection terminal is formed on a surface of the metal connection layer facing away from the connection improving layer.

[0069] Wherein, the connection improving layer comprises a metal silicide connection improving layer; and / or

[0070] The metal connection layer and the drain / source connection terminal are made of the same metal.

[0071] Wherein, a plurality of drain / source connection terminal units are arranged in at least one drain / source lead-out region of the semiconductor substrate, including:

[0072] A plurality of drain / source connection terminal units are respectively disposed in each of the plurality of drain / source lead-out regions of the semiconductor substrate.

[0073] The beneficial effects of the present application are different from those of the prior art: the storage block provided by the embodiment of the present application includes a substrate, a storage array and at least one drain / source lead-out area, the storage array includes a plurality of storage cells distributed in a three-dimensional array, wherein the storage array includes a plurality of storage sub-array layers stacked in sequence along the height direction, each storage sub-array layer includes a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each storage sub-array layer respectively include a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips distributed along the row direction, each drain semiconductor strip, channel semiconductor strip and source semiconductor strip respectively extends along the column direction; a column of drain semiconductor strips, channel semiconductor strips and source semiconductor strips in the multi-layer storage sub-array layer is defined as a column of semiconductor strip structures. At the same time, a plurality of drain / source connection terminal units are arranged in the drain / source lead-out region, and the plurality of drain / source connection terminal units are arranged at intervals along the row direction and the column direction respectively; in the drain / source lead-out region, the drain / source connection terminal in each drain / source connection terminal unit in the same drain / source lead-out region is connected to a layer of drain / source semiconductor strip in the corresponding column semiconductor strip structure; compared with the drain / source connection terminal in each drain / source connection terminal unit being connected to multiple layers of drain / source semiconductor strip in the corresponding column semiconductor strip structure, it is possible to avoid bridging of two adjacent drain / source connection terminals in the same drain / source connection terminal unit along the column direction, thereby causing a short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0075] Figure 1 A schematic diagram of a structure in which the drain / source connection hole is over-etched;

[0076] Figure 2a A top view of a storage block provided in another embodiment of the present application;

[0077] Figure 2b A partial top view of a storage block provided in one embodiment of the present application;

[0078] Figure 3 for Figure 2a A vertical cross-sectional view of the storage block shown at A along the row direction;

[0079] Figure 4 for Figure 2a A vertical cross-sectional view of a memory block taken at B along the row direction is shown.

[0080] Figure 5 A schematic plan view of forming a lead hole on a semiconductor substrate;

[0081] Figure 6 for Figure 5 A vertical cross-sectional view of the semiconductor substrate at C along the row direction;

[0082] Figure 7 for Figure 5 A vertical cross-sectional view of the semiconductor substrate at D along the row direction;

[0083] Figure 8 for Figure 5 Another vertical cross-sectional view of the semiconductor substrate along the row direction;

[0084] Fig. 9 for Figure 2a Another vertical cross-sectional view of the storage block shown at A along the row direction;

[0085] Fig.10 for Figure 2a Another vertical cross-sectional view of the memory block at B along the row direction;

[0086] Fig.11 Another flow chart of a method for manufacturing a memory block according to an embodiment of the present application;

[0087] Fig.12 A schematic plan view of another semiconductor structure provided in an embodiment of the present application;

[0088] Figure 13-Figure 30 for Fig.11 The structural schematic diagram corresponds to the specific process of the process method of the storage block shown.

[0089] Description of Reference Numerals

[0090] Memory block 10 / 10'; memory array 1; memory sub-array layer 1a; drain semiconductor strip 11; channel semiconductor strip 12; source semiconductor strip 13; a row of semiconductor strip structures 1b; isolation wall 3; word line hole 4; substrate 81; drain semiconductor layer 11c; channel semiconductor layer 12c; source semiconductor layer 13c; first drain / source connection terminal group 92a; second drain / source connection terminal group 92b; drain / source connection plug 94; first insulating material 95a; filler 95b; insulating layer 95c; drain / source hole 96; drain / source connection terminal hole 98;

[0091] Drain / source connection terminal unit 21; drain / source connection terminal 211; lead-out hole 22; first lead-out hole 22a; second lead-out hole 22b; third lead-out hole 22c; sixth lead-out hole 22d; (K / 2+1)th lead-out hole 22e; (K / 2+2)th lead-out hole 22f; (K / 2+3)th lead-out hole 22g; drain / source lead-out structure 23; semiconductor connection layer 231; connection improvement layer 232; metal connection layer 233; insulating isolation layer 24; drain / source isolation hole 25. DETAILED DESCRIPTION

[0092] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0093] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0094] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0095] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0096] All the contents of the "Specific Implementation Method" of Chinese Patent Application 2022113607924 are introduced here. Figures 43-46 and the corresponding text in Chinese Patent Application 2022113607924 introduce that each first drain / source connection terminal group 92a or second drain / source connection terminal group 92b includes multiple drain / source connection terminals 91a / 91b. At the same time, Figures 59 and 60 in Chinese Patent Application 2022113607924, as well as the relevant text of steps S435 and S436, also introduce: In the process of executing step S436, the source-drain continuous voltage region uses an insulating layer 95c as a cutoff layer for the drain / source connection terminal hole 98 (referred to as the drain / source isolation hole in this application), and then fills it with a filler 95b made of polysilicon. Then, the high selectivity of polysilicon to the insulating layer 95c is utilized to enable multiple drain / source connection terminal holes 98 to stay on steps of different heights. However, in combination with the appendix of this application, Figure 1 , Figure 1 Schematic diagram of the structure of the drain / source connection terminal hole 98 being over-etched; in the process of forming multiple drain / source connection terminal holes 98, when the height difference between the two steps is large, the drain / source connection terminal hole 98 corresponding to the higher step may be in an etched state for a long time, so that the bottom of the drain / source connection terminal hole 98 corresponding to the higher step gradually becomes larger, resulting in the spacing between the two drain / source connection terminal holes 98 corresponding to the two adjacent steps gradually decreasing or even directly connected, so that the two drain / source connection terminal holes 98 are filled with conductive materials to form a drain / source connection plug 94 (see Chinese patent application 2022113607924 in Figure 4 ), the drain / source connection plug 94 (referred to as the drain / source lead-out structure in the present embodiment) may be bridged, resulting in risks such as short circuit.

[0097] In order to solve the above problems, in this embodiment, another storage block and its process method are provided, which can avoid the risk of bridging between two adjacent drain / source connection plugs 94, resulting in short circuit, etc.; and can reduce the process difficulty and improve the preparation efficiency.

[0098] See also Figures 2a to 4 , Figure 2a A top view of a storage block provided in another embodiment of the present application; Figure 3 for Figure 2a A vertical cross-sectional view of the storage block shown at A along the row direction; Figure 4 for Figure 2a A vertical cross-sectional view of the memory block along the row direction at B is shown. In this embodiment, another memory block 10 ′ is provided, comprising a substrate 81 and a memory array 1 .

[0099] The specific structure and function of the substrate 81 and the storage array 1 can be found in Chinese patent application 2022113607924, attached Figures 2a to 3 , Attachment Fig.18 The corresponding text part introduces the specific structure and function of the memory array 1 and the substrate 81 and the specific method of forming the memory array 1 on the substrate 81. Specifically, Chinese patent application 2022113607924 specifically introduces that the substrate 81 can be a single crystal substrate; the memory array 1 is arranged on the substrate 81. The memory array 1 includes a plurality of memory cells distributed in a three-dimensional array. Figure 2a As shown, the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along a height direction Z, and each memory sub-array layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c, and a source semiconductor layer 13c stacked along the height direction Z. The drain semiconductor layer 11c, the channel semiconductor layer 12c, and the source semiconductor layer 13c may be single crystal semiconductor layers grown by epitaxial growth. The height direction Z is perpendicular to the substrate (e.g., Fig. 9 The term "stacked in sequence" refers to an arrangement from bottom to top on a substrate, and stacking represents an arrangement, without indicating or implying a structure or a relationship between upper and lower layers. In each storage subarray layer 1a, the drain semiconductor layer (D) includes a plurality of drain semiconductor strips 11 spaced apart along a row direction X, and each drain semiconductor strip 11 extends along a column direction Y; the channel semiconductor layer (CH) includes a plurality of channel semiconductor strips 12 spaced apart along a row direction X, and each channel semiconductor strip 12 extends along a column direction Y. The source semiconductor layer (S) includes a plurality of source semiconductor strips 13 spaced apart along a row direction X, and each source semiconductor strip 13 extends along a column direction Y. Each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 is a single crystal semiconductor strip. It can be understood by those skilled in the art that each drain semiconductor strip 11, channel semiconductor strip 12 and source semiconductor strip 13 can be a single crystal semiconductor strip formed by processing the drain semiconductor layer, channel semiconductor layer and source semiconductor layer formed by epitaxial growth. Figure 2a-3 As shown, for the convenience of description, it is defined that a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in each storage sub-array layer 1a constitute a semiconductor strip structure 1b.

[0100] The memory block 10' provided in the embodiment of the present application is different from the memory block 10 provided in Chinese patent application 2022113607924 in that: the memory block 10' comprises: at least one drain / source lead-out area, wherein one drain / source lead-out area is provided with a plurality of drain / source connection terminal units 21, and the plurality of drain / source connection terminal units 21 are respectively arranged at intervals along the row direction X and the column direction Y; that is, a plurality of drain / source connection terminal units 21 arranged at intervals are respectively distributed along the row direction X and the column direction Y. In the drain / source lead-out region, the drain / source connection terminal 211 (CT) in each drain / source connection terminal unit 21 in the same drain / source lead-out region is connected to a layer of drain / source semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b; compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 being connected to multiple layers of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b, it is possible to avoid bridging of two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection terminal unit 21, thereby causing a short circuit.

[0101] Specifically, the drain / source connection terminals 211 (CT) in the drain / source connection terminal units 21 in the same row are connected to the drain / source semiconductor strips 11 / 13 in the same layer in the multiple columns of semiconductor strip structures 1b, and the drain / source connection terminals 211 in the drain / source connection terminal units 21 in the same column are connected to multiple drain / source semiconductor strips 11 / 13 in different layers in a corresponding semiconductor strip structure 1b.

[0102] Each drain / source connection terminal unit 21 may include one drain / source connection terminal 211 or two drain / source connection terminals 211 distributed along the row direction X. When each drain / source connection terminal unit 21 includes one drain / source connection terminal 211, the drain / source connection terminal 211 is connected to the corresponding drain region / source region semiconductor strip 11 / 13. Each drain / source connection terminal unit 21 includes two drain / source connection terminals 211, and the two drain / source connection terminals 211 are respectively connected to two adjacent columns of semiconductor strip structures 1b, that is, one column of semiconductor strip structures 1b is connected to one drain / source connection terminal unit 21. Compared with a plurality of drain / source connection terminals 211 in a drain / source connection terminal unit 21 correspondingly connected to a plurality of drain / source connection terminals 211 in a column of semiconductor strip structures 1b, the scheme in which the plurality of drain / source connection terminals 211 are connected to the drain / source semiconductor strips 11 / 13 of different layers of the column of semiconductor strip structures 1b can avoid the bridge between two adjacent drain / source connection terminals 211 in the same drain / source connection terminal unit 21 along the column direction Y, resulting in a short circuit. At the same time, each drain / source connection terminal 211 extends to the side of the storage array 1 away from the substrate 81, that is, the drain / source connection terminals 211 all fall on the top of the storage block 10', which can reduce the difficulty of the preparation process of the storage block 10'.

[0103] In some embodiments, in combination Figures 2a to 4 Each drain / source connection terminal unit 21 includes a first drain / source connection terminal 211 and a second drain / source connection terminal 211 distributed along the row direction X; the first drain / source connection terminal 211 and the second drain / source connection terminal 211 are respectively connected to the drain / source semiconductor strips 11 / 13 of the same layer of two adjacent columns of semiconductor strip structures 1b.

[0104] In this embodiment, combined with Figure 2a Each semiconductor strip structure 1b is connected to a drain / source connection terminal 211 in the multiple drain / source connection terminal units 21 in the same row; that is, among the multiple drain / source connection terminal units 21 in the same row, two columns of semiconductor strip structures 1b are arranged between each two adjacent drain / source connection terminal units 21.

[0105] Of course, in other embodiments, see Figure 2b , Figure 2b A partial top view of a storage block provided in an embodiment of the present application; along the row direction X, a column of semiconductor strip structures 1b may also be provided between each two adjacent drain / source connection terminal units 21, and two mutually adjacent drain / source connection terminals 211 in the two drain / source connection terminal units 21 are respectively connected to the drain / source semiconductor strips 11 / 13 of the same layer of the semiconductor strip structure 1b located between the two, so that when the drain / source connection terminal 211 of one of the drain / source connection terminal units 21 is damaged and unable to transmit signals, the drain / source connection terminal 211 of another adjacent drain / source connection terminal unit 21 can be used to ensure the normal extraction of the corresponding layer of drain / source semiconductor strips 11 / 13. For example, in combination with Figure 2b The second column of semiconductor strip structures 1b from left to right shown in the figure respectively connects the right drain / source connection terminal 211 of the first drain / source connection terminal unit 21 from left to right, and connects the left drain / source connection terminal 211 of the second drain / source connection terminal unit 21 from left to right.

[0106] The following embodiments of this application are all based on Figure 2a The corresponding scheme is described.

[0107] In the following definition, along the row direction X, the two outermost columns of semiconductor strip structures 1b are edge semiconductor strip structures 1b; and the other columns of semiconductor strip structures 1b between the two edge columns of semiconductor strip structures 1b are non-edge semiconductor strip structures 1b.

[0108] Please continue reading Figure 2aIn the drain / source lead-out region, each non-edge column of semiconductor strip structures 1b is respectively connected to two columns of drain / source connection terminal units 21; wherein, the second drain / source connection terminal 211 in one column of drain / source connection terminal units 21 is connected to the drain / source semiconductor strips 11 / 13 of the odd-numbered layers in the non-edge semiconductor strip structures 1b, and the first drain / source connection terminal 211 in another column of drain / source connection terminal units 21 is connected to the drain / source semiconductor strips 11 / 13 of the even-numbered layers in the non-edge semiconductor strip structures 1b. In this way, the distance between two adjacent drain / source connection terminal units 21 along the column direction Y can be increased, and the drain / source connection terminals 211 in two adjacent drain / source connection terminal units 21 along the column direction Y can be avoided from being bridged.

[0109] Of course, in other embodiments, the second drain / source connection terminal 211 in one column of drain / source connection terminal units 21 may be connected to the multi-layer drain / source semiconductor strip 11 / 13 in the high area F2 of the non-edge semiconductor strip structure 1b, and the first drain / source connection terminal 211 in another column of drain / source connection terminal units 21 may be connected to the multi-layer drain / source semiconductor strip 11 / 13 in the low area F1 of the non-edge semiconductor strip structure 1b. Alternatively, the second drain / source connection terminal 211 in one column of drain / source connection terminal units 21 is connected to any several layers of drain / source semiconductor strips 11 / 13 in the non-edge semiconductor strip structure 1b, and the first drain / source connection terminal 211 in another column of drain / source connection terminal units 21 is connected to the remaining several layers of drain / source semiconductor strips 11 / 13 in the non-edge semiconductor strip structure 1b. The present application does not impose any limitation on this, as long as the two columns of drain / source connection terminal units 21 lead out the corresponding multiple layers of drain / source semiconductor strips 11 / 13 of the non-edge semiconductor strip structure 1b respectively.

[0110] Among them, the first drain / source connection terminal 211 and the second drain / source connection terminal 211 in the same drain / source connection terminal unit 21 can connect the drain / source semiconductor strips 11 / 13 of the same layer of two adjacent columns of semiconductor strip structures 1b; or connect the drain / source semiconductor strips 11 / 13 of different layers of two adjacent columns of semiconductor strip structures 1b.

[0111] It can be understood that the connection principle between the drain / source connection terminal unit 21 and the semiconductor strip structure 1 b is also applicable to the edge semiconductor strip structure 1 b .

[0112] Combination Figure 2a, the two columns of drain / source connection terminal units 21 corresponding to each column of semiconductor strip structures 1b of the non-edge are staggered with each other along the row direction X. In this way, the preparation of each row of drain / source connection terminal units 21 is facilitated, and while the drain / source lead-out region is within a preset size range along the column direction Y, the distance between two adjacent drain / source connection terminal units 21 in the same column can be increased as much as possible, thereby reducing the probability of bridging of the drain / source connection terminals 211 in the two drain / source connection terminal units 21.

[0113] Please continue reading Figure 2a-Figure 4 The first drain / source connection terminal 211 and the second drain / source connection terminal 211 in each drain / source connection terminal unit 21 share the same drain / source isolation hole 25 (see below). Fig.13 ); wherein the drain / source isolation hole 25 cooperates with the word line hole 4 and the isolation wall 3 to separate two adjacent columns of semiconductor strip structures 1b. The word line hole 4 and the isolation wall 3 can be referred to in Chinese patent application 2022113607924, attached Figure 4 and Figure 2a The corresponding text part introduces the word line hole 4 and the isolation wall 3.

[0114] The drain / source isolation hole 25 is used to remove the portion of the channel semiconductor strip 12 in the two adjacent columns of semiconductor strip structures 1b close to the drain / source isolation hole 25; the first insulating material 95a is filled in the removal area of ​​the drain / source isolation hole 25 and the channel semiconductor strip 12. The two adjacent drain / source semiconductor strips 11 / 13 of different layers in each column of semiconductor strip structures 1b in the area where each drain / source connection terminal unit 21 is located are isolated from each other by the first insulating material 95a. Among them, the "isolation from each other" refers to preventing short circuit when the two adjacent drain / source semiconductor strips 11 / 13 are led out. The structure, function and opening method of the drain / source isolation hole 25 are the same or similar to the structure, function and opening method of the above-mentioned drain / source hole 96, and the details can be found above. The filling method of the first insulating material 95a can refer to the relevant description of the filling method of the first insulating material 95a in Chinese patent application 2022113607924.

[0115] In some embodiments, see Figure 5 and Figure 6 , Figure 5 A schematic plan view of forming a lead hole on a semiconductor substrate; Figure 6 for Figure 5 A vertical cross-sectional view of the semiconductor substrate at C along the row direction; Figure 7 for Figure 5A vertical cross-sectional view of the semiconductor substrate at D along the row direction is shown. In the area where each drain / source connection terminal unit 21 is located, lead holes 22 are respectively opened on both sides of the drain / source isolation hole 25 along the row direction X, and each lead hole 22 corresponds to exposing a layer of drain / source semiconductor strips 11 / 13 in a column of semiconductor strip structures 1b. It can be understood that each drain / source isolation hole 25 has a lead hole 22 opened on both sides along the row direction X; one of the two lead holes 22 exposes a layer of drain / source semiconductor strips 11 / 13 in one of the two adjacent columns of semiconductor strip structures 1b; the other lead hole 22 exposes a layer of drain / source semiconductor strips 11 / 13 in the other of the two adjacent columns of semiconductor strip structures 1b.

[0116] Among them, comparison Figure 5 and Figure 6 As shown, the lead-out holes 22 in the same row corresponding to the drain / source connection terminal units 21 in the same row respectively expose the drain / source semiconductor strips 11 / 13 in the same layer in the multiple columns of semiconductor strip structures 1b. Figure 5 and Figure 7 As shown, the lead-out holes 22 in the same column corresponding to the drain / source connection terminal units 21 in the same column respectively expose the drain / source semiconductor strips 11 / 13 of different layers in the same semiconductor strip structure 1b, so as to respectively lead out the multi-layer drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b.

[0117] Combination Figure 3 or Figure 4 A drain / source lead-out structure 23 is disposed in the lead-out hole 22 , and the drain / source connection terminal 211 is connected to the drain / source semiconductor strips 11 / 13 in the semiconductor strip structure 1 b through the drain / source lead-out structure 23 .

[0118] In some embodiments, in combination Figure 3 and Figure 8 As shown, Figure 8 for Figure 5 Another vertical cross-sectional view of the semiconductor substrate along the row direction X is shown; the sidewalls and bottom wall of the lead-out hole 22 are partially covered with an insulating isolation layer 24 to expose only one corresponding drain / source semiconductor strip 11 / 13 in the semiconductor strip structure 1b; thereby ensuring that the corresponding drain / source lead-out structure 23 is only electrically connected to the corresponding drain / source semiconductor strip 11 / 13, and is insulated from the drain / source semiconductor strips 11 / 13 of other layers. The insulating isolation layer 24 can be made of silicon oxide or silicon nitride.

[0119] In some embodiments, Figure 3 or Figure 4As shown, the drain / source lead-out structure 23 includes a semiconductor connection layer 231 and a connection improvement layer 232 extending along the height direction Z; wherein the semiconductor connection layer 231 is in direct contact and connection with the corresponding exposed drain / source semiconductor strips 11 / 13. Since polysilicon has good filling properties, the semiconductor connection layer 231 may include a polysilicon connection layer. The connection improvement layer 232 is arranged on a side surface of the semiconductor connection layer 231 away from the substrate 81, and is in contact with the corresponding drain / source connection terminal 211. wherein the conductive property of the connection improvement layer 232 is better than the conductive property of the semiconductor connection layer 231. The connection improvement layer 232 specifically includes a metal silicide connection improvement layer 232; to ensure that the connection improvement layer 232 is effectively in contact and electrically connected with the corresponding drain / source connection terminal 211. The semiconductor connection layer 231 extends along the height direction Z to a port close to the end of the lead-out hole 22 away from the substrate 81; the surface of the connection improvement layer 232 away from the semiconductor connection layer 231 can be flush with the surface of the storage array 1 away from the substrate 81. The material of the drain / source connection terminal 211 includes metal.

[0120] In another embodiment, see Figure 9-10 , Fig. 9 for Figure 2a Another vertical cross-sectional view of the storage block shown at A along the row direction; Fig.10 for Figure 2a Another vertical cross-sectional view of the memory block at B along the row direction. The drain / source lead-out structure 23 includes a connection improvement layer 232 and a metal connection layer 233 extending along the height direction Z. The connection improvement layer 232 is in direct contact with and electrically connected to the corresponding exposed drain / source semiconductor strips 11 / 13. The connection improvement layer 232 includes a metal silicide connection improvement layer 232. The metal connection layer 233 is disposed on a side surface of the connection improvement layer 232 away from the substrate 81, and extends along the height direction Z to a side surface of the memory array 1 away from the substrate 81, and contacts the corresponding drain / source connection terminal 211. Among them, the conductive property of the metal connection layer 233 is better than the conductive property of the connection improvement layer 232. The size of the metal connection layer 233 along the height direction Z is much larger than the size of the connection improvement layer 232 along the height direction Z, and the side surface of the metal connection layer 233 away from the connection improvement layer 232 can be flush with the side surface of the memory array 1 away from the substrate 81. In some embodiments, the metal connection layer 233 and the drain / source connection terminal 211 are made of the same metal, such as tungsten, copper, or silver.

[0121] In some embodiments, please return to continue to refer to Chinese patent application 2022113607924, whose Figures 46, 54-60 and corresponding text parts introduce an example of dividing into a high area F2 and a low area F1, and synchronously etching to form connection ends connected to the drain / source semiconductor strips 11 / 13 of the corresponding layers respectively; the embodiments provided below in this application can also adopt a similar method. For example, if the current column semiconductor strip structure 1b corresponds to six layers of drain / source semiconductor strips 11 / 13, then the drain / source semiconductor strips 11 / 13 in the lower area F1 of the semiconductor strip structure 1b refer to the multi-layer drain / source semiconductor strips 11 / 13 corresponding to the fourth layer of drain / source semiconductor strips 11 / 13 to the sixth layer of drain / source semiconductor strips 11 / 13 from top to bottom, and the drain / source semiconductor strips 11 / 13 in the upper area F2 of the semiconductor strip structure 1b refer to the multi-layer drain / source semiconductor strips 11 / 13 corresponding to the first layer of drain / source semiconductor strips 11 / 13 to the third layer of drain / source semiconductor strips 11 / 13 from top to bottom.

[0122] Specifically, each drain / source lead-out region includes a drain / source high lead-out sub-region and a drain / source low lead-out sub-region. The drain / source connection terminal 211 in the drain / source high lead-out sub-region is used to connect the drain / source semiconductor strip 11 / 13 in the high region F2 in the semiconductor strip structure 1b; the drain / source connection terminal 211 in the drain / source low lead-out sub-region is used to connect the drain / source semiconductor strip 11 / 13 in the low region F1 in the semiconductor strip structure 1b; the drain / source connection terminal 211 corresponding to the drain / source semiconductor strip 11 / 13 in each layer of the high region F2, the drain / source connection terminal 211 corresponding to the drain / source semiconductor strip 11 / 13 in the matching layer of the drain / source semiconductor strip 11 / 13 in the low region F1, and the drain / source lead-out structure 23 can be formed in the same process; this can simplify the process and reduce the process difficulty. For specific process methods, please refer to the relevant description in the process method below.

[0123] In some embodiments, the memory block 10 ′ may include a plurality of drain / source lead-out regions, and the plurality of drain / source lead-out regions are arranged at intervals in the column direction Y. In this way, the same drain / source semiconductor strip 11 / 13 in each column of semiconductor strip structures 1b can be respectively connected to the corresponding drain / source connection terminals 211 in the corresponding drain / source connection terminal units 21 in the plurality of drain / source lead-out regions, that is, the same drain / source semiconductor strip 11 / 13 can be connected to a plurality of drain / source connection terminals 211 along the column direction Y; thereby, the portion of the same drain / source semiconductor strip 11 / 13 between two adjacent drain / source connection terminals 211 along the column direction Y can directly transmit signals through the drain / source connection terminals 211 at the corresponding positions to perform operations such as read (RD) and program (PGM); compared with the prior art in which the tail of each drain / source semiconductor strip 11 / 13 (i.e., the edge portion of the storage block 10'10) is led out through a connecting wire to perform related operations of the entire drain / source semiconductor strip 11 / 13 through the connecting wire, the resistance can be reduced, the signal transmission is convenient, and the speed of the storage block 10'10 in performing operations such as read (RD) and program (PGM) is improved.

[0124] The memory block 10' provided in this embodiment includes a substrate 81, a memory array 1 and at least one drain / source lead-out region, wherein the memory array 1 includes a plurality of memory cells distributed in a three-dimensional array, wherein the memory array 1 includes a plurality of memory sub-array layers 1a stacked in sequence along a height direction Z, each memory sub-array layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c and a source semiconductor layer 13c stacked along the height direction Z; the drain semiconductor layer 11c, the channel semiconductor layer 12c and the source semiconductor layer 13c in each memory sub-array layer 1a respectively include a plurality of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 distributed along a row direction X, each of the drain semiconductor strips 11, the channel semiconductor strips 12 and the source semiconductor strips 13 respectively extend along a column direction Y; a column of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in the multi-layer memory sub-array layer 1a is defined as a column of semiconductor strip structures 1b. At the same time, the drain / source lead-out region is provided with a plurality of drain / source connection terminal units 21, and the plurality of drain / source connection terminal units 21 are arranged at intervals along the row direction X and the column direction Y, respectively; in the drain / source lead-out region, the drain / source connection terminal 211 in each drain / source connection terminal unit 21 in the same drain / source lead-out region is connected to a layer of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b; compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 connected to the corresponding column semiconductor strip structure 1b, The multilayer drain / source semiconductor strips 11 / 13 in the structure 1b can avoid bridging of two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection terminal unit 21, which may cause a short circuit. At the same time, by extending each drain / source connection terminal 211 to the side of the storage array 1 away from the substrate 81, that is, the drain / source connection terminals 211 all fall on the top of the storage block 10', the difficulty of the preparation process of the storage block 10' can be reduced. The storage density of the storage block 10' is relatively high.

[0125] Above Figure 2a-Figure 10 The memory block 10 ′ shown can be specifically manufactured by the following memory block manufacturing method.

[0126] See also Figure 11 to Figure 12 , Fig.11 Another flow chart of a method for manufacturing a memory block according to an embodiment of the present application; Fig.12 A schematic plan view of another semiconductor substrate provided in an embodiment of the present application; in this embodiment, a process method for manufacturing a memory block is provided, the method specifically comprising:

[0127] Step S51: providing a semiconductor substrate.

[0128] Among them, the specific structure and function of the semiconductor substrate can refer to the relevant description of the semiconductor substrate provided in step S41 in Chinese patent application 2022113607924.

[0129] Step S52: Disposing a plurality of drain / source connection terminal units in at least one drain / source lead-out region of the semiconductor substrate.

[0130] It should be noted that the drain / source lead-out region may refer to the entire semiconductor substrate, or to a portion of the semiconductor substrate having a certain length along the column direction Y; the drain / source lead-out region is actually a virtual region artificially divided, and does not actually exist on the semiconductor substrate; it may correspond to any portion of the semiconductor substrate along the column direction Y according to actual needs. Fig.12 The portion of the semiconductor substrate shown can be divided into a drain / source extraction region.

[0131] The semiconductor substrate may include one drain / source lead-out region or multiple drain / source lead-out regions; step S52 specifically sets multiple drain / source connection terminal units 21 in each drain / source lead-out region. When the semiconductor substrate includes one drain / source lead-out region, the drain / source lead-out region may correspond to a non-end region of the semiconductor substrate along the column direction Y, that is, a region of the semiconductor substrate along the column direction Y that is different from the head end and the tail end; compared with the solution in which the drain / source lead-out region is an end region of the semiconductor substrate along the column direction Y, the resistance can be reduced, the signal transmission is facilitated, and the speed of the storage block 10'10 in performing operations such as read (RD) and program (PGM) is improved.

[0132] When a plurality of drain / source lead-out regions are included on a semiconductor substrate, the plurality of drain / source lead-out regions are spaced apart in the column direction Y; the plurality of drain / source lead-out regions can be simultaneously provided with a plurality of corresponding drain / source connection terminal units 21 using the same process to simplify the process.

[0133] The specific implementation of step S52 is described below by taking the example of providing a plurality of drain / source connection terminal units 21 in a drain / source lead-out region.

[0134] Among them, multiple drain / source connection terminal units 21 are arranged at intervals along the row direction X and the column direction Y respectively; in the drain / source lead-out area, the drain / source connection terminal 211 (CT) in each drain / source connection terminal unit 21 in the same drain / source lead-out area is connected to a layer of drain / source semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b; compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 being connected to multiple layers of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b, it can avoid that two adjacent drain / source connection terminals 211 in the same drain / source connection terminal unit 21 along the column direction Y are bridged, resulting in a short circuit.

[0135] Specifically, the drain / source connection terminals 211 (CT) in the drain / source connection terminal units 21 in the same row are connected to the drain / source semiconductor strips 11 / 13 in the same layer in the multiple columns of the semiconductor strip structure 1b, and the drain / source connection terminals 211 in the drain / source connection terminal units 21 in the same column are connected to the multiple drain / source semiconductor strips 11 / 13 in different layers in a corresponding semiconductor strip structure 1b. For details, please refer to the above Figure 2a-Figure 10 For the related description about the drain / source connection terminal unit 21.

[0136] In one embodiment, in combination Figure 13 to Figure 14 , Fig.13 for Fig.12 A schematic diagram of a product structure in which a plurality of drain / source isolation holes are arranged on a semiconductor substrate; Fig.14 The schematic diagram of the product plane after the first insulating material is filled in the drain / source isolation holes and the removed areas of the channel semiconductor strips; step S52 specifically includes:

[0137] Step S521: a plurality of drain / source isolation holes 25 are provided in the drain / source lead-out region.

[0138] Among them, Fig.13 As shown, the drain / source isolation holes 25 are arranged at intervals along the row direction X and the column direction Y, respectively, and each drain / source isolation hole 25 extends along the height direction Z to the substrate 81 .

[0139] Step S522 : removing portions of the channel semiconductor strips 12 near the drain / source lead-out regions in two adjacent columns of semiconductor strip structures 1 b through the drain / source isolation holes 25 , and filling the removed regions of the drain / source isolation holes 25 and the channel semiconductor strips 12 with a first insulating material 95 a .

[0140] The specific implementation of step S521 and step S522 is the same or similar to the specific implementation of opening multiple drain / source holes 96, removing part of the channel semiconductor strip 12 in the semiconductor strip structure 1b through the drain / source holes 96, and filling the first insulating material 95a in the above-mentioned step S42 and step S43. For details, please refer to the relevant description above.

[0141] Among them, the vertical cross-sectional view of the product after removing the portion of the channel semiconductor strip 12 close to the drain / source lead-out area in two adjacent columns of semiconductor strip structures 1b through the drain / source isolation holes 25 is similar to the structure illustrated in Figure 52 of Chinese patent application 2022113607924, wherein Figure 52 illustrates the structure after removing the portion of the channel semiconductor strip 12 close to the drain / source lead-out area in two adjacent columns of semiconductor strip structures 1b through the drain / source holes 96.

[0142] Step S523 : opening lead holes 22 of a preset depth on both sides of the drain / source isolation hole 25 , and each lead hole 22 correspondingly exposes a layer of drain / source semiconductor strips 11 / 13 in a row of semiconductor strip structures 1 b .

[0143] Combination Figures 5 to 8 , the lead holes 22 can be respectively opened on both sides of the drain / source isolation hole 25 by etching. Among them, the lead hole 22 with a preset depth of the first depth is defined as the first lead hole 22a, which is used to expose the first layer of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b; the lead hole 22 with a preset depth of the second depth is defined as the second lead hole 22b, which is used to expose the second layer of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b; the lead hole 22 with a preset depth of the third depth is defined as the third lead hole 22c, which is used to expose the third layer of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b... and so on. Step S523 can be specifically implemented by the following three implementation methods.

[0144] In the first implementation mode, step S523 specifically includes:

[0145] Step A: by a first removal operation, a-th lead-out holes are respectively opened on both sides of part of the drain / source isolation holes; each a-th lead-out hole exposes the drain / source semiconductor strip 11 / 13 of the a-th layer in each column of the semiconductor strip structure 1b.

[0146] Wherein, a can be 1, 2, 3, ... or Q; Q is the total number of layers of the memory subarray layer 1a. That is, the first removal operation can be used to form a first lead-out hole; or a second lead-out hole; or a lead-out hole 22 of other depths.

[0147] Step B: a bth lead-out hole is respectively opened on both sides of part of the drain / source isolation holes through a second removal operation; each bth lead-out hole exposes the bth layer of the drain / source semiconductor strip 11 / 13 in each column of the semiconductor strip structure 1b; and so on, until the last layer of the drain / source semiconductor strip 11 / 13 in each column of the semiconductor strip structure 1b is exposed; wherein a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

[0148] Wherein, b can be any natural number different from a and less than or equal to Q. That is, the second removal operation can also be used to open a lead hole 22 of any depth different from the ath lead hole. This embodiment does not limit the order of forming the lead holes 22 of each depth, as long as each removal operation forms the lead holes 22 of the same depth to prevent the adjacent lead holes 22 formed by the same removal operation from being connected.

[0149] In a specific embodiment, a row of lead holes 22 of corresponding depth are opened on both sides of each row of drain / source isolation holes 25, wherein the mth lead hole opened on both sides of the mth row of drain / source isolation holes exposes the drain / source semiconductor strip 11 / 14 of the mth layer in each column of semiconductor strip structures 1b.

[0150] A mask may be used to perform etching on both sides of the drain / source isolation holes 25 in the mth row to form the mth lead-out hole.

[0151] It should be noted that the mth row in this application is not specific to a particular row, but may refer to any row of drain / source isolation holes 25 on the semiconductor substrate; m is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer 1a. For example, the first row may be Fig.15 The top row along the column direction Y, the bottom row along the column direction Y, or any other row between the top and the bottom; the second row can be Fig.15 The topmost row or the bottommost row along the column direction Y in the present application is for the convenience of description. Fig.15 , taking the first row, the second row, and the mth row from top to bottom along the column direction Y as an example.

[0152] The step of sequentially and row by row opening a row of corresponding lead-out holes 22 on both sides of each row of drain / source isolation holes 25 specifically includes steps f1 - h1 .

[0153] Combination Figures 6 to 8 as well as Figure 15-18 ; Fig.15 for Fig.14 The product shown is a plan view of the product after step Sf1 processing; step f1: first lead-out holes 22a are respectively opened on both sides of the drain / source isolation holes 25 in the first row, and each first lead-out hole 22a exposes the drain / source semiconductor strip 11 / 13 of the first layer in each column of the semiconductor strip structure 1b.

[0154] Combination Figure 7 and Fig.16 , Fig.16 for Fig.15 The structure shown is a schematic diagram of a structure in which second lead-out holes are respectively opened on both sides of the drain / source isolation holes in the second row. Step g1: Second lead-out holes 22b are respectively opened on both sides of the drain / source isolation holes 25 in the second row, and each second lead-out hole 22b exposes the drain / source semiconductor strip 11 / 13 of the second layer in each column of the semiconductor strip structure 1b. And so on, until the drain / source semiconductor strip 11 / 13 of the last layer in each column of the semiconductor strip structure 1b is exposed.

[0155] For example, the total number of layers of the drain / source semiconductor strips 11 / 13 in a row of semiconductor strip structures 1b is six. Fig.17 and Fig.18 , Fig.17 for Fig.16 A schematic diagram of the structure shown in FIG. 1 in which third lead-out holes are respectively provided on both sides of the drain / source isolation holes in the third row; Fig.18 for Fig.17 The structure shown is a vertical cross-sectional view at the third lead-out hole; after step g1, it also includes: step h1: opening third lead-out holes 22c on both sides of the drain / source isolation holes 25 in the third row, each third lead-out hole 22c exposes the drain / source semiconductor strip 11 / 13 of the third layer in each column of the semiconductor strip structure 1b.

[0156] Afterwards, extraction holes 22 of corresponding depths are respectively opened on both sides of the drain / source isolation holes 25 in the fourth, fifth, and sixth rows using masks, and the drain / source semiconductor strips 11 / 13 of the corresponding layers are exposed; and then the drain / source semiconductor strips 11 / 13 of all layers are exposed.

[0157] The lead holes 22 of the same preset depth are opened in the same row, and the corresponding mask has a simple structure and a small area, which is convenient for processing. Of course, in other specific embodiments, by changing the mask, the lead holes 22a of the preset depth formed in each removal operation can also be located in different rows; or, some are located in the same row and some are located in different rows; this application does not limit this.

[0158] In the first embodiment described above, different depths of the lead holes 22 are formed by different etching processes; that is, each etching process only etches out the lead holes 22 of the same depth (the size along the height direction Z), and the etching time of each lead hole 22 corresponding to the etching process is the same, that is, each lead hole 22 reaches the preset depth at the same time, and there is no time difference, and there will not be a situation where some lead holes 22 reach the preset depth, but the other lead holes 22 continue to be etched because they have not reached the preset depth, resulting in the lead holes 22 that have reached the preset depth gradually becoming larger due to the extended etching time, and then connected with other adjacent lead holes 22, and finally resulting in the drain / source lead structure 23 in the corresponding lead hole 22 being bridged, resulting in the risk of short circuit, etc. For semiconductor substrates with a large number of layers of the storage subarray layer 1a, this is a better solution.

[0159] In the second embodiment, step S523 specifically includes: opening lead holes 22 of a preset depth on both sides of each drain / source isolation hole 25, and each lead hole 22 of the preset depth is formed by at least one removal operation, wherein the lead holes 22 of the preset depth after n removal operations expose the drain / source semiconductor strip 11 / 13 of the nth layer in the corresponding column of semiconductor strip structures 1b, and n is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer 1a. The removal operation may be an etching operation.

[0160] In one embodiment, in combination Figures 19 to 21 Lead holes 22 of a preset depth are respectively opened on both sides of each drain / source isolation hole 25, and each lead hole 22 of the preset depth is subjected to at least one removal operation step, specifically including the following steps f2-i2.

[0161] like Figure 5 and Figure 6 As shown, step f2: a first lead-out hole 22a is respectively opened on both sides of each drain / source isolation hole 25 by a first removal operation, wherein the lead-out holes 22 processed by the first removal operation respectively expose the drain / source semiconductor strips 11 / 13 of the first layer in each column of the semiconductor strip structure 1b.

[0162] In the second embodiment, the lead-out hole 22 formed by the n-th removal operation can be referred to as the n-th lead-out hole, and the n-th lead-out hole exposes the drain / source semiconductor strip 11 / 13 of the n-th layer in the semiconductor strip structure 1b of the corresponding column. For example, the lead-out hole 22 formed by the first removal operation can be referred to as the first lead-out hole 22a. The vertical cross-sectional views of the first lead-out holes 22a on both sides of each drain / source isolation hole 25 are as shown in FIG. Figure 6 shown.

[0163] See also Fig.19 , Fig.19 For Figure 5 A schematic structural diagram of a second drain / source connection terminal 211 hole formed on the product shown;

[0164] Step g2: except for the first lead-out holes 22a with a preset depth of the first depth, a second removal operation is performed on other first lead-out holes 22a to form second lead-out holes 22b, wherein the second lead-out holes 22b respectively expose the drain / source semiconductor strips 11 / 13 of the second layer in each column of the semiconductor strip structure 1b.

[0165] It can be understood that, for the second lead-out holes 22b formed by the second removal operation, the preset depth of part of the second lead-out holes 22b is the second depth, and the preset depth of the remaining second lead-out holes 22b is the third depth, or the fourth depth, or the fifth depth... or the Nth depth; that is, the remaining second lead-out holes 22b must continue to be removed in the future to reach the corresponding preset depth.

[0166] In the second embodiment, the lead-out holes 22 with a preset depth of the Qth depth are arranged in the same row as an example. For example, the first lead-out holes 22a with a preset depth of the first depth are arranged in the same row; in this embodiment, step g2 means that the first lead-out holes 22a in all rows except one row of the first lead-out holes 22a are removed for the second time to form second lead-out holes 22b; each second lead-out hole 22b exposes the drain / source semiconductor strips 11 / 13 of the second layer in each column of the semiconductor strip structure 1b.

[0167] Specifically, a mask may be used to cover the first lead holes 22a in one row of the plurality of rows of first lead holes 22a, and all other first lead holes 22a are exposed to perform step g2; the vertical cross-sectional views of the second lead holes 22b on both sides of each drain / source isolation hole 25 after the processing in step g2 are as shown in FIG. Figure 7 As shown. The covered row of first lead holes 22a may be the first row of first lead holes 22a, or the second row, third row, or other rows of first lead holes 22a. This application takes covering the first row of first lead holes 22a as an example.

[0168] See also Fig. 20 , Fig. 20 For Fig.19 Schematic diagram of the structure of forming a third lead-out hole on the product shown; step h2: except for the second lead-out hole 22b with a preset depth of the second depth, a third removal operation is performed on other second lead-out holes 22b to form a third lead-out hole 22c, wherein the third lead-out hole 22c respectively exposes the drain / source semiconductor strip 11 / 13 of the third layer in each column of the semiconductor strip structure 1b; and so on, until the drain / source semiconductor strip 11 / 13 of the last layer in each column of the semiconductor strip structure 1b is exposed.

[0169] For example, the third removal operation is performed on all rows of second lead holes 22b except one row of second lead holes 22b to form third lead holes 22c; each third lead hole 22c exposes the drain / source semiconductor strips 11 / 13 of the third layer in each column of semiconductor strip structures 1b.

[0170] As described above, a mask may be used to cover the first lead-out hole 22a having a preset depth of the first depth and the second lead-out hole 22b having a preset depth of the second depth, and all other second lead-out holes 22b are exposed to perform step h2; the vertical cross-sectional views of the third lead-out holes 22c on both sides of each drain / source isolation hole 25 after the processing of step h2 are as shown in FIG. Fig.18 As shown. The covered row of second lead-out holes 22b may be the second lead-out holes 22b of the first row, or the second row, the third row, or other rows of second lead-out holes 22b. This application takes covering the second lead-out holes 22b of the first row as an example.

[0171] For example, the total number of drain / source semiconductor strips 11 / 13 in a row of semiconductor strip structures 1b is six. After step h2, the method further includes using a mask to sequentially open corresponding lead-out holes 22 on both sides of the drain / source isolation holes 25 in the fourth and fifth rows, respectively, to expose the drain / source semiconductor strips 11 / 13 of the corresponding layers, and step i2.

[0172] See Figure 2 and Fig.21 , Fig.21 Schematic diagram of the product structure for forming the sixth lead-out hole; step i2: except for the lead-out holes 22 with a preset depth of the first depth to the fifth depth, the sixth removal operation is performed on the other fifth lead-out holes to form the sixth lead-out hole 22d, wherein the sixth lead-out hole 22d respectively exposes the drain / source semiconductor strips 11 / 13 of the sixth layer in each column of the semiconductor strip structure 1b.

[0173] For example, except for a row of fifth lead-out holes, a sixth removal operation is performed on another row of fifth lead-out holes to form sixth drain / source lead-out holes 22d; each sixth lead-out hole 22d exposes the drain / source semiconductor strip 11 / 13 of the sixth layer in the multi-column semiconductor strip structure 1b; and thus exposes the drain / source semiconductor strips 11 / 13 of all layers.

[0174] Of course, it can be understood that the lead-out holes 22 with a preset depth of the Qth depth can also be located in different rows; or partially located in the same row and partially located in different rows. For example, part of the lead-out holes 22 with a preset depth of the Qth depth are located in the first row, part in the second row, and the rest in the fourth row. In this specific embodiment, after step g2 specifically covers the first lead-out holes 22a with a preset depth of the first depth, the second removal operation is performed on the other first lead-out holes 22a; steps h2 and i2 are similar.

[0175] In the above-mentioned second embodiment, since each etching process etches to the storage sub-array layer 1a of the same layer of the semiconductor substrate, that is, the depth of the etched hole is the same; the etching time of each lead hole 22 corresponding to the etching process is the same, that is, each lead hole 22 reaches the preset depth at the same time, there is no time difference, and there will not be a situation where some lead holes 22 reach the preset depth, but the remaining lead holes 22 are continuously etched because they have not reached the preset depth, resulting in the lead holes 22 that have reached the preset depth gradually becoming larger due to the prolonged etching time; that is to say, when it is necessary to etch a lead hole 22 with a larger depth, the other lead holes 22 with a smaller depth will not be further etched; therefore, it is effectively avoided that the bottom of some lead holes 22 gradually becomes larger due to different etching times, and is connected with other adjacent lead holes 22, resulting in the drain / source lead structure 23 in the corresponding lead hole 22 being bridged, resulting in the risk of short circuit. This is a more optimal solution for semiconductor substrates with a larger number of storage sub-array layers 1a.

[0176] The third implementation manner is different from the third embodiment described above in that step S523 specifically includes steps f3 - h3 .

[0177] See also Fig. 22 , Fig. 22 A side view of a semiconductor substrate provided in an embodiment of the present application after being processed in step f3 along the column direction; step f3: opening first lead holes 22a on both sides of part of the drain / source isolation holes 25 by a first removal operation; opening (K / 2+1)th lead holes 22e on both sides of the remaining drain / source isolation holes 25 by a second removal operation; wherein each first lead hole 22a exposes the drain / source semiconductor strip 11 / 13 of the first layer in the semiconductor strip structure 1b of the corresponding column; each (K / 2+1)th lead hole 22e exposes the drain / source semiconductor strip 11 / 13 of the (K / 2+1)th layer in the semiconductor strip structure 1b of the corresponding column; K is the total number of drain / source semiconductor strips 11 / 13 in a column of semiconductor strip structures 1b. For example, if K is six, then each fourth lead hole 22d exposes the drain / source semiconductor strip 11 / 13 of the fourth layer in the semiconductor strip structure 1b of the corresponding column.

[0178] Among them, the first lead-out holes 22a can be respectively opened on both sides of multiple rows of drain / source isolation holes 25 adjacent to each other; or, the first lead-out holes 22a can be respectively opened on both sides of the drain / source isolation holes 25 in any few rows (such as the first row, the third row and the fourth row); and then the (K / 2+1)th lead-out holes 22e can be respectively opened on both sides of the drain / source isolation holes 25 in the remaining other rows.

[0179] In a specific implementation process, a plurality of first lead-out holes 22a can be formed by using a mask and adopting the same etching process; a plurality of (K / 2+1)th lead-out holes 22e can be formed by using a mask and adopting another etching process. Of course, in other implementation processes, as in step f2, firstly, a first lead-out hole 22a is opened on both sides of each drain / source isolation hole 25 through a first removal operation, and the first lead-out hole 22a exposes the drain / source semiconductor strip 11 / 13 of the first layer in each column of semiconductor strip structure 1b; then, a second removal operation is performed on all other first lead-out holes 22a except the first lead-out hole 22a with a preset depth of the first depth, so as to form the (K / 2+1)th drain / source lead-out hole 22e; each (K / 2+1)th lead-out hole 22e exposes the drain / source semiconductor strip 11 / 13 of the (K / 2+1)th layer in each column of semiconductor strip structure 1b.

[0180] See also Fig.23 , Fig.23 A side view of a semiconductor substrate provided in an embodiment of the present application after being processed by step g3 along the column direction; step g3: except for the lead-out holes 22 with a preset depth of the first depth and the (K / 2+1)th depth, a third removal operation is performed on all other first lead-out holes 22a and the (K / 2+1)th lead-out holes 22e to form second lead-out holes 22b and (K / 2+2)th lead-out holes 22f, respectively.

[0181] Among them, the third removal operation is performed on the other first lead-out holes 22a except the first lead-out holes 22a with the preset depth of the first depth to form the second lead-out holes 22b; the third removal operation is performed on all other (K / 2+1)th lead-out holes 22e except the preset depth of the (K / 2+1)th depth to form the (K / 2+2)th lead-out hole 22f.

[0182] The first lead holes 22 with a preset depth of the first depth may be located in the same row; the (K / 2+1)th lead holes 22 with a preset depth of the (K / 2+1)th depth may also be located in the same row. In this embodiment, the third removal operation may be performed on all rows of first lead holes 22 except for one row of first lead holes 22a; the third removal operation may be performed on all rows of (K / 2+1)th lead holes 22e except for one row of (K / 2+1)th lead holes 22e, so as to form lead holes 22f with a (K / 2+2)th depth.

[0183] It can be understood that in step g3, the second lead-out hole 22b and the (K / 2+2)th lead-out hole 22f are formed by the same removal operation; for example, they are formed simultaneously by using a mask and the same etching process; thus, the process can be simplified and the process efficiency can be improved. The second lead-out hole 22b exposes the drain / source semiconductor strip 11 / 13 of the second layer in each column of the semiconductor strip structure 1b; the (K / 2+2)th lead-out hole 22f exposes the drain / source semiconductor strip 11 / 13 of the (K / 2+2)th layer in each column of the semiconductor strip structure 1b.

[0184] See also Fig.24 , Fig.24 A side view of the semiconductor substrate provided in one embodiment of the present application after being processed by step h3 in the column direction; step h3: except for the lead holes 22 of the second depth and the (K / 2+2)th depth, the other second lead holes 22b and the (K / 2+2)th lead holes 22f are subjected to a fourth removal operation to form a third lead hole 22c and a (K / 2+3)th lead hole 22g; and so on, until the last layer of the drain / source semiconductor strip 11 / 13 in each column of the semiconductor strip structure 1b is exposed.

[0185] As above, the lead holes 22 with the preset depth of the first depth, the second depth, the (K / 2+1)th depth or the (K / 2+2)th depth can be located in the same row. In this embodiment, the second lead holes 22b of all rows except the row of second lead holes 22b can be removed for the fourth time to form the third lead holes 22c; the lead holes of the (K / 2+2)th depth opened on both sides of the drain / source isolation holes 25 of other rows except the row of (K / 2+2)th lead holes 22f can be removed for the fourth time to form the (K / 2+3)th lead holes 22g. And so on, until the last layer of the drain / source semiconductor strip 11 / 13 in each column of the semiconductor strip structure 1b is exposed.

[0186] It can be understood that the third lead-out hole 22c and the (K / 2+3)th lead-out hole 22g in step h3 are formed by the same removal operation; thus, the process can be simplified and the process efficiency can be improved. The third lead-out hole 22c exposes the drain / source semiconductor strips 11 / 13 of the third layer in each column of the semiconductor strip structure 1b; the (K / 2+3)th lead-out hole 22g exposes the drain / source semiconductor strips 11 / 13 of the (K / 2+3)th layer in the multiple columns of the semiconductor strip structure 1b.

[0187] The third embodiment described above can simplify the process and improve the process efficiency compared with the first and second embodiments. For example, when the total number of drain / source semiconductor strips 11 / 13 in a column of semiconductor strip structures 1b is six, the first and second embodiments require a total of six removal operations to expose all drain semiconductor strips 11 and source semiconductor strips 13; while the third embodiment only requires four removal operations to expose all drain semiconductor strips 11 and source semiconductor strips 13; two removal operations are omitted, the process is simple, and the efficiency is high.

[0188] Step S524 : forming a drain / source lead-out structure 23 in the lead-out hole 22 , and forming a drain / source connection terminal 211 on the drain / source lead-out structure 23 .

[0189] Step S524 can be specifically implemented through the following two implementations.

[0190] The first implementation method, see Figure 25 to Figure 28 , is a structural schematic diagram corresponding to a specific implementation process of step S524; Fig.25 Schematic diagram of the structure after the side wall and the bottom wall of the lead-out hole 22 are respectively covered with the insulating isolation layer 24; step S524 includes:

[0191] Step k1: depositing an insulating isolation layer 24 on the sidewalls and bottom wall of the lead-out hole 22 .

[0192] Step k2: removing at least a portion of the insulating isolation layer 24 on the bottom wall of the lead-out hole 22 to expose the drain / source semiconductor strips 11 / 13 of the corresponding layer in a column of semiconductor strip structures 1 b corresponding to the lead-out hole 22 .

[0193] The above method can ensure that the corresponding drain / source lead-out structure 23 formed later is only electrically connected to the corresponding drain / source semiconductor strip 11 / 13, and is insulated from the drain / source semiconductor strips 11 / 13 of other layers.

[0194] As shown in FIG. 2 , a portion of the insulating isolation layer 24 on the bottom wall of the lead-out hole 22 may be removed.

[0195] Step k3: forming a semiconductor connection layer 231 extending along the height direction Z in each lead-out hole 22 with the insulating isolation layer 24 deposited on the sidewall.

[0196] Specifically, Fig.26 As shown, a semiconductor connection layer 231 is deposited in each lead hole 22 and on the surface of the memory array 1 facing away from the substrate 81; then, as shown in FIG. Fig. 27As shown, the semiconductor connection layer 231 on the surface of the memory array 1 facing away from the substrate 81 is removed to form a semiconductor connection layer 231 in each lead hole 22. The semiconductor layer on the surface of the memory array 1 facing away from the substrate 81 can be removed by chemical mechanical polishing (CMP).

[0197] The semiconductor connection layer 231 includes a polysilicon connection layer.

[0198] Step k4: forming a connection improving layer 232 on the semiconductor connection layer 231 .

[0199] like Fig.28 As shown, the connection improvement layer 232 is formed on the surface of the semiconductor connection layer 231 on the side away from the substrate 81, and is used to improve the contact resistance between the drain / source lead-out structure 23 and the drain / source connection terminal 211. The connection improvement layer 232 specifically includes a metal silicide connection improvement layer; to ensure that the connection improvement layer 232 is effectively in contact and electrically connected with the corresponding drain / source connection terminal 211 formed later. In some embodiments, the connection improvement layer 232 may also be omitted.

[0200] Step k5: forming a drain / source connection terminal 211 on a surface of the connection improving layer 232 facing away from the semiconductor connection layer 231 .

[0201] like Figure 3 As shown, the drain / source connection terminals 211 are all located on the side surface of the memory array 1 away from the substrate 81, that is, located on the top of the memory block 10'. In this case, the gate connection terminal, the drain / source connection terminal 211 and the substrate 81 connection terminal of the memory block 10' can all be located on the top of the memory block 10', reducing the process difficulty.

[0202] Combination Figure 3 The positive projection of the drain / source connection terminal 211 on the memory array 1 covers the connection improvement layer 232 to ensure that the drain / source connection terminal 211 is in full contact with the corresponding connection improvement layer 232, thereby ensuring effective electrical connection between the two. The material of the drain / source connection terminal 211 includes metal.

[0203] As described above, the corresponding connection improvement layer 232 can be formed on each semiconductor connection layer 231 in the same process step; and the corresponding drain / source connection terminal 211 can be formed on each connection improvement layer 232 in the same process step to improve the manufacturing efficiency. Of course, the connection improvement layer 232 and the drain / source connection terminal 211 corresponding to each semiconductor connection layer 231 can also be formed separately in multiple processes, and this application does not limit this.

[0204] The second implementation method, see Figure 29 to Figure 30 , is a structural diagram corresponding to another specific implementation process of step S524; step S524 specifically includes:

[0205] Step j1 : depositing an insulating isolation layer 24 on the sidewalls and bottom wall of the lead-out hole 22 .

[0206] Step j2: removing at least a portion of the insulating isolation layer 24 on the bottom wall of the lead-out hole 22 to expose the drain / source semiconductor strips 11 / 13 of the corresponding layer in a column of semiconductor strip structures 1 b corresponding to the lead-out hole 22 .

[0207] The specific implementation of step j1 and step j2 is similar to the above-mentioned step k1 and step k2.

[0208] Step j3: forming a connection improving layer 232 in the lead-out hole 22 .

[0209] like Fig.29 As shown, the connection improvement layer 232 is formed on the bottom wall of the lead-out hole 22 and contacts the drain / source semiconductor strip 11 / 13 of the corresponding layer, so as to improve the contact resistance between the drain / source lead-out structure 23 and the drain / source semiconductor strip 11 / 13. The connection improvement layer 232 includes a metal silicide connection improvement layer 232.

[0210] Step j4: forming a metal connection layer 233 extending along the height direction Z on the connection improving layer 232 .

[0211] like Fig.30 As shown, metal material can be filled in the lead-out hole 22 to form a metal connection layer 233. The metal connection layer 233 can be a tungsten layer; the size of the metal connection layer 233 along the height direction Z is much larger than the size of the connection improvement layer 232 along the height direction Z.

[0212] Step j5: forming a drain / source connection terminal 211 on a surface of the metal connection layer 233 that is away from the connection improving layer 232 .

[0213] Combination Fig.10 The specific implementation process of step j5 is the same or similar to the specific implementation process of step k5. The metal connection layer 233 and the drain / source connection terminal 211 can be made of the same metal.

[0214] In some embodiments, during the execution process, if the metal material filled in step j4 overflows the lead-out hole 22, the metal material outside the lead-out hole 22 can be removed by CMP grinding; then step j5 is performed. Of course, the metal material outside the lead-out hole 22 can also be not removed, and step j5 can be directly performed; in this case, it can be understood that the metal material outside the lead-out hole 22 serves as part of the corresponding drain / source connection terminal 211, and the metal material inside the lead-out hole 22 serves as the metal connection layer 233.

[0215] like Fig.10As shown, at this time, the drain / source connection terminal 211 is located on the side surface of the memory array 1 away from the substrate 81, that is, located on the top of the memory block 10', and is connected to the metal connection layer 233 in the lead-out hole 22. In this case, the gate connection terminal, the drain / source connection terminal 211 and the substrate 81 connection terminal of the memory block 10' can all fall on the top of the memory block 10', reducing the process difficulty.

[0216] The process method of the memory block provided in the present embodiment is to arrange a plurality of drain / source connection terminal units 21 in at least one drain / source lead-out region of a semiconductor substrate, wherein the plurality of drain / source connection terminal units 21 are arranged at intervals along the row direction X and the column direction Y; in the drain / source lead-out region, the drain / source connection terminals 211 (CT) in the plurality of drain / source connection terminal units 21 in the same row are connected to the drain / source semiconductor strips 11 / 13 in the same layer of the plurality of columns of semiconductor strip structures 1b, and the drain / source connection terminals 211 in the plurality of drain / source connection terminal units 21 in the same column are connected to the plurality of drain / source semiconductor strips 11 / 13 in different layers of a corresponding semiconductor strip structure 1b; that is, the drain / source connection terminals 21 in each drain / source connection terminal unit 21 in the same drain / source lead-out region are connected to the plurality of drain / source semiconductor strips 11 / 13 in different layers of the corresponding semiconductor strip structure 1b. The drain / source connection terminal 211 is connected to a layer of drain / source semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b; compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 being connected to multiple layers of drain / source semiconductor strips 11 / 13 in the corresponding column semiconductor strip structure 1b, it is possible to avoid bridging of two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection terminal unit 21, thereby causing a short circuit; at the same time, by extending each drain / source connection terminal 211 to the side of the storage array 1 away from the substrate 81, that is, the drain / source connection terminals 211 all fall on the top of the storage block 10', the difficulty of the preparation process of the storage block 10' can be reduced; the storage density of the storage block 10' is relatively high.

[0217] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage block, characterized in that: include: substrate; A memory array is provided on the substrate and comprises a plurality of memory cells distributed in a three-dimensional array, wherein the memory array comprises a plurality of memory sub-array layers stacked in sequence along a height direction, each of the memory sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked along the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each of the memory sub-array layers respectively comprise a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips distributed along a row direction, each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips respectively extending along a column direction; a column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips in the plurality of memory sub-array layers is defined as a column of semiconductor strip structures; At least one drain / source lead-out region, wherein the drain / source lead-out region is provided with a plurality of drain / source connection terminal units, and the plurality of drain / source connection terminal units are respectively arranged at intervals along the row direction and the column direction; wherein the drain / source connection terminal in each of the drain / source connection terminal units is connected to a layer of drain / source semiconductor strips in the semiconductor strip structure of the corresponding column.

2. The storage block according to claim 1, characterized in that: In the drain / source lead-out region, the drain / source connection ends in several of the drain / source connection end units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structures, and the drain / source connection ends in several of the drain / source connection end units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structures.

3. The storage block according to claim 1, characterized in that: Each of the drain / source connection terminal units includes a first drain / source connection terminal and a second drain / source connection terminal distributed along the row direction; the first drain / source connection terminal and the second drain / source connection terminal are respectively connected to the drain / source semiconductor strips of the same layer of two adjacent columns of the semiconductor strip structures.

4. The storage block according to claim 3, characterized in that: In the drain / source lead-out region, each non-edge column of the semiconductor strip structure corresponds to two columns of the drain / source connection terminal units; wherein the second drain / source connection terminals in one column of the drain / source connection terminal units are connected to the drain / source semiconductor strips of the odd-numbered layers in the non-edge semiconductor strip structure, and the first drain / source connection terminals in another column of the drain / source connection terminal units are connected to the drain / source semiconductor strips of the even-numbered layers in the non-edge semiconductor strip structure.

5. The storage block according to claim 4, characterized in that: The two columns of drain / source connection terminal units corresponding to each non-edge column of the semiconductor strip structures are staggered with each other.

6. The storage block according to claim 3, characterized in that: The first drain / source connection terminal and the second drain / source connection terminal in each of the drain / source connection terminal units share the same drain / source isolation hole; wherein the drain / source isolation hole is used to remove a portion of the channel semiconductor strip in two adjacent columns of the semiconductor strip structure close to the drain / source isolation hole; a first insulating material is filled in the removed area of ​​the drain / source isolation hole and the channel semiconductor strip; Two adjacent drain / source semiconductor strips of different layers in each column of the semiconductor strip structure in the area where each drain / source connection terminal unit is located are isolated from each other by the first insulating material.

7. The storage block according to claim 6, characterized in that: In the area where each of the drain / source connection terminal units is located, lead holes are respectively opened on both sides of the drain / source isolation hole, and each of the lead holes corresponds to exposing one of the drain / source semiconductor strips in a column of the semiconductor strip structures; The lead-out holes in the same row corresponding to the drain / source connection terminal units in the same row respectively expose the drain / source semiconductor strips in the same layer in multiple columns of the semiconductor strip structures; The lead-out holes in the same column corresponding to the drain / source connection terminal units in the same column respectively expose the drain / source semiconductor strips of different layers in the semiconductor strip structures in the same column.

8. The storage block according to claim 7, characterized in that: A drain / source lead-out structure is arranged in the lead-out hole, and the drain / source connection end is connected to the drain region / source region semiconductor strip in the semiconductor strip structure through the drain / source lead-out structure.

9. The storage block according to claim 7, characterized in that: Parts of the sidewalls and bottom wall of the lead-out hole are covered with an insulating isolation layer to expose only one corresponding drain / source semiconductor strip in the semiconductor strip structure.

10. The storage block according to claim 8, characterized in that: The drain / source lead-out structure includes a semiconductor connection layer and a connection improvement layer extending along the height direction; wherein the semiconductor connection layer contacts the corresponding exposed drain / source semiconductor strips, and the connection improvement layer is arranged on the semiconductor connection layer and contacts the corresponding drain / source connection terminals.

11. The storage block according to claim 10, characterized in that: The semiconductor connection layer comprises a polysilicon connection layer, and the connection improving layer comprises a metal silicide connection improving layer.

12. The storage block according to claim 8, characterized in that: The drain / source lead-out structure includes a connection improvement layer and a metal connection layer extending along the height direction; wherein the connection improvement layer contacts the corresponding exposed drain / source semiconductor strip, and the metal connection layer is arranged on the connection improvement layer and contacts the corresponding drain / source connection terminal.

13. The storage block according to claim 12, characterized in that: The connection improving layer comprises a metal silicide connection improving layer; and / or The metal connection layer and the drain / source connection terminal are made of the same metal.

14. The storage block according to claim 1, characterized in that: The drain / source lead-out region includes a drain / source high lead-out sub-region and a drain / source low lead-out sub-region, wherein the drain / source connection terminal in the drain / source high lead-out sub-region is used to connect the drain / source semiconductor strip in the high region of the semiconductor strip structure; the drain / source connection terminal in the drain / source low lead-out sub-region is used to connect the drain / source semiconductor strip in the low region of the semiconductor strip structure; The drain / source connection terminals corresponding to the drain / source semiconductor strips in each upper layer and the drain / source connection terminals corresponding to the drain / source semiconductor strips in the matching layer of the drain / source semiconductor strips in the lower layer are formed in the same process.

15. The storage block according to claim 1, characterized in that: The memory block includes a plurality of drain / source lead-out regions, and the plurality of drain / source lead-out regions are arranged at intervals in the column direction.

16. A method for manufacturing a memory block, characterized in that: A semiconductor substrate is provided, wherein the semiconductor substrate comprises a substrate and a plurality of storage sub-array layers arranged on the substrate and sequentially stacked in a height direction, each of the storage sub-array layers comprises a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked in the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each of the storage sub-array layers respectively comprise a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips distributed in a row direction; each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips respectively extends in a column direction; a column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips in the plurality of storage sub-array layers is defined as a column of semiconductor strip structures; A plurality of drain / source connection terminal units are arranged in at least one drain / source lead-out region of the semiconductor substrate, and the plurality of drain / source connection terminal units are arranged at intervals along the row direction and the column direction, respectively; wherein the drain / source connection terminal in each of the drain / source connection terminal units is connected to a layer of drain / source semiconductor strips in the semiconductor strip structure of the corresponding column.

17. The process method according to claim 16, characterized in that: In the drain / source lead-out region, the drain / source connection ends in several of the drain / source connection end units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structures, and the drain / source connection ends in several of the drain / source connection end units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structures.

18. The process method according to claim 16, characterized in that: The at least one drain / source lead-out region of the semiconductor substrate is provided with a plurality of drain / source connection terminal units, including: In the drain / source lead-out region, a plurality of drain / source isolation holes are provided; Removing portions of the channel semiconductor strips close to the drain / source lead-out regions in two adjacent columns of the semiconductor strip structures through the drain / source isolation holes, and filling a first insulating material in the removed regions of the drain / source isolation holes and the channel semiconductor strips; Lead holes of a preset depth are respectively opened on both sides of the drain / source isolation hole, and each of the lead holes corresponds to exposing a layer of the drain / source semiconductor strip in a column of the semiconductor strip structure; A drain / source lead-out structure is formed in the lead-out hole, and the drain / source connection terminal is formed on the drain / source lead-out structure.

19. The process method according to claim 18, characterized in that: The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises: By means of a first removal operation, a-th lead-out holes are respectively opened on both sides of part of the drain / source isolation holes; each of the a-th lead-out holes exposes the drain / source semiconductor strip of the a-th layer in each column of the semiconductor strip structure; Through the second removal operation, bth lead-out holes are respectively opened on both sides of part of the drain / source isolation holes; each of the bth lead-out holes exposes the bth layer of the drain / source semiconductor strip in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed; wherein a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

20. The process method according to claim 19, characterized in that: The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises: A row of lead holes of corresponding depth is opened on both sides of the drain / source isolation holes in each row, row by row, wherein the mth lead hole opened on both sides of the drain / source isolation holes in the mth row exposes the drain / source semiconductor strip of the mth layer in each column of the semiconductor strip structure, and m is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

21. The process method according to claim 20, characterized in that: The step of sequentially opening a row of lead-out holes of corresponding depth on both sides of each row of drain / source isolation holes row by row comprises: First lead-out holes are respectively opened on both sides of the drain / source isolation holes in the first row, and each of the first lead-out holes exposes the drain / source semiconductor strip of the first layer in each column of the semiconductor strip structure; Second lead-out holes are respectively opened on both sides of the drain / source isolation holes in the second row, and each of the second lead-out holes exposes the drain / source semiconductor strip of the second layer in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed.

22. The process method according to claim 18, characterized in that: The step of respectively opening extraction holes of a preset depth on both sides of the drain / source isolation hole comprises: Lead holes of a preset depth are respectively opened on both sides of each of the drain / source isolation holes, and each of the lead holes of the preset depth is respectively subjected to at least one removal operation, wherein the lead holes of the preset depth after n removal operations expose the drain / source semiconductor strip of the nth layer in a corresponding column of the semiconductor strip structure, where n is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray layer.

23. The process method according to claim 22, characterized in that: The step of opening the lead-out holes of the preset depth on both sides of each drain / source isolation hole, and each lead-out hole of the preset depth undergoing at least one removal operation, comprises: First lead holes are respectively opened on both sides of each drain / source isolation hole by a first removal operation, wherein the lead holes processed by the first removal operation respectively expose the drain / source semiconductor strip of the first layer in each column of the semiconductor strip structure; Except for the first lead-out holes having a preset depth of the first depth, a second removal operation is performed on the other first lead-out holes to form second lead-out holes, wherein the second lead-out holes respectively expose the drain / source semiconductor strips of the second layer in each column of the semiconductor strip structure; Except for the second lead-out holes having a preset depth of the second depth, a third removal operation is performed on the other second lead-out holes to form third lead-out holes, wherein the third lead-out holes respectively expose the drain / source semiconductor strips of the third layer in each column of the semiconductor strip structures; and so on, until the drain / source semiconductor strips of the last layer in each column of the semiconductor strip structures are exposed.

24. The process method according to claim 22, characterized in that: The step of opening the lead-out holes of the preset depth on both sides of each drain / source isolation hole, and each lead-out hole of the preset depth undergoing at least one removal operation, comprises: First lead holes are respectively opened on both sides of part of the drain / source isolation holes by a first removal operation; (K / 2+1)th lead holes are respectively opened on both sides of the remaining drain / source isolation holes by a second removal operation; wherein each of the first lead holes exposes the drain / source semiconductor strip of the first layer in the semiconductor strip structure of the corresponding column; each of the (K / 2+1)th lead holes exposes the drain / source semiconductor strip of the (K / 2+1)th layer in the semiconductor strip structure of the corresponding column; K is the total number of layers of the drain / source semiconductor strips in a column of the semiconductor strip structure; Except for the lead-out holes with a preset depth of the first depth and the (K / 2+1)th depth, a third removal operation is performed on the other first lead-out holes and the (K / 2+1)th lead-out holes to form a second lead-out hole and a (K / 2+2)th lead-out hole respectively; Except for the lead-out holes with a preset depth of the second depth and the (K / 2+2)th depth, the fourth removal operation is performed on the other second lead-out holes and the (K / 2+2)th lead-out holes to form a third lead-out hole and a (K / 2+3)th lead-out hole, respectively; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed.

25. The process method according to claim 18, characterized in that: The step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection terminal on the drain / source lead-out structure comprises: Depositing an insulating isolation layer on the sidewalls and bottom wall of the lead-out hole; Removing at least a portion of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in a column of semiconductor strip structures corresponding to the lead-out hole; forming a semiconductor connection layer extending in a height direction in the lead-out hole having the insulating isolation layer deposited on the sidewall; forming a connection improving layer on the semiconductor connection layer; The drain / source connection terminal is formed on a side of the connection improving layer facing away from the semiconductor connection layer.

26. The process method according to claim 25, characterized in that: The semiconductor connection layer comprises a polysilicon connection layer, and the connection improving layer comprises a metal silicide connection improving layer.

27. The process method according to claim 18, characterized in that: The step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection terminal on the drain / source lead-out structure comprises: Depositing an insulating isolation layer on the sidewalls and bottom wall of the lead-out hole; Removing at least a portion of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in a column of semiconductor strip structures corresponding to the lead-out hole; forming a connection improving layer in the lead-out hole having the insulating isolation layer deposited on the sidewall; forming a metal connection layer extending in a height direction on the connection improving layer; The drain / source connection terminal is formed on a surface of the metal connection layer facing away from the connection improving layer.

28. The process method according to claim 27, characterized in that: The connection improving layer comprises a metal silicide connection improving layer; and / or The metal connection layer and the drain / source connection terminal are made of the same metal.

29. The process method according to any one of claims 18 to 28, characterized in that: The at least one drain / source lead-out region of the semiconductor substrate is provided with a plurality of drain / source connection terminal units, including: A plurality of drain / source connection terminal units are respectively disposed in each of the plurality of drain / source lead-out regions of the semiconductor substrate.

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