A memristor array and a method for preparing the same

Abstract

The present invention discloses a memristor array and a preparation method thereof, wherein the memristor array comprises: a substrate, an oxide functional layer, and an electrode. The substrate is of a first conductivity type; the substrate comprises a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region comprises a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other; the oxide functional layer is of a second conductivity type, the oxide functional layer is located on one side of the substrate, and the vertical projection of the oxide functional layer on the substrate is located within the sub-region; the electrode is located on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode comprises a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction. The present invention has a simple structure, a preparation method compatible with CMOS technology, a high degree of integration, and avoids the problem of crosstalk between memristor units during the operation of the memristor array.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a memristor array and a preparation method thereof. Background Art

[0002] In the context of the rapid development of artificial intelligence (AI), machine learning, and deep learning, the surge in information processing and computing needs has posed new challenges to memory technology. The traditional von Neumann architecture is increasingly unable to cope with the growing demand for data processing due to data transmission bottlenecks and power consumption issues. In order to overcome these limitations, the storage-computing integrated architecture has emerged as a key solution. By combining storage and computing functions, it significantly reduces the bottleneck of data transmission and improves computing efficiency, showing great potential in artificial intelligence and generative AI applications.

[0003] As a new type of non-volatile memory, memristor devices can not only store information but also perform logical operations. Therefore, they play a vital role in the storage-computing integrated architecture. Inspired by the biological nervous system, the integrated sensing-storage-computing system that integrates perception, storage and computing functions is gradually emerging. Such systems can significantly improve computing efficiency and response speed, and are particularly suitable for edge computing application scenarios. Multimodally regulated memristors provide a feasible technical path for realizing the integration of sensing, storage and computing by integrating multiple sensing functions such as light, pressure and chemistry. This integration method not only effectively alleviates the bottleneck of the von Neumann architecture, but also provides important support for the implementation of multimodal large models and interactive artificial intelligence systems in terminal applications. However, with the large-scale integration of memristor arrays, the crosstalk problem has gradually become prominent. Summary of the invention

[0004] The present invention provides a memristor array and a preparation method thereof, which has a simple structure and a high degree of integration and avoids the crosstalk problem between memristor units during the operation of the memristor array.

[0005] According to one aspect of the present invention, there is provided a memristor array, comprising:

[0006] A substrate, the substrate is of a first conductive type; the substrate includes a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region includes a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other;

[0007] An oxide functional layer, the oxide functional layer is of the second conductivity type, the oxide functional layer is located on one side of the substrate, and a vertical projection of the oxide functional layer on the substrate is located within the sub-region; the oxide functional layer includes a plurality of functional units, each of which extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction;

[0008] An electrode, the electrode is located on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode includes a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction;

[0009] The mask layer is arranged at the same layer as the oxide functional layer; the mask layer covers a portion of the second region of the substrate.

[0010] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0011] Optionally, along the second direction, the width of the sub-region is the same as the width of the oxide functional layer, and the width of the sub-region ranges from 10 μm to 200 μm;

[0012] Along the third direction, the thickness of the substrate ranges from 250 μm to 500 μm; the third direction is perpendicular to both the first direction and the second direction;

[0013] Along the third direction, the thickness of the oxide functional layer ranges from 10nm to 40nm;

[0014] Along the first direction, the width of the electrode ranges from 10 μm to 200 μm; along the third direction, the thickness of the electrode ranges from 10 nm to 80 nm.

[0015] Optionally, the material of the substrate includes at least one of silicon, germanium, gallium nitride, and silicon carbide;

[0016] The material of the oxide functional layer includes at least one of nickel oxide, copper oxide, tungsten oxide and hafnium oxide;

[0017] The material of the electrode includes at least one of nickel, platinum, titanium, titanium nitride, and indium tin oxide;

[0018] The mask layer material includes at least one of silicon oxide, aluminum oxide, silicon nitride and aluminum nitride.

[0019] According to another aspect of the present invention, there is provided a method for preparing a memristor array, comprising:

[0020] A substrate and a mask layer are formed; the substrate is of a first conductivity type; the substrate includes a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region includes a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other; the mask layer covers a portion of the second region of the substrate;

[0021] An oxide functional layer is formed on one side of the substrate; the oxide functional layer is of the second conductivity type; a vertical projection of the oxide functional layer on the substrate is located in the sub-region; the oxide functional layer includes a plurality of functional units, each functional unit extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction; the mask layer is disposed on the same layer as the oxide functional layer;

[0022] An electrode is formed on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode comprises a plurality of electrode strips extending along the second direction and arranged at intervals along the first direction.

[0023] Optionally, forming a substrate and a mask layer includes:

[0024] providing a substrate material layer;

[0025] forming a mask material layer on one side of the substrate material layer;

[0026] Patterning the mask material layer to form the mask layer and a plurality of grooves; the plurality of grooves expose a portion of the substrate material layer; the grooves extend along a first direction, and the plurality of grooves are arranged at intervals along a second direction;

[0027] Ion implantation is performed on the exposed substrate material layer through the plurality of trenches to form a plurality of sub-regions to form a substrate;

[0028] An oxide functional layer is formed on one side of the substrate, comprising:

[0029] Forming a plurality of functional units in the plurality of trenches to form an oxide functional layer; wherein each functional unit extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction;

[0030] An electrode is formed on a side of the oxide functional layer away from the substrate, comprising:

[0031] forming an electrode material layer on a side of the oxide functional layer away from the substrate;

[0032] The electrode material layer is patterned to form a plurality of electrode strips to form electrodes.

[0033] Optionally, forming an oxide functional layer on one side of the substrate includes:

[0034] The oxide functional layer is formed on one side of the substrate by a pulse laser deposition method, a magnetron sputtering method, an atomic layer deposition method, or a sol-gel spin coating method.

[0035] Optionally, forming an electrode on a side of the oxide functional layer away from the substrate includes:

[0036] The electrode is formed on the side of the oxide functional layer facing away from the substrate by a magnetron sputtering method, an electron beam evaporation method or a pulsed laser deposition method.

[0037] Optionally, forming a mask material layer on one side of the substrate material layer includes:

[0038] A mask material layer is formed on one side of the substrate material layer by a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or an inductively coupled plasma chemical vapor deposition method.

[0039] The memristor array provided by the technical solution of the embodiment of the present invention includes: a substrate; the substrate is of a first conductivity type; the substrate includes a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region includes a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other; an oxide functional layer, the oxide functional layer is of a second conductivity type, the oxide functional layer is located on one side of the substrate, and the vertical projection of the oxide functional layer on the substrate is located in the sub-region; the oxide functional layer includes a plurality of functional units, each functional unit extends along the first direction, and the plurality of functional units are arranged at intervals along the second direction; an electrode, the electrode is located on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode includes a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction; a mask layer; the mask layer and the oxide functional layer are arranged in the same layer; the mask layer covers a portion of the second region of the substrate. In the embodiment of the present invention, the first region of the substrate and the oxide functional layer form a PN heterostructure, which can effectively avoid the crosstalk problem between the memristor units, and the memristor array is a single stack structure for easy integration, thus having low power consumption, high uniformity and the potential for multi-polar storage.

[0040] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 It is a structural schematic diagram of a memristor array provided by an embodiment of the present invention.

[0043] Figure 2 It is a top view of the structure of a memristor array provided by an embodiment of the present invention.

[0044] Figure 3 yes Figure 2Schematic diagram of the cross-sectional structure along the section line B1B2.

[0045] Figure 4 It is a structural schematic diagram of another memristor array provided by an embodiment of the present invention.

[0046] Figure 5 It is a flow chart of a method for preparing a memristor array provided in an embodiment of the present invention.

[0047] Figure 6 This is a flow chart of another method for preparing a memristor array provided in an embodiment of the present invention.

[0048] Figure 7 It is a schematic diagram of the structure of a memristor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0051] The inventors found that the two-terminal metal-insulator-semiconductor (MIS) structure of the memristor device enables it to be integrated into a dense crossbar array. The crossbar array consists of parallel lines, which are called word lines and bit lines, respectively. As the top electrode and bottom electrode are perpendicular to each other, the two-terminal memristor device is formed at the intersection of the word line and the bit line; during the read conductance process, the selected cell is in a high resistance state (HRS). During this readout process, the sneak path of other cells will carry unnecessary current. The unnecessary current flows through the series resistor parallel to the selected memristor device, resulting in crosstalk. This sneak current will cause additional energy consumption of the unselected cells and reduce the read margin, thereby limiting the size of the array.

[0052] In order to solve the above problems, an embodiment of the present invention provides a memristor array. Figure 1 is a schematic diagram of the structure of a memristor array provided by an embodiment of the present invention, Figure 2 is a top view of the structure of a memristor array provided by an embodiment of the present invention, Figure 3 yes Figure 2 Schematic diagram of the cross-section structure along the section line B1B2, refer to Figure 1-Figure 3 , the memristor array includes:

[0053] The substrate 10 is of a first conductive type; the substrate 10 includes a first region 11 and a second region 12, the doping concentration of the first region 11 is greater than the doping concentration of the second region 12; the first region 11 includes a plurality of sub-regions 111, the sub-regions 111 extend along a first direction X, and the plurality of sub-regions 111 are arranged at intervals along a second direction Y; the first direction X and the second direction Y are perpendicular to each other.

[0054] The oxide functional layer 20 is of the second conductivity type, the oxide functional layer 20 is located on one side of the substrate 10, and the vertical projection of the oxide functional layer 20 on the substrate 10 is located in the sub-region 111; Figure 1 and Figure 2 , the oxide functional layer 20 includes a plurality of functional units 201; each functional unit 201 extends along a first direction X, and the plurality of functional units 201 are arranged at intervals along a second direction Y;

[0055] The electrode 30 is located on a side of the oxide functional layer 20 away from the substrate 10 ; the electrode 30 covers a portion of the oxide functional layer 20 ; the electrode 30 includes a plurality of electrode strips 31 , the electrode strips 31 extend along the second direction Y, and the plurality of electrode strips 31 are arranged at intervals along the first direction X.

[0056] The resistivity of the substrate 10 is 0.001 ohm·cm-10 ohm·cm. Since heavy doping can make semiconductors conductive, the substrate 10 can also serve as a bottom electrode; the electrode 30 can serve as a top electrode, and the work function of the electrode 30 matches the Fermi level of the oxide functional layer 20 and the substrate 10. The oxide functional layer 20 covers part of the sub-region 111, and the uncovered sub-region 111 can serve as a PAD region of the sub-region 111 for connecting to the outside.

[0057] The first conductivity type is opposite to the second conductivity type. If the first conductivity type is N type, then the second conductivity type is P type; if the first conductivity type is P type, then the second conductivity type is N type; the substrate 10 includes a first region 11 and a second region 12. The doping concentration of the first region 11 is greater than the doping concentration of the second region 12. The first region 11 can be an N+ heavily doped region, and the second region 12 can be an undoped region. The first region 11 is an N+ heavily doped region, which can make the first region 11 of the substrate 10 conductive as an electrode; the oxide functional layer 20 can be divided into a depletion layer 21 and a resistive layer 22. The depletion layer 21 contacts the first region 11 of the substrate 10. The first region 11 and the depletion layer 21 form a PN heterostructure, that is, a diode (1D) structure. At the same time, the first region 11, the resistive layer 22 and the electrode 30 constitute a memristor structure, that is, a memristor (1R) structure.

[0058] Among them, reference Figure 1 and Figure 2 , each functional unit 201 extends along the first direction X, and a plurality of functional units 201 are arranged at intervals along the second direction Y; Figure 1 and Figure 2 A functional unit 201 covers a sub-area 111, and the functional unit 201 and the sub-area 111 are arranged in a one-to-one correspondence; each red frame is a memristor unit, that is, a memristor device; the PN heterostructure formed by the first region 11 of the substrate 10 and the oxide functional layer 20 can effectively avoid the crosstalk problem between the memristor units.

[0059] Specifically, the memristor array can be set as a cross-bar array structure, the first region 11 is an N-type heavily doped region, and the oxide functional layer 20 is a P-type oxide functional layer; the first region 11 and the electrode 30 can form two parallel lines in the cross-bar array, and the parallel lines are respectively called word lines and bit lines. The first region 11 can be used as a word line, and the electrode 30 can be used as a bit line; Figure 2 , the region where the vertical projection of the electrode 30 on the substrate 10 overlaps with the first region 11 forms a memristor unit, each memristor unit is a memristor device, and the memristor device is a sub-region 111, an oxide functional layer 20 and an electrode 30 stacked along a third direction Z; a memristor array includes a plurality of memristor devices arranged vertically in the first direction X and the second direction Y; Figure 3 This is a schematic diagram of a memristor unit. Figure 1 and Figure 2The invention comprises four memristor units, namely A1, A2, A3 and A4, each memristor unit at least comprises a first region 11, an oxide functional layer 20 and an electrode 30 which are stacked in sequence; illustratively, all the units are first activated (Forming): a gradually increasing positive scanning voltage under a small current limiting state is applied to the top electrode, and a negative bias voltage or grounding is applied to the bottom electrode, so that all the units are in a low resistance state (LRS); A1 is set as the selected memristor unit, and a gradually increasing positive scanning voltage under a large current limiting state is applied to the electrode strip 31 where A1 is located, and a negative bias voltage or grounding is applied to the first region 11 where A1 is located. At this time, the first region 11 of A1 and the depletion layer 21 form a pn heterostructure which is in a conducting state, and the memristor structure of A1 is reset (RESET) to make it in a high resistance state (HRS). Figure 1 The black solid line in the figure is the on-current; the electrode strip 31 where A3 and A4 are located is negatively biased or grounded, and the first region 11 where the electrode strip 31 where A3 and A4 are located is applied with a gradually increasing positive scanning voltage. At this time, the electrode strip 31 where A2 is located is the same as A1, and both are applied with a gradually increasing positive scanning voltage. The first region 11 where A2 is located is the same as A4, and a gradually increasing positive scanning voltage is applied. At this time, A2, A3 and A4 are unselected memristive units, and the first region 11 of A2, A3 and A4 forms a pn heterostructure with the depletion layer 21 and is in a cut-off state, so that the applied voltage cannot be transmitted to the memristive structure of A2, A3 and A4, so that A2, A3 and A4 are still in a low resistance state (LRS), so Figure 1 The sneak current represented by the blue dotted line in the figure cannot flow through A2, A3 and A4, and the current is reversely cut off, causing the sneak current to disappear, thereby successfully suppressing the crosstalk behavior.

[0060] Exemplarily, the first region 11 is an N-type heavily doped region, and the oxide functional layer 20 is a P-type oxide functional layer. Figure 3The cross-sectional structural diagram in is a cross-sectional structural diagram of the selected unit A1; a gradually increasing positive scanning voltage is applied to the electrode strip 31 where A1 is located, and a negative bias voltage or grounding is applied to the first region 11 where A1 is located, so that the holes in the oxide functional layer 20 in A1 and the electrons in the first region 11 diffuse to the contact interface between the substrate 10 and the oxide functional layer 20 to form a depletion region; the contact interface between the substrate 10 and the oxide functional layer 20 is the central region of the PN heterostructure, thereby reducing the height of the potential barrier; when the height of the potential barrier is reduced to a certain extent, the electrons and holes can pass through the contact interface between the substrate 10 and the oxide functional layer 20, from A current is formed, and the current shows a linear increasing trend, thereby forming a linearly increasing current, that is, the PN heterostructure is in a conductive state; by applying a positive scanning voltage under a small current limiting state to the electrode strip 31, the oxygen ions in the oxide functional layer 20 migrate, and oxygen vacancies gradually accumulate to form a conductive filament (CF), thereby causing the memristive structure to enter a low resistance state (LRS); a gradually increasing positive voltage is applied to the electrode strip 31 under a large current limiting state, and a negative bias or grounding is applied to the first region 11 where A1 is located, so that the conductive filament (CF) breaks, thereby causing the memristive structure to enter a high resistance state (HRS), and the conductive filament (CF) only exists in the resistive layer 22.

[0061] The memristor array provided by the technical solution of the embodiment of the present invention includes: a substrate 10; the substrate 10 is of the first conductivity type; the substrate 10 includes a first region 11 and a second region 12, the doping concentration of the first region 11 is greater than the doping concentration of the second region 12; the first region 11 includes a plurality of sub-regions 111, the sub-regions 111 extend along a first direction X, and the plurality of sub-regions 111 are arranged at intervals along a second direction Y; the first direction X and the second direction Y are perpendicular to each other; an oxide functional layer 20, the oxide functional layer 20 is of the second conductivity type, the oxide functional layer 20 is located on one side of the substrate 10, and the oxide functional layer 20 is on the substrate 10 is located in the sub-region 111; the oxide functional layer includes a plurality of functional units, each functional unit extends along the first direction, and the plurality of functional units are arranged at intervals along the second direction; the electrode 30, the electrode 30 is located on the side of the oxide functional layer 20 away from the substrate 10; the electrode 30 covers part of the oxide functional layer 20; the electrode 30 includes a plurality of electrode strips 31, the electrode strips 31 extend along the second direction Y, and the plurality of electrode strips 31 are arranged at intervals along the first direction X; the mask layer 40; the mask layer 40 is arranged in the same layer as the oxide functional layer 20, and the mask layer 40 covers part of the second region 12 of the substrate 10. In the embodiment of the present invention, the first region 11 of the substrate 10 and the oxide functional layer 20 form a PN heterostructure, which can effectively avoid the crosstalk problem between the memristor units, and the memristor array is a single stacking structure, which is convenient for 3D integration, so as to have low power consumption, high uniformity and the potential of multi-polar storage.

[0062] Optional, Figure 4is a schematic diagram of the structure of another memristor array provided by an embodiment of the present invention, referring to Figure 4 When each functional unit 201 extends along the first direction X and multiple functional units 201 are arranged at intervals along the second direction Y, the memristor array further includes: a mask layer 40; the mask layer 40 is arranged at the same layer as the oxide functional layer 20; and the mask layer 40 covers a portion of the second region 12 of the substrate 10.

[0063] Among them, the mask layer 40 can be a hard mask layer, and the material of the mask layer 40 includes at least one of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride; the thickness of the mask layer 40 is 40nm-200nm, which can be set according to the thickness of the oxide functional layer 20. The mask layer 40 and the oxide functional layer 20 are set in the same layer, and the thickness of the mask layer 40 is greater than the thickness of the oxide functional layer 20, which can simplify the preparation process. The mask layer 40 is used for insulation isolation to make the device unit small in size, low in power consumption, and low in cost, which is convenient for preparation into a cross array to achieve large-scale integration, and is very suitable for industrial production.

[0064] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0065] Among them, the first conductivity type is N type, and the second conductivity type is P type, and suitable materials can be selected according to needs.

[0066] Optional, reference Figure 1-Figure 4 , along the second direction Y, the width of the sub-region 111 is the same as the width of the oxide functional layer 20, and the width range of the sub-region 111 is 10μm-200μm; along the third direction Z, the thickness range of the substrate 10 is 250μm-500μm; the third direction Z is perpendicular to both the first direction X and the second direction Y; along the third direction Z, the thickness range of the oxide functional layer 20 is 10nm-40 nm; along the first direction, the width range of the electrode is 10μm-200μm; along the third direction, the thickness range of the electrode is 10nm-80 nm.

[0067] The width of the sub-region 111 is the same as the width of the oxide functional layer 20 , and the width of the sub-region 111 ranges from 10 μm to 200 μm. The process is simple and is easy to prepare into a cross array, thereby realizing large-scale integration and industrialized production.

[0068] The thickness of the substrate 10 is in the range of 250 μm to 500 μm, and the thickness of the first region 11 may be half of the thickness of the substrate 10 , which may be set according to requirements.

[0069] The thickness of the oxide functional layer 20 is in the range of 10 nm to 40 nm. The thickness of the oxide functional layer 20 may be the same as the thickness of the mask layer 40, which simplifies the process and facilitates large-scale integration and industrial production.

[0070] The width of the electrode ranges from 10μm to 200μm; the thickness of the electrode ranges from 10nm to 80nm, which can facilitate the integration of the memristor array.

[0071] Optionally, the material of the substrate includes at least one of silicon, germanium, gallium nitride, and silicon carbide; the material of the oxide functional layer includes at least one of nickel oxide, copper oxide, tungsten oxide, and hafnium oxide; the material of the electrode includes at least one of nickel, platinum, titanium, titanium nitride, and indium tin oxide; and the material of the mask layer includes at least one of silicon oxide, aluminum oxide, silicon nitride, and aluminum nitride.

[0072] Among them, the memristor array is prepared by the above materials, and the preparation process is mature, which can ensure the performance of the device.

[0073] An embodiment of the present invention provides a method for preparing a memristor array based on the above embodiment, which is used to prepare the memristor array described in any of the above embodiments; Figure 5 is a flow chart of a method for preparing a memristor array provided by an embodiment of the present invention, with reference to Figure 5 , the preparation method comprises:

[0074] S110, forming a substrate and a mask layer; the substrate is of a first conductive type; the substrate includes a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region includes a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other; the mask layer covers a portion of the second region of the substrate.

[0075] S120, forming an oxide functional layer on one side of the substrate; the oxide functional layer is of the second conductivity type, and a vertical projection of the oxide functional layer on the substrate is located within the sub-region; the oxide functional layer includes a plurality of functional units, each of which extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction.

[0076] S130, forming an electrode on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode includes a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction; the mask layer is disposed on the same layer as the oxide functional layer.

[0077] In the preparation method of the memristor array provided in the embodiment of the present invention, the first region of the substrate and the oxide functional layer form a PN heterostructure, which can effectively avoid the crosstalk problem between the memristor units, and the memristor array is a single stacking structure, which is convenient for 3D integration, thereby having low power consumption, high uniformity and the potential for multi-polar storage, and the preparation process is simple, the device unit is small in size, low in power consumption, low in cost, and is easy to prepare into a cross array to achieve large-scale integration, which is very suitable for industrial production.

[0078] The embodiment of the present invention provides a method for preparing a memristor array based on the above embodiment. The oxide functional layer formed in the embodiment of the present invention includes a plurality of functional units arranged in an array. Figure 6 is a flowchart of another method for preparing a memristor array provided by an embodiment of the present invention, with reference to Figure 6 , the preparation method comprises:

[0079] S111, providing a substrate material layer, wherein the substrate material layer is polished on one side.

[0080] Among them, the substrate material layer is first organically cleaned; the cleaning step is to put the substrate material layer in acetone, isopropanol, deionized water or acetone, ethanol, deionized water in turn and ultrasonically clean it for 5-10 minutes, then blow it dry with a nitrogen gun, repeat the organic cleaning once, and then perform inorganic cleaning. The inorganic cleaning step is: prepare SPM solution, DHF solution, APM solution or HPM solution; SPM solution includes sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) in a certain proportion; DHF solution includes hydrofluoric acid (HF); APM solution includes ammonia water (NH4OH), hydrogen peroxide (H2O2) and deionized water (H2O) in a certain proportion; HPM solution includes hydrochloric acid (HC1), ammonia water (NH4OH) and deionized water (H2O) in a certain proportion; preferably, the ratio of H2SO4 and H2O2 in the SPM solution is 1:4, and it is heated in a water bath at 120-150°C for 5 min-10min.

[0081] S112, forming a mask material layer on one side of the substrate material layer.

[0082] Wherein, a mask material layer is deposited on the substrate material layer by a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or an inductively coupled plasma chemical vapor deposition method, and the mask material layer covers the surface of the substrate material layer to be polished. Preferably, the inductively coupled plasma chemical vapor deposition method is used, the growth temperature is 50-100° C., and the process pressure is 1-10 mTorr.

[0083] S113, patterning the mask material layer to form a mask layer and a plurality of grooves; the plurality of grooves expose a portion of the substrate material layer; the grooves extend along a first direction, and the plurality of grooves are spaced apart along a second direction;

[0084] Among them, photolithography is used to define the shape of the mask material layer, and an inductively coupled plasma etching method, a reactive ion etching method, or an ion beam etching method is used to etch the mask material layer to form multiple grooves and the final shape of the mask layer, and a portion of the substrate material layer is exposed. The shape of the first area of ​​the substrate can be defined by the shape of the groove.

[0085] Specifically, the shape of the sub-area is defined by using a UV lithography process; the adhesive hexamethyldisilazane (HMDS) is sprayed on the grown hard mask layer, and after 15 minutes, it is placed in the center of the coating machine, and the photoresist is dripped on the surface after vacuum suction. The photoresist can be AZ5214 or AZ6112, and the spin coating speed is set to first spin coating at a low speed of 500 rpm for 5 seconds, and then spin coating at a high speed of 4000 rpm for 30 seconds. Then, it is pre-baked at 100°C for 120 seconds; the photomask and the sample structure are placed in the stepper lithography machine MA6, and the hard contact mode or soft contact mode or vacuum (Vac) mode or low vacuum (Low-Vac) mode or flood-E mode is selected for exposure for 1-3 seconds or 5-8 seconds or 30-60 seconds, and developed with 3038 liquid for 20-60 seconds. Subsequently, it is post-baked at 110°C for 90 seconds. After that, the sample structure is etched using an inductively coupled plasma etching method, a reactive ion etching method, or an ion beam etching method. After etching, it is removed using a fully automatic degumming machine or a plasma degumming machine or by placing it in acetone, isopropanol, deionized water, or acetone, ethanol, and deionized water and ultrasonically removing it for 5-15 minutes each twice to form multiple grooves.

[0086] S114, performing ion implantation on the exposed substrate material layer through a plurality of grooves to form a plurality of sub-regions to form a substrate.

[0087] The resistivity of the substrate is 0.001-10 ohm·cm. The exposed substrate material layer is formed into a first region by ion implantation, and the rest is an undoped substrate. Specifically, the patterned mask layer is used as a mask to dope Si atoms into the undoped substrate, with an implantation energy of 50-100 keV, an implantation depth of 100-400 nm, and a doping concentration of 10 16- 10 19 / cm2; then high temperature annealing is used to repair the damage caused by ion implantation, and the temperature is raised to 800-1200℃ in N2 atmosphere for annealing for 30-90 min to ensure the performance of the device.

[0088] S1201, forming a plurality of functional units in a plurality of trenches to form an oxide functional layer; wherein each functional unit extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction.

[0089] The oxide functional layer is formed by using a pulsed laser deposition method, a magnetron sputtering method, an atomic layer deposition method, or a sol-gel-spin coating method using a hard mask layer as a mask. Preferably, the magnetron sputtering method is used, the sputtering power is 100-150W, the O2 / Ar2 ratio is 20%-50%, the deposition pressure is 1-10 mTorr, and the oxide functional layer thickness is 10nm-40nm.

[0090] S1301, forming an electrode material layer on a side of the oxide functional layer away from the substrate.

[0091] S1302, patterning the electrode material layer to form a plurality of electrode strips to form an electrode.

[0092] The electrodes are deposited on the oxide functional layer by magnetron sputtering, electron beam evaporation or pulsed laser deposition, and the shape of the electrode strips is defined by photolithography; and the strip array electrodes arranged along the second direction are obtained after peeling. Preferably, the electron beam evaporation method is used, and the thickness of the deposited electrodes is 10nm-80nm.

[0093] Specifically, the shape of the electrode strips is defined by ultraviolet photolithography; the adhesive hexamethyldisilazane (HMDS) is sprayed on the oxide functional layer and the mask layer plane, and after 15 minutes, it is placed in the center of the coating machine, and the photoresist is dripped on the surface after vacuum suction. The photoresist can be AZ5214 or AZ6112, and the spin coating speed is set to first spin coating at a low speed of 500 rpm for 5 seconds, and then spin coating at a high speed of 4000 rpm for 30 seconds. Then, it is pre-baked at 100°C for 120 seconds; the photomask and the sample structure are placed in the stepper lithography machine MA6, and the hard contact mode or soft contact mode or vacuum (Vac) mode or low vacuum (Low-Vac) mode or flood-E mode is selected for exposure for 1-3 seconds or 5-8 seconds or 30-60 seconds, and developed with 3038 liquid for 20-60 seconds. Then, it is post-baked at 110°C for 90 seconds.

[0094] Before preparing the structure of the present invention, it is necessary to verify the forward conduction characteristics and reverse cutoff characteristics of the formed PN heterostructure. Figure 7 is a schematic diagram of a memristor array provided by an embodiment of the present invention, with reference to Figure 7The substrate 10 includes a first region, which is not shown in the figure. It can be considered that the substrate 10 is heavily N-type doped. The substrate is an N-type substrate, and an N+GaN self-supporting substrate is adopted. The n+GaN in the n+GaN substrate can also be replaced by n+Si, and n+Si can be compatible with CMOS technology; the surface of the substrate 10 adjacent to the oxide functional layer 20 is single-sided polished. Since the heavy doping makes the semiconductor conductive, the substrate 10 can also serve as a bottom electrode; the thickness of the substrate 10 is 250μm-500μm; the resistivity of the substrate 10 is 0.001 ohm·cm-10 ohm·cm.

[0095] In some embodiments, the oxide functional layer 20 uses nickel oxide (NiO) of which the conductivity type is naturally P-type. The oxide functional layer 20 can be functionally divided into a depletion layer 21 and a resistive layer 22 along the third direction; the depletion layer 21 and the substrate 10 form a PN heterostructure; the substrate 10, the resistive layer 22 and the electrode 30 form a memristor structure; specifically, the oxide functional layer 20 is located on the surface of the polished side of the substrate 10; the oxide functional layer 20 uses a pulsed laser deposition method or a magnetron sputtering method or an atomic layer deposition method or a sol-gel-spin coating method to deposit a nickel oxide thin film on the substrate layer 10 as the oxide functional layer 20. The thickness of the oxide functional layer 20 is 10 nm-40 nm.

[0096] The material of the electrode 30 is metal platinum (Pt), and the electrode 30 is a cylindrical array; the diameter of the cylindrical array of the electrode 30 is 0.1 mm-10 mm respectively; the electrode 30 is located on the side surface of the oxide functional layer 20 away from the substrate 10. The electrode 30 is deposited on the oxide functional layer 20 by a magnetron sputtering method, an electron beam evaporation method, or a pulsed laser deposition method. The thickness of the electrode 30 is 10-80 nm. A cylindrical electrode and the oxide functional layer 20 and the substrate 10 below form a memristor unit. A positive bias is applied to the electrode 30 of the selected unit of the 1D1R memristor array to put the PN heterostructure in a conducting state, and a negative bias is applied to the electrode of the selected unit of the 1D1R memristor array to put the PN heterostructure in a cut-off state, so that the applied voltage cannot be transmitted to the memristor structure, realizing the rectification function of the 1D1R memristor array and avoiding crosstalk; thus, the forward conduction and reverse cut-off performance of the PN heterostructure can be verified.

[0097] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0098] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memristor array, characterized in that: include: A substrate, the substrate is of a first conductivity type; the substrate comprises a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region comprises a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction is perpendicular to the second direction; an oxide functional layer, the oxide functional layer being of the second conductivity type, the oxide functional layer being located on one side of the substrate, and the vertical projection of the oxide functional layer on the substrate being located within the sub-region; the oxide functional layer comprising a plurality of functional units, each of the functional units extending along a first direction, and a plurality of the functional units being arranged at intervals along a second direction; An electrode, the electrode is located on a side of the oxide functional layer away from the substrate; the electrode covers a portion of the oxide functional layer; the electrode comprises a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction; A mask layer is provided at the same layer as the oxide functional layer, and the mask layer covers a portion of the second region of the substrate.

2. The memristor array according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

3. The memristor array according to claim 1, characterized in that: Along the second direction, the width of the sub-region is the same as the width of the oxide functional layer, and the width of the sub-region ranges from 10 μm to 200 μm; Along the third direction, the thickness of the substrate ranges from 250 μm to 500 μm; the third direction is perpendicular to both the first direction and the second direction; Along the third direction, the thickness of the oxide functional layer ranges from 10 nm to 40 nm; Along the first direction, the width of the electrode ranges from 10 μm to 200 μm; along the third direction, the thickness of the electrode ranges from 10 nm to 80 nm.

4. The memristor array according to claim 1, characterized in that: The material of the substrate includes at least one of silicon, germanium, gallium nitride, and silicon carbide; The material of the oxide functional layer includes at least one of nickel oxide, copper oxide, tungsten oxide and hafnium oxide; The material of the electrode includes at least one of nickel, platinum, titanium, titanium nitride, and indium tin oxide; The mask layer material includes at least one of silicon oxide, aluminum oxide, silicon nitride and aluminum nitride.

5. A method for preparing a memristor array, characterized in that: include: A substrate and a mask layer are formed; the substrate is of a first conductivity type; the substrate includes a first region and a second region, the doping concentration of the first region is greater than the doping concentration of the second region; the first region includes a plurality of sub-regions, the sub-regions extend along a first direction, and the plurality of sub-regions are arranged at intervals along a second direction; the first direction and the second direction are perpendicular to each other; the mask layer covers a portion of the second region of the substrate; An oxide functional layer is formed on one side of the substrate; the oxide functional layer is of the second conductivity type, and a vertical projection of the oxide functional layer on the substrate is located within the sub-region; the oxide functional layer includes a plurality of functional units, each of which extends along a first direction, and a plurality of the functional units are arranged at intervals along a second direction; the mask layer is disposed on the same layer as the oxide functional layer; forming an electrode on a side of the oxide functional layer away from the substrate; The electrode covers a portion of the oxide functional layer; the electrode includes a plurality of electrode strips, the electrode strips extend along the second direction, and the plurality of electrode strips are arranged at intervals along the first direction.

6. The method for preparing a memristor array according to claim 5, characterized in that: Forming a substrate and a mask layer, including: providing a substrate material layer; forming a mask material layer on one side of the substrate material layer; Patterning the mask material layer to form a mask layer and a plurality of grooves; the plurality of grooves expose a portion of the substrate material layer; the grooves extend along a first direction, and the plurality of grooves are arranged at intervals along a second direction; Performing ion implantation on the exposed substrate material layer through a plurality of grooves to form a plurality of sub-regions to form a substrate; An oxide functional layer is formed on one side of the substrate, comprising: Forming a plurality of functional units in the plurality of trenches to form an oxide functional layer; wherein each of the functional units extends along a first direction, and the plurality of functional units are arranged at intervals along a second direction; The oxide functional layer forms an electrode on a side away from the substrate, comprising: forming an electrode material layer on a side of the oxide functional layer away from the substrate; The electrode material layer is patterned to form a plurality of electrode strips to form electrodes.

7. The preparation method according to claim 5, characterized in that: An oxide functional layer is formed on one side of the substrate, comprising: An oxide functional layer is formed on one side of the substrate by a pulse laser deposition method, a magnetron sputtering method, an atomic layer deposition method, or a sol-gel-spin coating method.

8. The preparation method according to claim 5, characterized in that: Forming an electrode on a side of the oxide functional layer away from the substrate, comprising: An electrode is formed on a side of the oxide functional layer away from the substrate by magnetron sputtering, electron beam evaporation or pulse laser deposition.

9. The preparation method according to claim 6, characterized in that: A mask material layer is formed on one side of the substrate material layer, comprising: A mask material layer is formed on one side of the substrate material layer by a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method or an inductively coupled plasma chemical vapor deposition method.

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