Semi-floating gate transistor and preparation method thereof, chip and electronic equipment

Abstract

The invention discloses a semi-floating gate transistor, a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to reduce leakage current of a device. The preparation method of the semi-floating gate transistor comprises the steps that a dielectric layer is formed on a substrate, a via hole penetrating through the dielectric layer is formed, and the substrate is exposed through the via hole. And forming a plug structure made of a single crystal material in the via hole, electrically connecting the plug structure with the substrate, and forming a floating gate on the dielectric layer, and electrically connecting the floating gate with the plug structure. And forming a control gate on one side, far away from the substrate, of the floating gate, and forming a source electrode and a drain electrode on the substrate. The semi-floating gate transistor can be applied to a memory to realize reading and writing of data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semi-floating gate transistor and a preparation method thereof, a chip, and an electronic device. Background Art

[0002] A semi-floating gate transistor (SFGT) is a microelectronic device that can be used in various integrated circuits. For example, a semi-floating gate transistor can be used in a memory as a storage unit, and has the advantage of being erasable and rewritable an unlimited number of times.

[0003] However, there is leakage current in the semi-floating gate transistor, which leads to its poor data retention ability as a storage unit. Based on this, how to reduce the leakage current in the semi-floating gate transistor has become a problem that needs to be solved urgently in the field. Summary of the invention

[0004] The present application provides a semi-floating gate transistor and a preparation method thereof, a chip, and an electronic device, aiming to reduce the leakage current of the device.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, a method for preparing a semi-floating gate transistor is provided, wherein the steps of the method include: forming a dielectric layer on a substrate, forming a via hole penetrating the dielectric layer, the via hole exposing the substrate. Forming a plug structure of a single crystal material in the via hole, the plug structure being electrically connected to the substrate, and forming a floating gate on the dielectric layer, the floating gate being electrically connected to the plug structure. Forming a control gate on a side of the floating gate away from the substrate, and forming a source and a drain on the substrate.

[0007] The preparation method provided in the present application first forms a dielectric layer with a via on a substrate, wherein the via exposes the substrate. Then, a plug structure of a single crystal material is formed in the via, and a floating gate is formed on the dielectric layer, wherein the floating gate is electrically connected to the substrate through the plug structure. Finally, a control gate is formed on the side of the floating gate away from the substrate, and a source and a drain are formed on the substrate to prepare a semi-floating gate transistor.

[0008] The vias on the dielectric layer can serve as a "window" for charge transfer between the floating gate and the substrate. By forming a plug structure of single crystal material in the via, since the single crystal is composed of regularly arranged grains with the same crystal plane orientation, the leakage current of the single crystal is small, and the plug structure is equivalent to a low leakage "plug" that can block the window. In the data retention stage, the plug structure can inhibit the charge in the floating gate from flowing into the substrate through the window, thereby reducing the leakage current in the semi-floating gate transistor and improving the data retention capability of the memory equipped with the semi-floating gate transistor.

[0009] In a possible implementation, the step of forming the plug structure and the floating gate may include: forming a conductive layer, the conductive layer including a first conductive portion filling the via hole and a second conductive portion located on the dielectric layer, the first conductive portion being in contact with the substrate. Annealing the conductive layer, the first conductive portion forming the plug structure, and the second conductive portion forming the floating gate.

[0010] For example, the material of the conductive layer includes polycrystalline silicon, and at the interface where the first conductive part of the conductive layer contacts the substrate, the crystal lattice in the material of the first conductive part terminates at the interface, and the surface of the first conductive part has interface dangling bonds. The conductive layer is annealed in a hydrogen atmosphere, and hydrogen ions can penetrate into the first conductive part of the conductive layer to saturate the interface dangling bonds of the first conductive part, and under the promotion of high temperature, the crystal nucleus of the crystal of the first conductive part grows, so that the material of the first conductive part is converted from polycrystalline silicon to single crystal silicon, and a low leakage plug structure is obtained.

[0011] In a possible implementation, the atmosphere for annealing the conductive layer includes hydrogen and nitrogen.

[0012] In a possible implementation, the temperature range of annealing the conductive layer is 400° C. to 450° C.

[0013] In a possible implementation, the duration of the annealing treatment on the conductive layer is 60 minutes to 90 minutes.

[0014] In another possible implementation, the step of forming the plug structure and the floating gate may include: using a selective epitaxial process to form a plug structure on the surface of the substrate through the hole, and forming a floating gate on the dielectric layer, wherein the floating gate is electrically connected to the plug structure.

[0015] For example, if the material of the substrate is single crystal silicon, a selective epitaxial process can be used to selectively epitaxially grow single crystal silicon on the surface of the substrate through the hole using the substrate as a seed layer to form a low leakage plug structure at the window.

[0016] In a possible implementation, the temperature range of forming the plug structure by the selective epitaxial process is 400° C. to 1650° C.

[0017] In a possible implementation, the pressure of the reaction chamber of the selective epitaxial process ranges from 40 Torr to 150 Torr.

[0018] In a second aspect, a semi-floating gate transistor is provided, which includes a substrate, and a source, a drain, a dielectric layer, a plug structure of a single crystal material, a floating gate and a control gate arranged on the substrate, wherein the plug structure penetrates the dielectric layer, and the plug structure is electrically connected to a portion of the substrate located between the source and the drain. The floating gate is arranged on the dielectric layer, and the floating gate is electrically connected to the plug structure. The control gate is arranged on a side of the floating gate away from the substrate.

[0019] The semi-floating gate transistor provided in the present application is provided with a plug structure at the window between the floating gate and the substrate. The material of the plug structure includes a single crystal. The leakage current of the single crystal is small. In the data retention stage, the charge in the floating gate can be suppressed from flowing into the substrate through the window, thereby reducing the leakage current in the semi-floating gate transistor and improving the data retention capability of the memory equipped with the semi-floating gate transistor.

[0020] In a possible implementation manner, the material of the plug structure includes at least one of single crystal silicon, single crystal germanium, or single crystal silicon germanium.

[0021] In one possible implementation, the dielectric layer includes a first part and a second part, the floating gate includes a first sub-floating gate and a second sub-floating gate that are connected, the first part and the first sub-floating gate are located inside the substrate, the second part and the second sub-floating gate are located above the substrate, part of the floating gate is embedded in the substrate, the plug structure passes through the second part, and the second sub-floating gate is electrically connected to the plug structure.

[0022] In a possible implementation, the floating gate includes a first sub-floating gate and a second sub-floating gate, the dielectric layer, the first sub-floating gate and the second sub-floating gate are located inside the substrate, and the floating gate is completely embedded in the substrate. The plug structure includes a first plug and a second plug, the first plug penetrates the dielectric layer, and the first sub-floating gate is electrically connected to the first plug. The second plug penetrates the dielectric layer, and the second sub-floating gate is electrically connected to the second plug.

[0023] In one possible implementation, the thickness direction of the dielectric layer is a reference direction, and the size (thickness) of the plug structure along the reference direction is equal to the thickness of the dielectric layer, so that the thickness of the plug structure is consistent with the thickness of the dielectric layer and the thickness is relatively thin, which can avoid the need to reduce the volume of the floating gate due to the excessive thickness of the plug structure, thereby avoiding affecting the performance of the floating gate in storing charge.

[0024] In a possible implementation, the plug structure includes two surfaces opposite to each other along a reference direction, and the dielectric layer includes two surfaces opposite to each other along the reference direction. The two surfaces of the plug structure correspond to the two surfaces of the dielectric layer one by one, and the corresponding surfaces are on the same plane, so that the thickness of the plug structure is consistent with the thickness of the dielectric layer and the thickness is relatively thin, which can avoid the need to reduce the volume of the floating gate due to the excessive thickness of the plug structure, thereby avoiding affecting the performance of the floating gate in storing charge.

[0025] In a third aspect, a chip is provided, which includes a controller and the above-mentioned semi-floating gate transistor, and the semi-floating gate transistor is electrically connected to the controller.

[0026] In a fourth aspect, an electronic device is provided. The electronic device includes a circuit board and the above-mentioned chip, and the chip is electrically connected to the circuit board.

[0027] It can be understood that the beneficial effects that can be achieved by the chip and electronic device provided in the present application can refer to the beneficial effects of the semi-floating gate transistor mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of the structure of the server provided for this application;

[0029] Figure 2 The architecture diagram of the memory provided for this application;

[0030] Figure 3 A structural diagram of a semi-floating gate transistor provided in this application;

[0031] Figure 4A A schematic diagram of a write operation for a semi-floating gate transistor;

[0032] Figure 4B A schematic diagram of an erase operation for a semi-floating gate transistor;

[0033] Figure 5 A structural diagram of another semi-floating gate transistor provided by the present application;

[0034] Figure 6 A structural diagram of another semi-floating gate transistor provided by the present application;

[0035] Fig. 7A and Figure 7B Flowcharts for preparing a semi-floating gate transistor provided in this application;

[0036] Figure 8A to Figure 8K A diagram of the steps for preparing a semi-floating gate transistor provided in this application;

[0037] Fig.9A and Fig. 9B Flowcharts for preparing a semi-floating gate transistor provided in this application;

[0038] Figure 10A to Figure 10K The following are diagrams of various steps for preparing a semi-floating gate transistor provided in this application. DETAILED DESCRIPTION

[0039] For ease of understanding, the technical terms involved in this application are first introduced as follows:

[0040] Crystal: A structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.

[0041] Lattice: The atoms inside the crystal are arranged according to a certain geometric pattern, and the spatial grid of this regular arrangement of atoms is called the lattice.

[0042] Crystal plane: A plane passing through the centers of atoms in a crystal.

[0043] Nucleus: the growth center of a crystal.

[0044] Grain: Grains are small crystals with irregular shapes that make up polycrystals.

[0045] Grain boundary: the interface between grains with the same structure but different crystal plane orientations.

[0046] The present application provides an electronic device, which may be, for example, a server. The present application does not impose any particular limitation on the specific type of the electronic device.

[0047] Figure 1 A schematic diagram of the structure of the server provided for this application.

[0048] See also Figure 1 The server 1 includes a cabinet 11, a circuit board 12 disposed in the cabinet 11, and a chip 13 disposed on the circuit board 12, wherein the chip 13 is electrically connected to the circuit board 12. The circuit board 12 includes but is not limited to a printed circuit board (PCB).

[0049] The chip 13 may include a memory chip, an image sensor chip, etc. Taking the chip 13 as a memory chip as an example, the memory may include a dynamic random access memory (DRAM) and a static random access memory (SRAM). Taking the chip 13 as an image sensor chip as an example, the image sensor may be an active image sensor.

[0050] Take DRAM as an example for explanation. Figure 2 The architecture diagram of the memory provided for this application.

[0051] See also Figure 2 The memory 2 includes a storage array 21 , a row decoder 22 , a column decoder 23 , a controller 24 , a read / write control circuit 25 , and a sense amplifier 26 .

[0052] The memory array 21 includes a plurality of memory cells 210 arranged in an array, and the plurality of memory cells 210 include a plurality of rows arranged along a first direction X and a plurality of columns arranged along a second direction Y. The first direction X intersects with the second direction Y, for example, the two are perpendicular to each other.

[0053] The controller 24 is electrically connected to the row decoder 22 , the column decoder 23 , the storage array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively, and is configured to control each circuit.

[0054] The row decoder 22 is electrically connected to the memory array 21 , and is configured to select the memory cells 210 of the corresponding row according to the row address, so as to address the memory cells 210 of the corresponding row.

[0055] The column decoder 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoder 23 is configured to select the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0056] The read / write control circuit 25 is electrically connected to the memory array 21 , and the read / write control circuit 25 is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0057] The sense amplifier 26 is electrically connected to the storage array 21 and is configured to read, amplify and output the data information stored in the selected storage cell 210 to implement a data read operation; or to input a data signal to the selected storage cell 210 to implement a data write operation.

[0058] In traditional DRAM, the storage unit 210 is based on the architecture of transistors and storage capacitors. As the size of the device decreases, the architecture faces many problems, such as the decrease in the driving current of the transistor, the increase in the leakage current, the smaller and smaller the capacity of the storage capacitor, resulting in a decrease in data retention capability and an increase in power consumption; the device process is complex, and the cost rises sharply, etc. Therefore, a new type of memory is urgently needed to replace DRAM.

[0059] Semi-Floating Gate Transistor (SFGT) memory is an alternative to DRAM. The storage array 21 of the semi-floating gate transistor memory can be arranged in a 4F2 formation. The semi-floating gate transistor memory can be compatible with the controller 24 and control instructions of DRAM, that is, the read and write operations of the semi-floating gate transistor memory can be implemented using the controller 24 and control instructions of DRAM, so as to avoid as much as possible the impact on the original functions or structures of other hardware circuits related to DRAM when using the semi-floating gate transistor memory to replace DRAM, thereby reducing the cost and complexity of replacing DRAM.

[0060] The difference from DRAM is that in the semi-floating gate transistor memory, the storage unit includes a semi-floating gate transistor, and the storage unit does not carry a storage capacitor. The semi-floating gate transistor memory has the characteristics of low operating (read / write) voltage, fast operating speed, unlimited erasable times, small device size and high storage density. In addition, the preparation process of the semi-floating gate transistor is compatible with the currently mature complementary metal oxide semiconductor (CMOS) process, making the preparation process of the semi-floating gate transistor memory simple and low in cost. However, there is a leakage current defect in the semi-floating gate transistor, which leads to poor data retention ability of the semi-floating gate transistor memory. Based on this, how to reduce the leakage current in the semi-floating gate transistor has become a problem to be solved in the field.

[0061] To solve the above problems, the present application provides a semi-floating gate transistor. Figure 3 A structural diagram of a semi-floating gate transistor provided in this application.

[0062] See also Figure 3 The semi-floating gate transistor 3 includes a substrate 30 , and a source S, a drain D, a floating gate 31 and a control gate 32 arranged on the substrate 30 . The floating gate 31 is located between the source S and the drain D, and the control gate 32 is arranged on a side of the floating gate 31 away from the substrate 30 .

[0063] Exemplarily, the substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a. The material of the p-well 30a includes a p-type semiconductor material, the material of the n-well 30b includes an n-type semiconductor material, and the source S and the drain D are located on the n-well 30b.

[0064] Continue to see Figure 3 The semi-floating gate transistor 3 further includes a first dielectric layer 33, which is disposed between the floating gate 31 and the substrate 30. A via H is provided on the first dielectric layer 33, which can serve as a "window" for charge transfer between the floating gate 31 and the substrate 30.

[0065] Exemplarily, the projection of the via H on the plane XY may be circular or rectangular. When the via H is circular, the diameter of the via H is in the range of 10 nm to 20 nm. When the via H is rectangular, the length of the via H is in the range of 10 nm to 20 nm, and the width is in the range of 10 nm to 20 nm.

[0066] Figure 4A A schematic diagram of a write operation for a semi-floating gate transistor; Figure 4B Schematic diagram of the erase operation of a semi-floating gate transistor.

[0067] See also Figure 4AA write operation voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor 3. For example, the operation voltage received by the control gate 32 is -1.5V, the source S is connected to the ground terminal GND, and the operation voltage of the drain D is 3V. Under the action of the electric field, positive charges enter the floating gate 31 from the drain D and the n-well 30b through the hole H. The positive charges in the floating gate 31 increase, causing the threshold voltage of the semi-floating gate transistor 3 to decrease, thereby realizing the writing of data (writing data "1").

[0068] Based on this, by applying a fixed read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor 3, the threshold voltage of the semi-floating gate transistor 3 is low, so that the semi-floating gate transistor 3 is fully turned on, and a large drain-source current I is generated between the drain D and the source S. ds , at this time the data "1" can be read.

[0069] See also Figure 4B , an operating voltage is applied to the control gate 32, source S and drain D of the semi-floating gate transistor 3. For example, the operating voltage received by the control gate 32 is 1.2V, the source S is connected to the ground terminal GND, and the operating voltage of the drain D is 0.6V. Under the action of the electric field, the positive charge enters the n-well 30b and the drain D from the floating gate 31 through the hole H, and the positive charge in the floating gate 31 is reduced, so that the threshold voltage of the semi-floating gate transistor 3 is increased, thereby realizing data erasure (also known as: writing data "0").

[0070] Based on this, by applying the same read operation voltage to the control gate 32, source S and drain D of the semi-floating gate transistor 3, due to the high threshold voltage of the semi-floating gate transistor 3, the semi-floating gate transistor 3 is not fully turned on, and a small drain-source current I is generated between the drain D and the source S. ds , at this time the data "0" can be read.

[0071] The inventors of the present application have discovered that in the semi-floating gate transistor 3, the material of the floating gate 31 is a polycrystalline material, for example, the polycrystalline material may include polycrystalline silicon, and the polycrystalline silicon is composed of irregularly arranged grains with different crystal plane orientations. The grain boundaries of the polycrystalline silicon present complex grain structures and structural defects, so that leakage channels are formed at the grain boundaries, resulting in poor data retention capability of the semi-floating gate transistor 3.

[0072] For example, the data "1" stored in the semi-floating gate transistor 3, during the data retention stage, due to the existence of the leakage channel in the polysilicon, the positive charge in the floating gate 31 will be lost through the window (via H), and leakage current will be generated at the window. The threshold voltage of the semi-floating gate transistor 3 will increase. During the data reading stage, the data "0" will be read in the semi-floating gate transistor 3, and the data "1" stored in the semi-floating gate transistor 3 will be lost, making its data retention capability poor.

[0073] Based on this, see again Figure 3 The semi-floating gate transistor 3 further includes a plug structure 34, which is disposed in the via H to penetrate the first dielectric layer 33. The plug structure 34 is electrically connected to a portion of the substrate 30 between the source S and the drain D, for example, the plug structure 34 is electrically connected to the n-well 30b, and the plug structure 34 is also electrically connected to the floating gate 31. It can be understood that, at the window, the floating gate 31 and the n-well 30b are separated by the plug structure 34. The material of the plug structure 34 includes a single crystal, and the single crystal may include, for example, at least one of single crystal silicon, single crystal germanium, or single crystal silicon germanium (chemical formula: SiGe).

[0074] By setting a plug structure 34 at the window, the material of the plug structure 34 includes a single crystal, and the single crystal is composed of grains that are regularly arranged and have the same crystal plane orientation. The leakage channel of the single crystal is less than that of the polycrystalline. The plug structure 34 is equivalent to a low leakage "plug" that can block the window. In the data retention stage, the positive charge in the floating gate 31 can be suppressed from flowing into the n-well 30b through the window, thereby reducing the leakage current in the semi-floating gate transistor 3 and improving the data retention capability of the semi-floating gate transistor memory.

[0075] See also Figure 3 The semi-floating gate transistor 3 further includes a split gate (also referred to as a "select gate") 35, which is located on the side of the control gate 32 close to the drain D. Therefore, the semi-floating gate transistor 3 can be referred to as a "split-gate semi-floating gate transistor". A second dielectric layer 36 is provided between the control gate 32 and the split gate 35 to achieve insulation between the two. In addition, a second dielectric layer 36 is also provided between the control gate 32 and the floating gate 31 to achieve insulation between the two.

[0076] See also Figure 3 The semi-floating gate transistor 3 also includes a spacer layer 37. Typically, a plurality of semi-floating gate transistors 3 are arranged on the substrate 30, and the spacer layer 37 is located between two adjacent semi-floating gate transistors 3 to separate the floating gate 31, the control gate 32 and the sub-gate 35 of the two adjacent semi-floating gate transistors 3 to achieve insulation between the devices.

[0077] Figure 5 This is a structural diagram of another semi-floating gate transistor provided in this application.

[0078] See also Figure 5 The floating gate 31 of the semi-floating gate transistor 3 includes a first sub-floating gate 31a and a second sub-floating gate 31b connected to each other, the first dielectric layer 33 includes a first part 33a and a second part 33b, the first sub-floating gate 31a and the first part 33a are located inside the substrate 30, and the second sub-floating gate 31b and the second part 33b are located above the substrate 30, that is, part of the floating gate 31 (the first sub-floating gate 31a) is embedded in the substrate 30, and the semi-floating gate transistor 3 can be called a "trench gate type semi-floating gate transistor".

[0079] Continue to see Figure 5 The plug structure 34 penetrates the second portion 33 b of the first dielectric layer 33 , and the second sub-floating gate 31 b of the floating gate 31 is electrically connected to the plug structure 34 .

[0080] By adopting a design in which the floating gate 31 is partially embedded in the substrate 30, the size of the floating gate 31 along the direction Z (the thickness direction of the device) is increased. While ensuring that the performance of the floating gate 31 in storing charges remains unchanged, the area of ​​the floating gate 31 along the plane XY can be reduced, which is beneficial to reducing the occupied area of ​​the device.

[0081] and Figure 3 The difference between the semi-floating gate transistor shown in Figure 5 The semi-floating gate transistor 3 shown in FIG. 1 does not include a split gate 35. Figure 5 The control gate 32 of the half-floating gate transistor 3 is equivalent to, Figure 3 The control gate 32 and the sub-gate 35 of the middle half-floating gate transistor 3 are integrated into one structure.

[0082] Figure 6 A structural diagram of another semi-floating gate transistor provided in this application, Figure 5 The difference between the semi-floating gate transistor is that, Figure 6 The floating gate in the FET is divided into two parts and both are embedded in the substrate, as follows:

[0083] See also Figure 6 The floating gate 31 of the half-floating gate transistor 3 includes a first sub-floating gate 31a and a second sub-floating gate 31b. The first dielectric layer 33, the first sub-floating gate 31a and the second sub-floating gate 31b are all located inside the substrate 30. The first sub-floating gate 31a and the second sub-floating gate 31b are all embedded in the substrate 30, and the first sub-floating gate 31a and the second sub-floating gate 31b extend along the direction Z. Therefore, the half-floating gate transistor 3 can be called a "vertical half-floating gate transistor".

[0084] Continue to see Figure 6 The plug structure 34 includes a first plug 34a and a second plug 34b. The first plug 34a penetrates the first dielectric layer 33, and the first sub-floating gate 31a is electrically connected to the first plug 34a. The second plug 34b also penetrates the first dielectric layer 33, and the second sub-floating gate 31b is electrically connected to the second plug 34b.

[0085] Exemplarily, the first sub-floating gate 31a is not connected to the second sub-floating gate 31b, and the sub-gate 35 is located between the first sub-floating gate 31a and the second sub-floating gate 31b, so that the first sub-floating gate 31a and the second sub-floating gate 31b share the sub-gate 35.

[0086] By adopting a design in which the floating gate 31 is fully embedded in the substrate 30, the size of the floating gate 31 along the direction Z is further increased. While ensuring the charge storage performance of the floating gate 31 remains unchanged, the area of ​​the floating gate 31 along the plane XY can be reduced, which is beneficial to reducing the occupied area of ​​the device.

[0087] by Figure 3 Taking the semi-floating gate transistor shown in as an example, the present application provides a method for preparing the semi-floating gate transistor. Fig. 7A and Figure 7B Flowcharts for preparing a semi-floating gate transistor provided in this application; Figure 8A to Figure 8K The following are diagrams of various steps for preparing a semi-floating gate transistor provided in this application.

[0088] See also Fig. 7A The method for preparing a semi-floating gate transistor includes the following steps S10 to S50:

[0089] S10: See Fig. 8A and Figure 8B , a first dielectric layer 33 is formed on the substrate 30.

[0090] For example, see Fig. 8A A substrate 30 is formed on a substrate 4, wherein the substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a. Then, a photolithography process is used to etch the substrate 30 to form a trench C1.

[0091] See also Figure 8B A first dielectric layer 33 and a mask layer K are sequentially formed on the surface of the substrate 30 by a thin film deposition process, and then a surface of the mask layer K away from the substrate 30 is polished by a chemical mechanical polishing (CMP) process to improve the surface flatness of the mask layer K.

[0092] S20: See Figure 8C , a via hole H penetrating the first dielectric layer 33 is formed, and the via hole H exposes the substrate 30 .

[0093] Exemplarily, a photolithography process is adopted to etch the mask layer K, and the mask layer K is used as a mask to etch the first dielectric layer 33 to form a via H penetrating the first dielectric layer 33 , so as to “open a window” on the first dielectric layer 33 .

[0094] S30: See Figure 8C to Figure 8E , forming a plug structure 34 and a floating gate 31, the plug structure 34 is located in the via hole H of the first dielectric layer 33, and the plug structure 34 is electrically connected to the substrate 30, and the material of the plug structure 34 includes a single crystal. The floating gate 31 is located on the first dielectric layer 33, and the floating gate 31 is electrically connected to the plug structure 34.

[0095] For example, see Figure 7B , the above S30 may include the following S31-S32:

[0096] S31: See Figure 8C and Fig.8D The material of the mask layer K can be the same as that of the floating gate 31, for example, both include polysilicon. Based on this, a thin film deposition process can be used to deposit polysilicon material to fill the mask layer K. Then, a chemical mechanical polishing process is used to polish the surface of the mask layer K away from the substrate 30, and the obtained mask layer K is used as the conductive layer L.

[0097] See also Fig.8D The conductive layer L includes a first conductive portion L1 filling the via hole H, and a second conductive portion L2 located on the first dielectric layer 33 , and the first conductive portion L1 contacts the substrate 30 .

[0098] S32: See Fig.8D and Fig. 8E , the conductive layer L is annealed, the first conductive portion L1 of the conductive layer L forms a plug structure 34 , and the second conductive portion L2 forms a floating gate 31 .

[0099] It can be understood that at the interface where the first conductive part L1 of the conductive layer L contacts the substrate 30, the crystal lattice in the material of the first conductive part L1 terminates at the interface, and each atom in the outermost layer of the surface of the first conductive part L1 will have an unpaired electron, that is, an unsaturated bond, which is called an interface dangling bond.

[0100] The conductive layer L is annealed in a hydrogen atmosphere, and hydrogen ions can penetrate into the first conductive part L1 of the conductive layer L to saturate the interface dangling bonds of the first conductive part L1. Under the promotion of high temperature, the crystal nucleus of the first conductive part L1 grows, so that the material of the first conductive part L1 is converted from polycrystalline silicon to single crystal silicon, so as to obtain a low leakage plug structure 34 at the window.

[0101] The second conductive portion L2 of the conductive layer L does not react with the hydrogen ions, so the material of the second conductive portion L2 is still polysilicon, and the second conductive portion L2 can serve as the floating gate 31 .

[0102] The process conditions of the annealing treatment may, for example, include: the atmosphere of the annealing treatment may include nitrogen in addition to hydrogen, and the volume ratio of hydrogen to nitrogen is 1:5; the annealing treatment is under normal pressure, and the temperature range is 400°C to 450°C, for example, the temperature of the annealing treatment is 400°C, 415°C, 425°C, 435°C or 450°C; the annealing treatment duration is 60 minutes to 90 minutes, for example, the annealing treatment duration is 60 minutes, 65 minutes, 75 minutes, 85 minutes or 90 minutes.

[0103] S40: See Fig.8F, forming a control gate 32 , which is located on a side of the floating gate 31 away from the substrate 30 .

[0104] Exemplarily, the second dielectric layer 36 is first formed on the surface of the floating gate 31 , and then a conductive material is deposited on the surface of the second dielectric layer 36 . The upper surface of the conductive material is polished using a chemical mechanical polishing process to form the control gate 32 .

[0105] See also Fig.8F and Figure 8G After forming the control gate 32, the control gate 32, the second dielectric layer 36, the floating gate 31 and the first dielectric layer 33 are etched to form a trench C2.

[0106] See also Figure 8G and Figure 8H , a third dielectric layer 38 and a split gate 35 are sequentially formed on the surface of the trench C2.

[0107] See also Figure 8H and Fig.8I , the gate 35 and the third dielectric layer 38 are etched to form a trench C3.

[0108] See also Fig.8I and Figure 8J A spacer 37 is formed on the sidewall of the trench C3, and the bottom of the spacer 37 exposes the substrate 30. The spacer 37 can disconnect the floating gate 31, the control gate 32 and the split gate 35 of two adjacent half-floating gate transistors 3, thereby achieving insulation between the two adjacent half-floating gate transistors 3.

[0109] S50: See Figure 8K , a source S and a drain D are formed on the substrate 30 .

[0110] Exemplarily, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing process is performed to form a source S and a drain D on the substrate 30 .

[0111] The preparation method provided in the present application first forms a first dielectric layer 33 on a substrate 30, and forms a through-hole H on the first dielectric layer 33, wherein the through-hole H exposes the substrate 30. Then, a plug structure 34 made of a single crystal material is formed in the through-hole H, wherein the plug structure 34 is electrically connected to the substrate 30, and a floating gate 31 is formed on the first dielectric layer 33, wherein the floating gate 31 is electrically connected to the plug structure 34. Finally, a control gate 32 is formed on a side of the floating gate 31 away from the substrate 30, and a source S and a drain D are formed on the substrate 30.

[0112] By forming a plug structure 34 made of a single crystal material in the via H, the single crystal is a low leakage material. During the data retention stage, the plug structure 34 can suppress the positive charge in the floating gate 31 from flowing into the n-well 30b of the substrate 30 through the hole H, thereby reducing the leakage current in the semi-floating gate transistor 3 and improving the data retention capability of the semi-floating gate transistor memory.

[0113] The present application also provides another method for preparing a semi-floating gate transistor. Fig.9A and Fig. 9B Flowcharts for preparing a semi-floating gate transistor provided in this application; Figure 10A to Figure 10K The following are diagrams of various steps for preparing a semi-floating gate transistor provided in this application.

[0114] See also Fig.9A The method for preparing a semi-floating gate transistor includes the following steps S60 to S100:

[0115] S60: See Fig. 10A and Fig. 10B , a first dielectric layer 33 is formed on the substrate 30.

[0116] For example, see Fig. 10A A substrate 30 is formed on a substrate 4, wherein the substrate 30 includes a p-well 30a and an n-well 30b disposed on the p-well 30a. Then, a photolithography process is used to etch the substrate 30 to form a trench C1.

[0117] See also Fig. 10B A first dielectric layer 33 and a mask layer K are sequentially formed on the surface of the substrate 30 by a thin film deposition process, and then a surface of the mask layer K away from the substrate 30 is polished by a chemical mechanical polishing process to improve the surface flatness of the mask layer K.

[0118] S70: See Fig. 10C , a via hole H penetrating the first dielectric layer 33 is formed, and the via hole H exposes the substrate 30 .

[0119] Exemplarily, a photolithography process is adopted to etch the mask layer K, and the mask layer K is used as a mask to etch the first dielectric layer 33 to form a via H penetrating the first dielectric layer 33 , so as to “open a window” on the first dielectric layer 33 .

[0120] S80: See Fig. 10D and Fig.10E , forming a plug structure 34 and a floating gate 31, wherein the plug structure 34 is located in the via hole H of the first dielectric layer 33 and is electrically connected to the substrate 30. The floating gate 31 is located on the first dielectric layer 33 and is electrically connected to the plug structure 34.

[0121] For example, see Fig. 9B , the above S80 may include the following S81-S82:

[0122] S81: See Fig. 10D , a plug structure 34 is formed on the surface of the substrate 30 through the hole H by using a selective epitaxial process.

[0123] For example, the n-well 30b in the substrate 30 is made of single crystal silicon, and a chemical vapor deposition (CVD) device can be used to selectively epitaxially grow single crystal silicon on the surface of the substrate 30 through the hole H using the substrate 30 as a seed layer to form a low leakage plug structure 34 at the window.

[0124] The process conditions for selective epitaxy may include, for example: a temperature range of the equipment reaction chamber is 400°C to 1650°C, for example, the temperature of the equipment reaction chamber is 400°C, 700°C, 1025°C, 1300°C or 1650°C; a pressure range of the equipment reaction chamber is 40 Torr to 150 Torr, for example, the pressure of the equipment reaction chamber is 40 Torr, 70 Torr, 95 Torr, 125 Torr or 150 Torr.

[0125] It is understandable that the selective epitaxial process is mature and the thickness of the grown film layer is controllable. Taking the thickness direction of the first dielectric layer 33 as the reference direction, for example, Fig. 10D The reference direction in the figure is direction Z, and the size of the plug structure 34 along direction Z can be controlled by adjusting the process parameters.

[0126] For example, the size of the plug structure 34 along the direction Z is equal to the thickness of the first dielectric layer 33. For another example, two opposite surfaces of the plug structure 34 along the direction Z correspond to two opposite surfaces of the first dielectric layer 33 along the direction Z, and the corresponding surfaces are on the same plane. That is, the thickness of the plug structure 34 is controlled to be as thin as the thickness of the first dielectric layer 33, so as to avoid the size of the floating gate 31 being too small due to the excessive thickness of the plug structure 34, thereby avoiding affecting the performance of the floating gate 31 in storing charges.

[0127] S82: See Fig. 10D and Fig.10E , a floating gate 31 is formed. The floating gate 31 is located on the first dielectric layer 33 , and the floating gate 31 is electrically connected to the plug structure 34 .

[0128] Exemplarily, the material of the mask layer K may be the same as that of the floating gate 31 , for example, both may include polysilicon. Based on this, a thin film deposition process may be used to deposit polysilicon material to fill the mask layer K. Then, a chemical mechanical polishing process may be used to polish the surface of the mask layer K away from the substrate 30 , and the obtained mask layer K is used as the floating gate 31 .

[0129] S90: See Fig.10F, forming a control gate 32 , which is located on a side of the floating gate 31 away from the substrate 30 .

[0130] Exemplarily, the second dielectric layer 36 is first formed on the surface of the floating gate 31 , and then a conductive material is deposited on the surface of the second dielectric layer 36 . The upper surface of the conductive material is polished using a chemical mechanical polishing process to form the control gate 32 .

[0131] See also Fig.10F and Figure 10G After forming the control gate 32, the control gate 32, the second dielectric layer 36, the floating gate 31 and the first dielectric layer 33 are etched to form a trench C2.

[0132] See also Figure 10G and Fig. 10H , a third dielectric layer 38 and a split gate 35 are sequentially formed on the surface of the trench C2.

[0133] See also Fig. 10H and Fig.10I , the gate 35 and the third dielectric layer 38 are etched to form a trench C3.

[0134] See also Fig.10I and Fig.10J A spacer 37 is formed on the sidewall of the trench C3, and the bottom of the spacer 37 exposes the substrate 30. The spacer 37 can disconnect the floating gate 31, the control gate 32 and the split gate 35 of two adjacent half-floating gate transistors 3, thereby achieving insulation between the two adjacent half-floating gate transistors 3.

[0135] S100: See Figure 10K , a source S and a drain D are formed on the substrate 30 .

[0136] Exemplarily, an ion implantation process is used to implant n-type ions into the n-well 30 b of the substrate 30 , and an annealing process is performed to form a source S and a drain D on the substrate 30 .

[0137] In addition, the semi-floating gate transistor 3 provided in the present application can also be used as a photoelectric sensor, and the photoelectric sensor can be applied to an active image sensor to realize image acquisition.

[0138] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for preparing a semi-floating gate transistor, characterized in that: include: forming a dielectric layer on the substrate; forming a via hole penetrating the dielectric layer, wherein the via hole exposes the substrate; forming a plug structure and a floating gate, wherein the plug structure is located in the via hole and is electrically connected to the substrate, and the material of the plug structure includes a single crystal; the floating gate is located on the dielectric layer and is electrically connected to the plug structure; forming a control gate, wherein the control gate is located on a side of the floating gate away from the substrate; A source electrode and a drain electrode are formed on the substrate.

2. The preparation method according to claim 1, characterized in that: The forming of the plug structure and the floating gate comprises: forming a conductive layer, wherein the conductive layer comprises a first conductive portion filling the via hole and a second conductive portion located on the dielectric layer, wherein the first conductive portion contacts the substrate; The conductive layer is annealed, the first conductive portion forms the plug structure, and the second conductive portion forms the floating gate.

3. The preparation method according to claim 2, characterized in that: The annealing process is performed in an atmosphere including hydrogen and nitrogen.

4. The preparation method according to claim 2 or 3, characterized in that: The temperature range of the annealing treatment is 400°C to 450°C.

5. The preparation method according to any one of claims 2 to 4, characterized in that: The annealing treatment lasts for 60 to 90 minutes.

6. The preparation method according to claim 1, characterized in that: The forming of the plug structure and the floating gate comprises: Using a selective epitaxial process, a plug structure is formed on the surface of the substrate through the via hole; The floating gate is formed, and the floating gate is located on the dielectric layer and is electrically connected to the plug structure.

7. The preparation method according to claim 6, characterized in that: The temperature range of the selective epitaxial process is 400°C to 1650°C.

8. The preparation method according to claim 6 or 7, characterized in that: The pressure range of the reaction chamber of the selective epitaxial process is 40 Torr to 150 Torr.

9. A semi-floating gate transistor, characterized in that: include: substrate; A source electrode and a drain electrode are arranged on the substrate; A dielectric layer is disposed on the substrate; A plug structure, penetrating the dielectric layer and electrically connected to a portion of the substrate located between the source and the drain; A floating gate, disposed on the dielectric layer and electrically connected to the plug structure; A control gate is disposed on a side of the floating gate away from the substrate; Wherein, the material of the plug structure includes single crystal.

10. The semi-floating gate transistor according to claim 9, characterized in that: The material of the plug structure includes at least one of single crystal silicon, single crystal germanium or single crystal silicon germanium.

11. The semi-floating gate transistor according to claim 9 or 10, characterized in that: The dielectric layer includes a first portion and a second portion, and the floating gate includes a first sub-floating gate and a second sub-floating gate connected to each other; The first portion and the first sub-floating gate are located inside the substrate, and the second portion and the second sub-floating gate are located above the substrate; The plug structure passes through the second portion, and the second sub-floating gate is electrically connected to the plug structure.

12. The semi-floating gate transistor according to claim 9 or 10, characterized in that: The floating gate includes a first sub-floating gate and a second sub-floating gate; The dielectric layer, the first sub-floating gate and the second sub-floating gate are located inside the substrate; The plug structure includes a first plug and a second plug. The first plug penetrates the dielectric layer, and the first sub-floating gate is electrically connected to the first plug. The second plug penetrates the dielectric layer, and the second sub-floating gate is electrically connected to the second plug.

13. The semi-floating gate transistor according to any one of claims 9 to 12, characterized in that: The thickness direction of the dielectric layer is a reference direction; The dimension of the plug structure along the reference direction is equal to the thickness of the dielectric layer.

14. The semi-floating gate transistor according to any one of claims 9 to 13, characterized in that: The thickness direction of the dielectric layer is a reference direction; The plug structure includes two surfaces opposite to each other along the reference direction, and the dielectric layer includes two surfaces opposite to each other along the reference direction. The two surfaces of the plug structure correspond to the two surfaces of the dielectric layer in a one-to-one manner and are coplanar.

15. A chip, characterized in that: include: The semi-floating gate transistor according to any one of claims 9 to 14; A controller is electrically connected to the semi-floating gate transistor.

16. An electronic device, characterized in that: include: The chip as claimed in claim 15; A circuit board, wherein the chip is electrically connected to the circuit board.

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