IGBT device and manufacturing method thereof

Abstract

The invention provides an IGBT (Insulated Gate Bipolar Translator) device and a manufacturing method thereof, the IGBT device comprises an N-type semiconductor layer and a plurality of grooves located in the N-type semiconductor layer, gate electrodes are arranged in the grooves, and the gate electrodes are insulated and isolated from the N-type semiconductor layer through gate dielectric layers; the P-type body region is located between the adjacent grooves, and an N-type emitter region is arranged in the P-type body region; the N-type carrier storage layer is positioned below the P-type body region and is positioned between the adjacent grooves; the bottom of each groove is provided with a P-type protection layer, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove. The IGBT device adopts the shallow trench, so that the on-state voltage drop can be reduced, and the process yield can be improved; the bottom of the groove is surrounded by the P-type protection layer, so that local charge balance can be formed, and voltage resistance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to an IGBT device and a manufacturing method thereof. Background Art

[0002] The insulated gate bipolar transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and a MOS (Metal-Oxide-Semiconductor) transistor. It has the advantages of low driving power and fast switching speed of MOS transistors, as well as low saturation voltage drop and large capacity of bipolar transistors. It is very suitable for use in converter systems with a DC voltage of 600V or above, such as AC motors, inverters, switching power supplies, lighting circuits, traction drives, and other fields. The IGBT of the prior art usually adopts deep trench technology, and at the same time, a carrier storage layer is added to increase the surface carrier concentration. The higher the doping concentration of the carrier storage layer, the more the surface carrier concentration accumulates, the lower the on-state voltage drop of the device, and the lower the power consumption. However, the increase in the doping concentration of the carrier storage layer will lead to a decrease in the withstand voltage of the device; moreover, the deep trench process makes the stress of the wafer larger, and the wafer is prone to warping problems, which affects the manufacturing yield of the IGBT. Summary of the invention

[0003] In view of this, an object of the present invention is to provide an IGBT device and a method for manufacturing the same, which can improve the withstand voltage of the IGBT while increasing the doping concentration of the carrier storage layer.

[0004] The present invention provides an IGBT device, comprising:

[0005] An N-type semiconductor layer, and located in the N-type semiconductor layer:

[0006] A plurality of trenches, each of which is provided with a gate electrode, and the gate electrode is insulated and isolated from the N-type semiconductor layer by a gate dielectric layer;

[0007] A P-type body region located between adjacent grooves, wherein an N-type emitter region is provided in the P-type body region;

[0008] An N-type carrier storage layer located below the P-type body region and between adjacent trenches;

[0009] A P-type protection layer is provided at the bottom of each trench. The P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the trench.

[0010] Furthermore, a middle portion of the N-type carrier storage layer extends downwardly to between adjacent P-type protection layers, and a lower surface of the P-type protection layer is lower than a lower surface of the N-type carrier storage layer.

[0011] Furthermore, it also includes a shielding electrode located in the trench, the gate electrode is located on both sides of the shielding electrode, and the gate electrode is insulated and isolated from the shielding electrode.

[0012] Furthermore, it also includes an N-type field stop region and a P-type collector region located at the bottom of the N-type semiconductor layer, and the N-type field stop region is located above the P-type collector region.

[0013] The present invention provides a method for manufacturing an IGBT device, comprising:

[0014] S1: forming a mask layer on the provided N-type semiconductor layer, and then forming a mask layer opening in the mask layer by photolithography and etching processes;

[0015] S2: etching the N-type semiconductor layer to form a plurality of grooves arranged in sequence in the N-type semiconductor layer;

[0016] S3: performing inclined N-type ion implantation in the N-type semiconductor layer to form an N-type carrier storage layer located at the bottom of the trench;

[0017] S4: performing P-type ion implantation in the N-type semiconductor layer to form a P-type protective layer located at the bottom of the trench, wherein a lower surface of the P-type protective layer is lower than a lower surface of the N-type carrier storage layer;

[0018] S5: forming a gate dielectric layer on the surface of the trench, then depositing a polysilicon layer and etching back to form a gate electrode in the trench;

[0019] S6: removing the mask layer, and then performing P-type ion implantation to form a P-type body region in the N-type semiconductor layer, wherein the P-type body region is located between adjacent trenches;

[0020] S7: performing N-type ion implantation to form an N-type emitter region in the P-type body region;

[0021] S8: Perform high temperature annealing to diffuse the N-type carrier storage layer and the P-type protection layer to predetermined positions, wherein the N-type carrier storage layer is located below the P-type body region, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove.

[0022] Further, the S2 includes:

[0023] S21: etching the N-type semiconductor layer to form a plurality of grooves arranged in sequence in the N-type semiconductor layer;

[0024] S22: performing isotropic etching so that the width of the groove is greater than the width of the mask opening.

[0025] The S5 includes:

[0026] S51: forming a gate dielectric layer on the surface of the trench, then depositing a polysilicon layer and etching back to form a gate electrode in the trench, wherein the gate electrode is located at a sidewall position of the trench;

[0027] S52: forming an insulating dielectric layer to cover the exposed surface of the gate electrode, then depositing a polysilicon layer and etching back to form a shielding electrode in the trench, wherein the shielding electrode is insulated and isolated from the gate electrode and the N-type semiconductor layer by the insulating dielectric layer.

[0028] Furthermore, S8 includes: performing high temperature annealing so that the N-type carrier storage layer and the P-type protective layer diffuse to predetermined positions, the N-type carrier storage layer is located below the P-type body region, the P-type protective layer is located below the N-type carrier storage layer and surrounds the bottom of the groove, the middle part of the N-type carrier storage layer extends downward between adjacent P-type protective layers, and the lower surface of the P-type protective layer is lower than the lower surface of the carrier storage layer.

[0029] Furthermore, the S4 includes: performing vertical P-type ion implantation to form a P-type protective layer on the N-type semiconductor layer, wherein the lower surface of the P-type protective layer is lower than the lower surface of the N-type carrier storage layer.

[0030] An IGBT device provided by the present invention has a P-type protective layer at the bottom of the gate. Firstly, the P-type protective layer can protect the gate electrode and increase the effective curvature of the groove; secondly, the P-type protective layer forms a charge balance with the N-type carrier storage layer, which can increase the doping concentration of the N-type carrier storage layer while ensuring that the withstand voltage of the device will not be reduced.

[0031] The present invention provides a method for manufacturing an IGBT device, which adopts a shallow trench technology, can reduce the stress of the wafer, improve the flatness and warping problems of the wafer, and further reduce the epitaxial thickness of the wafer, thereby further reducing the on-state voltage drop of the IGBT device; at the same time, the ion implantation of the N-type carrier storage layer and the P-type protective layer at the bottom of the trench adopts a self-aligned form, and the process consistency is good, which can further improve the manufacturing yield of the IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following is a brief introduction to the drawings required for describing the embodiments. It should be noted that in the drawings, for the convenience of explanation, the thickness of the layers and regions are exaggerated, and the sizes shown do not represent the actual sizes. The drawings are schematic diagrams of idealized embodiments of the present invention, and the embodiments shown in the present invention should not be considered to be limited to the specific shapes of the regions shown in the drawings, but include the resulting shapes, such as deviations caused by manufacturing.

[0033] Figure 1 It is a schematic cross-sectional structure diagram of a first embodiment of an IGBT device provided by the present invention;

[0034] Figure 2 is a schematic cross-sectional structural diagram of a second embodiment of an IGBT device provided by the present invention;

[0035] Figures 3 to 10 It is a schematic cross-sectional structure diagram of main process nodes of an embodiment of a method for manufacturing an IGBT device of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0037] Figure 1 FIG. 1 is a schematic cross-sectional view of a first embodiment of an IGBT device provided by the present invention. Figure 1 As shown, an IGBT device of the present invention includes: an N-type semiconductor layer 101, and a plurality of trenches 102 located in the N-type semiconductor layer 101, a gate electrode 103 is arranged in the trench 102, and the gate electrode 103 is insulated and isolated from the N-type semiconductor layer 101 by a gate dielectric layer 104. The material of the N-type semiconductor layer 101 is generally silicon, and the material of the gate electrode 103 can be polysilicon or metal.

[0038] A P-type body region 105 is located between adjacent trenches 102 , and an N-type emitter region 106 is disposed in the P-type body region 105 . An N-type carrier storage layer 107 is located below the P-type body region 105 and between adjacent trenches 102 .

[0039] A P-type protective layer 108 is provided at the bottom of each trench 102, and the P-type protective layer 108 is located below the N-type carrier storage layer 107 and surrounds the bottom of the trench 102. The P-type protective layer 108 surrounds the bottom of the trench 102, which can protect the gate electrode 103 and increase the effective curvature of the trench 102; at the same time, the P-type protective layer 108 and the N-type carrier storage layer 107 can form a local charge balance, which can effectively improve the withstand voltage of the IGBT device.

[0040] The IGBT device of the present invention further includes an N-type field stop region 110 and a P-type collector region 111 located at the bottom of the N-type semiconductor layer 101 . The N-type field stop region 110 is located above the P-type collector region 111 .

[0041] Figure 2 is a schematic cross-sectional structure diagram of a second embodiment of an IGBT device provided by the present invention, such as Figure 2 As shown, a shielding electrode 112 may be further provided in the groove 102 of the IGBT device of the present invention, and gate electrodes 113a and 113b are located on both sides of the shielding electrode 112. The gate electrodes 113a and 113b are insulated and isolated from the shielding electrode 112 by an insulating dielectric layer 114. The IGBT device of this embodiment adopts a split-gate structure, which can reduce parasitic capacitance, thereby reducing switching losses of the IGBT device.

[0042] Figures 3 to 10 FIG. 1 is a schematic cross-sectional structure diagram of the main process nodes of an embodiment of the method for manufacturing an IGBT device of the present invention. Figures 3 to 10 As shown, the manufacturing method of the IGBT device of the present invention comprises:

[0043] First, if Figure 3 As shown, a mask layer 202 is formed on the provided N-type semiconductor layer 201 , and then the position of the mask layer opening is defined by photolithography, and then the mask layer 202 is etched to form a mask opening 212 in the mask layer 202 .

[0044] Next, if Figure 4 As shown, the N-type semiconductor layer 201 is etched using the mask layer 202 as a mask to form a plurality of trenches 202 arranged in sequence in the N-type semiconductor layer 201 .

[0045] In a preferred embodiment, when forming the groove 202, the N-type semiconductor layer 201 can be etched using the mask layer 202 as a mask to form a plurality of grooves arranged in sequence in the N-type semiconductor layer 201, and then isotropic etching is performed to increase the width of the formed groove, so that the width of the formed groove 209 is greater than the width of the mask layer opening 212, such as Figure 5 shown.

[0046] Next, if Figure 6 and Figure 7 As shown, an N-type carrier storage layer 203 located at the bottom of the trench 202 is formed in the N-type semiconductor layer 201 by oblique N-type ion implantation using the mask layer 202 as a mask, and the N-type carrier storage layer 203 surrounds the bottom of the trench 202; next, a P-type ion implantation is performed using the mask layer 202 as a mask to form a P-type protective layer 204 located at the bottom of the trench 202 in the N-type semiconductor layer 201, and the lower surface of the P-type protective layer 204 is lower than the lower surface of the N-type carrier storage layer 203. Figure 6 is based on Figure 4 The structure shown in FIG. 1 is a structure after forming an N-type carrier storage layer 203 and a P-type protective layer 204. Figure 7 is based on Figure 5 The structure shown is a structure after the N-type carrier storage layer 203 and the P-type protection layer 204 are formed.

[0047] Next, if Figure 8 As shown, a gate dielectric layer 205 is formed on the surface of the trench 202, and then a polysilicon layer is deposited and etched back to form a gate electrode 206 in the trench 202. Figure 8 is based on Figure 6 The structure shown is a structure after the gate electrode 206 is formed.

[0048] based on Figure 7 The structure shown can form an IGBT device with a split-gate structure, and the specific process includes: Fig. 9 As shown, a gate dielectric layer 205 is first formed on the surface of the trench 209, and then a polysilicon layer is deposited and etched back to form a gate electrode 210a and a gate electrode 210b in the trench 209, and the gate electrode 210a and the gate electrode 210b are located at the sidewall position of the trench 209; then, an insulating dielectric layer 213 is formed to cover the exposed surface of the gate electrode 210a and the gate electrode 210b, and then a polysilicon layer is deposited and etched back to form a shielding electrode 211 in the trench 209, and the shielding electrode 211 is insulated and isolated from the gate electrode 210a and the gate electrode 210b by the insulating dielectric layer 213.

[0049] Next, Figure 8 The structure shown in the figure continues to describe the manufacturing method of the IGBT device of the present invention, as shown in the figure. Fig.10 As shown, the mask layer 202 is removed, and then P-type ion implantation is performed to form a P-type body region 207 in the N-type semiconductor layer 201 , and the P-type body region 207 is located between adjacent trenches 202 ; then N-type ion implantation is performed to form an N-type emitter region 208 in the P-type body region 207 .

[0050] Next, if Fig.10As shown, high temperature annealing is performed so that the N-type carrier storage layer 203 and the P-type protection layer 204 diffuse to predetermined positions, the N-type carrier storage layer 203 is located below the P-type body region 207 , and the P-type protection layer 204 is located below the N-type carrier storage layer 203 and surrounds the bottom of the groove 202 .

[0051] Finally, a conventional process is used to form an N-type field stop region and a P-type collector region, and to form a passivation layer and a metal electrode layer. This process is a conventional process in the industry and will not be specifically demonstrated in the embodiments of the present invention.

[0052] The present invention provides a method for manufacturing an IGBT device, which adopts a shallow trench technology, can reduce the stress of the wafer, improve the flatness and warping problems of the wafer, and further reduce the epitaxial thickness of the wafer, thereby further reducing the on-state voltage drop of the IGBT device; at the same time, the ion implantation of the N-type carrier storage layer and the P-type protective layer at the bottom of the trench adopts a self-aligned form, and the process consistency is good, which can further improve the manufacturing yield of the IGBT device.

[0053] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. An IGBT device, characterized in that: include: An N-type semiconductor layer, and located in the N-type semiconductor layer: A plurality of trenches, each of which is provided with a gate electrode, and the gate electrode is insulated and isolated from the N-type semiconductor layer by a gate dielectric layer; A P-type body region located between adjacent grooves, wherein an N-type emitter region is provided in the P-type body region; An N-type carrier storage layer located below the P-type body region and between adjacent trenches; A P-type protection layer is provided at the bottom of each trench. The P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the trench.

2. An IGBT device as claimed in claim 1, characterized in that: The middle portion of the N-type carrier storage layer extends downward to between the adjacent P-type protection layers, and the lower surface of the P-type protection layer is lower than the lower surface of the N-type carrier storage layer.

3. An IGBT device according to claim 1, characterized in that: It also includes a shielding electrode located in the trench, the gate electrode is located on both sides of the shielding electrode, and the gate electrode is insulated and isolated from the shielding electrode.

4. An IGBT device according to claim 1, characterized in that: It also includes an N-type field stop region and a P-type collector region located at the bottom of the N-type semiconductor layer, and the N-type field stop region is located above the P-type collector region.

5. A method for manufacturing an IGBT device, characterized in that: include: S1: forming a mask layer on the provided N-type semiconductor layer, and then forming a mask layer opening in the mask layer by photolithography and etching processes; S2: etching the N-type semiconductor layer to form a plurality of grooves arranged in sequence in the N-type semiconductor layer; S3: performing inclined N-type ion implantation in the N-type semiconductor layer to form an N-type carrier storage layer located at the bottom of the trench; S4: performing P-type ion implantation in the N-type semiconductor layer to form a P-type protective layer located at the bottom of the trench, wherein a lower surface of the P-type protective layer is lower than a lower surface of the N-type carrier storage layer; S5: forming a gate dielectric layer on the surface of the trench, then depositing a polysilicon layer and etching back to form a gate electrode in the trench; S6: removing the mask layer, and then performing P-type ion implantation to form a P-type body region in the N-type semiconductor layer, wherein the P-type body region is located between adjacent trenches; S7: performing N-type ion implantation to form an N-type emitter region in the P-type body region; S8: Perform high temperature annealing to diffuse the N-type carrier storage layer and the P-type protection layer to predetermined positions, wherein the N-type carrier storage layer is located below the P-type body region, and the P-type protection layer is located below the N-type carrier storage layer and surrounds the bottom of the groove.

6. The method for manufacturing an IGBT device according to claim 5, characterized in that: The S2 includes: S21: etching the N-type semiconductor layer to form a plurality of grooves arranged in sequence in the N-type semiconductor layer; S22: performing isotropic etching so that the width of the trench is greater than the width of the mask layer opening.

7. The method for manufacturing an IGBT device according to claim 6, characterized in that: The S5 includes: S51: forming a gate dielectric layer on the surface of the trench, then depositing a polysilicon layer and etching back to form a gate electrode in the trench, wherein the gate electrode is located at a sidewall position of the trench; S52: forming an insulating dielectric layer to cover the exposed surface of the gate electrode, then depositing a polysilicon layer and etching back to form a shielding electrode in the trench, wherein the shielding electrode is insulated and isolated from the gate electrode and the N-type semiconductor layer by the insulating dielectric layer.

8. The method for manufacturing an IGBT device according to claim 5, characterized in that: The S8 includes: performing high temperature annealing so that the N-type carrier storage layer and the P-type protective layer diffuse to predetermined positions, the N-type carrier storage layer is located below the P-type body region, the P-type protective layer is located below the N-type carrier storage layer and surrounds the bottom of the groove, the middle part of the N-type carrier storage layer extends downward between adjacent P-type protective layers, and the lower surface of the P-type protective layer is lower than the lower surface of the carrier storage layer.

9. The method for manufacturing an IGBT device according to claim 5, characterized in that: The step S4 includes: performing vertical P-type ion implantation to form a P-type protective layer on the N-type semiconductor layer, wherein the lower surface of the P-type protective layer is lower than the lower surface of the N-type carrier storage layer.

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