A GGNMOS device

Abstract

This invention provides a GGNMOS device in which a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer are formed at the N-type well layer. This is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer, and similarly, a large parasitic resistance between the first N-type sub-doped layer and the third N-type sub-doped layer. This ensures that the drain structure of the GGNMOS device has a high breakdown voltage while reducing the manufacturing cost of the GGNMOS device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a GGNMOS (Gate-Grounded NMOS) device. Background Technology

[0002] Integrated circuits are easily damaged by static electricity. ESD protection circuits are typically designed at the input / output terminals or in power supply protection devices to prevent damage to internal circuitry caused by static electricity. GGNMOS (Gate-Grounded NMOS) is a widely used ESD protection structure. It provides ESD protection through electrostatic discharge. The mechanism is as follows: since the power dissipation on a MOSFET is the product of the current flowing through it and the voltage drop, under a certain ESD current, reducing the voltage drop across the MOSFET can reduce the power dissipation, thereby lowering the junction temperature and protecting the MOSFET.

[0003] As an ESD device, GGNMOS relies on its parasitic NPN (N+ active region at the drain - P-type substrate - N+ active region at the source) BJT to conduct and discharge ESD current in the forward direction; and on its reverse direction, it relies on its PN diode (P-type substrate - N+ active region at the drain) to conduct and discharge ESD current in the reverse direction. In the overall chip ESD network, when an ESD event occurs, the GGNMOS may conduct in both forward and reverse directions, determined by the potential ESD path. ESD current will always flow to the low-resistance path. Therefore, the forward and reverse ESD performance of the GGNMOS must be considered during design to absolutely ensure chip reliability. Typically, the forward discharge capability of the diode is very strong. The parasitic PN junction diode at the P-type substrate and N+ drain of the GGNMOS can serve as a negative voltage discharge path. When there is positive static electricity at the drain, the parasitic PN junction between the drain and the substrate will first undergo avalanche breakdown, and then the parasitic bipolar NPN of the GGNMOS will turn on to form a low-resistance path to discharge the static current.

[0004] To improve the breakdown voltage of the drain structure, existing GGNMOS devices typically form non-metallic silicides on the drain structure using a salicide block mask process. Since the preparation of non-metallic silicides requires a salicide block mask, the process is cumbersome, which increases the number of steps and manufacturing costs of GGNMOS devices. Summary of the Invention

[0005] In view of this, the present invention provides a GGNMOS device that effectively solves the problems existing in the prior art. While ensuring that the drain structure of the GGNMOS device has a high withstand voltage, it also reduces the manufacturing cost of the GGNMOS device.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0007] A GGNMOS device, comprising:

[0008] P-type substrate;

[0009] A gate structure located on one side surface of the P-type substrate;

[0010] The source structure and drain structure are located on both sides of the gate structure, and a substrate electrode structure is located on the side of the source structure away from the gate structure; wherein, the drain structure includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer and a second N-type sub-doped layer implanted into the N-type well layer, the second N-type sub-doped layer being located between the gate structure and the first N-type sub-doped layer, the first N-type sub-doped layer being used for external terminals, and the doping concentration of the first N-type sub-doped layer and the second N-type sub-doped layer being greater than the doping concentration of the N-type well layer.

[0011] Optionally, a set gap is provided between the N-type well layer and the gate structure;

[0012] The second N-type sub-doped layer covers the defined gap and extends into the N-type well layer.

[0013] Optionally, the gate structure includes a gate oxide layer located on one side of the P-type substrate and a polysilicon layer located on the side of the gate oxide layer opposite to the P-type substrate.

[0014] Optionally, the source structure includes an N-type doped layer implanted into the P-type substrate.

[0015] Optionally, the substrate electrode structure includes a P-type doped layer implanted into the P-type substrate, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate.

[0016] Accordingly, the present invention also provides a GGNMOS device, comprising:

[0017] P-type substrate;

[0018] A first gate structure and a second gate structure located on one side surface of the P-type substrate;

[0019] A drain structure located between the first gate structure and the second gate structure, a first source structure and a first substrate electrode structure located on the side of the first gate structure away from the drain structure, and a second source structure and a second substrate electrode structure located on the side of the second gate structure away from the drain structure;

[0020] The drain structure includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer implanted into the N-type well layer. The first N-type sub-doped layer is located between the second N-type sub-doped layer and the third N-type sub-doped layer. The second N-type sub-doped layer is located near the first gate structure. The first N-type sub-doped layer is used for external terminals, and the doping concentration of the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer is greater than the doping concentration of the N-type well layer.

[0021] Optionally, the N-type well layer and the first gate structure have a first predetermined gap, and the N-type well layer and the second gate structure have a second predetermined gap;

[0022] The second N-type sub-doped layer covers the first predetermined gap and extends to the N-type well layer, and the third N-type sub-doped layer covers the second predetermined gap and extends to the N-type well layer.

[0023] Optionally, either the first gate structure or the second gate structure includes a gate oxide layer located on one side of the surface of the P-type substrate, and a polysilicon layer located on the side of the gate oxide layer opposite to the P-type substrate.

[0024] Optionally, either the first source structure or the second source structure includes an N-type doped layer implanted into the P-type substrate.

[0025] Optionally, either the first substrate electrode structure or the second substrate electrode structure includes a P-type doped layer implanted into the P-type substrate, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate.

[0026] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0027] The present invention provides a GGNMOS device. The drain structure provided by the present invention includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer and a second N-type sub-doped layer implanted into the N-type well layer, the second N-type sub-doped layer being located between the gate structure and the first N-type sub-doped layer, the first N-type sub-doped layer being used for external terminals, and the doping concentration of the first N-type sub-doped layer and the second N-type sub-doped layer being greater than the doping concentration of the N-type well layer.

[0028] Alternatively, the drain structure provided by the present invention includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer implanted into the N-type well layer, wherein the first N-type sub-doped layer is located between the second N-type sub-doped layer and the third N-type sub-doped layer, the second N-type sub-doped layer is located on the side closer to the first gate structure, the first N-type sub-doped layer is used for external terminals, and the doping concentration of the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer is greater than the doping concentration of the N-type well layer.

[0029] As can be seen from the above, the technical solution provided by the present invention forms the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer at the N-type well layer, which is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer, and similarly, forming a large parasitic resistance between the first N-type sub-doped layer and the third N-type sub-doped layer. Thus, while ensuring the high breakdown voltage of the drain structure of the GGNMOS device, the manufacturing cost of the GGNMOS device is reduced. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a GGNMOS device provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of another GGNMOS device provided in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the structure of another GGNMOS device provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of another GGNMOS device provided in an embodiment of the present invention. Detailed Implementation

[0035] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] As described in the background section, GGNMOS, as an ESD device, relies on the parasitic NPN (N+ active region of the drain - P-type substrate - N+ active region of the source) BJT to conduct and discharge ESD current in the forward direction; and relies on the PN diode (P-type substrate - N+ active region of the drain) to conduct and discharge ESD current in the reverse direction. In the overall chip ESD network, when an ESD event occurs, the GGNMOS may conduct in both forward and reverse directions, determined by the potential ESD path. The ESD current will always flow to the low-resistance path. Therefore, the forward and reverse ESD performance of the GGNMOS must be considered during design to absolutely guarantee the reliability of the chip. Typically, the forward discharge capability of the diode is very strong. The parasitic PN junction diode of the P-type substrate and N+ drain of the GGNMOS can serve as a negative voltage discharge path. When there is positive static electricity at the drain, the parasitic PN junction between the drain and the substrate will first undergo avalanche breakdown, and then the parasitic bipolar NPN of the GGNMOS will turn on to form a low-resistance path to discharge the static current.

[0037] To improve the breakdown voltage of the drain structure, existing GGNMOS devices typically form non-metallic silicides on the drain structure using a Salicide Block Mask. Since the preparation of non-metallic silicides requires a Salicide Block Mask, the process is complicated, which increases the number of steps and the manufacturing cost of GGNMOS devices.

[0038] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 4 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0039] refer to Figure 1 The diagram shown is a structural schematic of a GGNMOS device according to an embodiment of the present invention, wherein the GGNMOS device includes:

[0040] P-type substrate 100;

[0041] Gate structure 200 located on one side surface of the P-type substrate 100;

[0042] The gate structure 200 has a source structure 300 and a drain structure 400 located on both sides of it, and a substrate electrode structure 500 located on the side of the source structure 300 away from the gate structure 200. The drain structure 400 includes an N-type well layer 410 implanted into the P-type substrate 100, a first N-type sub-doped layer 421 and a second N-type sub-doped layer 422 implanted into the N-type well layer 410. The second N-type sub-doped layer 422 is located between the gate structure 200 and the first N-type sub-doped layer 421. The first N-type sub-doped layer 421 is used for connecting an external terminal PAD, and the doping concentration of the first N-type sub-doped layer 421 and the second N-type sub-doped layer 422 is greater than the doping concentration of the N-type well layer 410.

[0043] like Figure 1 As shown, the gate structure semiconductor device provided in this embodiment of the invention is a GGNMOS device, and therefore its gate structure 200, source structure 300 and substrate electrode structure 500 are electrically connected to the ground terminal GND.

[0044] like Figure 1 As shown in the embodiment of the present invention, a predetermined gap exists between the N-type well layer 410 and the gate structure 200. The second N-type sub-doped layer 422 covers the predetermined gap and extends to the N-type well layer 410.

[0045] In one embodiment of the present invention, the P-type substrate 100 provided by the present invention can be a P-type silicon substrate, and the present invention does not impose specific limitations on it.

[0046] It is understood that the technical solution provided by the embodiments of the present invention forms the first N-type sub-doped layer and the second N-type sub-doped layer at the N-type well layer, which is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer. Thus, while ensuring that the drain structure of the GGNMOS device has a high breakdown voltage, it is not necessary to use Salicide BlockMask to form non-metallic silicides on the drain structure, thereby reducing the manufacturing cost of the GGNMOS device.

[0047] refer to Figure 2 The diagram shown is a structural schematic of another GGNMOS device provided in an embodiment of the present invention, wherein the GGNMOS device includes:

[0048] P-type substrate 100;

[0049] Gate structure 200 located on one side surface of the P-type substrate 100;

[0050] The gate structure 200 has a source structure 300 and a drain structure 400 located on both sides of it, and a substrate electrode structure 500 located on the side of the source structure 300 away from the gate structure 200. The drain structure 400 includes an N-type well layer 410 implanted into the P-type substrate 100, a first N-type sub-doped layer 421 and a second N-type sub-doped layer 422 implanted into the N-type well layer 410. The second N-type sub-doped layer 422 is located between the gate structure 200 and the first N-type sub-doped layer 421. The first N-type sub-doped layer 421 is used for connecting an external terminal PAD, and the doping concentration of the first N-type sub-doped layer 421 and the second N-type sub-doped layer 422 is greater than the doping concentration of the N-type well layer 410.

[0051] In one embodiment of the present invention, the gate structure provided by the present invention includes a gate oxide layer 210 located on one side surface of the P-type substrate 100, and a polysilicon layer 220 located on the side of the gate oxide layer 210 opposite to the P-type substrate 100.

[0052] In one embodiment of the present invention, the source structure 300 provided by the present invention includes an N-type doped layer implanted into the P-type substrate 100, wherein the doping concentration of the N-type doped layer can be greater than the doping concentration of the N-type well layer. Optionally, the doping concentration of the N-type doped layer provided in the embodiment of the present invention can be the same as the doping concentration of the first N-type sub-doped layer and the second N-type sub-doped layer.

[0053] In one embodiment of the present invention, the substrate electrode structure 500 provided by the present invention includes a P-type doped layer implanted into the P-type substrate 100, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate 100.

[0054] Furthermore, in the GGNMOS device provided in this embodiment of the invention, the surfaces of the polysilicon layer of the gate structure, the N-type doped layer of the source structure, the P-type doped layer of the substrate electrode structure, and the first N-type sub-doped layer and the second N-type sub-doped layer of the drain structure can all be metallized, thereby improving the ohmic contact of the relevant structural layers and improving the performance of the GGNMOS device.

[0055] In one embodiment of the present invention, the GGNMOS device provided by the present invention can be a single device structure, or it can be two device structures fabricated on the same P-type substrate and connected together. The present invention also provides a multi-structure GGNMOS device, see details below. Figure 3 The diagram shown is a structural schematic of another GGNMOS device provided in an embodiment of the present invention, wherein the GGNMOS device includes:

[0056] P-type substrate 100;

[0057] A first gate structure 201 and a second gate structure 202 are located on one side surface of the P-type substrate 100;

[0058] A drain structure 400 located between the first gate structure 201 and the second gate structure 202, a first source structure 301 and a first substrate electrode structure 501 located on the side of the first gate structure 201 away from the drain structure 400, and a second source structure 302 and a second substrate electrode structure 502 located on the side of the second gate structure 202 away from the drain structure 400.

[0059] The drain structure 400 includes an N-type well layer 410 implanted into the P-type substrate 100, a first N-type sub-doped layer 421, a second N-type sub-doped layer 422, and a third N-type sub-doped layer 423 implanted into the N-type well layer 410. The first N-type sub-doped layer 421 is located between the second N-type sub-doped layer 422 and the third N-type sub-doped layer 423. The second N-type sub-doped layer 422 is located near the first gate structure 201. The first N-type sub-doped layer 421 is used for connecting an external terminal PAD, and the doping concentration of the first N-type sub-doped layer 421, the second N-type sub-doped layer 422, and the third N-type sub-doped layer 423 is greater than the doping concentration of the N-type well layer 410.

[0060] like Figure 3 As shown, the gate structure semiconductor device provided in this embodiment of the invention is a GGNMOS device, therefore its first gate structure 201, second gate structure 202, first source structure 301, second source structure 302, first substrate electrode structure 501 and second substrate electrode structure 502 are all electrically connected to the ground terminal GND.

[0061] like Figure 3 As shown in the embodiment of the present invention, the N-type well layer 410 and the first gate structure 201 have a first predetermined gap, and the N-type well layer 410 and the second gate structure 202 have a second predetermined gap. The second N-type sub-doped layer 421 covers the first predetermined gap and extends to the N-type well layer 410, and the third N-type sub-doped layer 423 covers the second predetermined gap and extends to the N-type well layer 410.

[0062] In one embodiment of the present invention, the P-type substrate 100 provided by the present invention can be a P-type silicon substrate, and the present invention does not impose specific limitations on it.

[0063] It is understood that the technical solution provided by the embodiments of the present invention forms the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer at the N-type well layer, which is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer, and similarly, forming a large parasitic resistance between the first N-type sub-doped layer and the third N-type sub-doped layer. Thus, while ensuring that the drain structure of the GGNMOS device has a high breakdown voltage, it is not necessary to form non-metallic silicides on the drain structure using a Salicide Block Mask, thereby reducing the manufacturing cost of the GGNMOS device.

[0064] refer to Figure 4 The diagram shown is a structural schematic of another GGNMOS device provided in an embodiment of the present invention, wherein the GGNMOS device includes:

[0065] P-type substrate 100;

[0066] A first gate structure 201 and a second gate structure 202 are located on one side surface of the P-type substrate 100;

[0067] A drain structure 400 located between the first gate structure 201 and the second gate structure 202, a first source structure 301 and a first substrate electrode structure 501 located on the side of the first gate structure 201 away from the drain structure 400, and a second source structure 302 and a second substrate electrode structure 502 located on the side of the second gate structure 202 away from the drain structure 400.

[0068] The drain structure 400 includes an N-type well layer 410 implanted into the P-type substrate 100, a first N-type sub-doped layer 421, a second N-type sub-doped layer 422, and a third N-type sub-doped layer 423 implanted into the N-type well layer 410. The first N-type sub-doped layer 421 is located between the second N-type sub-doped layer 422 and the third N-type sub-doped layer 423. The second N-type sub-doped layer 422 is located near the first gate structure 201. The first N-type sub-doped layer 421 is used for connecting an external terminal PAD, and the doping concentration of the first N-type sub-doped layer 421, the second N-type sub-doped layer 422, and the third N-type sub-doped layer 423 is greater than the doping concentration of the N-type well layer 410.

[0069] In one embodiment of the present invention, either the first gate structure 201 or the second gate structure 202 provided by the present invention includes a gate oxide layer 210 located on one side surface of the P-type substrate 100, and a polysilicon layer 220 located on the side of the gate oxide layer 210 opposite to the P-type substrate 100.

[0070] In one embodiment of the present invention, either the first source structure 301 or the second source structure 302 provided by the present invention includes an N-type doped layer implanted into the P-type substrate 100. The doping concentration of the N-type doped layer can be greater than the doping concentration of the N-type well layer. Optionally, the doping concentration of the N-type doped layer provided in this embodiment of the present invention can be the same as the doping concentration of the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer.

[0071] In one embodiment of the present invention, either the first substrate electrode structure 501 or the second substrate electrode structure 502 provided by the present invention includes a P-type doped layer implanted into the P-type substrate 100, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate 100.

[0072] Furthermore, in the GGNMOS device provided by the embodiments of the present invention, the surfaces of the polysilicon layer in the first gate structure and the second gate structure, the N-type doped layer in the first source structure and the second source structure, the P-type doped layer in the first substrate electrode structure and the second substrate electrode structure, and the first N-type sub-doped layer, the second N-type sub-doped layer and the third sub-N-type doped layer in the drain structure can all be metallized, thereby improving the ohmic contact of the relevant structural layers and improving the performance of the GGNMOS device.

[0073] This invention provides a GGNMOS device. The drain structure provided by this invention includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer and a second N-type sub-doped layer implanted into the N-type well layer, the second N-type sub-doped layer being located between the gate structure and the first N-type sub-doped layer, the first N-type sub-doped layer being used for external terminals, and the doping concentration of the first N-type sub-doped layer and the second N-type sub-doped layer being greater than the doping concentration of the N-type well layer.

[0074] Alternatively, the drain structure provided in this embodiment of the invention includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer implanted into the N-type well layer. The first N-type sub-doped layer is located between the second N-type sub-doped layer and the third N-type sub-doped layer. The second N-type sub-doped layer is located near the first gate structure. The first N-type sub-doped layer is used for external terminals, and the doping concentration of the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer is greater than the doping concentration of the N-type well layer.

[0075] As can be seen from the above, the technical solution provided by the embodiments of the present invention forms the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer at the N-type well layer, which is equivalent to forming a large parasitic resistance between the first N-type sub-doped layer and the second N-type sub-doped layer, and similarly, forming a large parasitic resistance between the first N-type sub-doped layer and the third N-type sub-doped layer. Thus, while ensuring that the drain structure of the GGNMOS device has a high breakdown voltage, the manufacturing cost of the GGNMOS device is reduced.

[0076] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A GGNMOS device, characterized in that, include: P-type substrate; A gate structure located on one side surface of the P-type substrate; The gate structure has a source structure and a drain structure located on opposite sides of the gate structure, and a substrate electrode structure located on the side of the source structure away from the gate structure. The drain structure includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer and a second N-type sub-doped layer implanted into the N-type well layer, the second N-type sub-doped layer being located between the gate structure and the first N-type sub-doped layer, the first N-type sub-doped layer being used for external terminals, and the doping concentration of the first N-type sub-doped layer and the second N-type sub-doped layer being greater than the doping concentration of the N-type well layer. Within the range of the N-type well layer: there is no non-metallic silicide phase isolation in the gap region between adjacent N-type sub-doped layers, and the gap region between adjacent N-type sub-doped layers is only a part of the structure of the N-type well layer. Furthermore, within the range of the N-type well layer: any side of any N-type sub-doped layer is a partial structure of the N-type well layer, such that there is no P-type structure on any side of any N-type sub-doped layer.

2. The GGNMOS device according to claim 1, characterized in that, A predetermined gap exists between the N-type well layer and the gate structure; The second N-type sub-doped layer covers the defined gap and extends into the N-type well layer.

3. The GGNMOS device according to claim 1, characterized in that, The gate structure includes a gate oxide layer located on one side of the P-type substrate and a polysilicon layer located on the side of the gate oxide layer opposite to the P-type substrate.

4. The GGNMOS device according to claim 1, characterized in that, The source structure includes an N-type doped layer implanted into the P-type substrate.

5. The GGNMOS device according to claim 1, characterized in that, The substrate electrode structure includes a P-type doped layer implanted into the P-type substrate, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate.

6. A GGNMOS device, characterized in that, include: P-type substrate; A first gate structure and a second gate structure located on one side surface of the P-type substrate; A drain structure located between the first gate structure and the second gate structure, a first source structure and a first substrate electrode structure located on the side of the first gate structure away from the drain structure, and a second source structure and a second substrate electrode structure located on the side of the second gate structure away from the drain structure; The drain structure includes an N-type well layer implanted into the P-type substrate, a first N-type sub-doped layer, a second N-type sub-doped layer, and a third N-type sub-doped layer implanted into the N-type well layer. The first N-type sub-doped layer is located between the second N-type sub-doped layer and the third N-type sub-doped layer. The second N-type sub-doped layer is located near the first gate structure. The first N-type sub-doped layer is used for external terminals, and the doping concentration of the first N-type sub-doped layer, the second N-type sub-doped layer, and the third N-type sub-doped layer is greater than the doping concentration of the N-type well layer. Within the range of the N-type well layer: there is no non-metallic silicide phase isolation in the gap region between adjacent N-type sub-doped layers, and the gap region between adjacent N-type sub-doped layers is only a part of the structure of the N-type well layer. Furthermore, within the range of the N-type well layer: any side of any N-type sub-doped layer is a partial structure of the N-type well layer, such that there is no P-type structure on any side of any N-type sub-doped layer.

7. The GGNMOS device according to claim 6, characterized in that, The N-type well layer and the first gate structure have a first predetermined gap, and the N-type well layer and the second gate structure have a second predetermined gap; The second N-type sub-doped layer covers the first predetermined gap and extends to the N-type well layer, and the third N-type sub-doped layer covers the second predetermined gap and extends to the N-type well layer.

8. The GGNMOS device according to claim 6, characterized in that, Either the first gate structure or the second gate structure includes a gate oxide layer located on one side of the surface of the P-type substrate, and a polysilicon layer located on the side of the gate oxide layer opposite to the P-type substrate.

9. The GGNMOS device according to claim 6, characterized in that, Either the first source structure or the second source structure includes an N-type doped layer implanted into the P-type substrate.

10. The GGNMOS device according to claim 6, characterized in that, Either the first substrate electrode structure or the second substrate electrode structure includes a P-type doped layer implanted into the P-type substrate, wherein the doping concentration of the P-type doped layer is greater than the doping concentration of the P-type substrate.

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