A semiconductor device structure, a method of fabricating the same, and a semiconductor device
By filling the contact holes with a doped semiconductor layer and forming a recessed structure, the problem of increased contact resistance was solved, thereby increasing the contact area and reducing the resistance, thus improving the performance and lifespan of the DRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BANGXIN SEMI TECHNOLOGY CO LTD
- Filing Date
- 2026-01-08
- Publication Date
- 2026-05-19
AI Technical Summary
As dynamic random access memory (DRAM) structures are miniaturized, the reduced size of the contact holes leads to increased contact resistance, causing problems such as resistance-capacitance delay, increased power consumption, loss of signal integrity, and shortened lifespan.
A doped semiconductor layer is filled into the contact hole, and a recessed structure is formed on its top surface to increase the contact area. At the same time, the doping concentration is increased to form holes and gaps. The recessed structure is formed by using a back-etching process to increase the contact area and reduce the resistance.
It significantly reduces contact resistance, decreases RC delay, reduces power consumption, enhances signal integrity, extends device life, and enables further miniaturization of devices.
Smart Images
Figure CN121487246B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor processing technology, and in particular to a semiconductor device structure, a method for fabricating the same, and a semiconductor device. Background Technology
[0002] As the architecture of Dynamic Random Access Memory (DRAM) continues to miniaturize, the size of contact holes (such as word line contact holes / bit line contact holes) also needs to be continuously reduced. This leads to a natural increase in contact resistance (resistance is inversely proportional to contact area), resulting in a series of problems such as resistance-capacitance delay (RC delay), increased power consumption, loss of signal integrity, and shortened lifespan. If the contact resistance cannot be further reduced, device miniaturization will face physical limits. Therefore, it is necessary to study a process method that can significantly reduce contact resistance. Summary of the Invention
[0003] The purpose of this application is to overcome the above-mentioned problems existing in the prior art, and to provide a semiconductor device structure, a method for fabricating the same, and a semiconductor device, so as to significantly increase the contact area at the top of the contact hole, thereby reducing the contact resistance.
[0004] To achieve the above objectives, the technical solution of this application is as follows:
[0005] According to a first aspect of this application, embodiments of this application provide a semiconductor device structure, including:
[0006] Substrate;
[0007] Active region provided on the substrate;
[0008] Contact holes provided on the active region;
[0009] The contact hole is filled with a doped semiconductor layer, and the top surface of the doped semiconductor layer away from the substrate has a recessed structure, which increases the contact area on the top surface of the doped semiconductor layer.
[0010] In some embodiments, the device further includes: a wire disposed on the contact hole, the wire being located on the top surface of the doped semiconductor layer and entering the recessed structure for filling, and being in close contact with the doped semiconductor layer.
[0011] In some embodiments, the doped semiconductor layer has filling defects that are used to form the recessed structure.
[0012] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer.
[0013] In some embodiments, the filling defect includes holes and / or gaps.
[0014] In some embodiments, the doping concentration of the doped semiconductor layer is 2 × 10⁻⁶. 21 atoms / cm 3 above.
[0015] In some embodiments, the doped semiconductor layer includes a phosphorus-doped semiconductor layer.
[0016] In some embodiments, an interlayer dielectric layer is provided on the substrate to cover the active region, a contact hole is disposed in the interlayer dielectric layer and connected to the active region through its bottom, and a wire is located on the interlayer dielectric layer and connected to the top surface of the doped semiconductor layer exposed from the top of the contact hole.
[0017] According to a second aspect of this application, embodiments of this application also provide a method for fabricating a semiconductor device structure, comprising:
[0018] Provide substrate;
[0019] An active region is formed on the substrate;
[0020] A contact hole is formed in the active region, and a doped semiconductor layer is filled in the contact hole. The top surface of the doped semiconductor layer away from the substrate has a recessed structure, which increases the contact area on the top surface of the doped semiconductor layer.
[0021] In some embodiments, forming a contact hole on the active region specifically includes:
[0022] An interlayer dielectric layer is formed on the surface of the substrate to cover the active region;
[0023] A contact hole trench is formed on the surface of the interlayer dielectric layer, with its bottom connected to the active region;
[0024] A doped semiconductor layer is filled into the contact hole trench, and the doped semiconductor layer is made to have filling defects.
[0025] The excess doped semiconductor layer on the top of the contact hole trench is removed, and the filling defects present in the doped semiconductor layer are used to form a recessed structure on the top surface of the doped semiconductor layer after removal, thereby forming a contact hole.
[0026] In some embodiments, an epitaxial process is used to fill the contact hole trench with a polysilicon layer, and the polysilicon layer is phosphorus-doped to form a phosphorus-doped polysilicon layer as the doped semiconductor layer; by increasing the doping concentration of the polysilicon layer to a higher level than the conventional doping concentration, the doped polysilicon layer is made to generate holes and / or gaps, thereby forming filling defects; an etch-back process is used to remove the excess doped polysilicon layer on the top of the contact hole trench, and the flaring effect of etching on the holes and / or gaps is used to form the recessed structure.
[0027] In some embodiments, it also includes:
[0028] A metal layer is formed on the surface of the interlayer dielectric layer, such that the metal layer covers the top surface of the doped semiconductor layer exposed from the top of the contact hole, and enters the recessed structure to fill it, and is in close contact with the doped semiconductor layer;
[0029] The metal layer is patterned, and a conductive line connected to the top surface of the doped semiconductor layer is formed on the surface of the interlayer dielectric layer.
[0030] According to a third aspect of this application, embodiments of this application also provide a semiconductor device, including the semiconductor device structure provided in any of the embodiments of the first aspect above, wherein the semiconductor device includes a dynamic random access memory, and the contact holes contained in the semiconductor device structure include bit line contact holes.
[0031] According to a fourth aspect of this application, embodiments of this application also provide a semiconductor device, including a semiconductor device structure obtained using the semiconductor device structure fabrication method provided in any of the embodiments of the second aspect above, wherein the semiconductor device includes a dynamic random access memory, and the contact holes contained in the semiconductor device structure include bit line contact holes.
[0032] The embodiments of this application may have, or at least have, the following advantages:
[0033] (1) By setting a recessed structure on the top surface of the doped semiconductor layer filled in the contact hole, the surface area of the top surface of the doped semiconductor layer can be increased, thereby significantly increasing the contact area on the top surface of the doped semiconductor layer. Therefore, the wires on the top surface of the contact hole (top surface of the doped semiconductor layer) can naturally enter the recessed structure for filling and form a tight contact with the doped semiconductor layer, significantly increasing the contact area when the wires are connected to the contact hole, thereby greatly reducing the contact resistance.
[0034] (2) By increasing the doping concentration of the doped polysilicon layer (doped semiconductor layer) to a higher level than the conventional doping concentration, the filling ability of the doped polysilicon layer is weakened, which can cause the doped polysilicon layer to naturally form holes and / or gaps during filling, thus forming filling defects. By using the etch-back process to remove the excess doped polysilicon layer on the top of the contact hole trench, the flaring effect of etching on the holes and / or gaps can be used to naturally form a recessed structure, thereby forming a special contact structure between the wire and the contact hole. Therefore, no additional process is required to effectively increase the contact area. The process is simple and reliable.
[0035] (3) By increasing the doping concentration of the doped polysilicon layer (doped semiconductor layer) to 2×10 21 atoms / cm 3 The above-mentioned doping concentration, which is higher than that of conventional doping, not only reduces the contact resistance, but also significantly reduces the resistance of the contact hole itself. Thus, by optimizing the contact structure when the contact hole is connected to the wire, the overall resistance of the circuit is significantly reduced.
[0036] Therefore, when the semiconductor device structure of the present application embodiment is applied to semiconductor devices including dynamic random access memory, the device can be further miniaturized, and RC delay can be reduced, power consumption can be reduced, signal integrity can be enhanced, and lifespan can be extended.
[0037] Other advantages of this application will be described in the following detailed description. Attached Figure Description
[0038] Figure 1 This is a schematic diagram of a semiconductor device structure according to a preferred embodiment of this application.
[0039] Figure 2 This is a schematic diagram of a semiconductor device structure according to a preferred embodiment of this application.
[0040] Figure 3 This is a flowchart of a semiconductor device structure fabrication method according to a preferred embodiment of this application.
[0041] Figure 4 This is a schematic diagram of a preferred embodiment of the present application after an isolation layer and an active region have been formed on a substrate.
[0042] Figure 5 This is a schematic diagram of a preferred embodiment of the present application after an interlayer dielectric layer has been formed on a substrate.
[0043] Figure 6 This is a schematic diagram of a preferred embodiment of the present application after forming a contact hole trench in the active region.
[0044] Figure 7 This is a schematic diagram of a preferred embodiment of the present application after a contact hole trench has been filled with a doped semiconductor layer to form a contact hole.
[0045] Figure 8 This is a schematic diagram of a preferred embodiment of the present application after a metal layer that is in close contact with a contact hole is formed on an interlayer dielectric layer.
[0046] Figure 9 This is a schematic diagram of a preferred embodiment of the present application, showing a wire formed on a contact hole and a contact plug formed below the wire.
[0047] In the figure: 10. Substrate; 11. Active region; 12. Isolation layer; 13. Contact trench; 14. Doped semiconductor layer; 15. Contact hole; 16. Recessed structure; 17. Interlayer dielectric layer; 18. Wire; 19. Contact plug; 20. Metal layer. Detailed Implementation
[0048] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0049] refer to Figure 1 According to a first aspect of this application, embodiments of this application provide a semiconductor device structure, including a substrate 10, an active region 11 disposed on the substrate 10, and a contact hole 15 disposed on the active region 11. Figure 1 An example is shown of a contact hole 15 disposed on one of the active regions 11 (but is not limited thereto). The contact hole 15 is filled with a conductive doped semiconductor layer 14. Furthermore, the top surface of the doped semiconductor layer 14 has a recessed structure 16, which is used to increase the contact area on the top surface of the doped semiconductor layer 14.
[0050] In some embodiments, substrate 10 includes any suitable type of semiconductor substrate and material. For example, substrate 10 may include a silicon (Si) substrate, a germanium (Ge) substrate, a germanium-silicon (SiGe) substrate, or a III / V compound semiconductor substrate, such as a gallium arsenide (GaAs) substrate, an indium gallium arsenide (InGaAs) substrate, or similar materials. Substrate 10 may also include a silicon-on-insulator (SOI) substrate.
[0051] In some embodiments, the active region 11 may be doped with p-type or n-type dopant to form a doped region (not shown).
[0052] In some embodiments, the active region 11 is doped with an n-type dopant, such as phosphorus (P) or arsenic (As).
[0053] In some embodiments, the active region 11 is doped with a p-type dopant, such as boron (B).
[0054] In some embodiments, the doped region may form the source / drain region of the transistor. In one example, the source / drain region is either a source region or a drain region. In another example, the source / drain region includes merged source / drain regions.
[0055] In some embodiments, the source / drain regions may be epitaxially grown on the active region 11.
[0056] In some embodiments, an isolation layer 12 is provided on the substrate 10, and the isolation layer 12 defines an active region 11 located on the substrate 10.
[0057] In some embodiments, the isolation layer 12 is used to form an isolation structure (e.g., shallow trench isolation).
[0058] In some embodiments, the material of the insulating layer 12 includes oxides (such as silicon dioxide (SiO2)), or nitrides (such as silicon nitride (Si3N4) and silicon carbonitride (SiCN)), combinations thereof, or other dielectric materials.
[0059] In some embodiments, an interlayer dielectric layer 17 is provided on the upper surface of the substrate 10. The interlayer dielectric layer 17 covers the active region 11 and the isolation layer 12.
[0060] In some embodiments, the material of the interlayer dielectric layer 17 includes oxides (such as silicon dioxide (SiO2)) or other dielectric materials.
[0061] In some embodiments, the interlayer dielectric layer 17 material includes tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), or spin-coated dielectric (SOD), etc.
[0062] In some embodiments, the interlayer dielectric layer 17 may be a single layer or multiple layers.
[0063] In some embodiments, other functional layers may also be provided between the interlayer dielectric layer 17 and the substrate 10.
[0064] In some embodiments, the contact hole 15 includes a contact hole trench 13 and a doped semiconductor layer 14 filled in the contact hole trench 13 to form a conductive contact portion.
[0065] In some embodiments, the contact hole 15 is disposed in the interlayer dielectric layer 17 and connected to the active region 11 via its bottom. Specifically, the contact hole 15 is disposed on the upper surface of the interlayer dielectric layer 17. Furthermore, the bottom of the contact hole 15 (contact hole trench 13) passes through the interlayer dielectric layer 17 into the substrate 10 and connects to the source / drain region of the active region 11, so that the source / drain region of the active region 11 is exposed at the bottom of the contact hole trench 13 and in close contact with the doped semiconductor layer 14 filled in the contact hole 15, forming an electrical connection.
[0066] In some embodiments, the bottom of the contact hole 15 (contact hole groove 13) enters the active region 11 from the upper portion of the active region 11, thereby making the bottom of the contact hole 15 (contact hole groove 13) lower than the top of the active region 11.
[0067] In some embodiments, the left and right sidewalls of the contact hole groove 13 can enter the isolation layer 12 on both sides of the connected active region 11, but are isolated from other active regions 11 adjacent to both sides by the isolation layer 12.
[0068] In some embodiments, the contact hole groove 13 may have any suitable size and shape. In some examples, viewed from a top view, the contact hole groove 13 may have a substantially circular or substantially rectangular shape (not shown).
[0069] In some embodiments, the aspect ratio of the contact hole groove 13 may be less than or equal to 1.
[0070] In some embodiments, the aspect ratio of the contact hole groove 13 is greater than 1.
[0071] In some embodiments, the doped semiconductor layer 14 filling the contact hole trench 13 has filling defects, and the filling defects are used to form the recessed structure 16.
[0072] In some embodiments, filling defects include spaces such as holes and / or gaps formed in the doped semiconductor layer 14 due to poor filling that are not filled by the material of the doped semiconductor layer 14.
[0073] In some embodiments, the doping concentration of the doped semiconductor layer 14 is higher than that of conventional doping. By increasing the doping concentration of the doped semiconductor layer 14 and making it higher than that of conventional doping, the filling ability of the doped semiconductor layer 14 during the filling process can be weakened, causing poor filling and generating morphologies such as holes and / or gaps that are conventionally considered defects, thereby forming filling defects, and using these filling defects to fabricate a recessed structure 16 (see the following description of a method for fabricating a semiconductor device structure).
[0074] Since the recessed structure 16 is formed by filling defects such as holes and / or gaps, the present application embodiments do not limit the size and shape of the recessed structure 16.
[0075] In some embodiments, the longitudinal cross-section of the recessed structure 16 can be a groove shape that is larger at the top and smaller at the bottom. For example, the longitudinal cross-section of the recessed structure 16 can be approximately inverted conical or approximately inverted trapezoidal, or approximately U-shaped, or other regular or irregular shapes.
[0076] In some embodiments, the doping concentration of the doped semiconductor layer 14 is 2 × 10⁻⁶.21 atoms / cm 3 The above. This doping concentration is higher than the conventional doping concentration. For example, the doping concentration of the doped semiconductor layer 14 can be 2 × 10⁻⁶. 21 atoms / cm 3 Above, 3×10 21 atoms / cm 3 Above, 4×10 21 atoms / cm 3 Above, 5×10 21 atoms / cm 3 Above, 6×10 21 atoms / cm 3 Above, 7×10 21 atoms / cm 3 Above, 8×10 21 atoms / cm 3 Above, or 9×10 21 atoms / cm 3 The above are examples. However, it is not limited to this. It is limited to the ability to form filling defects such as holes and / or gaps in the doped semiconductor layer 14, and the filling defects can be used to form a recessed structure 16 on the top surface of the doped semiconductor layer 14.
[0077] In some embodiments, provided that filling defects such as holes and / or gaps can be formed, the doping concentration of the doped semiconductor layer 14 can be 2 × 10⁻⁶. 21 atoms / cm 3 For example, the doping concentration of the doped semiconductor layer 14 can be 2 × 10⁻⁶. 21 atoms / cm 3 Below, 1×10 21 atoms / cm 3 Below, 9×10 20 atoms / cm 3 Below, 8×10 20 atoms / cm 3 Below, 7×10 20 atoms / cm 3 Below, 6×10 20 atoms / cm 3 Below, 5×10 20 atoms / cm 3 Below, 4×10 20 atoms / cm 3 Below, 3×10 20 atoms / cm 3 Below, 2×10 20 atoms / cm3 Below, or 1×10 20 atoms / cm 3 The following are examples, but are not limited to these.
[0078] In some embodiments, the doping concentration in the doped semiconductor layer 14 is the same.
[0079] In some embodiments, the doping concentration in the doped semiconductor layer 14 varies. For example, from the bottom to the top of the contact hole 15, the doped semiconductor layer 14 may have a gradually increasing doping concentration, and the doping concentration is higher than the conventional doping concentration or higher than 2 × 10⁻⁶. 21 atoms / cm 3 Alternatively, at the bottom of the contact hole 15, the doping concentration of the doped semiconductor layer 14 can be lower than the conventional doping concentration or lower than 2 × 10⁻⁶. 21 atoms / cm 3 However, at least above the middle of the contact hole 15, the doping concentration of the doped semiconductor layer 14 is higher than the conventional doping concentration or higher than 2 × 10⁻⁶. 21 atoms / cm 3 .
[0080] In some embodiments, the dopant type of the doped semiconductor layer 14 is n-type. For example, by doping the doped semiconductor layer 14 with phosphorus (P) and making the phosphorus doping concentration higher than the conventional doping concentration, a phosphorus-doped semiconductor layer 14 with filling defects is formed.
[0081] In some embodiments, the doped semiconductor layer 14 may include any suitable silicon-doped semiconductor layer, such as a doped polysilicon layer.
[0082] In some embodiments, the top surface of the doped semiconductor layer 14 filling the contact hole 15 is flush with or substantially flush with the upper surface of the interlayer dielectric layer 17. The opening of the recessed structure 16 is exposed on the top surface of the doped semiconductor layer 14.
[0083] refer to Figure 2 In conjunction with references Figure 1 In some embodiments, the semiconductor device structure further includes a conductive wire 18 disposed on the contact hole 15. The conductive wire 18 is located on the top surface of the doped semiconductor layer 14, and its lower end enters the recessed structure 16 for filling, making close contact with the doped semiconductor layer 14. This forms a special contact structure at the connection point between the conductive wire 18 and the doped semiconductor layer 14, creating an interlocking connection between them.
[0084] In the embodiments described above, by providing a recessed structure 16 on the top surface of the doped semiconductor layer 14 filling the contact hole 15, the surface area of the top surface of the doped semiconductor layer 14 is increased, thereby significantly increasing the contact area on the top surface of the doped semiconductor layer 14. Therefore, when a wire 18 connected to the contact hole 15 is provided on the top surface of the contact hole 15 (the top surface of the doped semiconductor layer 14), the lower end of the wire 18 can naturally enter the recessed structure 16 for filling and form a tight contact with the doped semiconductor layer 14, thereby significantly increasing the contact area when the wire 18 is connected to the contact hole 15, and thus greatly reducing the contact resistance.
[0085] Furthermore, by increasing the doping concentration of the doped semiconductor layer 14 (doped polysilicon layer) to a level higher than the conventional doping concentration (e.g., 2 × 10⁻⁶), 21 atoms / cm 3 (Above) While reducing the contact resistance, it also significantly reduces the resistance of the contact hole 15 itself and improves the conductivity of the contact hole 15. Thus, by optimizing the contact structure when the contact hole 15 is connected to the wire 18, the overall resistance of the circuit is significantly reduced.
[0086] In some embodiments, the wire 18 is disposed on the upper surface of the interlayer dielectric layer 17 and connected to the top surface of the doped semiconductor layer 14 exposed from the top of the contact hole 15.
[0087] In some embodiments, the material of the conductor 18 includes, but is not limited to, tungsten, cobalt, copper, aluminum, ruthenium, titanium, silver, platinum, palladium, alloys or derivatives of the above, or any combination thereof.
[0088] In some embodiments, the semiconductor device structure of this application can be applied to semiconductor devices including dynamic random access memory (DRAM). The contact hole 15 of this application embodiment may include a bit line contact hole, and the wire 18 may include a bit line.
[0089] In some embodiments, by means of Figure 1 The doped semiconductor layer 14 shown is patterned vertically to form contact plugs 19 in the contact hole trench 13, as shown. Figure 2 As shown, it can be used as a bit line contact plug for DRAM. Figure 2 The contact plug 19 shown in the image is through... Figure 1 This is evolved from the doped semiconductor layer 14 shown in the image. The side of the contact plug 19 is spaced from the sidewall of the contact hole trench 13, and the side of the contact plug 19 is aligned or substantially aligned with the side of the wire 18 (bit line), as shown in the image. Figure 2 As shown.
[0090] In some embodiments, the lower end of the contact plug 19 is located on the bottom of the contact hole groove 13 and connected to the active region 11, and the lower end of the contact plug 19 is located in the area within the active region 11.
[0091] In some other embodiments, a sidewall (not shown) may be provided on the side of the conductor 18 (bit line), and the sidewall extends downward along the side of the contact plug 19 (bit line contact plug) into the contact hole groove 13, up to the bottom of the contact hole groove 13. The sidewall can fill the gap between the contact plug 19 (bit line contact plug) and the inner wall of the contact hole groove 13. The sidewall can enhance the electrical isolation effect between the conductor 18 (bit line) and the contact plug 19 (bit line contact plug). The sidewall material may include one or any combination of silicon nitride or silicon dioxide, or any other suitable material.
[0092] As semiconductor devices are further miniaturized, by setting the semiconductor device structure of the present application embodiment on the semiconductor device, and by utilizing the effect of the special contact structure set at the connection site between the wire 18 (bit line) and the doped semiconductor layer 14 to significantly reduce the overall circuit resistance, the semiconductor device can achieve reduced RC delay, reduced power consumption, enhanced signal integrity, and extended lifespan.
[0093] The following detailed description, in conjunction with specific embodiments and accompanying drawings, illustrates a method for fabricating a semiconductor structure according to an embodiment of this application.
[0094] According to a second aspect of this application, embodiments of this application also provide a method for fabricating a semiconductor device structure. A method for fabricating a semiconductor device structure according to embodiments of this application can be used to fabricate such... Figure 1 and Figure 2 The above-described embodiment of this application shows a semiconductor device structure.
[0095] refer to Figure 3 A method for fabricating a semiconductor device structure according to an embodiment of this application includes the following steps:
[0096] Step S11: Provide a substrate.
[0097] refer to Figure 4 In this embodiment, a silicon substrate is used as substrate 10.
[0098] In some embodiments, the silicon substrate may be doped to provide a substrate 10 that meets the required electrical properties.
[0099] In some embodiments, the substrate 10 may be doped with an n-type dopant, such as phosphorus (P) or arsenic (As).
[0100] In some embodiments, a p-type dopant, such as boron (B), may be used to dope the substrate 10.
[0101] Step S12: Form an active region on the substrate.
[0102] refer to Figure 4 In some embodiments, photolithography, etching, and deposition processes can be used to form a plurality of isolation layers 12 on the upper surface of the substrate 10 to define active regions 11 located on the substrate 10. The isolation layers 12 can be used to form isolation structures (e.g., shallow trench isolation). This results in the formation of a plurality of active regions 11 isolated from each other on the substrate 10 by the isolation layers 12. In this embodiment, the isolation layer 12 is made of silicon dioxide (SiO2).
[0103] In some embodiments, an ion implantation process may be used to form source / drain regions (not shown) on the active region 11.
[0104] Step S13: Form contact hole trenches in the active region.
[0105] refer to Figure 5 In some embodiments, a deposition process may be used to form an interlayer dielectric layer 17 covering the active region 11 and the isolation layer 12 on the upper surface of the substrate 10. In this embodiment, the interlayer dielectric layer 17 is made of silicon dioxide (SiO2).
[0106] refer to Figure 6 In some embodiments, photolithography and etching processes can be employed to etch and pattern the interlayer dielectric layer 17 above the corresponding active region 11, forming a contact hole trench 13 on the surface of the interlayer dielectric layer 17, with its bottom stopping at the top of the active region 11 and connected to it. The contact hole trench 13 penetrates the interlayer dielectric layer 17 and partially enters the substrate 10, exposing the source / drain regions on the active region 11 (substrate 10) at its bottom. The sidewalls of the contact hole trench 13 can enter the isolation layers 12 on both sides of the active region 11 below it, but are still isolated from other adjacent active regions 11 on the left and right sides by the isolation layers 12.
[0107] In some embodiments, fluorine-containing gases and oxidizing gases may be used as etching gases to etch the interlayer dielectric layer 17 and form contact hole trenches 13.
[0108] In some embodiments, the fluorine-containing gas includes at least one of CHF3, CF4, and C4F8, the oxidizing gas includes O2, and Ar may also be added to the etching gas.
[0109] In some embodiments, the temperature during etching to form the contact hole trench 13 is between 10°C and 60°C. For example, the temperature can be 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, 40°C, 50°C, or 60°C, or any value between any two of the aforementioned temperature values. However, it is not limited to these.
[0110] In some embodiments, the pressure during etching to form the contact hole trench 13 is 50 mTorr to 150 mTorr. For example, the pressure can be 50 mTorr, 60 mTorr, 70 mTorr, 80 mTorr, 90 mTorr, 100 mTorr, 110 mTorr, 120 mTorr, 130 mTorr, 140 mTorr, or 150 mTorr, or any value between any two of the aforementioned pressure values. However, it is not limited to these.
[0111] In some embodiments, when etching to form the contact hole trench 13, the flow rate of the fluorine-containing gas is 5 sccm to 20 sccm. For example, the flow rate of the fluorine-containing gas can be 5 sccm, 6 sccm, 8 sccm, 10 sccm, 12 sccm, 15 sccm, 18 sccm, or 20 sccm, or any value between any two of the aforementioned flow rates. However, it is not limited to this.
[0112] In some embodiments, when etching to form the contact hole trench 13, the flow rate of the oxidizing gas is 50 sccm to 200 sccm. For example, the flow rate of the oxidizing gas can be 50 sccm, 60 sccm, 80 sccm, 100 sccm, 120 sccm, 150 sccm, 180 sccm, or 200 sccm, or any value between any two of the aforementioned flow rates. However, it is not limited to this.
[0113] Step S14: Fill the contact hole trench with a doped semiconductor layer to form a contact hole, and form a recessed structure on the top surface of the doped semiconductor layer.
[0114] refer to Figure 7 In some embodiments, an epitaxial process can be used to grow a semiconductor layer from bottom to top in the contact hole trench 13 to fill the contact hole trench 13 until the semiconductor layer completely fills the contact hole trench 13. An in-situ doping process is then used to dope the semiconductor layer filling the contact hole trench 13 to form a doped semiconductor layer 14, thereby forming a conductive contact hole 15 formed by the doped semiconductor layer 14 and the contact hole trench 13. In this embodiment, the semiconductor layer is a polycrystalline silicon layer, and phosphorus (P) doping is performed on the polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer that serves as the doped semiconductor layer 14 in the contact hole trench 13.
[0115] In some embodiments, the epitaxial process may employ chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), ultra-low-pressure chemical vapor deposition (VLPCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), atomic pressure chemical vapor deposition (APCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or similar processes to form a polycrystalline silicon layer.
[0116] In some embodiments, the silicon source gas used when epitaxially growing a polycrystalline silicon layer may include silane (SiH4), disilane (Si2H6), trisilane (Si3H8), or tetrasilane (Si4H4H6). 10 ), dichlorosilane (SiH2Cl2), or combinations thereof.
[0117] In some embodiments, an in-situ doping process can be used to dope the polycrystalline silicon layer with phosphorus. The doping gas used when doping the polycrystalline silicon layer with phosphorus includes a phosphorus-based gas. The phosphorus-based gas may include, for example, phosphine (PH3).
[0118] In some embodiments, when filling the contact trench 13 with a doped polysilicon layer (doped semiconductor layer 14), filling defects are intentionally created in the doped polysilicon layer. The purpose is that, after filling is complete and excess doped polysilicon layer on top of the contact trench 13 is removed, the existing filling defects in the doped polysilicon layer are utilized to form a recessed structure 16 on the top surface of the resulting doped polysilicon layer after removing the excess doped polysilicon layer, thereby forming a contact hole 15 with the recessed structure 16 on top. This increases the surface area of the top surface of the doped polysilicon layer, significantly increasing the contact area on the top surface of the doped polysilicon layer, thereby greatly reducing the contact resistance.
[0119] In some embodiments, by increasing the doping concentration of the polysilicon layer to a higher level than conventional doping concentrations, the filling capacity of the doped polysilicon layer is weakened, which can induce the natural formation of voids and / or gaps during filling, thereby creating filling defects. Voids and / or gaps appear on top of the deposited doped polysilicon layer. In this embodiment, a 2×10⁻⁶ doping concentration is used. 21 atoms / cm 3 The above doping concentration is used to phosphorus-dope the polysilicon layer, forming a doped polysilicon layer with filling defects such as pores and / or gaps at the top in the contact trench 13. A recessed structure 16 is then further formed on top of the doped polysilicon layer, thereby forming a conductive contact hole 15 composed of the doped polysilicon layer and the contact trench 13. In this way, while reducing the contact resistance, the resistance of the contact hole 15 itself is also significantly reduced, improving the conductivity of the contact hole 15.
[0120] In some embodiments, after the epitaxial process is completed, a reverse etching process can be used to remove excess doped polysilicon layer on the top of the contact hole trench 13 and on the surface of the interlayer dielectric layer 17. During this process, the ablation and widening effect of etching on the holes and / or gaps (filling defects) located on the top of the doped polysilicon layer can be used to naturally form a recessed structure 16 on the top surface of the reverse-etched doped polysilicon layer, such as... Figure 7 As shown, the recessed structure 16 creates a unique contact structure between the subsequently formed conductive wire 18 and the top surface of the doped polysilicon layer. This effectively increases the contact area on the top surface of the doped polysilicon layer without requiring additional processing steps, resulting in a simple and reliable process.
[0121] After the doped polysilicon layer is etched back, the top surface of the doped polysilicon layer is made flush or substantially flush with the upper surface of the interlayer dielectric layer 17, and the opening of the recessed structure 16 is exposed on the top surface of the doped semiconductor layer 14, thereby forming a contact hole 15 with a recessed structure 16 on the top.
[0122] In some embodiments, the temperature during the epitaxial growth of the polysilicon layer is 400°C to 600°C. For example, the temperature during the epitaxial growth of the polysilicon layer can be 400°C, 410°C, 420°C, 430°C, 440°C, 450°C, 460°C, 470°C, 480°C, 490°C, 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, 560°C, 570°C, 580°C, 590°C, or 600°C, or any value between any two of the aforementioned temperature values. However, it is not limited to these.
[0123] In some embodiments, the pressure during the epitaxial growth of the polysilicon layer is 1 Torr to 100 Torr. For example, the pressure during the epitaxial growth of the polysilicon layer can be 1 Torr, 2 Torr, 5 Torr, 10 Torr, 20 Torr, 30 Torr, 40 Torr, 50 Torr, 60 Torr, 70 Torr, 80 Torr, 90 Torr, or 100 Torr, or any value between any two of the aforementioned pressure values. However, it is not limited to these values.
[0124] In some embodiments, when epitaxially forming a polycrystalline silicon layer, the flow rate of the silicon source gas is 10 sccm to 500 sccm. For example, the flow rate of the silicon source gas can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 100 sccm, 200 sccm, 300 sccm, 400 sccm, or 500 sccm, or any value between any two of the aforementioned flow rates. However, it is not limited to this.
[0125] In some embodiments, when epitaxially forming a polycrystalline silicon layer, the flow rate of the phosphorus-based gas is 100 sccm to 2000 sccm. For example, the flow rate of the phosphorus-based gas can be 100 sccm, 200 sccm, 500 sccm, 600 sccm, 800 sccm, 1000 sccm, 1200 sccm, 1300 sccm, 1500 sccm, 1900 sccm, or 2000 sccm, or any value between any two of the aforementioned flow rates. However, it is not limited to this.
[0126] In some embodiments, when etching back the doped polycrystalline silicon layer, the etching gas includes CF4, Cl2, HBr, SF6 and O2, and the dilution and dissociation gas includes at least one of N2 and Ar.
[0127] In some embodiments, the temperature during the etch-back of the doped polysilicon layer is 0°C to 80°C. For example, the temperature during the etch-back of the doped polysilicon layer can be 0°C, 5°C, 10°C, 20°C, 30°C, 40°C, 50°C, 60°C, 70°C, or 80°C, or any value between any two of the aforementioned temperature values. However, it is not limited to these.
[0128] In some embodiments, the pressure during the etch-back of the doped polysilicon layer is 5 mTorr to 500 mTorr. For example, the pressure during the etch-back of the doped polysilicon layer can be 5 mTorr, 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 150 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, or 500 mTorr, or any value between any two of the aforementioned pressure values. However, it is not limited to these.
[0129] In some embodiments, after forming a contact hole 15 with a recessed structure 16 on top, the following step S05 may be further performed.
[0130] Step S15: Form a wire on the contact hole and allow the wire to enter the recessed structure for filling.
[0131] refer to Figure 8In some embodiments, a deposition process can be used to form a metal layer 20 on the surface of the interlayer dielectric layer 17, and the metal layer 20 covers the top surface of the contact hole 15, so that the metal layer 20 covers the upper surface of the interlayer dielectric layer 17 and the top surface of the doped polysilicon layer exposed from the top of the contact hole 15. Simultaneously, since there is a recessed structure 16 on the top surface of the doped polysilicon layer, the metal layer 20 will naturally enter and fill the recessed structure 16 during deposition until it is completely filled and in close contact with the doped polysilicon layer on the sidewall of the recessed structure 16. This forms a special contact structure on the top of the contact hole 15, formed by the close contact between the metal layer 20 material and the doped polysilicon layer material. Therefore, this method simultaneously reduces the resistance of the doped polysilicon layer (contact hole 15) and the contact resistance between the metal layer 20 and the doped polysilicon layer (contact hole 15).
[0132] One or more deposition processes, such as CVD, PECVD, ALD, PEALD, PVD, electroless plating, electroplating, or other suitable deposition methods, can be used to deposit a metal layer 20 on the surface of the interlayer dielectric layer 17.
[0133] In this embodiment, a deposition process is used to deposit metallic tungsten (W) on the surface of the interlayer dielectric layer 17 as the material of the metal layer 20, and to form a tungsten layer as the metal layer 20.
[0134] In other embodiments, before depositing the tungsten layer, a titanium nitride (TiN) layer is first deposited on the surface of the interlayer dielectric layer 17 as a barrier layer, and the titanium nitride layer is deposited along the sidewalls of the recessed structure 16; then, a tungsten layer is deposited on the titanium nitride layer, and the tungsten layer fills the recessed structure 16 within the titanium nitride layer. The titanium nitride layer and the tungsten layer together constitute the metal layer 20.
[0135] refer to Figure 9 In some embodiments, photolithography and etching processes can be used to pattern the metal layer 20, forming a conductive line 18 on the surface of the interlayer dielectric layer 17 (on top of the contact hole 15) that connects to the top surface of the doped polysilicon layer (doped semiconductor layer 14). The width of the conductive line 18 is greater than the width of the recessed structure 16, meaning the conductive line 18 needs to completely cover the recessed structure 16, allowing it to fully fill the recessed structure 16 through its lower end. This creates a special contact structure at the connection between the conductive line 18 and the doped polysilicon layer, forming an interlocking connection between the conductive line 18 and the doped polysilicon layer.
[0136] In some embodiments, when etching to form the patterned wire 18, after etching through the metal layer 20 and reaching the top surface of the doped polysilicon layer, the etching continues downwards through the doped polysilicon layer until the bottom of the contact hole trench 13, thereby forming a contact plug 19 connected to the wire 18 in the contact hole trench 13 below the wire 18. It is understood that the contact plug 19 is a device structure obtained from the patterned doped polysilicon layer (doped semiconductor layer 14).
[0137] According to a third aspect of this application, embodiments of this application also provide a semiconductor device, which includes the semiconductor device structure provided in any of the embodiments of the first aspect described above. The semiconductor device may include dynamic random access memory (DRAM), etc., and the contact holes 15 contained in the semiconductor device structure may include bit line contact holes, and the wires 18 may include bit lines.
[0138] According to a fourth aspect of this application, embodiments of this application also provide a semiconductor device, comprising a semiconductor device structure obtained using the semiconductor device structure fabrication method provided in any of the embodiments of the second aspect described above. The semiconductor device may include dynamic random access memory, etc., and the contact holes 15 contained in the semiconductor device structure may include bit line contact holes, and the conductive lines 18 may include bit lines.
[0139] In other aspects, embodiments of this application also provide an electronic device, including the semiconductor device structure of the above embodiments or a semiconductor device structure obtained using the semiconductor device structure fabrication method of the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, television, artificial intelligence device, etc.
[0140] In summary, this embodiment of the application increases the doping concentration of the doped semiconductor layer 14 (doped polysilicon layer) to a higher level than the conventional doping concentration when filling the contact hole 15, thereby weakening the filling ability of the doped semiconductor layer 14. This causes the doped semiconductor layer 14 to naturally form filling defects such as holes and / or gaps during filling. By utilizing the ablation and widening effect of the holes and / or gaps generated when the doped semiconductor layer 14 is etched back, a recessed structure 16 is naturally formed on the top, which can significantly increase the surface area of the top surface of the doped semiconductor layer 14, thereby significantly increasing the contact area on the top surface of the doped semiconductor layer 14 and thus greatly reducing the contact resistance. When a metal layer 20 for forming a conductor 18 is deposited on top of a contact hole 15 with a recessed structure 16, the metal layer 20 naturally fills the recessed structure 16 and forms a tight contact with the doped semiconductor layer 14, thereby forming a special contact structure on top of the contact hole 15. This significantly increases the contact area when the subsequently formed conductor 18 connects to the contact hole 15, reducing not only the contact resistance between the conductor 18 and the contact hole 15 but also the resistance of the contact hole 15 itself. By optimizing the contact structure when connecting the contact hole 15 and the conductor 18, the overall resistance of the circuit is significantly reduced. This embodiment of the application achieves an effective increase in the contact area of the contact hole 15 without adding any additional processes, making the process simple and reliable. When the semiconductor device structure of this embodiment is applied to semiconductor devices, including dynamic random access memory (DRAM), further miniaturization of the device can be achieved, and RC delay can be reduced, power consumption can be lowered, signal integrity can be enhanced, and lifespan can be extended.
[0141] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.
Claims
1. A method for fabricating a semiconductor device structure, characterized in that, include: Provide substrate; An active region is formed on the substrate; A contact hole is formed on the active region, and a doped semiconductor layer is filled in the contact hole. The top surface of the doped semiconductor layer away from the substrate has a recessed structure, and the recessed structure increases the contact area on the top surface of the doped semiconductor layer. A wire is formed that is connected to the top surface of the doped semiconductor layer. The lower end of the wire enters the recessed structure to fill it and is in close contact with the doped semiconductor layer. The wire is a bit line and the material of the wire includes metal. Specifically, by increasing the doping concentration of the doped semiconductor layer, the filling ability of the doped semiconductor layer during the filling process is weakened, causing poor filling at the top of the doped semiconductor layer deposition, thereby forming a filling defect. The etching process is used to ablate and widen the filling defect located on the top of the doped semiconductor layer, naturally forming the recessed structure on the top surface of the doped semiconductor layer after the re-etching.
2. The method for fabricating a semiconductor device structure according to claim 1, characterized in that, The formation of a contact hole in the active region specifically includes: An interlayer dielectric layer is formed on the surface of the substrate to cover the active region; A contact hole trench is formed on the surface of the interlayer dielectric layer, with its bottom connected to the active region; A doped semiconductor layer is filled into the contact hole trench, and the doped semiconductor layer is made to have filling defects. The excess doped semiconductor layer on the top of the contact hole trench is removed, and the filling defects present in the doped semiconductor layer are used to form a recessed structure on the top surface of the doped semiconductor layer after removal, thereby forming a contact hole.
3. The method for fabricating a semiconductor device structure according to claim 2, characterized in that, An epitaxial process is used to fill the contact hole trench with a polycrystalline silicon layer, and the polycrystalline silicon layer is phosphorus-doped to form a phosphorus-doped polycrystalline silicon layer, which serves as the doped semiconductor layer. By increasing the doping concentration when doping the polycrystalline silicon layer, the doped polycrystalline silicon layer is encouraged to generate pores and / or gaps, thereby forming filling defects. The excess doped polysilicon layer on the top of the contact hole trench is removed by using a back etching process, and the recessed structure is formed by the widening effect of etching on the holes and / or gaps.
4. The method for fabricating a semiconductor device structure according to claim 2, characterized in that, Also includes: A metal layer is formed on the surface of the interlayer dielectric layer, such that the metal layer covers the top surface of the doped semiconductor layer exposed from the top of the contact hole, and enters the recessed structure to fill it, and is in close contact with the doped semiconductor layer; The metal layer is patterned, and a conductive line connected to the top surface of the doped semiconductor layer is formed on the surface of the interlayer dielectric layer.
5. A semiconductor device structure, characterized in that, include: Substrate; Active region provided on the substrate; Contact holes provided on the active region; The contact hole is filled with a doped semiconductor layer, and the top surface of the doped semiconductor layer away from the substrate has a recessed structure, which increases the contact area on the top surface of the doped semiconductor layer. The semiconductor device structure is prepared using the semiconductor device structure preparation method according to any one of claims 1-4.
6. The semiconductor device structure according to claim 5, characterized in that, Also includes: A wire is provided on the contact hole, the wire is located on the top surface of the doped semiconductor layer and enters the recessed structure to fill it, and is in close contact with the doped semiconductor layer.
7. The semiconductor device structure according to claim 5, characterized in that, The doped semiconductor layer has filling defects, which are used to form the recessed structure.
8. The semiconductor device structure according to claim 7, characterized in that, The doped semiconductor layer includes a doped polysilicon layer; and / or, the filling defects include holes and / or gaps; and / or, the doping concentration of the doped semiconductor layer is 2 × 10⁻⁶. 21 atoms / cm 3 The above; and / or, the doped semiconductor layer includes a phosphorus-doped semiconductor layer.
9. The semiconductor device structure according to claim 6, characterized in that, An interlayer dielectric layer is provided on the substrate to cover the active region. The contact hole is disposed in the interlayer dielectric layer and is connected to the active region through the bottom. The wire is located on the interlayer dielectric layer and is connected to the top surface of the doped semiconductor layer exposed from the top of the contact hole.
10. A semiconductor device, characterized in that, The semiconductor device includes the semiconductor device structure according to any one of claims 5-9, or the semiconductor device structure obtained by the semiconductor device structure preparation method according to any one of claims 1-4, wherein the semiconductor device includes a dynamic random access memory, and the contact holes contained in the semiconductor device structure include bit line contact holes.