High-reliability and low-parasitic-parameter GaN hybrid integrated module

Abstract

The invention relates to a GaN hybrid integrated module with high reliability and low parasitic parameters. The GaN hybrid integrated module comprises a substrate and a plurality of devices arranged at the top of the substrate, the plurality of devices comprise a GaN power device, a driving chip and a resistance-capacitance device. The GaN power device, the driving chip and the capacitor device are integrated on the thick-film ceramic substrate by using an advanced hybrid integration process, parasitic parameters and thermal noise introduced by a bonding wire can be avoided, and meanwhile, the ceramic substrate with low expansion coefficient, high thermal conductivity and high insulativity can quickly conduct heat of the power device, so that the power device is more compact in structure. The thick film circuit sintered on the substrate can maintain excellent stability in a high-temperature and high-voltage working environment.

Description

Technical Field

[0001] The invention relates to the technical field of power electronic hybrid integrated circuits, and in particular to a high-reliability, low-parasitic parameter GaN hybrid integrated module. Background Art

[0002] Compared with traditional Si (silicon) materials, GaN (gallium nitride) materials have a larger bandgap, higher electron mobility, saturation drift velocity and critical breakdown electric field, can achieve smaller on-resistance, faster on-speed, and can ensure more stable electrical performance under high temperature conditions. Therefore, GaN devices have broad application prospects in the field of DC / DC converters, can effectively reduce the size of the converter, improve efficiency and power density, and help to achieve miniaturization and lightweight of the power supply system.

[0003] In the prior art, GaN devices have some inherent problems in their applications that are difficult to solve: the parasitic parameters of the driving circuit at high frequencies cannot be ignored, and the Miller oscillation, turn-on oscillation, and turn-off oscillation caused by high di / dt and high dv / dt may lead to mis-conduction of the switch tube, and even device breakdown and damage. In the layout and wiring of GaN devices, the power circuit and the driving circuit are the main aspects of introducing parasitic parameters. The parasitic inductance in the circuit will generate an offset voltage at the switching moment, thereby affecting the switching speed, increasing the switching loss, and increasing the oscillation amplitude of the switch tube driving voltage. Summary of the invention

[0004] In order to solve the deficiencies in the prior art, an object of the present invention is to provide a high-reliability, low-parasitic parameter GaN hybrid integrated module.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A high-reliability, low-parasitic parameter GaN hybrid integrated module comprises a substrate and a plurality of devices arranged on the top of the substrate.

[0007] The substrate is a thick film ceramic substrate printed by a hybrid integration process; conductive wires are printed on the surface of the substrate; a glass layer, a first conductive layer, a second conductive layer, and a third conductive layer are sintered in sequence on the top surface of the substrate from top to bottom, and a fourth conductive layer is sintered on the bottom surface of the substrate; a plurality of through holes and vias for realizing electrical connection between different layers are provided on the substrate; all devices are arranged above the glass layer, and the device pads corresponding to each device are located in the first conductive layer; a bottom pad is provided on the bottom surface of the fourth conductive layer, and the bottom pad includes a first pad HS, a second pad VCL, a third pad VCC, a fourth pad GND, a fifth pad H, a sixth pad L, and a seventh pad BST.

[0008] The several devices include a high-side clamping power circuit, a driving chip N1, a first driving circuit, a second driving circuit, a first power supply circuit, a second power supply circuit and a dead zone control circuit; the high-side clamping power circuit includes a first GaN switch tube Q1 and a second GaN switch tube Q2.

[0009] The first GaN switch tube Q1 and the second GaN switch tube Q2 are symmetrically arranged in the middle area above the top surface of the substrate; the drain of the first GaN switch tube Q1 and the source of the second GaN switch tube Q2 are connected through the first conductive layer, and are connected to the first pad HS through the corresponding through hole; the source of the first GaN switch tube Q1 is connected to the fourth pad GND through the first conductive layer, the third conductive layer and the corresponding through hole; the drain of the second GaN switch tube Q2 is connected to the second pad VCL through the first conductive layer, the second conductive layer and the corresponding through hole.

[0010] The driving chip N1 is located in the middle area of ​​the lower side of the top surface of the substrate; the first driving circuit is arranged on the right side of the driving chip N1 on the top surface of the substrate; the second driving circuit is arranged on the left side of the driving chip N1 on the top surface of the substrate; the driving chip N1 is connected to the gate of the first GaN switch tube Q1 through the first driving circuit, the first conductive layer, the second conductive layer and the corresponding vias; the driving chip N1 is connected to the gate of the second GaN switch tube Q2 through the second driving circuit, the first conductive layer, the second conductive layer and the corresponding vias.

[0011] The first power supply circuit is arranged on the right side of the driver chip N1 on the top surface of the substrate, and is connected to the third pad VCC and the fourth pad GND through the first conductive layer and the corresponding through hole; the second power supply circuit is arranged on the left side of the driver chip N1 on the top surface of the substrate, and is connected to the seventh pad BST through the first conductive layer, the second conductive layer and the corresponding through hole; the fifth pad H and the sixth pad L are connected to the driver chip N1 through the corresponding vias and the gold solder balls arranged on the first conductive layer.

[0012] The dead zone control loop is arranged on the right side of the driver chip N1 on the top surface of the substrate, below the first driver circuit, and the dead zone control loop includes a dead zone resistor R4 and a decoupling capacitor C5; the dead zone resistor R4 is printed on the substrate, and the decoupling capacitor C5 is placed parallel to the dead zone resistor R4, and the two are connected in parallel; one end of the decoupling capacitor C5 is connected to the DT pin of the driver chip N1 through the first conductive layer, and the other end is connected to the fourth pad GND through the first conductive layer and the corresponding through hole.

[0013] According to the preferred embodiment of the present invention, the first driving circuit includes a first driving resistor R1 and a first driving capacitor C1; the first driving resistor R1 is printed on a film-forming substrate. The first end of the first driving resistor R1 is connected to the LO_SC pin of the driving chip N1, and the second end of the first driving resistor R1 is connected to the gate of the first GaN switch tube Q1 and the LO_SK pin of the driving chip N1; the first end of the first driving capacitor C1 is connected to the VDDL pin of the driving chip N1, and the second end of the first driving capacitor C1 is grounded. The first driving resistor R1 is printed together with the wire by thick film technology and is in the same layer as the first conductive layer. The first end of the first driving resistor R1 is connected to the pad corresponding to the LO_SC pin of the driving chip, and the second end of the first driving resistor R1 is connected to the gate of the first GaN switch tube Q1 and the pad corresponding to the LO_SK pin of the driving chip N1 through a wire. The first end of the first driving capacitor C1 is connected to the pad corresponding to the VDDL pin of the driving chip N1, and the second end of the first driving capacitor C1 is connected to the large area GND of the third conductive layer through a via on the pad.

[0014] According to the preferred embodiment of the present invention, the second driving circuit includes a second driving resistor R2 and a second driving capacitor C2; the second driving resistor R2 is printed on the film-forming substrate. The first end of the second driving resistor R2 is connected to the HO_SC pin of the driving chip N1, and the second end of the second driving resistor R2 is connected to the gate of the second GaN switch tube Q2 and the HO_SK pin of the driving chip N1; the first end of the second driving capacitor C2 is connected to the VDDH pin of the driving chip N1, and the second end of the second driving capacitor C2 is connected to the first pad HS. The second driving resistor R2 is printed by thick film technology together with the wire and is in the same layer as the first conductive layer. The first end of the second driving resistor R2 is connected to the pad corresponding to the HO_SC pin of the driving chip N1, and the second end of the second driving resistor R2 is connected to the gate of the second GaN switch tube Q2 and the pad corresponding to the HO_SK pin of the driving chip N1 through the wire; the first end of the second driving capacitor C2 is connected to the pad corresponding to the VDDH pin of the driving chip N1, and the second end of the second driving capacitor C2 is connected to the first pad HS of the fourth conductive layer through the via on the pad.

[0015] According to the preferred embodiment of the present invention, the first power supply circuit includes an enable resistor R3 and a first energy storage capacitor C3. The enable resistor R3 is printed on a film-forming substrate; the first end of the enable resistor R3 is connected to the EN pin of the driver chip N1, and the second end of the enable resistor R3 is respectively connected to the VCC power supply and the VCC pin of the driver chip N1; the first end of the first energy storage capacitor C3 is respectively connected to the VCC power supply and the VCC pin of the driver chip N1, and the second end of the first energy storage capacitor C3 is connected to the PGND pin of the driver chip N1. The enable resistor R3 is printed together with the wire by thick film technology and is in the same layer as the first conductive layer. The first end of the enable resistor R3 is connected to the pad corresponding to the EN pin of the driver chip N1, and the second end of the enable resistor R3 is connected to the third pad VCC of the fourth conductive layer through a via on the pad; the first end of the first energy storage capacitor C3 is connected to the second end of the enable resistor R3, and the second end of the first energy storage capacitor C3 is connected to the large-area GND of the third conductive layer through a via on the pad.

[0016] Preferably, according to the present invention, the second power supply circuit includes a second energy storage capacitor C4; the first end of the second energy storage capacitor C4 is connected to the BST pin of the driver chip N1, and the second end of the second energy storage capacitor C4 is respectively connected to the HS pin of the driver chip N1 and the drain of the first GaN switch tube Q1; the first end of the second energy storage capacitor C4 is connected to the pad corresponding to the BST pin of the driver chip N1, and the second end of the second energy storage capacitor C4 is connected to the first pad HS of the fourth conductive layer through a via on the pad.

[0017] Preferably, according to the present invention, the dead zone control loop includes a dead zone resistor R4 and a decoupling capacitor C5; the dead zone resistor R4 is printed on a film-forming substrate; one end of the dead zone resistor R4 and the decoupling capacitor C5 connected in parallel is connected to the DT pin of the driver chip N1, and the other end is connected to the GND pin of the driver chip N1. The dead zone resistor R4 is printed together with the wire by a thick film process, the dead zone resistor R4 is in the same layer as the first conductive layer, the first end of the dead zone resistor R4 is connected to the pad corresponding to the DT pin of the driver chip N1, and the second end of the dead zone resistor R4 is connected to the large area GND of the third conductive layer through a via on the pad. The decoupling capacitor C5 is placed in parallel with the dead zone resistor R4, and the two ends of the electrode of the decoupling capacitor C5 are respectively connected to the two ends of the electrode of the dead zone resistor R4 through a wire.

[0018] Preferably according to the present invention, the high-side clamping power circuit further includes a clamping capacitor outside the module.

[0019] Preferably according to the present invention, the third conductive layer is printed as a whole block of silver paste and is only connected to the GND signals of the remaining conductive layers.

[0020] Preferably, according to the present invention, the first GaN switch tube and the second GaN switch tube are bare chips without packaging, and the connection between the two and the substrate is flip-chip.

[0021] Preferably, according to the present invention, the driver chip N1 is a bare chip that has not been packaged, and the driver chip is connected to the substrate by flip-chip bonding.

[0022] Compared with the prior art, the advantages of the present invention are:

[0023] (1) In order to solve the application problems of GaN and improve its applicability in the high-frequency field, the present invention designs a GaN integrated module with high reliability and low parasitic parameters. The GaN driving circuit and the GaN switch tube are integrated into the same ceramic substrate through the low parasitic parameter multi-layer wiring technology and the double-sided printing hybrid integration process. Two capacitors are configured externally to be applied to the power circuit of the power module, realizing the high-side clamping topology and facilitating the power level layout and application of the power module. Compared with discrete devices, the integrated module described in the present invention has higher reliability and lower parasitic parameters. The integration of the switch tube and the driver chip can effectively reduce the design difficulty of the peripheral circuit of the GaN device and improve the engineering applicability of the GaN device.

[0024] (2) The present invention realizes the minimum current loop through reasonable layout, ensuring that the current loop of each switch tube and the power current loop of the entire module are minimized; through the hybrid integration process, the length of the interconnection line between devices is reduced, the connection contact area is increased, and the common source inductance and parasitic capacitance of the GaN drive loop and the power loop can be effectively reduced. The GaN integrated module described in the present invention can effectively reduce the board area occupied by the GaN device and its drive loop, solve the problem of the usability and ease of use of the GaN device, and the module pin definition is simple. High-side active clamping can be achieved by configuring fewer external capacitors and connection ports, and it has a wide range of application prospects in small and medium power DC / DC converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the top surface structure of the GaN hybrid integrated module with high reliability and low parasitic parameters in the present invention;

[0026] Figure 2 It is a schematic diagram of the bottom structure of the GaN hybrid integrated module with high reliability and low parasitic parameters in the present invention;

[0027] Figure 3 It is a left-view structural schematic diagram of a GaN hybrid integrated module with high reliability and low parasitic parameters in the present invention;

[0028] Figure 4It is a circuit connection diagram of the GaN hybrid integrated module with high reliability and low parasitic parameters in the present invention;

[0029] Figure 5 It is a circulation loop diagram of the GaN hybrid integrated module with high reliability and low parasitic parameters in the present invention.

[0030] in:

[0031] 1. Second GaN switch tube Q2, 2. First GaN switch tube Q1, 3. Driving chip N1, 4. Second driving resistor R2, 5. Second driving capacitor C2, 6. Second energy storage capacitor C4, 7. First driving resistor R1, 8. First driving capacitor C1, 9. Dead zone resistor R4, 10. Decoupling capacitor C5, 11. Enable resistor R3, 12. First energy storage capacitor C3, 13. Second pad VCL, 14. Fourth pad GND, 15. Fifth pad H, 16. Sixth pad L, 17. Fourth pad GND, 18. First pad HS, 19. Seventh pad BST, 20. First pad HS, 21. Third pad VCC, 22. Second GaN switch tube Q2 turns off the current loop, 23. First GaN switch tube Q1 turns on the current loop, 24. Second GaN switch tube Q2 turns on the current loop, 25. First GaN switch tube Q1 turns off the current loop. DETAILED DESCRIPTION

[0032] The present invention will be further described below in conjunction with the accompanying drawings:

[0033] like Figures 1 to 4 A high-reliability, low-parasitic parameter GaN hybrid integrated module is shown, and the GaN hybrid integrated module includes a substrate and a plurality of devices arranged on the top of the substrate. The plurality of devices include a GaN power device, a driver chip, and a resistor and capacitor device. The GaN power device includes a first GaN switch tube and a second GaN switch tube. The GaN power device and the driver chip are flipped on the substrate, and the resistor and capacitor device are connected to the GaN power device and the driver chip N1 to drive the GaN power device to turn on and off. The packaging and pad form of the GaN device in the present invention are not limited to the illustrated styles.

[0034] The substrate is a thick film ceramic substrate with double-sided multilayer wiring printed by hybrid integration process. The top surface of the double-sided multilayer wiring thick film ceramic substrate is printed with conductors and resistors, and the bottom surface is printed with pads. The substrate adopts an alumina ceramic substrate, and its excellent performance of high mechanical strength, high insulation, high thermal stability, low thermal expansion coefficient, and high thermal conductivity coefficient helps to improve the reliability and heat dissipation capacity of the integrated module. The top surface of the substrate is sintered with a glass layer, a first conductive layer, a second conductive layer, and a third conductive layer from top to bottom, and the bottom surface of the substrate is sintered with a fourth conductive layer; the substrate is provided with a plurality of through holes and vias for realizing electrical connection between different layers; all devices are arranged above the glass layer, and the device pads corresponding to each device are all located in the first conductive layer; the bottom surface of the fourth conductive layer is provided with a bottom pad, and the bottom pad includes a first pad HS, a second pad VCL, a third pad VCC, a fourth pad GND, a fifth pad H, a sixth pad L, and a seventh pad BST.

[0035] The several devices include a high-side clamped power circuit, a driver chip N1, a first driver circuit, a second driver circuit, a first power supply circuit, a second power supply circuit and a dead zone control circuit; the high-side clamped power circuit includes a first GaN switch tube Q1 and a second GaN switch tube Q2. The high-side clamped power circuit includes two GaN devices. The two GaN devices, the driver chip N1 and the resistor and capacitor devices are all arranged on the top of the substrate. The GaN device and the driver chip N1 are connected to the welding area on the substrate by flip-chip welding. The capacitor is integrated on the substrate as a patch component. The capacitor and the substrate are connected by a current-carrying welding process. The resistor is sintered and printed together with the conductive layer by a thick film process. The conduction and shutdown of the GaN device are controlled by the driver chip N1 and the resistor and capacitor devices.

[0036] like Figure 1 and Figure 2As shown, the first GaN switch tube Q1 and the second GaN switch tube Q2 are symmetrically arranged in the middle area above the top surface of the substrate; the drain of the first GaN switch tube Q1 and the source of the second GaN switch tube Q2 are connected through the first conductive layer, and connected to the first pad HS through the corresponding through hole; the source of the first GaN switch tube Q1 is connected to the fourth pad GND through the first conductive layer, the third conductive layer and the corresponding through hole; the drain of the second GaN switch tube Q2 is connected to the second pad VCL through the first conductive layer, the second conductive layer and the corresponding through hole. The driver chip N1 is located in the middle area of ​​the lower side of the top surface of the substrate; the first drive circuit is arranged on the right side of the driver chip N1 on the top surface of the substrate; the second drive circuit is arranged on the left side of the driver chip N1 on the top surface of the substrate; the driver chip N1 is connected to the gate of the first GaN switch tube Q1 through the first drive circuit, the first conductive layer, the second conductive layer and the corresponding through hole; the driver chip N1 is connected to the gate of the second GaN switch tube Q2 through the second drive circuit, the first conductive layer, the second conductive layer and the corresponding through hole. The first power supply circuit is arranged on the right side of the driver chip N1 on the top surface of the substrate, and is connected to the third pad VCC and the fourth pad GND through the first conductive layer and the corresponding through hole; the second power supply circuit is arranged on the left side of the driver chip N1 on the top surface of the substrate, and is connected to the seventh pad BST through the first conductive layer, the second conductive layer and the corresponding through hole; the fifth pad H and the sixth pad L are connected to the driver chip N1 through the corresponding vias and the gold solder balls arranged on the first conductive layer.

[0037] Furthermore, the dead zone control loop is arranged on the right side of the driver chip N1 on the top surface of the substrate, below the first driver circuit, and the dead zone control loop includes a dead zone resistor R4 and a decoupling capacitor C5; the dead zone resistor R4 is printed on the substrate, and the decoupling capacitor C5 is placed parallel to the dead zone resistor R4, and the two are connected in parallel; one end of the decoupling capacitor C5 is connected to the DT pin of the driver chip N1 through the first conductive layer, and the other end is connected to the fourth pad GND through the first conductive layer and the corresponding through hole.

[0038] Furthermore, the internal topology of the high-side clamp power circuit adopts a high-side active clamp topology based on a GaN switch tube. The power circuit is composed of two GaN switch tubes forming a high-side active clamp circuit, and the GaN switch tube is controlled to turn on and off by the signal given by the driver chip N1. The connection with the main power board is achieved through the bottom pad of the GaN hybrid integrated module substrate.

[0039] Furthermore, the driving circuit of the GaN switch tube includes a first driving circuit and a second driving circuit, both of which are implemented through the second conductive layer, and the power circuit is implemented through the first conductive layer and the fourth conductive layer, which can reduce the common-mode inductance of the driving circuit caused by the high dv / dt of the power circuit.

[0040] Furthermore, the second energy storage capacitor C4 in the second power supply circuit is a bootstrap capacitor, which can ensure that the voltage provided by the second power supply circuit does not exceed the voltage of the first power supply circuit and can effectively reduce the ringing caused by the parasitic inductance between the drain and source of the second GaN switch tube.

[0041] Furthermore, the present invention uses a GaN-specific driver chip N1, which is placed under the GaN device, and the driving and supply capacitors are placed around the driver chip N1. The driving signal is connected to the gate of the GaN device through the first conductive layer, the via, the second conductive layer, the via, and then to the first conductive layer. The first energy storage capacitor and the second energy storage capacitor are both close to the pins of the driver chip N1, shortening the drive turn-on loop and reducing conduction oscillation. By utilizing the different current pulling and sinking capabilities of the driver chip N1, different driving resistance parameters are configured at the SC and SK pins of the driver chip N1, which can ensure the normal operation of the device while effectively reducing the number of components, optimizing the circuit design, reducing the board area, and improving the module power density.

[0042] The functions of the pins of the driver chip N1 are:

[0043] BST is used to provide an external boost voltage for starting the internal circuit or improving the driving capability. VDDH is the high-voltage power input terminal, which is used as the operating voltage of some internal circuits. DT is the dead time control pin, which is used to control the dead time of the switch tube to prevent short circuit caused by simultaneous conduction. LI and HI refer to the low side and high side drive signal input terminals respectively. HO-SC and LO-SC refer to the high side and low side short circuit detection output terminals respectively. HO-SK and LO-SK refer to the high side and low side overcurrent protection or fault detection signal output terminals respectively. HS is the high side drive signal output terminal, which is used to drive the high side power switch tube. GND is the signal ground (Ground), which is used for the grounding of the dead time control circuit part. PGND is the power ground (Power Ground), which is used for the grounding of the drive circuit part. VDDL is the logic power supply voltage input terminal, which is used to drive the logic circuit inside the chip to work. EN is the enable pin, which is used to control the opening or closing of the driver chip. VCC is the power input terminal, which is usually used to provide the main power voltage of the driver chip.

[0044] The working principle of the high reliability and low parasitic parameter GaN hybrid integrated module described in the present invention is:

[0045] like Figure 4 and Figure 5 As shown, the present invention is used as a power device of a power module, and is connected to the main power circuit of the power supply through the bottom pad. Among them, the second pad VCL is connected to the input terminal VIN of the power module through an external clamping capacitor, the first pad HS is connected to the transformer of the power module, the working voltage provided by the power supply circuit is obtained through the third pad VCC, the fifth pad H and the sixth pad L respectively obtain the PWM signal sent by the control chip of the power module, and the fourth pad GND is connected to the power ground of the power module. An input filter capacitor is configured between VIN and GND in the main power circuit.

[0046] The working principle of the high reliability and low parasitic parameter GaN hybrid integrated module described in the present invention is:

[0047] The present invention first turns on the first GaN switch tube Q1, and then controls the driving chip N1 to charge the second driving capacitor and the second energy storage capacitor. When the first GaN switch tube Q1 is turned on and the second GaN switch tube Q2 is turned off, the conduction current flows out from the positive end of the first energy storage capacitor C3, passes through the first driving resistor R1 to the gate of the first GaN switch tube Q1, and then flows back from the source of the first GaN switch tube Q1 to the negative end of the first energy storage capacitor C3, forming a first switch tube conduction current loop. At this time, the midpoint position HS of the two switch tubes is a low level. The second GaN switch tube Q2 turn-off current is pulled down from the gate of the second GaN switch tube Q2 to the drive recovery pin of the driving chip to the reference level HS of the second GaN switch tube Q2 drive loop, forming a second switch tube turn-off current loop.

[0048] When the second GaN switch tube Q2 is turned on and the first GaN switch tube Q1 is turned off, the on-current flows out from the positive end of the second energy storage capacitor C4, passes through the second drive resistor R2 to the gate of the second GaN switch tube Q2, and then flows from the source of the second GaN switch tube Q2 to the reference level HS of the second GaN switch tube Q2 drive circuit, forming a second switch tube on-current loop. At this time, the HS level is consistent with the voltage on the external clamping capacitor. The off-current of the first GaN switch tube Q1 is pulled down from the gate of the first GaN switch tube Q1 to the drive recovery pin of the driver chip and then to GND, forming a first switch tube off-current loop.

[0049] When the first GaN switch tube Q1 is turned on, the HS point voltage is pulled down to a low level, and the clamping capacitor configured outside the module stores energy; when the second GaN switch tube Q2 is turned on, the HS point voltage is the voltage on the clamping capacitor, and the energy of the clamping capacitor configured outside the module is released, thereby limiting the rising speed of the gate voltage of the first GaN switch tube Q1, thereby effectively reducing overvoltage and overcurrent phenomena in the circuit, thereby improving the reliability and stability of the circuit.

[0050] The innovative features of the high reliability and low parasitic parameter GaN hybrid integrated module described in the present invention are:

[0051] (1) The present invention realizes the separation of the power device driving circuit and the power circuit of the power module, and connects them at a single point through the bottom pad, thereby avoiding the interference of the power circuit of the power module on the GaN signal circuit. The present invention concentrates the GaN device and the driver chip on a ceramic substrate, and connects them at a single point through the bottom pad, thereby avoiding the interference of the power circuit of the power module on the GaN signal circuit. The advanced packaging process and reasonable board layout design are used to directly connect the GaN drive signal to the device, and the drive circuit is extremely short. The parallel routing of the upper and lower layers of the multi-layer board and the inverted pile welding technology avoid the introduction of parasitic inductance, which can effectively reduce the tailing phenomenon caused by the parasitic parameters in the circuit on the GaN drive and improve the reliability of the circuit.

[0052] (2) The present invention can select GaN devices according to actual working conditions, and only the pads of the GaN module on the substrate can be changed to achieve the replacement of different GaN devices. The fixed GaN drive circuit and layout board solve the application problem of GaN devices, have high portability, and can be applied to various circuit topologies such as forward, flyback, and half-bridge. Only two capacitors are required to realize high-side active clamping, which makes full use of the excellent electrical characteristics of GaN devices while improving the applicability and reliability of GaN devices, thereby effectively reducing the design cost of the iterative power module solution.

[0053] In summary, the present invention utilizes an advanced hybrid integration process to integrate GaN power devices with driver chips and capacitor devices on a thick-film ceramic substrate, which can avoid parasitic parameters and thermal noise introduced by bonding wires. At the same time, the ceramic substrate with low expansion coefficient, high thermal conductivity and high insulation can quickly conduct the heat of the power devices. The thick-film circuit sintered on the substrate can maintain excellent stability in a high-temperature and high-voltage working environment.

[0054] The above-described embodiments are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the scope of protection determined by the claims of the present invention.

Claims

1. A high reliability, low parasitic parameter GaN hybrid integrated module, characterized in that: The GaN hybrid integrated module includes a substrate and a plurality of devices arranged on top of the substrate; The substrate is a thick film ceramic substrate printed by hybrid integration process; the surface of the substrate is printed with conductive wires; the top surface of the substrate is sintered with a glass layer, a first conductive layer, a second conductive layer, and a third conductive layer in sequence from top to bottom, and the bottom surface of the substrate is sintered with a fourth conductive layer; the substrate is provided with a plurality of through holes and vias for realizing electrical connection between different layers; all devices are arranged above the glass layer, and the device pads corresponding to each device are located in the first conductive layer; the bottom surface of the fourth conductive layer is provided with bottom pads, and the bottom pads include a first pad HS, a second pad VCL, a third pad VCC, a fourth pad GND, a fifth pad H, a sixth pad L, and a seventh pad BST; The several devices include a high-side clamping power circuit, a driving chip N1, a first driving circuit, a second driving circuit, a first power supply circuit, a second power supply circuit and a dead zone control circuit; the high-side clamping power circuit includes a first GaN switch tube Q1 and a second GaN switch tube Q2; The first GaN switch tube Q1 and the second GaN switch tube Q2 are symmetrically arranged in the middle area above the top surface of the substrate; the drain of the first GaN switch tube Q1 and the source of the second GaN switch tube Q2 are connected through the first conductive layer, and connected to the first pad HS through the corresponding through hole; the source of the first GaN switch tube Q1 is connected to the fourth pad GND through the first conductive layer, the third conductive layer and the corresponding through hole; the drain of the second GaN switch tube Q2 is connected to the second pad VCL through the first conductive layer, the second conductive layer and the corresponding through hole; The driver chip N1 is located in the middle area of ​​the lower side of the top surface of the substrate; the first drive circuit is arranged on the right side of the driver chip N1 on the top surface of the substrate; the second drive circuit is arranged on the left side of the driver chip N1 on the top surface of the substrate; the driver chip N1 is connected to the gate of the first GaN switch tube Q1 through the first drive circuit, the first conductive layer, the second conductive layer and the corresponding via hole; the driver chip N1 is connected to the gate of the second GaN switch tube Q2 through the second drive circuit, the first conductive layer, the second conductive layer and the corresponding via hole; The first power supply circuit is arranged on the right side of the driver chip N1 on the top surface of the substrate, and is connected to the third pad VCC and the fourth pad GND through the first conductive layer and the corresponding through hole; the second power supply circuit is arranged on the left side of the driver chip N1 on the top surface of the substrate, and is connected to the seventh pad BST through the first conductive layer, the second conductive layer and the corresponding through hole; the fifth pad H and the sixth pad L are connected to the driver chip N1 through the corresponding via hole and the gold solder ball arranged on the first conductive layer; The dead zone control loop is arranged on the right side of the driver chip N1 on the top surface of the substrate, below the first driver circuit, and the dead zone control loop includes a dead zone resistor R4 and a decoupling capacitor C5; the dead zone resistor R4 is printed on the substrate, and the decoupling capacitor C5 is placed parallel to the dead zone resistor R4, and the two are connected in parallel; one end of the decoupling capacitor C5 is connected to the DT pin of the driver chip N1 through the first conductive layer, and the other end is connected to the fourth pad GND through the first conductive layer and the corresponding through hole.

2. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The first driving circuit includes a first driving resistor R1 and a first driving capacitor C1; the first driving resistor R1 is printed on a film forming substrate; The first end of the first driving resistor R1 is connected to the LO_SC pin of the driving chip N1, and the second end of the first driving resistor R1 is connected to the gate of the first GaN switch tube Q1 and the LO_SK pin of the driving chip N1; the first end of the first driving capacitor C1 is connected to the VDDL pin of the driving chip N1, and the second end of the first driving capacitor C1 is grounded; The first drive resistor R1 is printed together with the wire by thick film process and is in the same layer as the first conductive layer. The first end of the first drive resistor R1 is connected to the pad corresponding to the LO_SC pin of the driver chip, and the second end of the first drive resistor R1 is connected to the gate of the first GaN switch tube Q1 and the pad corresponding to the LO_SK pin of the driver chip N1 through a wire. The first end of the first drive capacitor C1 is connected to the pad corresponding to the VDDL pin of the driver chip N1, and the second end of the first drive capacitor C1 is connected to the large area GND of the third conductive layer through a via on the pad.

3. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The second driving circuit includes a second driving resistor R2 and a second driving capacitor C2; the second driving resistor R2 is printed on the film forming substrate; The first end of the second driving resistor R2 is connected to the HO_SC pin of the driving chip N1, and the second end of the second driving resistor R2 is connected to the gate of the second GaN switch tube Q2 and the HO_SK pin of the driving chip N1; the first end of the second driving capacitor C2 is connected to the VDDH pin of the driving chip N1, and the second end of the second driving capacitor C2 is connected to the first pad HS; The second driving resistor R2 is printed together with the wire by thick film process and is in the same layer as the first conductive layer. The first end of the second driving resistor R2 is connected to the pad corresponding to the HO_SC pin of the driving chip N1, and the second end of the second driving resistor R2 is connected to the gate of the second GaN switch tube Q2 and the pad corresponding to the HO_SK pin of the driving chip N1 through the wire; the first end of the second driving capacitor C2 is connected to the pad corresponding to the VDDH pin of the driving chip N1, and the second end of the second driving capacitor C2 is connected to the first pad HS of the fourth conductive layer through a via on the pad.

4. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The first power supply circuit includes an enabling resistor R3 and a first energy storage capacitor C3; The enabling resistor R3 is printed on the film forming substrate; the first end of the enabling resistor R3 is connected to the EN pin of the driving chip N1, and the second end of the enabling resistor R3 is respectively connected to the VCC power supply and the VCC pin of the driving chip N1; the first end of the first energy storage capacitor C3 is respectively connected to the VCC power supply and the VCC pin of the driving chip N1, and the second end of the first energy storage capacitor C3 is connected to the PGND pin of the driving chip N1; The enable resistor R3 is printed together with the wire by thick film process and is in the same layer as the first conductive layer. The first end of the enable resistor R3 is connected to the pad corresponding to the EN pin of the driver chip N1, and the second end of the enable resistor R3 is connected to the third pad VCC of the fourth conductive layer through a via on the pad; the first end of the first energy storage capacitor C3 is connected to the second end of the enable resistor R3, and the second end of the first energy storage capacitor C3 is connected to the large area GND of the third conductive layer through the via on the pad.

5. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The second power supply circuit includes a second energy storage capacitor C4; the first end of the second energy storage capacitor C4 is connected to the BST pin of the driver chip N1, and the second end of the second energy storage capacitor C4 is respectively connected to the HS pin of the driver chip N1 and the drain of the first GaN switch tube Q1; the first end of the second energy storage capacitor C4 is connected to the pad corresponding to the BST pin of the driver chip N1, and the second end of the second energy storage capacitor C4 is connected to the first pad HS of the fourth conductive layer through a via on the pad.

6. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The dead zone control loop includes a dead zone resistor R4 and a decoupling capacitor C5; the dead zone resistor R4 is printed on a film-forming substrate; one end of the dead zone resistor R4 and the decoupling capacitor C5 connected in parallel is connected to the DT pin of the driver chip N1, and the other end is connected to the GND pin of the driver chip N1; The dead zone resistor R4 is printed together with the wire by thick film process, the dead zone resistor R4 is in the same layer as the first conductive layer, the first end of the dead zone resistor R4 is connected to the pad corresponding to the DT pin of the driver chip N1, and the second end of the dead zone resistor R4 is connected to the large area GND of the third conductive layer through the via hole on the pad; The decoupling capacitor C5 is placed in parallel with the dead zone resistor R4, and two ends of the electrode of the decoupling capacitor C5 are respectively connected to two ends of the electrode of the dead zone resistor R4 through wires.

7. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The high-side clamping power loop also includes a clamping capacitor outside the module.

8. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The third conductive layer is printed with a whole piece of silver paste and is only connected to the GND signals of the remaining conductive layers.

9. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The first GaN switch tube and the second GaN switch tube are bare chips without packaging, and the connection between the two and the substrate is flip-chip.

10. The high reliability, low parasitic parameter GaN hybrid integrated module according to claim 1, characterized in that: The driver chip N1 is a bare chip without packaging, and the driver chip is connected to the substrate by flip-chip bonding.

Images