Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a first substrate which is provided with a first surface and a second surface which are opposite to each other, and comprises a plurality of photosensitive regions and isolation regions located between the adjacent photosensitive regions; forming a first reflecting layer in each isolation region; and forming a first device layer on the surface of the first surface, the first device layer is internally provided with a second reflection layer located on each photosensitive area, and the second reflection layer is connected with the first reflection layer.

Description

Technical Field

[0001] The invention relates to a semiconductor manufacturing process, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Direct Time Of Flight (DTOF) sensors have become a hot direction for the development of 3D depth vision technology due to their long measurement distance and good low-light performance. In the early stage of the development of direct time of flight, the front side illuminated (FSI) technology was the main one. Due to the presence of a large number of metal wires, the front side illuminated technology has a large interference on the light entering the sensor surface, which prevents a considerable part of the light from entering the photodiode (PD) of the next layer, and the signal-to-noise ratio is low. With the improvement of technology, the back-side illuminated (BSI) technology has been developed. The back-side illumination technology transfers the metal wires to the back of the photodiode, and the light can directly enter the photodiode, so the signal-to-noise ratio can be greatly improved, and it can be used with more complex and larger-scale circuits to improve the sensor reading speed. Compared with the front-incident technology, the performance of the back-side illumination technology has been greatly improved. Combined with the deep trench isolation structure, the optical and electrical isolation of adjacent photosensitive areas can be achieved. When the photons enter the photosensitive area, some enter the PN junction area and avalanche occurs, and some do not enter the PN junction area and avalanche occurs, resulting in waste.

[0003] However, the photon detection efficiency of the photosensitive area of ​​current photoelectric sensors needs to be further improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so that the five sides of the photosensitive area are isolated, the photon loss is reduced, and the photon detection efficiency of the photosensitive area of ​​the photoelectric sensor is improved.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, wherein the method comprises: providing a first substrate, the first substrate having a first surface and a second surface opposite to each other, the first substrate comprising a plurality of photosensitive regions and isolation regions located between adjacent photosensitive regions; forming a first reflective layer in each isolation region; forming a first device layer on the surface of the first surface, the first device layer having a second reflective layer located on each photosensitive region, and the second reflective layer is connected to the first reflective layer.

[0006] Optionally, the photosensitive region has a photoelectric doping region, and the first surface exposes the photoelectric doping region; the doping ions of the photoelectric doping region include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

[0007] Optionally, the method for forming the photoelectric doping region includes: performing ion implantation on the photosensitive region; the process parameters of the ion implantation include: the implanted ions are P-type conductive ions or N-type conductive ions; the dose range of the implanted ions is 3E11 ions / cm 2 ~5E15 ions / cm 2 ; The energy range of implanted ions is 5KeV~2200KeV.

[0008] Optionally, the method for forming the first reflective layer includes: forming a first opening in each isolation region; and forming a first reflective layer in each first opening to fill the first opening.

[0009] Optionally, the method for forming the first opening includes: forming a first mask layer on the surface of the first substrate, the first mask layer exposing a portion of the surface of the first substrate; and etching the first substrate using the first mask layer as a mask to form a first opening located between adjacent photosensitive areas.

[0010] Optionally, before forming the first opening, the method further includes: forming a second dielectric layer on the surface of the first substrate; the second dielectric layer includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

[0011] Optionally, after forming the first opening and before forming the first reflective layer, the method further includes: forming a third dielectric layer on a surface of the first opening, wherein the third dielectric layer includes one of an oxide layer and a high dielectric constant layer, or both of them overlap.

[0012] Optionally, it also includes: providing a second substrate, the second substrate having a third surface and a fourth surface relative to each other; forming a second device layer on the second substrate, the second device layer including: a fourth dielectric layer, a second interconnect structure located in the fourth dielectric layer, and a second device located in the fourth dielectric layer, the second device being electrically connected to the second interconnect structure; and bonding the fourth surface of the second substrate toward the first surface of the first substrate.

[0013] Optionally, the first device layer further includes: a first dielectric layer, a first interconnect structure located in the first dielectric layer, and a first device located in the first dielectric layer, the first device being electrically connected to the first interconnect structure; after the second substrate is bonded to the first substrate, the second interconnect structure is electrically connected to the first interconnect structure.

[0014] Optionally, the method further includes: after the first substrate and the second substrate are bonded, the method further includes: performing a planarization process on the second surface of the first substrate until the bottom surface of the first reflective layer is exposed.

[0015] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a first substrate having a first surface and a second surface relative to each other, the first substrate including a plurality of photosensitive areas and isolation areas located between adjacent photosensitive areas; a first reflective layer located in each isolation area; a first device layer located on the surface of the first surface, the first device layer having a second reflective layer located on each photosensitive area, and the second reflective layer is connected to the first reflective layer.

[0016] Optionally, the photosensitive region has a photoelectric doping region, and the first surface exposes the photoelectric doping region; the doping ions of the photoelectric doping region include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

[0017] Optionally, the first device layer further includes: a first dielectric layer, a first interconnect structure located in the first dielectric layer, and a first device located in the first dielectric layer, wherein the first device is electrically connected to the first interconnect structure.

[0018] Optionally, the first interconnect structure is also electrically connected to the photosensitive area, and the second reflective layer is electrically insulated from the first interconnect structure.

[0019] Optionally, it further includes: a second substrate bonded to the first substrate, the second substrate having a third surface and a fourth surface opposite to each other, and the fourth surface is bonded toward the first surface.

[0020] Optionally, it also includes: a second device layer located on the surface of the fourth surface; the second device layer includes: a fourth dielectric layer located on the surface of the second substrate, a second interconnect structure located in the fourth dielectric layer, and a second device located in the fourth dielectric layer, the second device is electrically connected to the second interconnect structure, and the second interconnect structure is electrically connected to the first interconnect structure.

[0021] Optionally, it also includes: a second dielectric layer located between the first substrate and the first device layer; the second dielectric layer includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

[0022] Optionally, it also includes: a third dielectric layer located on the side wall surface of the first reflective layer, the third dielectric layer is located between the side wall of the photosensitive area and the side wall of the first reflective layer; the third dielectric layer includes one or both of an oxide layer and a high dielectric constant layer overlapping.

[0023] Optionally, the material of the first reflective layer includes aluminum; the material of the second reflective layer includes aluminum.

[0024] Optionally, it also includes: a lens structure located on the surface of the second face.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the semiconductor structure provided by the technical solution of the present invention, the first reflective layer is located in the isolation area, the second reflective layer is located on each photosensitive area, the first reflective layer isolates adjacent photosensitive areas, and the second reflective layer is connected to the first reflective layer. When light is incident on the photosensitive area from the second surface, the first reflective layer and the second reflective layer change the propagation path of the light, so that the light incident on the photosensitive area is reflected in the photosensitive area, reducing the loss of photons, increasing the light signal collected by the photosensitive area, and improving the photon detection efficiency.

[0027] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first reflective layer is formed in the isolation area, a second reflective layer is formed on each photosensitive area, the first reflective layer isolates adjacent photosensitive areas, and the second reflective layer is connected to the first reflective layer. When light is incident on the photosensitive area from the second surface, the first reflective layer and the second reflective layer change the propagation path of the light, so that the light incident on the photosensitive area is reflected in the photosensitive area, reducing the loss of photons, increasing the light signal collected by the photosensitive area, and improving the photon detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0029] Figures 2 to 10 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As mentioned in the background technology, the photon detection efficiency of the photosensitive area of ​​the current photoelectric sensor needs to be further improved.

[0031] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0032] Please refer to Figure 1 The semiconductor structure includes: a first substrate 101 having a first surface and a second surface opposite to each other, the first substrate including a plurality of photosensitive areas 102; a plurality of first openings (not shown) located between adjacent photosensitive areas 102; a reflective layer 103 located in the first openings (not shown) and filling the first openings (not shown); and a second substrate 104 bonded to the first substrate 101, the second substrate 104 having a third surface and a fourth surface opposite to each other, the fourth surface being bonded to the first surface.

[0033] The material of the reflective layer 103 includes metal.

[0034] The semiconductor structure further includes: a first device layer 105 located on the surface of the first substrate 101, the first device layer 105 includes a first dielectric layer, a first interconnect layer located in the first dielectric layer, and a first device located in the first dielectric layer; the first interconnect layer is electrically connected to the first device.

[0035] The reflective layer 103 is located between adjacent photosensitive areas 102, optically isolating the adjacent photosensitive areas 102 to prevent optical crosstalk between adjacent photosensitive areas 102. When light enters the photosensitive area 102 and the light enters the reflective layer 103, light reflection occurs, causing the reflected light to fall into the photosensitive area 102, increasing the light signal collected by the photosensitive area 102 and reducing the loss of photons. However, the reflective layer 103 is only located between adjacent photosensitive areas 102, and there is no reflective layer 103 between the first substrate 101 and the first device layer 105, so the incident light will be reflected onto the first device layer 105, causing the loss of photons.

[0036] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein a first reflective layer is formed in an isolation region, a second reflective layer is formed on each photosensitive region, the first reflective layer isolates adjacent photosensitive regions, and the second reflective layer is connected to the first reflective layer. When light is incident on the photosensitive region from the second surface, the first reflective layer and the second reflective layer change the propagation path of the light, so that the light incident on the photosensitive region is reflected in the photosensitive region, reducing the loss of photons, increasing the light signal collected by the photosensitive region, and improving the photon detection efficiency.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 10 It is a schematic cross-sectional structural diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 2 , providing a first substrate 200, the first substrate 200 having a first surface and a second surface opposite to each other, the first substrate 200 including a plurality of photosensitive regions I and isolation regions II located between adjacent photosensitive regions I.

[0040] The material of the first substrate 200 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0041] Specifically, in this embodiment, the photosensitive area I is used to collect light signals.

[0042] The photosensitive region I has a photoelectric doping region 201, and the first surface exposes the photoelectric doping region 201; the doping ions of the photoelectric doping region 201 include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

[0043] Specifically, in this embodiment, the method for forming the photoelectric doping region 201 includes: performing ion implantation on the photosensitive region I; the process parameters of the ion implantation include: the implanted ions are P-type conductive ions or N-type conductive ions; the dose range of the implanted ions is 3E11 ions / cm 2 ~5E15 ions / cm2 ; The energy range of implanted ions is 5KeV~2200KeV.

[0044] Specifically, in this embodiment, the isolation region II provides a structural basis for the subsequent formation of the first reflective layer 203 .

[0045] Please refer to Figure 3 , a second dielectric layer 202 is formed on the surface of the first substrate 200 .

[0046] Specifically, in this embodiment, the second dielectric layer 202 includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

[0047] The function of the second dielectric layer 202 is: the silicon oxide layer serves as a buffer layer between the silicon nitride layer and the substrate, and the silicon nitride layer serves as an etching stop layer for subsequent etching.

[0048] Specifically, in this embodiment, the thickness of the silicon oxide layer is in the range of The thickness of the silicon nitride layer ranges from

[0049] After forming the second dielectric layer 202, a first reflective layer 203 is formed in each isolation region II. For details, please refer to Figures 4 to 6 .

[0050] Please refer to Figure 4 , a first mask layer (not shown) is formed on the surface of the first substrate 200, and the first mask layer (not shown) exposes a portion of the surface of the first substrate 200; using the first mask layer (not shown) as a mask, the first substrate 200 is etched to form a first opening 204 located between adjacent photosensitive regions I.

[0051] Etching methods include: dry etching.

[0052] The depth of the first opening 204 ranges from 3 μm to 10 μm.

[0053] The width of the first opening 204 parallel to the surface of the first substrate 200 ranges from 400 nm to 600 nm.

[0054] Please refer to Figure 5 After the first opening 204 is formed, a third dielectric layer 205 is formed on the surface of the first opening 204 .

[0055] Specifically, in this embodiment, the third dielectric layer 205 includes an oxide layer, a high dielectric constant layer, or a combination of the two.

[0056] The third dielectric layer 205 has the following functions: electrical isolation, reducing optical crosstalk, and protecting the photoelectric doping region 201 .

[0057] The thickness range of the third dielectric layer 205 is:

[0058] Please refer to Figure 6 , forming a filling-up first opening 204 in each first opening 204 (such as Figure 5 The first reflective layer 203 is shown in FIG.

[0059] The material of the first reflective layer 203 includes aluminum or tungsten.

[0060] Specifically, in this embodiment, the material of the first reflective layer 203 is aluminum.

[0061] The thickness range of the first reflective layer 203 is:

[0062] The width of the first reflective layer 203 parallel to the surface of the first substrate 200 is:

[0063] The function of the first reflective layer 203 is that when light is incident on the photosensitive area I, the first reflective layer 203 changes the propagation path of the light so that the light incident on the photosensitive area I is reflected in the photosensitive area I, thereby reducing the loss of photons, increasing the light signal collected by the photosensitive area I, and improving the photon detection efficiency.

[0064] Please refer to Figure 7 A first device layer 206 is formed on the surface of the first surface, wherein the first device layer 206 has a second reflective layer 207 located on each photosensitive area I, and the second reflective layer 207 is connected to the first reflective layer 203 .

[0065] The second reflective layer 207 is formed on each photosensitive area I, the first reflective layer 203 is formed in the isolation area II, the first reflective layer 203 isolates the adjacent photosensitive areas I, and the second reflective layer 207 is connected to the first reflective layer 203. When light is incident on the photosensitive area I from the second surface, the first reflective layer 203 and the second reflective layer 207 change the propagation path of the light, so that the light incident on the photosensitive area I is reflected in the photosensitive area I, reducing the loss of photons, increasing the light signal collected by the photosensitive area I, and improving the photon detection efficiency.

[0066] Specifically, in this embodiment, the thickness range of the second reflective layer 207 is:

[0067] The material of the second reflective layer 207 includes aluminum or tungsten. Specifically, in this embodiment, the material of the second reflective layer 207 is aluminum.

[0068] Specifically, in this embodiment, the first device layer 206 further includes: a first dielectric layer 208 , a first interconnect structure 209 located in the first dielectric layer 208 , and a first device (not shown) located in the first dielectric layer 208 , and the first device (not shown) is electrically connected to the first interconnect structure 209 .

[0069] Specifically, in this embodiment, the material of the first dielectric layer 208 includes silicon oxide, silicon nitride or nitrogen-doped silicon.

[0070] Specifically, in this embodiment, the material of the first interconnect structure 209 includes tungsten.

[0071] Specifically, in this embodiment, the first interconnect structure 209 is also electrically connected to the photosensitive area 201 ; and the second reflective layer 207 is electrically insulated from the first interconnect structure 209 .

[0072] Specifically, in this embodiment, the first device (not shown) includes: a filter and an electrode.

[0073] Please refer to Figure 8 , providing a second substrate 210, the second substrate 210 having a third surface and a fourth surface opposite to each other; forming a second device layer 211 on the fourth surface of the second substrate 210; and bonding the fourth surface of the second substrate 210 to the first surface of the first substrate 200.

[0074] The material of the second substrate 210 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0075] In this embodiment, the second device layer 211 includes: a fourth dielectric layer 212 , a second interconnect structure 213 located in the fourth dielectric layer 212 , and a second device (not shown) located in the fourth dielectric layer 212 . The second device (not shown) is electrically connected to the second interconnect structure 213 .

[0076] Specifically, in this embodiment, the material of the fourth dielectric layer 212 includes silicon oxide, silicon nitride or nitrogen-doped silicon.

[0077] Specifically, in this embodiment, the material of the second interconnect structure 213 includes tungsten.

[0078] Specifically, in this embodiment, the second device (not shown) includes: a filter and an electrode.

[0079] Specifically, in this embodiment, after the second substrate 210 is bonded to the first substrate 200 , the second interconnect structure 213 is electrically connected to the first interconnect structure 209 .

[0080] Please refer to Fig. 9After the first substrate 200 and the second substrate 210 are bonded, the method further includes: performing a planarization process on the second surface of the first substrate 200 until the bottom surface of the first reflective layer 203 is exposed.

[0081] The planarization method includes mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization method is chemical mechanical polishing. Different from the traditional pure mechanical or pure chemical polishing method, the chemical mechanical polishing method avoids the surface damage caused by pure mechanical polishing and the shortcomings of slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high planarization polishing of various materials at the nano level.

[0082] Please refer to Fig.10 Specifically, in this embodiment, the first substrate 200 also includes a lead-out region III.

[0083] The function of the lead-out region III is to generate photogenerated charges under the action of light.

[0084] After the planarization process, a lens structure (not shown) is formed on the second surface.

[0085] The lens structure (not shown) penetrates the lead-out region III; the lens structure (not shown) is electrically connected to the first device layer 206 .

[0086] The function of the lens structure is to focus the incident light.

[0087] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.10 , including: a first substrate 200, having a first surface and a second surface opposite to each other, the first substrate 200 including a plurality of photosensitive regions I and isolation regions II located between adjacent photosensitive regions I; a first reflective layer 203 located in each isolation region II; a first device layer 206 located on the surface of the first surface, the first device layer 206 having a second reflective layer 207 located on each photosensitive region I, and the second reflective layer 207 is connected to the first reflective layer 203.

[0088] The semiconductor structure includes: a first substrate 200 having a first surface and a second surface opposite to each other. The first substrate 200 includes a plurality of photosensitive regions I and isolation regions II located between adjacent photosensitive regions I.

[0089] The material of the first substrate 200 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0090] The photosensitive region I has a photoelectric doping region 201, and the first surface exposes the photoelectric doping region 201; the doping ions of the photoelectric doping region 201 include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

[0091] Specifically, in this embodiment, the first substrate 200 further includes a lead-out region III.

[0092] The semiconductor structure includes: a second dielectric layer 202 located on the surface of a first substrate 200 .

[0093] Specifically, in this embodiment, the second dielectric layer 202 includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

[0094] The thickness of the silicon oxide layer ranges from The thickness of the silicon nitride layer ranges from

[0095] The semiconductor structure includes: a first reflective layer 203 located in each isolation region II.

[0096] The material of the first reflective layer 203 includes aluminum or tungsten.

[0097] The thickness range of the first reflective layer 203 is:

[0098] The width of the first reflective layer 203 parallel to the surface of the first substrate 200 is:

[0099] The semiconductor structure includes: a third dielectric layer 205 located on the side wall surface of the first reflective layer 203 , and the third dielectric layer 205 is located between the side wall of the photosensitive region I and the side wall of the first reflective layer 203 .

[0100] The third dielectric layer 205 includes an oxide layer, a high dielectric constant layer, or a combination of the two.

[0101] The thickness range of the third dielectric layer 205 is:

[0102] The semiconductor structure includes: a first device layer 206 located on the surface of the first side, a second reflective layer 207 located on each photosensitive area I in the first device layer 206 , and the second reflective layer 207 is connected to the first reflective layer 203 .

[0103] Specifically, in this embodiment, the thickness range of the second reflective layer 207 is:

[0104] The material of the second reflective layer 207 includes aluminum or tungsten. Specifically, in this embodiment, the material of the second reflective layer 207 is aluminum.

[0105] Specifically, in this embodiment, the first device layer 206 further includes: a first dielectric layer 208 , a first interconnect structure 209 located in the first dielectric layer 208 , and a first device (not shown) located in the first dielectric layer 208 , and the first device (not shown) is electrically connected to the first interconnect structure 209 .

[0106] Specifically, in this embodiment, the material of the first dielectric layer 208 includes silicon oxide, silicon nitride or nitrogen-doped silicon.

[0107] Specifically, in this embodiment, the material of the first interconnect structure 209 includes tungsten.

[0108] Specifically, in this embodiment, the first interconnect structure 209 is also electrically connected to the photosensitive area 201 ; and the second reflective layer 207 is electrically insulated from the first interconnect structure 209 .

[0109] Specifically, in this embodiment, the first device (not shown) includes: a filter and an electrode.

[0110] The semiconductor structure includes: a second substrate 210 bonded to the first substrate 200, the second substrate 210 has a third surface and a fourth surface opposite to each other, and the fourth surface is bonded toward the first surface.

[0111] The material of the second substrate 210 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0112] The semiconductor structure includes: a second device layer 211 located on the surface of the fourth surface; the second device layer 211 includes: a fourth dielectric layer 212 located on the surface of the second substrate 210, a second interconnect structure 213 located in the fourth dielectric layer 212, and a second device (not shown) located in the fourth dielectric layer 212, the second device (not shown) is electrically connected to the second interconnect structure 213, and the second interconnect structure 213 is electrically connected to the first interconnect structure 209.

[0113] Specifically, in this embodiment, the material of the fourth dielectric layer 212 includes silicon oxide, silicon nitride or nitrogen-doped silicon.

[0114] Specifically, in this embodiment, the material of the second interconnect structure 213 includes tungsten.

[0115] Specifically, in this embodiment, the second device (not shown) includes: a filter and an electrode.

[0116] The semiconductor structure includes a lens structure (not shown) located on the surface of the second surface.

[0117] The lens structure (not shown) penetrates the lead-out region III; the lens structure (not shown) is electrically connected to the first device layer 206 .

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first substrate having a first surface and a second surface opposite to each other, wherein the first substrate comprises a plurality of photosensitive regions and an isolation region between adjacent photosensitive regions; a first reflective layer located in each of the isolation regions; A first device layer is located on the surface of the first face, wherein the first device layer has a second reflective layer located on each photosensitive area, and the second reflective layer is connected to the first reflective layer.

2. The semiconductor structure according to claim 1, wherein: The photosensitive region has a photoelectric doping region, and the first surface exposes the photoelectric doping region; the doping ions of the photoelectric doping region include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

3. The semiconductor structure according to claim 1, wherein: The first device layer further includes: a first dielectric layer, a first interconnection structure located in the first dielectric layer, and a first device located in the first dielectric layer, wherein the first device is electrically connected to the first interconnection structure.

4. The semiconductor structure according to claim 3, characterized in that The first interconnect structure is also electrically connected to the photosensitive area, and the second reflective layer is electrically insulated from the first interconnect structure.

5. The semiconductor structure according to claim 4, characterized in that Also includes: A second substrate bonded to the first substrate, the second substrate having a third surface and a fourth surface opposite to each other, the fourth surface being bonded toward the first surface.

6. The semiconductor structure according to claim 5, characterized in that Also includes: A second device layer located on the surface of the fourth surface; The second device layer includes: a fourth dielectric layer located on the surface of the second substrate, a second interconnect structure located in the fourth dielectric layer, and a second device located in the fourth dielectric layer, the second device is electrically connected to the second interconnect structure, and the second interconnect structure is electrically connected to the first interconnect structure.

7. The semiconductor structure according to claim 1, wherein: Also includes: a second dielectric layer located between the first substrate and the first device layer; The second dielectric layer includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

8. The semiconductor structure according to claim 1, wherein: Also includes: A third dielectric layer is located on the side wall surface of the first reflective layer, and the third dielectric layer is located between the side wall of the photosensitive area and the side wall of the first reflective layer; the third dielectric layer includes one of an oxide layer and a high dielectric constant layer, or both of them overlap.

9. The semiconductor structure according to claim 1, wherein: The material of the first reflective layer includes aluminum; the material of the second reflective layer includes aluminum.

10. The semiconductor structure according to claim 1, wherein: Also includes: A lens structure is located on the surface of the second face.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a first substrate, wherein the first substrate has a first surface and a second surface opposite to each other, and the first substrate includes a plurality of photosensitive regions and an isolation region between adjacent photosensitive regions; forming a first reflective layer in each of the isolation regions; A first device layer is formed on the surface of the first face, wherein the first device layer includes a second reflective layer located on each photosensitive region, and the second reflective layer is connected to the first reflective layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The photosensitive region has a photoelectric doping region, and the first surface exposes the photoelectric doping region; The doping ions of the photoelectric doping region include: arsenic, boron, carbon, boron fluoride, fluorine, phosphorus, nitrogen, aluminum, germanium or antimony.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the photoelectric doping region includes: performing ion implantation on the photosensitive region; the process parameters of the ion implantation include: the implanted ions are P-type conductive ions or N-type conductive ions; the dose range of the implanted ions is 3E11 ions / cm 2 ~5E15 ions / cm 2 ; The energy range of implanted ions is 5KeV~2200KeV.

14. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first reflective layer comprises: forming a first opening in each of the isolation regions; and forming a first reflective layer in each of the first openings to fill the first openings.

15. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the first opening includes: forming a first mask layer on the surface of the first substrate, wherein the first mask layer exposes a portion of the surface of the first substrate; and etching the first substrate using the first mask layer as a mask to form a first opening located between adjacent photosensitive areas.

16. The method for forming a semiconductor structure according to claim 15, wherein: Before forming the first opening, the method further includes: forming a second dielectric layer on the surface of the first substrate; the second dielectric layer includes a silicon oxide layer and a silicon nitride layer located on the surface of the silicon oxide layer.

17. The method for forming a semiconductor structure according to claim 14, wherein: After forming the first opening and before forming the first reflective layer, the method further includes: forming a third dielectric layer on a surface of the first opening, wherein the third dielectric layer includes one of an oxide layer and a high dielectric constant layer or both of them overlap.

18. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: Providing a second substrate, wherein the second substrate has a third surface and a fourth surface opposite to each other; forming a second device layer on the second substrate, the second device layer comprising: a fourth dielectric layer, a second interconnect structure located in the fourth dielectric layer, and a second device located in the fourth dielectric layer, the second device being electrically connected to the second interconnect structure; The fourth surface of the second substrate is bonded toward the first surface of the first substrate.

19. The method for forming a semiconductor structure according to claim 18, wherein: The first device layer also includes: a first dielectric layer, a first interconnect structure located in the first dielectric layer, and a first device located in the first dielectric layer, the first device is electrically connected to the first interconnect structure; after the second substrate is bonded to the first substrate, the second interconnect structure is electrically connected to the first interconnect structure.

20. The method for forming a semiconductor structure according to claim 19, wherein: Also includes: After the first substrate and the second substrate are bonded, the method further includes: performing a planarization process on the second surface of the first substrate until the bottom surface of the first reflective layer is exposed.

Images