Preparation method of solar cell and solar cell

Abstract

The invention provides a preparation method of a solar cell and the solar cell, and the method comprises the steps: providing a solar cell precursor which comprises a conductive layer and an insulating layer located on the conductive layer; forming a conductive paste covering a local area of the insulating layer, wherein the conductive paste has a triangular cross section; the conductive slurry is sintered to form a seed layer penetrating through the insulating layer to be in contact with the conductive layer, and the seed layer has a triangular cross section; and forming a plating layer covering the seed layer exposed outside the insulating layer using a plating process to form a gate line including the seed layer and the plating layer, the gate line having a triangular cross section. The electroplated layer has the triangular cross section, so that the light irradiated on the electroplated layer can be reflected to the active region of the solar cell.

Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] The grid line is one of the important components of solar cells. The methods for preparing the grid line include screen printing, electroplating, etc. The current screen printing, electroplating and other processes cannot prepare grid lines with triangular cross sections, or even if they can be prepared, the preparation process is complicated. How to prepare grid lines with triangular cross sections is one of the research hotspots in this field. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a method for preparing a solar cell and a solar cell. The method for preparing a solar cell and the solar cell can prepare a grid line with a triangular cross section, and the preparation process is simple.

[0004] To solve the above technical problems, the present application provides a method for preparing a solar cell, comprising: providing a solar cell precursor, the solar cell precursor comprising a conductive layer and an insulating layer located on the conductive layer; forming a conductive paste covering a local area of ​​the insulating layer, the conductive paste having a triangular cross-section; sintering the conductive paste to form a seed layer passing through the insulating layer and contacting the conductive layer, the seed layer having a triangular cross-section; and using an electroplating process to form an electroplating layer covering the seed layer exposed outside the insulating layer to form a grid line comprising the seed layer and the electroplating layer, the grid line having a triangular cross-section.

[0005] In one embodiment of the present application, the angle between the two side surfaces of the seed layer is equal to or less than 120°.

[0006] In one embodiment of the present application, the angle between the two side surfaces of the electroplating layer is equal to or less than 120°.

[0007] In one embodiment of the present application, the electroplating layer includes an inner layer and an outer layer, the inner layer is located between the seed layer and the outer layer, and the reflectivity of the outer layer is greater than the reflectivity of the inner layer.

[0008] In one embodiment of the present application, the conductive layer includes N-type single crystal silicon or P-type single crystal silicon.

[0009] In an embodiment of the present application, the solar cell has a tunneling oxide layer, and the tunneling oxide layer is located between the conductive layer and the silicon substrate, wherein the conductive layer includes N-type polysilicon or P-type polysilicon.

[0010] In an embodiment of the present application, the conductive layer and the tunnel oxide layer are disposed on a local area of ​​the silicon substrate, and a width of the conductive layer is equal to or greater than a width of the seed layer.

[0011] In one embodiment of the present application, the width of the electroplating layer is equal to or greater than the width of the conductive layer.

[0012] In an embodiment of the present application, the insulating layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0013] On the other hand, the present application also proposes a solar cell, comprising: a conductive layer; an insulating layer located on the conductive layer; and a grid line, comprising a seed layer and a plating layer, the seed layer passes through the insulating layer and contacts the conductive layer, the seed layer has a triangular cross-section, the electroplating layer covers the seed layer exposed outside the insulating layer, and the grid line has a triangular cross-section.

[0014] In one embodiment of the present application, the angle between the two side surfaces of the seed layer is equal to or less than 120°.

[0015] In one embodiment of the present application, the angle between the two side surfaces of the electroplating layer is equal to or less than 120°.

[0016] In one embodiment of the present application, the electroplating layer includes an inner layer and an outer layer, the inner layer is located between the seed layer and the outer layer, and the reflectivity of the outer layer is greater than the reflectivity of the inner layer.

[0017] In one embodiment of the present application, the conductive layer includes N-type single crystal silicon or P-type single crystal silicon.

[0018] In an embodiment of the present application, the solar cell further includes a tunneling oxide layer, wherein the tunneling oxide layer is located between the conductive layer and the silicon substrate, wherein the conductive layer includes N-type polysilicon or P-type polysilicon.

[0019] In an embodiment of the present application, the conductive layer and the tunnel oxide layer are disposed on a local area of ​​the silicon substrate, and a width of the conductive layer is equal to or greater than a width of the seed layer.

[0020] In one embodiment of the present application, the width of the electroplating layer is equal to or greater than the width of the conductive layer.

[0021] In an embodiment of the present application, the insulating layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0022] Compared with the prior art, this application has the following advantages:

[0023] (1) The electroplating layer has a triangular cross section, which can reflect the light irradiated on the electroplating layer to the active area of ​​the solar cell, thereby increasing the total amount of light irradiated to the active area of ​​the solar cell.

[0024] (2) The process of forming the gate line does not require forming a seed layer covering the entire insulating layer. Instead, the seed layer is formed by directly forming a slurry on a local area of ​​the insulating layer and sintering it, which eliminates the process step of removing excess seed layer.

[0025] (3) Before electroplating the electroplating layer, there is no need to cover the insulating layer with insulating material, which simplifies the process steps of forming the gate line, improves production efficiency and reduces costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0027] Figure 1 is a schematic flow chart of a method for preparing a solar cell in one embodiment of the present application;

[0028] Figures 2 to 5 is a schematic cross-sectional view of a solar cell in different steps of a method for preparing a solar cell in an embodiment of the present application;

[0029] Figure 6 is a schematic cross-sectional view of a seed layer in one embodiment of the present application;

[0030] Figure 7 is a schematic cross-sectional view of a gate line in an embodiment of the present application;

[0031] Figure 8 is a schematic cross-sectional view of a gate line in another embodiment of the present application;

[0032] Fig. 9 is a schematic cross-sectional view of a solar cell in one embodiment of the present application;

[0033] Fig.10 is a schematic cross-sectional view of a solar cell in another embodiment of the present application.

[0034] Reference numerals

[0035] Solar cell precursor 210 , silicon substrate 211 , conductive layer 212 , insulating layer 213 , tunneling oxide layer 214 , passivation layer 216 , conductive paste 220 , seed layer 230 , electroplating layer 240 , inner layer 241 , and outer layer 242 . DETAILED DESCRIPTION

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0037] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0038] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0039] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0040] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0041] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0042] Flowcharts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0043] Next, the preparation method of the solar cell and the solar cell of the present application are described through examples.

[0044] refer to Figure 1 The schematic flow chart of a method for preparing a solar cell in an embodiment is shown. The method in this embodiment includes the following steps S110 to S140.

[0045] Step S110: providing a solar cell precursor, wherein the solar cell precursor comprises a conductive layer and an insulating layer located on the conductive layer;

[0046] Step S120: forming a conductive paste covering a local area of ​​the insulating layer, wherein the conductive paste has a triangular cross section;

[0047] Step S130: sintering the conductive paste to form a seed layer that passes through the insulating layer and contacts the conductive layer, wherein the seed layer has a triangular cross section;

[0048] Step S140: using an electroplating process to form an electroplating layer covering the seed layer exposed outside the insulating layer, so as to form a gate line including the seed layer and the electroplating layer, wherein the gate line has a triangular cross section.

[0049] Next, steps S110 to S140 are described in detail.

[0050] refer to Figure 2 As shown, in step S110, a solar cell precursor 210 is provided, and the solar cell precursor 210 includes a silicon substrate 211, a conductive layer 212 and an insulating layer 213, and the conductive layer 212 and the insulating layer 213 are stacked on the silicon substrate 211. The silicon substrate 211 can be N-type single crystal silicon or P-type single crystal silicon. The conductive layer 212 can be N-type silicon or P-type silicon. Specifically, the conductive layer 212 can be N-type single crystal silicon, P-type single crystal silicon, N-type polycrystalline silicon or P-type polycrystalline silicon. The insulating layer 213 can be a passivation layer, an anti-reflection layer or a passivation anti-reflection layer, and the insulating layer 213 includes one or more layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0051] refer to Figure 2 and Figure 3 As shown, in step S120, a conductive paste 220 is formed, and the conductive paste 220 covers a local area of ​​the insulating layer 213, and the conductive paste 220 has a triangular cross-section. Preferably, the conductive paste 220 covering the local area of ​​the insulating layer 213 is directly formed, rather than first forming a conductive paste covering the entire surface of the insulating layer 213 and then selectively removing unnecessary conductive paste. The conductive paste 220 can be formed on the insulating layer 213 by printing, laser transfer, and other methods.

[0052] The conductive paste 220 contains metal particles, such as copper particles, silver particles, etc. It should be noted that due to the process, the characteristics of the conductive paste itself, etc., the cross section of the conductive paste 220 may not be a strict triangle, for example, the top of the conductive paste 220 has a certain curvature, the side of the conductive paste 220 is not a flat surface, etc., and the above situations are all within the protection scope of this application.

[0053] refer to Figure 3 and Figure 4As shown, in step S130, the conductive paste 220 is sintered. After the sintering process, the conductive paste 220 burns through the insulating layer 213 and is transformed into the seed layer 230, and the seed layer 230 is in contact with the conductive layer 212. During the sintering process, the shape of the cross section of the conductive paste 230 remains basically unchanged, so the seed layer 230 also has a triangular cross section. It should be noted that due to process, material and other reasons, the cross section of the seed layer 230 may not be a strict triangle. For example, the top of the seed layer 230 has a certain curvature, the side of the seed layer 230 is not a flat surface, etc., and the above situations are all within the scope of protection of this application.

[0054] refer to Figure 6 Schematic diagram of a triangular cross section of the seed layer 230 shown. In one embodiment, the angle α between the two sides of the seed layer 230 is equal to or less than 120°, for example, the angle α is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110° or 120°, preferably, the angle α is equal to or less than 60°. The restriction of the angle α is conducive to limiting the size of the angle β of the electroplating layer formed in the subsequent steps, which will be described in detail later.

[0055] refer to Figure 4 and Figure 5 As shown, in step S140, the electroplating layer 240 is electroplated on the seed layer 230. Specifically, the lower portion of the seed layer 230 is located in the insulating layer 213, the upper portion of the seed layer 230 is not covered by the insulating layer 213 and is exposed outside the insulating layer 213, and the electroplating layer 240 covers the seed layer exposed outside the insulating layer 213.

[0056] Figure 5 The cross section of the solar cell prepared by step S110 to step S140 is schematically shown, and the grid line of the solar cell includes a seed layer 230 and an electroplating layer 240. Since the electroplating layer 240 has a cross section with a triangular outer contour, the grid line has a triangular cross section. It should be noted that due to electroplating process, materials, etc., the outer contour of the cross section of the electroplating layer 240 may not be a strict triangle. For example, the top of the electroplating layer 240 has a certain curvature, the side of the electroplating layer 240 is not a flat surface, etc., and the above situations are all within the protection scope of this application.

[0057] The process of forming the gate line in the above embodiment does not need to form a seed layer covering the entire insulating layer, but forms the seed layer by directly forming a slurry on a local area of ​​the insulating layer and sintering it, which saves the process step of removing the excess seed layer. In addition, the present application does not need to cover the insulating layer with an insulating material before electroplating the electroplating layer, which further simplifies the process steps.

[0058] refer to Figure 7 The schematic cross-sectional view of the gate line in one embodiment of the present application (also a schematic cross-sectional view of the seed layer 230 and the electroplating layer 240) is shown in FIG. Figure 7 In the embodiment, the angle β between the two sides of the electroplating layer 240 (also the two sides of the grid line) is equal to or less than 120°, for example, the angle β is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110° or 120°, preferably, the angle β is equal to or less than 60°. The above setting of the size of the angle β is conducive to reflecting the light irradiated on the electroplating layer 240 to the active area of ​​the solar cell, thereby increasing the total amount of light irradiated to the active area.

[0059] refer to Figure 8 The schematic cross-sectional view of the grid line in another embodiment shown, in order to improve the reflectivity of the electroplating layer 240 to the incident light, the electroplating layer 240 includes an inner layer 241 and an outer layer 242, the inner layer 241 is located between the seed layer 230 and the outer layer 242, and the reflectivity of the outer layer 242 is greater than the reflectivity of the inner layer 241. The reflectivity of the outer layer 242 can be made greater than the reflectivity of the inner layer 241 by limiting the material of the outer layer 242, for example, the material of the outer layer 242 is metallic silver, and the material of the inner layer 241 is metallic copper.

[0060] The above embodiment obtains a grid line with a triangular cross section by limiting the seed layer 230 to have a triangular cross section. To expand, when the electroplating layer 240 is electroplated on the seed layer 230, the metal is gradually deposited on the seed layer. Since the seed layer 230 has a triangular cross section, the outer contour of the cross section of the electroplating layer 240 finally formed is also a triangle (that is, the cross section of the grid line is a triangle). It can be seen from the above description that the size of the angle β can be controlled by controlling the size of the angle α, and the sizes between the two are positively correlated. In one embodiment, the angle β is substantially equal to the angle α, or slightly larger than the angle α.

[0061] refer to Fig. 9 A schematic cross-sectional view of a solar cell in an embodiment shown, wherein the solar cell in the embodiment has a tunneling oxide layer 214, the tunneling oxide layer 214 is located between the conductive layer 212 and the silicon substrate 211, and the conductive layer 212 includes N-type polysilicon or P-type polysilicon. The tunneling oxide layer 214 may include silicon oxide or aluminum oxide. The bottom end of the seed layer 230 in the gate line passes through the insulating layer 213 and contacts the conductive layer 212, and the electroplating layer 240 in the gate line covers the seed layer exposed outside the insulating layer 213 and is located on the insulating layer 213.

[0062] refer to Fig.10 A schematic cross-sectional view of a solar cell in another embodiment is shown, Fig.10 and Fig. 9 One difference is that Fig.10 The conductive layer 212 and the tunnel oxide layer 214 are disposed on a local region of the silicon substrate 211 . Fig.10 and Fig. 9 Another difference is that Fig.10 The solar cell precursor further includes a passivation layer 216, which is disposed on the conductive layer 212 and the silicon substrate 211 without the tunneling oxide layer 214, and the passivation layer 216 may include silicon oxide and / or aluminum oxide.

[0063] Continue to refer Fig.10 As shown, in one embodiment, the width W1 of the conductive layer 212 is equal to or greater than the width W2 of the seed layer 230. This helps to minimize the charge recombination loss caused by the metal-semiconductor contact.

[0064] In another embodiment, the width W3 of the electroplating layer 240 is equal to or greater than the width W1 of the conductive layer 212. The polysilicon in the conductive layer 212 has a high optical absorption coefficient, and the light absorbed by the conductive layer 212 does not contribute to power generation, that is, parasitic absorption loss. The width W3 being equal to or greater than the width W1 can prevent the incident light from being parasitically absorbed by the conductive layer 212, but being reflected by the electroplating layer 240 to the active area.

[0065] On the other hand, the present application also proposes a solar cell, Figure 5 As shown, the solar cell of this embodiment includes a silicon substrate 211, a conductive layer 212, an insulating layer 213 and gate lines.

[0066] In detail, the conductive layer 212 and the insulating layer 213 are stacked on the silicon substrate 211, and the gate line includes a seed layer 230 and an electroplating layer 240. The bottom end of the seed layer 230 passes through the insulating layer 213 and contacts the conductive layer 212. The seed layer 230 has a triangular cross-section, and the electroplating layer 240 covers the seed layer exposed outside the insulating layer 213. The gate line has a triangular cross-section.

[0067] refer to Figure 5 As shown, in one embodiment, the conductive layer 212 includes N-type single crystal silicon or P-type single crystal silicon. The method of forming N-type single crystal silicon (P-type single crystal silicon) can be to dope N-type dopant (P-type dopant) into the silicon substrate to transform a certain thickness of the silicon substrate into the conductive layer 212.

[0068] refer to Fig. 9 As shown, in another embodiment, the solar cell further includes a tunneling oxide layer 214, which is located between the conductive layer 212 and the silicon substrate 211, and the conductive layer 212 includes N-type polysilicon or P-type polysilicon. The tunneling oxide layer 214 can be silicon oxide or aluminum oxide.

[0069] refer to Fig.10As shown, in yet another embodiment, the conductive layer 212 and the tunnel oxide layer 214 are disposed on a local area of ​​the silicon substrate 211, and the width W1 of the conductive layer 212 is equal to or greater than the width W2 of the seed layer 230. Fig.10 In the embodiment, the solar cell further includes a passivation layer 216, which may include silicon oxide or aluminum oxide.

[0070] The width W3 of the electroplating layer 240 may be equal to or greater than the width W1 of the conductive layer 212 .

[0071] In one embodiment, the insulating layer 213 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0072] refer to Figure 6 As shown, in one embodiment, the angle α between the two side surfaces of the seed layer 230 is equal to or less than 120°. For example, the angle α is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110° or 120°. Preferably, the angle α is equal to or less than 60°.

[0073] refer to Figure 7 As shown, in one embodiment, the angle β between the two side surfaces of the electroplating layer 240 is equal to or less than 120°, for example, the angle β is 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110° or 120°, preferably, the angle α is equal to or less than 60°.

[0074] refer to Figure 8 As shown, in one embodiment, the electroplating layer 240 includes an inner layer 241 and an outer layer 242 , the inner layer 241 is located between the seed layer 230 and the outer layer 242 , and the reflectivity of the outer layer 242 is greater than the reflectivity of the inner layer 241 .

[0075] For other descriptions about the solar cell of the present application, please refer to the relevant parts of the previous text, which will not be elaborated here.

[0076] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0077] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0078] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0079] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0080] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a solar cell precursor, the solar cell precursor comprising a conductive layer and an insulating layer located on the conductive layer; forming a conductive paste covering a local area of ​​the insulating layer, wherein the conductive paste has a triangular cross section; sintering the conductive paste to form a seed layer that passes through the insulating layer and contacts the conductive layer, the seed layer having a triangular cross section; and An electroplating process is used to form an electroplating layer covering the seed layer exposed outside the insulating layer to form a gate line including the seed layer and the electroplating layer, wherein the gate line has a triangular cross section.

2. The method for preparing a solar cell according to claim 1, characterized in that: The angle between the two side surfaces of the seed layer is equal to or less than 120°.

3. The method for preparing a solar cell according to claim 1, wherein: The angle between the two side surfaces of the electroplating layer is equal to or less than 120°.

4. The method for preparing a solar cell according to claim 1, wherein: The electroplating layer includes an inner layer and an outer layer, the inner layer is located between the seed layer and the outer layer, and the reflectivity of the outer layer is greater than the reflectivity of the inner layer.

5. The method for preparing a solar cell according to claim 1, wherein: The conductive layer includes N-type single crystal silicon or P-type single crystal silicon.

6. The method for preparing a solar cell according to claim 1, wherein: The solar cell has a tunneling oxide layer, and the tunneling oxide layer is located between the conductive layer and the silicon substrate, wherein the conductive layer includes N-type polysilicon or P-type polysilicon.

7. The method for preparing a solar cell according to claim 6, characterized in that: The conductive layer and the tunnel oxide layer are disposed on a local area of ​​the silicon substrate, and a width of the conductive layer is equal to or greater than a width of the seed layer.

8. The method for preparing a solar cell according to claim 7, characterized in that: The width of the electroplating layer is equal to or greater than the width of the conductive layer.

9. The method for preparing a solar cell according to claim 1, wherein: The insulating layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

10. A solar cell, characterized in that: include: Conductive layer; an insulating layer, located on the conductive layer; as well as The gate line comprises a seed layer and an electroplating layer, wherein the seed layer passes through the insulating layer and contacts the conductive layer, the seed layer has a triangular cross section, the electroplating layer covers the seed layer exposed outside the insulating layer, and the gate line has a triangular cross section.

11. The solar cell according to claim 10, wherein: The angle between the two side surfaces of the seed layer is equal to or less than 120°.

12. The solar cell according to claim 10, wherein: The angle between the two side surfaces of the electroplating layer is equal to or less than 120°.

13. The solar cell according to claim 10, wherein: The electroplating layer includes an inner layer and an outer layer, the inner layer is located between the seed layer and the outer layer, and the reflectivity of the outer layer is greater than the reflectivity of the inner layer.

14. The solar cell according to claim 10, wherein: The conductive layer includes N-type single crystal silicon or P-type single crystal silicon.

15. The solar cell according to claim 10, wherein: It also includes a tunneling oxide layer, which is located between the conductive layer and the silicon substrate, wherein the conductive layer includes N-type polysilicon or P-type polysilicon.

16. The solar cell according to claim 15, characterized in that The conductive layer and the tunnel oxide layer are disposed on a local area of ​​the silicon substrate, and a width of the conductive layer is equal to or greater than a width of the seed layer.

17. The solar cell according to claim 16, wherein: The width of the electroplating layer is equal to or greater than the width of the conductive layer.

18. The solar cell according to claim 10, wherein: The insulating layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

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