Integrated circuit cell with dual row, back-to-back transistor body bind

Abstract

An integrated circuit (IC) includes a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region; a second row cell comprising a second set of one or more CMOS signal processing cells comprising a second diffusion region; and a first body bond electrically coupling the first voltage rail to the first diffusion region and the second diffusion region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 878,825, filed on August 1, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to integrated circuits (ICs), and particularly to integrated circuit (IC) cells having dual standard cell rows, back-to-back, field effect transistor (FET) body attachment points. Background Art

[0004] An integrated circuit (IC) may include a two-dimensional array of signal processing complementary metal oxide semiconductor (CMOS) cells (also referred to as standard cells). Each signal processing CMOS cell may include one or more p-channel metal oxide semiconductor field effect transistors (PMOS FETs) and one or more n-channel metal oxide semiconductor field effect transistors (NMOS FETs). Typically, the PMOS FETs are formed on a continuous n+ diffusion region or N-well extending along a row of cells, while the NMOS FETs are formed on a continuous p+ diffusion substrate region also extending along the row of cells. In order to provide latch coverage for the PMOS FETs and the NMOS FETs, p-body tie points and n-body tie points are provided to electrically couple the upper voltage rail Vdd and the lower voltage rail Vss to the n+ diffusion region and the p+ diffusion region of the PMOS FET and the NMOSFET, respectively. Summary of the invention

[0005] The following content presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is subsequently presented.

[0006] One aspect of the present disclosure relates to an integrated circuit (IC). The IC includes a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region, a second row of cells including a second set of one or more CMOS signal processing cells including a second diffusion region, and a first body tie point electrically coupling a first voltage rail to the first diffusion region and the second diffusion region.

[0007] Another aspect of the present disclosure relates to a method. The method includes electrically coupling a first voltage rail to a first diffusion region and a second diffusion region in a first row of integrated circuit (IC) cells and a second row of IC cells, respectively, via a first body tie point extending across the first row of IC cells and the second row of IC cells; and electrically coupling a second voltage rail to a third diffusion region in the first row of IC cells via a second body tie point at least partially seated within the first row of IC cells.

[0008] Another aspect of the present disclosure is directed to an apparatus that includes a first component for electrically coupling a first voltage rail to a first diffusion region and a second diffusion region in a first IC cell and a second row of integrated circuit (IC) cells, respectively, the first electrical coupling component extending across the first row of IC cells and the second row of IC cells, and a second component for electrically coupling a second voltage rail to a third diffusion region in the first row of IC cells, the second electrical coupling component at least partially seated within the first row of IC cells.

[0009] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver, wherein the one or more signal processing cores include: a first row of cells including a first set of one or more signal processing complementary metal oxide semiconductor (CMOS) cells including a first diffusion region; a second row of cells including a second set of one or more signal processing CMOS cells including a second diffusion region; and a first body tie point electrically coupling a first voltage rail to the first diffusion region and the second diffusion region.

[0010] To achieve the foregoing and related purposes, one or more implementations include the features fully described below and specifically pointed out in the claims. The following description and the attached figures set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of several of the various ways in which the principles of each implementation may be employed, and the specification implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A layout view of an example integrated circuit (IC) according to an aspect of the present disclosure is illustrated.

[0012] Figure 2 A layout view of an example end cap unit according to another aspect of the present disclosure is illustrated.

[0013] Figure 3A layout view of another example integrated circuit (IC) according to another aspect of the disclosure is illustrated.

[0014] Figure 4 A layout view of another example integrated circuit (IC) according to another aspect of the disclosure is illustrated.

[0015] Figure 5 A layout view of another example integrated circuit (IC) according to another aspect of the disclosure is illustrated.

[0016] Figure 6 A layout view of another example end cap unit according to another aspect of the present disclosure is illustrated.

[0017] Figure 7 A flow chart illustrating an example method of providing latch coverage to field effect transistors (FETs) in a row of an integrated circuit (IC) according to another aspect of the disclosure.

[0018] Figure 8 A block diagram of an example wireless communication device according to another aspect of the disclosure is illustrated. DETAILED DESCRIPTION

[0019] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations with which the concepts described herein can be practiced. In order to provide a comprehensive understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0020] Figure 1 Illustrated is a layout view of an example integrated circuit (IC) 100 according to an aspect of the present disclosure. IC 100 includes a two-dimensional array of IC cells; and in this example, the array is an N+2 row by three (3) column array of cells.

[0021] More specifically, IC 100 includes a central column including an upper boundary cell 140, N groups (rows) of one or more signal processing complementary metal oxide semiconductor (CMOS) (also referred to as "standard") cells 150-1 to 150-N, and a lower boundary cell 160, all of which are substantially aligned in the column dimension. IC 100 also includes a left column including an upper left corner cell 110, N groups (rows) of left end cap cells 120-1 to 120-N, and a lower left corner cell 130, all of which are substantially aligned in the column dimension. Similarly, IC 100 also includes a right column including an upper right corner cell 170, N groups (rows) of right end cap cells 180-1 to 180-N, and a lower right corner cell 190, all of which are substantially aligned in the column dimension.

[0022] The upper row of IC cells including the upper left corner cell 110, the upper boundary cell 140, and the upper right corner cell 170 are substantially aligned in the row dimension. The rows of IC cells including the group of left end cap cells 120-1 to 120-N, the multiple groups of one or more signal processing CMOS cells 150-1 to 150-N, and the group of right end cap cells 180-1 to 180-N are substantially aligned in the row dimension, respectively. The lower row including the lower left corner cell 130, the lower boundary cell 160, and the lower right corner cell 190 are substantially aligned in the row dimension.

[0023] Each row of CMOS cells 150-1 to 150-N may include one or more CMOS cells staggered in the row dimension, wherein each of the CMOS cells may be defined in a standard cell library. As an example, each CMOS cell may functionally process one or more signals and may be implemented as an inverter, an OR gate, a NOR gate, an AND gate, a NAND gate, an XOR gate, an XNOR gate, an AOI gate, an OAI gate, a flip-flop, a latch, a buffer, a multiplexer, a comparator, and the like. The one or more CMOS cells in each row include a common n+ diffusion region (shown as a shaded area) associated with one or more p-channel metal oxide semiconductor field effect transistors (PMOS FETs). The one or more CMOS cells in each row also include a common p+ diffusion region (also shown as a shaded area) associated with one or more n-channel metal oxide semiconductor field effect transistors (NMOS FETs).

[0024] If the substrate on which IC 100 is formed is a p-type doped substrate, the n+ diffusion region is coupled to the n-well, which includes the p+ regions of the source and drain of the PMOS FET; and the p+ diffusion region is coupled to the p-doped substrate including the n+ regions of the source and drain of the NMOS FET. If the substrate on which IC 100 is formed is an n-type doped substrate, the n+ diffusion region is coupled to the n-doped substrate, which includes the p+ regions of the source and drain of the PMOS FET; and the p+ diffusion region is coupled to the p-well including the n+ regions of the source and drain of the NMOS FET. It should be understood that IC 100 may include other types of FETs, such as FETs having both n-wells and p-wells.

[0025] Typically, the n+ diffusion region and the p+ diffusion region extend longitudinally, continuously, and horizontally (along the row dimension) across each of the multiple rows of CMOS cells 150-1 to 150-N and into the corresponding left end cap cells 120-1 to 120-N and right end cap cells 180-1 and 180-N, respectively. To prevent latch-up, i.e., forward biasing of the pn junctions in the PMOS FETs and PMOS FETs, an upper supply voltage Vdd (represented as a horizontal line between every other pair (e.g., odd pairs) of rows) is applied to the n+ diffusion region, and a lower supply voltage Vss (represented as a horizontal line between every other pair (e.g., even pairs) of rows) is applied to the p+ diffusion region. Therefore, IC100 includes body tie points to achieve electrical coupling of the Vdd and Vss voltage rails to the n+ diffusion region and the p+ diffusion region, respectively. Since the n+ diffusion region is associated with a PMOS FET, the p-body tie point refers to the Vdd connection to the n+ diffusion region; and since the p+ diffusion region is associated with an NMOS FET, the n-body tie point refers to the Vss connection to the p+ diffusion region.

[0026] As shown, each of the left end cap cells 120-1 to 120-N and the right end cap cells 180-1 to 180-N includes a p-body tie point and an n-body tie point, as indicated by the Vdd-n+ connection and the Vss-p+ connection. According to certain design rule check (DRC) requirements of IC manufacturing foundries, the size of the p-body tie point and the n-body tie point provides a certain length L for the n+ diffusion region and the p+ diffusion region within the CMOS cell of the corresponding row due to their inherent resistance. LUP_CVR Latch (LUP) coverage. For example, a p-body tie point or n-body tie point with six (6) fin sizes can provide a latch coverage length L of 16 microns (μm). LUP_CVR. Therefore, if the length of the row of CMOS cells 150-1 to 150-N is 32 μm, the p-body tie points and the n-body tie points in the left end cap cells 120-1 to 120-N provide latching coverage for the left half of the multiple rows of CMOS cells 150-1 to 150-N, and the p-body tie points and the n-body tie points in the right end cap cells 180-1 to 180-N provide latching coverage for the right half of the multiple rows of CMOS cells 150-1 to 150-N, respectively.

[0027] Figure 2 A layout view of an example end cap unit 200 according to another aspect of the present disclosure is illustrated. The end cap unit 200 may be an example of any left end cap unit 120-1, 120-3, and 120-(N-1) including an upper p-body tie point and a lower n-body tie point. It should be understood that the vertically flipped version of the end cap unit 200 may be an example of any left end cap unit 120-2, 120-(N-2), and 120-N including an upper n-body tie point and a lower p-body tie point. It should also be understood that the horizontally flipped version of the end cap unit 200 may be an example of any right end cap unit 180-1, 180-3, and 180-(N-1) including an upper p-body tie point and a lower n-body tie point. In addition, it should be understood that the vertical and horizontal flipped versions of the end cap unit 200 may be an example of any right end cap unit 180-2, 180-(N-2), and 180-N including an upper n-body tie point and a lower p-body tie point. Furthermore, it should be understood that end cap unit 200 may include additional components, such as dummy polysilicon gates for terminating a row of cells of IC 100 .

[0028] Specifically, the end cap unit 200 includes a p-body tie point 210 and an n-body tie point 250. The p-body tie point 210 electrically couples the upper voltage metal rail Vdd to the n+ diffusion region extending into the corresponding row of CMOS cells. Similarly, the n-body tie point 250 electrically couples the lower voltage metal rail Vss to the p+ diffusion region extending into the corresponding row of CMOS cells.

[0029] More specifically, the p-body tie 210 includes a pair of fin structures 212 electrically coupled to the n+ diffusion region, seated above the n+ diffusion region, and extending longitudinally parallel to the n+ diffusion region (along the row dimension). It should be understood that the p-body tie 210 may include a single such fin structure 212 or more than two such fin structures 212. The p-body tie 210 also includes at least a portion of a set of four (4) polysilicon structures 214 seated above the pair of fin structures 212 and extending longitudinally perpendicular to the pair of fin structures (along the column dimension). It should be understood that the p-body tie 210 may include two or more such polysilicon structures 214.

[0030] In addition, the p-body tie 210 includes a set of three (3) metal strips 216 (e.g., middle-of-line (MOL) metallization) that are respectively electrically coupled to the fin structures 212 in the region between adjacent polysilicon structures 214, sit above the fin structures, and extend longitudinally perpendicular to the fin structures (along the column dimension). It should be understood that the p-body tie 210 may include one or more such MOL metal strips 216. Furthermore, the p-body tie 210 includes a set of metallized vias 218 that electrically couple the MOL metal strips 216 to the upper voltage metal rail Vdd, respectively. Thus, the upper voltage metal rail Vdd is electrically coupled to the n+ diffusion region via the metallized vias 218, the MOL metal strips 216, and the pair of fin structures 212.

[0031] Similarly, the n-body tie 250 includes a pair of fin structures 252 electrically coupled to the p+ diffusion region, seated above the p+ diffusion region, and extending longitudinally parallel to the p+ diffusion region (along the row dimension). It should be understood that the n-body tie 250 may include a single such fin structure 252 or more than two such fin structures 252. The n-body tie 250 also includes at least a portion of a set of four (4) polysilicon structures 254 seated above the pair of fin structures 252 and extending longitudinally perpendicular to the pair of fin structures (along the column dimension). It should be understood that the n-body tie 250 may include two or more such polysilicon structures 254.

[0032] In addition, the n-body tie 250 includes a set of three (3) metal strips 256 (e.g., middle-of-line (MOL) metallization) that are respectively seated above the fin structures 252 in the region between adjacent polysilicon structures 254, electrically coupled to the fin structures, and extending longitudinally perpendicular to the fin structures (along the column dimension). It should be understood that the n-body tie 250 may include one or more such MOL metal strips 256. Furthermore, the n-body tie 250 includes a set of metallized vias 258 that electrically couple the MOL metal strips 256 to the lower voltage metal rail Vss, respectively. Thus, the lower voltage metal rail Vss is electrically coupled to the p+ diffusion region via the metallized vias 258, the MOL metal strips 256, and the pair of fin structures 252.

[0033] As mentioned above, the length L covered by the latch LUP_CVR Based on the fin size of p body tie point 210 and n body tie point 250 (for example, a 6-fin body tie point may have a length L LUP_CVR=16μm latch coverage). For example, each of the p-body binding 210 and the n-body binding 250 has a size of six (6) fins. The fin size of the body binding is calculated by the number of fins between different adjacent pairs of polysilicon structures; because these fins 212 / 252 are coupled to the voltage rails Vdd / Vss via MOL metal strips 216 / 256 and metallized vias 218 / 258, respectively. For example, in the p-body binding 210 or the n-body binding 250, there are two (2) fins between each pair of polysilicon structures, and there are three (3) different adjacent pairs of polysilicon structures (e.g., the fin size is 2×3=6). If a longer latch coverage length L is required LUP_CVR (For example, L LUP_CVR =30 μm), the fin size of the p-body tie 210 and the n-body tie 250 should be increased by, for example, increasing the length of the fin structures 212 / 252 so that they traverse more different adjacent pairs (e.g., eight (8) pairs) of polysilicon structures 214 / 254 (e.g., 16 fin-body tie).

[0034] Figure 3 A layout view of another example integrated circuit (IC) 300 according to another aspect of the present disclosure is illustrated. IC 300 is similar to IC 100, including many similar elements indicated by the same reference numerals, except that the most significant digit (MSD) is "3" in the case of IC 300 instead of "1" in the case of IC 100.

[0035] That is, in this example, IC 300 is configured as an N+2 row by 3 column two-dimensional array of IC cells, the array including: a left column, which includes an upper left (UL) corner cell 310, a group (row) of left end cap cells 320-1 to 320-N and a lower left (LL) corner cell 330; a middle column, which includes an upper boundary cell 340, multiple groups (rows) of one or more signal processing CMOS cells (also called "standard" cells) 350-1 to 350-N and a lower boundary cell 360; and a right column, which includes an upper right (UR) corner cell 370, a group (row) of right end cap cells 380-1 to 380-N and a lower right (LR) corner cell 390.

[0036] The group of left end cap cells 320-1 to 320-N include p-body tie points 322-1 to 322-N and n-body tie points 324-1 and 324-N, respectively. Similarly, the group of right end cap cells 380-1 to 380-N include p-body tie points 382-1 to 382-N and n-body tie points 384-1 and 384-N, respectively. The p-body tie points 322-1 to 322-N and 382-1 to 382-N electrically couple the upper voltage rail Vdd (represented as horizontal lines between every other pair (e.g., odd pairs) of rows) to n+ diffusion regions (e.g., n-wells) within the left end cap cells 320-1 to 320-N, the ICCMOS cells 350-1 to 350-N, and the right end cap cells 380-1 to 380-N, respectively. Similarly, n-body tie points 324-1 to 324-N and 384-1 to 384-N electrically couple the lower voltage rail Vss (represented as horizontal lines between every other pair (e.g., even pairs) of rows) to p+ diffusion regions (e.g., p-substrate) within the left end cap cells 320-1 to 320-N, IC CMOS cells 350-1 to 350-N, and right end cap cells 380-1 to 380-N, respectively. As previously mentioned, the n+ diffusion regions are associated with the PMOS FETs of the IC CMOS cells, and the p+ diffusion regions are associated with the NMOS FETs of the IC CMOS cells.

[0037] In this example, the p-body tie points 322-1 to 322-N and 382-1 to 382-N and the n-body tie points 324-1 to 324-N and 384-1 to 384-N can each be implemented as a 6-fin body tie point. Therefore, according to certain DRC requirements, the p-body tie points and the n-body tie points can each provide a length L LUP_CVR1 Thus, the p-body tie points 322-1 to 322-N and the n-body tie points 324-1 to 324-N in the left end cap units 320-1 to 320-N provide, for example, latch coverage (e.g., L) for the left end portions of the p+ diffusion regions and n+ diffusion regions of a group of IC CMOS cells 350-1 to 350-N, respectively. LUP_CVR1 =16 μm). Similarly, p-body tie points 382-1 to 382-N and n-body tie points 384-1 to 384-N in right end cap units 380-1 to 380-N provide, for example, latching covers (e.g., L LUP_CVR1=16 μm). Although in this example, the body tie points in the left end cap unit are the same size as the body tie points in the right end cap unit (e.g., 6 fins), it should be understood that they can be different; this means that the latch coverage of the left end portion of the IC CMOS unit 350-1 to 350-N may be different from the latch coverage of the right end portion of the IC CMOS unit 350-1 to 350-N.

[0038] Furthermore, according to this example, the lengths of the p+ diffusion regions and the n+ diffusion regions in a group of IC CMOS cells 350-1 to 350-N may be greater than (e.g., 45 μm) the latch coverage length L provided by the left end cap cells 320-1 to 320-N and the right end cap cells 380-1 to 380-N, respectively. LUP_CVR1 (e.g., 16 μm). Therefore, in this example, the group of IC CMOS cells 350-1 to 350-N also includes a group of intermediate p-body binding points 352-1 to 352-N and a group of intermediate n-body binding points 354-1 to 354-N, respectively. Similarly, the group of intermediate p-body binding points 352-1 to 352-N electrically couples the upper voltage rail Vdd to the n+ diffusion regions of the group of IC CMOS cells 350-1 to 350-N, and the group of intermediate n-body binding points 354-1 to 354-N electrically couples the lower voltage rail Vss to the p+ diffusion regions of the group of IC CMOS cells 350-1 to 350-N, respectively.

[0039] Similarly, the size of each of the intermediate p-body tie points 352-1 to 352-N and n-body tie points 354-1 to 354-N can be the same as (or optionally different from) the size of each of the p-body tie points and n-body tie points of the left end cap unit and the right end cap unit, respectively (e.g., 6-fin size body tie points). Therefore, the intermediate p-body tie points 352-1 to 352-N and the n-body tie points 354-1 to 354-N provide, for example, latching coverage (e.g., L L) for the intermediate portions of the p+ diffusion regions and n+ diffusion regions of the group of IC CMOS cells 350-1 to 350-N, respectively. LUP_CVR2 =16μm; between at least two signal processing ("standard") CMOS cells). Thus, by using the intermediate p-body and n-body tie points, as well as the p-body and n-body tie points of the end cap cells, latch coverage can be provided for the entire p+ diffusion region and n+ diffusion region in the group of IC CMOS cells 350-1 to 350-N, respectively (e.g., 3x16μm=48μm>45μm).

[0040] However, a disadvantage of the intermediate body tie point approach is that it tends to occupy a significant amount of additional IC footprint. For example, in a certain technology node (e.g., four (4) nanometer (nm) technology node (N4)) and IC implementation, the additional intermediate p-body tie points 352-1 to 352-N and n-body tie points 354-1 to 354-N may result in an IC area penalty of 79 percent (%). Therefore, a more IC area efficient approach for providing additional latch coverage for a group of IC CMOS cells 350-1 to 350-N may be desired.

[0041] Figure 4 A layout view of another example integrated circuit (IC) 400 according to another aspect of the present disclosure is illustrated. IC 400 is similar to ICs 100 and 300, including many similar elements indicated by the same reference numerals, except that the most significant digit (MSD) is "4" in the case of IC 400, rather than "1" and "3" in the case of ICs 100 and 300, respectively.

[0042] That is, in this example, IC 400 is configured as an N+2 row by three (3) column two-dimensional array of IC cells, the array including: a left column, which includes an upper left (UL) corner cell 410, a group (row) of left end cap cells 420-1 to 420-N and a lower left (LL) corner cell 430; a middle column, which includes an upper boundary cell 440, multiple groups (rows) of one or more signal processing CMOS cells 450-1 to 450-N and a lower boundary cell 460; and a right column, which includes an upper right (UR) corner cell 470, a group (row) of right end cap cells 480-1 to 480-N and a lower right (LR) corner cell 490.

[0043] The set of left end cap cells 420-1 to 420-N include p-body tie points 422-1 to 422-N and n-body tie points 424-1 and 424-N, respectively. Similarly, the set of right end cap cells 480-1 to 480-N include p-body tie points 482-1 to 482-N and n-body tie points 484-1 and 484-N, respectively. Similarly, the p-body tie points 422-1 to 422-N and 482-1 to 482-N electrically couple the upper voltage rail Vdd (represented as horizontal lines between every other pair (e.g., odd pairs) of rows) to n+ diffusion regions (e.g., n-wells) within the left end cap cells 420-1 to 420-N, the IC CMOS cells 450-1 to 450-N, and the right end cap cells 480-1 to 480-N, respectively. Similarly, n-body tie points 424-1 to 424-N and 484-1 to 484-N electrically couple the lower voltage rail Vss (represented as horizontal lines between every other pair (e.g., even pairs) of rows) to p+ diffusion regions (e.g., p-substrate) within the left end cap cells 420-1 to 420-N, IC CMOS cells 450-1 to 450-N, and right end cap cells 480-1 to 480-N, respectively. As discussed, the n+ diffusion regions are associated with the PMOS FETs of the IC CMOS cells, and the p+ diffusion regions are associated with the NMOS FETs of the IC CMOS cells.

[0044] In the previous example IC 300, the p-body tie points 322-1 to 322-N and 382-1 to 382-N and the n-body tie points 324-1 to 324-N and 384-1 to 384-N are each implemented as a 6-fin body tie point. Therefore, based on certain DRC requirements, the p-body tie points and the n-body tie points can each provide a length L LUP_CVR1 Therefore, the p-body tie points 322-1 to 322-N and 382-1 to 382-N and the n-body tie points 324-1 to 324-N and 384-1 to 384-N in the left end cap unit 320-1 to 320-N and the right end cap unit 380-1 to 380-N provide a length of 2*L for the p+ diffusion region and the n+ diffusion region of the group of IC CMOS cells 350-1 to 350-N, respectively. LUP_CVR1 =32 μm latch coverage. However, as discussed, the set of IC CMOS cells 350-1 to 350-N may have a latch coverage greater than 2*L LUP_CVR1 =32 μm latch covers a large length (eg, 45 μm), which is smaller than the 45 μm of the p+ diffusion region and the n+ diffusion region.

[0045] In the case of IC 400, p-body tie points 422-1 to 422-N and 482-1 to 482-N and n-body tie points 424-1 to 424-N and 484-1 to 484-N are implemented as 16-fin body tie points. According to certain DRC requirements, the 16-fin body tie points can provide a length L LUP_CVR3 Therefore, the p-body tie points 422-1 to 422-N and 482-1 to 482-N and the n-body tie points 424-1 to 424-N and 484-1 to 484-N in the left end cap units 420-1 to 420-N and the right end cap units 480-1 to 480-N provide a length of 2*L for the p+ diffusion region and the n+ diffusion region of the group of IC CMOS cells 450-1 to 450-N, respectively. LUP_CVR3 = 60 μm latch coverage. Considering the previous similar example IC CMOS cells 450-1 to 450-N with a length of 45 μm, the latch coverage provided by the 16-fin p-body tie points and n-body tie points is sufficient for the entire length of the p+ diffusion regions and n+ diffusion regions of the group of IC CMOS cells 450-1 to 450-N.

[0046] However, a disadvantage of the longer (e.g., 16 fin) body tie approach is that it still tends to occupy a significant amount of additional IC footprint. For example, at a certain technology node (e.g., four (4) nm technology node (N4)) and IC implementation, longer (e.g., 16 fin) p-body tie and n-body tie may result in a 10.5% IC area penalty. Such an approach may be an improvement over the intermediate p-body tie and n-body tie approach of IC 300 discussed previously, but a more IC area efficient approach may still be desired to provide additional latch coverage for IC CMOS cells.

[0047] Figure 5 A layout view of another example integrated circuit (IC) 500 according to another aspect of the present disclosure is illustrated. As discussed in further detail herein, IC 500 can be implemented to provide latch coverage for multiple rows of IC CMOS cells in a more IC area efficient manner than the previously discussed ICs 300 and 400. IC 500 is structurally similar to ICs 100, 300, and 400, including many similar elements indicated by the same reference numerals, except that the most significant digit (MSD) is "5" in the case of IC 500, rather than "1", "3", and "4" in the case of ICs 100, 300, and 400, respectively.

[0048] That is, IC 500 is configured as an N+2 row by 3 column two-dimensional array of IC cells, the array comprising: a left column, which includes an upper left (UL) corner cell 510, a group (row) of left end cap cells 520-1 to 520-N and a lower left (LL) corner cell 530; a middle column, which includes an upper boundary cell 540, multiple groups (rows) of one or more signal processing CMOS ("standard") cells 550-1 to 550-N and a lower boundary cell 560; and a right column, which includes an upper right (UR) corner cell 570, a group (row) of right end cap cells 580-1 to 580-N and a lower right (LR) corner cell 590.

[0049] In this case, each adjacent row pair of left end cap cells 520-1 to 520-N includes body tie points combined in a back-to-back configuration to provide latching coverage for two diffusion regions of corresponding adjacent row pairs of IC CMOS cells 550-1 to 550-N, respectively. For example, the adjacent row pair of left end cap cells 520-1 and 520-2 includes an n body tie point 524-12 that electrically couples the lower voltage rail Vss to the p+ diffusion region of the adjacent row pair of IC CMOS cells 550-1 and 550-2, respectively. Similarly, the adjacent row pair of left end cap cells 520-2 and 520-3 includes a p body tie point 522-23 that electrically couples the upper voltage rail Vdd to the n+ diffusion region of the adjacent row pair of IC CMOS cells 550-2 and 550-3, respectively. Likewise, adjacent row pairs of left end cap cells 520-M (where M=N-1) and 520-N include n-body tie points 524-MN that electrically couple lower voltage rail Vss to p+ diffusion regions of adjacent row pairs of IC CMOS cells 550-M and 550-N, respectively.

[0050] Similarly, each adjacent row pair of right end cap cells 580-1 to 580-N includes body tie points combined in a back-to-back configuration to provide latching coverage for two diffusion regions of corresponding adjacent row pairs of IC CMOS cells 550-1 to 550-N, respectively. For example, the adjacent row pair of right end cap cells 580-1 and 580-2 includes an n body tie point 584-12 that electrically couples the lower voltage rail Vss to the p+ diffusion regions of the adjacent row pair of IC CMOS cells 550-1 and 550-2, respectively. Similarly, the adjacent row pair of right end cap cells 580-2 and 580-3 includes a p body tie point 582-23 that electrically couples the upper voltage rail Vdd to the n+ diffusion regions of the adjacent row pair of IC CMOS cells 550-2 and 550-3, respectively. Likewise, the adjacent row pair of right end cap cells 580-M and 580-N include n-body tie points 584-MN that electrically couple the lower voltage rail Vss to the p+ diffusion regions of the adjacent row pair of IC CMOS cells 550-M and 550-N, respectively.

[0051] In addition, the upper left end cap cell and the upper right end cap cell include a body tie point coupled to a single diffusion region of the top row of IC CMOS cells. For example, the upper left end cap cell 520-1 and the upper right end cap cell 580-1 include a p body tie point coupled to the n+ diffusion region of the top row of IC CMOS cells 550-1. It should be understood that if the top row of IC CMOS cells 550-1 is arranged so that the p+ diffusion region is closer to the upper boundary cell 540 than the n+ diffusion region (for example, if the p+ diffusion region and the n+ diffusion region are flipped in a row of IC CMOS cells 550-1), then the upper left end cap cell 520-1 and the upper right end cap cell 580-1 will include an n body tie point coupled to the p+ diffusion region of the top row of IC CMOS cells 550-1.

[0052] Similarly, the left and right lower end cap cells include body tie points coupled to a single diffusion region of the bottom row of IC CMOS cells. For example, the left and right lower end cap cells 520-N and 580-N include p body tie points coupled to the n+ diffusion region of the bottom row of IC CMOS cells 550-N. Similarly, it should be understood that if the bottom row of IC CMOS cells 550-N is arranged with the p+ diffusion region closer to the lower boundary cell 560 than the n+ diffusion region (e.g., if the p+ diffusion region and the n+ diffusion region are flipped in the row of IC CMOS cells 550-N), then the left and right lower end cap cells 520-N and 580-N will include n body tie points coupled to the p+ diffusion region of the bottom row of IC CMOS cells 550-N.

[0053] Considering the previous example of a p+ diffusion region and an n+ diffusion region having a length of 45 μm, a combined body tie point spanning two adjacent rows can be implemented with 16 fins (e.g., an 8-fin body tie point combined back-to-back with another 8-fin body tie point). Depending on certain DRCs, each 16-fin body tie point can provide a length of L LUP_CVR3The combined body tie points in each adjacent row pair of the left end cap unit and the right end cap unit should therefore provide full length latch coverage for the corresponding diffusion regions of the corresponding adjacent row pairs of the IC unit (e.g., 2*30μm=60μm>45μm). Therefore, the n body tie points 524-12 and 584-12 of the adjacent row pairs of the left end cap unit 520-1 / 520-2 and the right end cap unit 580-1 / 580-2 provide full length latch coverage for the p+ diffusion regions of the adjacent row pairs of the IC units 550-1 and 550-2, respectively; the p body tie points 522-23 of the adjacent row pairs of the left end cap unit 520-2 / 520-3 and the right end cap unit 580-2 / 580-3 provide full length latch coverage for the p+ diffusion regions of the adjacent row pairs of the IC units 550-1 and 550-2, respectively; and 582-23 provide full-length latch coverage for the n+ diffusion regions of adjacent row pairs of IC units 550-2 and 550-3, respectively; and so on, n-body binding points 524-MN and 584-MN to adjacent row pairs of left end cap units 520-M / 520-N and right end cap units 580-M / 580-N, respectively, provide full-length latch coverage for the p+ diffusion regions of adjacent row pairs of IC units 550-M and 550-N, respectively.

[0054] As discussed above, the top / bottom end cap unit 520-1 / 520-N and the left / right end cap unit 580-1 / 580-N include p-body tie points 522-1 / 522-N and 582-1 / 582-N coupled to the n+ diffusion regions of the top row IC unit 550-1 and the bottom row IC unit 550-N, respectively. Since the p-body tie points 522-1 / 522-N and 582-1 / 582-N are not combined back-to-back, each body tie point can have a size of 8 fins. Therefore, each of the p-body tie points 522-1 / 522-N and 582-1 / 582-N can provide a latch coverage length L of 16 μm. LUP_CVR1 . Therefore, the top row of p-body binders 522-1 and 582-1 and the bottom row of p-body binders 522-N and 522-N may not provide full length latch coverage (e.g., 2*16μm=32μm<45μm) for the n+ diffusion regions of the top row of IC CMOS cells 550-1 and the bottom row of IC CMOS cells 550-N, respectively. Therefore, the top row of IC CMOS cells 550-1 and the bottom row of IC CMOS cells 550-N may include intermediate p-body binders 552-1 and 552-N, each configured with 8 fins to provide an additional 16μm in the intermediate region of the n+ diffusion regions of the top row of IC CMOS cells 550-1 and the bottom row of IC CMOS cells 550-N, so as to provide full length latch coverage (e.g., 3*16μm=48μm<45μm) for the n+ diffusion regions, respectively.

[0055] Figure 6A layout view of another example end cap unit 600 according to another aspect of the present disclosure is illustrated. The end cap unit 600 can be an example of the left end cap unit 520-3 or other similarly configured left end cap units such as the end cap unit 520-M. As further discussed herein, the left end cap unit 600 includes a back-to-back combination p body tie points on the upper side of the unit and a back-to-back combination n body tie points on the lower side of the unit. Other left end cap unit configurations, such as the end cap unit 520-2, include a back-to-back combination n body tie points on the upper side of the unit and a back-to-back combination p body tie points on the lower side of the unit; but in other respects, the configuration is substantially similar (e.g., a vertically flipped version of the left end cap unit 600).

[0056] In addition, the upper left end cap unit 520-1 and the lower left end cap unit 520-N can be similar in structure to the left end cap unit 600, except that one of the body tie points is a single body tie point that electrically couples the voltage rail to a single diffusion region of the corresponding row of IC CMOS cells (e.g., not a back-to-back combination body tie point), and some are vertically flipped. For example, the upper left end cap unit 520-1 includes a single p body tie point 522-1 that electrically couples the upper voltage rail Vdd to the n+ diffusion region of the row of IC CMOS cells 550-1, and a back-to-back combination n body tie point 524-12. Similarly, the lower left end cap unit 520-N includes a single p body tie point 522-N that electrically couples the upper voltage rail Vdd to the n+ diffusion region of the row of IC CMOS cells 550-N, and a back-to-back combination n body tie point 524-12.

[0057] Similarly, it should also be understood that the right end cap units 580-1 to 580-N can be horizontally flipped versions of the left end cap unit 600, horizontally and vertically flipped versions of the left end cap unit 600, horizontally flipped versions of the left end cap unit 600 in which one of the body binding points is a single body binding point, and horizontally and vertically flipped versions of the left end cap unit 600 in which one of the body binding points is a single body binding point.

[0058] In particular, the end cap unit 600 includes a back-to-back combined p-body tie point 610 and a back-to-back combined n-body tie point 650. The back-to-back combined p-body tie point 610 electrically couples the upper voltage metal rail Vdd to the n+ diffusion regions of two adjacent J-1 and Jh rows of the IC CMOS cell, respectively. Similarly, the back-to-back combined n-body tie point 650 electrically couples the lower voltage metal rail Vss to the p+ diffusion regions of the other two adjacent J and J+1 rows of the IC CMOS cell, respectively.

[0059] More specifically, the back-to-back combined p-body tie points 610 include a first pair of fin structures 612-1 that are electrically coupled to the n+ diffusion regions of the J-1th row of IC cells, extend longitudinally horizontally parallel (along the row dimension) to the n+ diffusion regions of the row of IC cells, and sit above the n+ diffusion regions of the row of IC cells. It should be understood that the p-body tie points 610 can include a single such fin structure 612-1 or more than two such fin structures 612-1. The back-to-back combined p-body tie points 610 also include a second pair of fin structures 612-2 that are electrically coupled to the n+ diffusion regions of the Jth row of IC cells, extend horizontally parallel (along the row dimension) to the n+ diffusion regions of the row of IC cells, and sit above the n+ diffusion regions of the row of IC cells. It should be understood that the p-body tie points 610 can include a single such fin structure 612-2 or more than two such fin structures 612-2. The p-body tie 610 also includes at least a portion of a set of five (5) polysilicon structures 614 that sit above and extend longitudinally perpendicular to the pair of fin structures 612-1 and 612-2 (along the column dimension). It should be understood that the p-body tie 610 may include two or more such polysilicon structures 614.

[0060] In addition, the p-body tie 610 includes a set of four (4) metal strips 616 (e.g., middle-of-line (MOL) metallization) that are electrically coupled to the fin structures 612-1 and 612-2 in the region between the adjacent polysilicon structures 614 and extend longitudinally perpendicular to the fin structures (in the column dimension). It should be understood that the p-body tie 610 may include one or more MOL metal strips 616. Furthermore, the p-body tie 610 includes a set of metallized vias 618 that electrically couple the MOL metal strips 616 to an upper voltage metal rail Vdd, respectively. Thus, the upper voltage metal rail Vdd is electrically coupled to the n+ diffusion regions of the adjacent J-1th and Jth rows of the IC CMOS cells, respectively, via the metallized vias 618, the MOL metal strips 616, and the pair of fin structures 612-1 and 612-2.

[0061] Similarly, the back-to-back combined n-body tie point 650 includes a first pair of fin structures 652-1 that are electrically coupled to the p+ diffusion regions of the Jth row of IC cells, extend longitudinally horizontally parallel (along the row dimension) to the p+ diffusion regions of the row of IC cells, and sit above the p+ diffusion regions of the row of IC cells. It should be understood that the n-body tie point 650 can include a single such fin structure 652-1 or more than two such fin structures 652-1. The back-to-back combined n-body tie point 650 also includes a second pair of fin structures 652-2 that are electrically coupled to the p+ diffusion regions of the J+1th row of IC cells, extend horizontally parallel (along the row dimension) to the p+ diffusion regions of the row of IC cells, and sit above the p+ diffusion regions of the row of IC cells. It should be understood that the n-body tie point 650 can include a single such fin structure 652-2 or more than two such fin structures 652-2. The n-body tie point 650 also includes at least a portion of a set of five (5) polysilicon structures 654 that sit above and extend longitudinally perpendicular to the pair of fin structures 652-1 and 652-2 (along the column dimension). It should be understood that the n-body tie point 650 may include two or more such polysilicon structures 654.

[0062] In addition, the n-body tie 650 includes a set of four (4) metal strips 656 (e.g., middle-of-line (MOL) metallization) that are electrically coupled to the fin structures 652-1 and 652-2 in the region between adjacent polysilicon structures 654 and extend longitudinally perpendicular to the fin structures (along the column dimension). It should be understood that the n-body tie 650 may include one or more MOL metal strips 656. In addition, the n-body tie 650 includes a set of metallization vias 658 that electrically couple the MOL metal strips 656 to the lower voltage metal rail Vss, respectively. Thus, the lower voltage metal rail Vss is electrically coupled to the p+ diffusion regions of the adjacent J-th and J+1-th rows of the IC CMOS cells via the metallization vias 658, the MOL metal strips 656, and the first and second pairs of fin structures 652-1 and 652-2, respectively.

[0063] Figure 7 A flow chart illustrating an example method 700 of providing latch coverage to field effect transistors (FETs) in a row of an integrated circuit (IC) according to another aspect of the disclosure.

[0064] The method 700 includes electrically coupling a first voltage rail to first and second diffusion regions in a first and second rows of integrated circuit (IC) cells, respectively, via a first body bond extending across the first and second rows of IC cells (block 710). Examples of components for electrically coupling the first voltage rail to first and second diffusion regions in the first and second rows of integrated circuit (IC) cells include n-body bonds 524-12, 584-12, 524-34, 584-34 ... 524-MN and 584-MN of IC 500, p-body bonds 522-23, 582-23 ... of IC 500, and n-body bonds 650 and p-body bonds 610 of end cap 600.

[0065] Method 700 also includes electrically coupling the second voltage rail to a third diffusion region in the first row of IC cells via a second body tie point at least partially seated within the first row of IC cells (block 720). Examples of components for electrically coupling the second voltage rail to the third diffusion region in the first row of IC cells include n-body tie points 524-12, 584-12, 524-34, 584-34 ... 524-MN, and 584-MN of IC 500, p-body tie points 522-1, 582-1, 522-23, 582-23 ... 522-N, and 582-N of IC 500, and n-body tie point 650 and p-body tie point 610 of end cap 600.

[0066] Method 700 may also include electrically coupling the second voltage rail to a fourth diffusion region in a third row of IC cells via the second body. Examples of components for electrically coupling the second voltage rail to a fourth diffusion region in a third row of IC cells include n-body binding points 524-12, 584-12, 524-34, 584-34 ... 524-MN and 584-MN of IC 500, p-body binding points 522-23, 582-23 ... of IC 500, and n-body binding point 650 and p-body binding point 610 of end cap 600.

[0067] Additionally, method 700 may include electrically coupling the first voltage rail to the first diffusion region and the second diffusion region, respectively, via a third body tie point extending across the first row of IC cells and the second row of IC cells. Examples of components for electrically coupling the first voltage rail to the first diffusion region and the second diffusion region include n-body tie points 524-12, 584-12, 524-34, 584-34 ... 524-MN and 584-MN of IC 500, p-body tie points 522-23, 582-23 ... of IC 500, and n-body tie points 650 and p-body tie points 610 of end cap 600.

[0068] Figure 8A block diagram of an example wireless communication device 800 according to another aspect of the present disclosure is illustrated. The wireless communication device 800 may be a smartphone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0069] Specifically, the wireless communication device 800 includes an integrated circuit (IC) that can be implemented as a system on a chip (SOC) 810. The SOC 810 includes one or more signal processing cores 820, which can be implemented with a two-dimensional array of IC cells 830, including a body tie point spanning two rows of IC cells for each of the previously discussed ICs 500 and end caps 600. The one or more signal processing cores 820 can be configured to generate a transmit baseband (BB) signal and process a receive baseband (BB) signal.

[0070] The wireless communication device 800 may also include a transceiver 850 and at least one antenna 860 (e.g., an antenna array). The transceiver 850 is coupled to the one or more signal processing cores 820 to receive a transmit BB signal therefrom and provide a receive BB signal thereto. The transceiver 850 is configured to convert the transmit BB signal into a transmit radio frequency (RF) signal and convert the receive RF signal into a receive BB signal. The transceiver 850 is coupled to at least one antenna 860 to provide it with a transmit RF signal for electromagnetic radiation into a wireless medium for wireless transmission, and to receive a receive RF signal electromagnetically picked up from the wireless medium by the at least one antenna 860.

[0071] The following provides an overview of various aspects of the present disclosure:

[0072] Aspect 1: An integrated circuit (IC), comprising: a first row of cells, the first row of cells comprising a first group of one or more signal processing complementary metal oxide semiconductor (CMOS) cells including a first diffusion region; a second row of cells, the second row of cells comprising a second group of one or more signal processing CMOS cells including a second diffusion region; and a first body binding point, the first body binding point electrically coupling a first voltage rail to the first diffusion region and the second diffusion region.

[0073] Aspect 2: The IC according to aspect 1, wherein: the first row unit includes a first end cap including a first portion of the first body attachment point; and the second row unit includes a second end cap unit including a second portion of the first body attachment point.

[0074] Aspect 3: An IC according to Aspect 1 or 2, wherein the first row of cells includes a third diffusion region, and the IC also includes: a third row of cells, the third row of cells including a third group of one or more signal processing CMOS cells including a fourth diffusion region; and a second body binding point, the second body binding point electrically coupling a second voltage rail to the third diffusion region and the fourth diffusion region.

[0075] Aspect 4: An IC according to Aspect 3, wherein: the first row unit includes a first end cap unit including a first portion of the first body binding point and a first portion of the second body binding point; the second row unit includes a second end cap unit including a second portion of the first body binding point; and the third row unit includes a third end cap unit including a second portion of the second body binding point.

[0076] Aspect 5: An IC according to Aspect 3 or 4, wherein: the first body binding point includes an n body binding point, the first voltage rail includes a lower voltage rail, and the first diffusion region and the second diffusion region include p+ diffusion regions, and the second body binding point includes a p body binding point, the second voltage rail includes an upper voltage rail, and the third diffusion region and the fourth diffusion region include n+ diffusion regions.

[0077] Aspect 6: An IC according to Aspect 3 or 4, wherein: the first body binding point includes a p-body binding point, the first voltage rail includes an upper voltage rail, and the first diffusion region and the second diffusion region include n+ diffusion regions, and the second body binding point includes an n-body binding point, the second voltage rail includes a lower voltage rail, and the third diffusion region and the fourth diffusion region include p+ diffusion regions.

[0078] Aspect 7: The IC of aspect 1 or 2, wherein the first row of cells comprises a third diffusion region, and the IC further comprises a second body tie point electrically coupling a second voltage rail to the third diffusion region.

[0079] Aspect 8: The IC of aspect 7, further comprising a corner cell sitting adjacent to the first row cell in a column dimension.

[0080] Aspect 9: The IC according to aspect 7 or 8, further comprising a third body tie point electrically coupling the second voltage rail to the third diffusion region, wherein the third body tie point is located between the two signal processing CMOS cells of the first group.

[0081] Aspect 10: The IC of aspect 9, wherein the second body attachment point and the third body attachment point are substantially the same size but smaller than the first body attachment point.

[0082] Aspect 11: The IC of any of aspects 1 to 10, further comprising a second body tie point electrically coupling the first voltage rail to the first diffusion region and the second diffusion region.

[0083] Aspect 12: An IC according to Aspect 11, wherein: the first row unit includes: a first left end cover unit including a first part of the first main body binding point; and a first right end cover unit including a first part of the second main body binding point; and the second row unit includes: a second left end cover unit including a second part of the first main body binding point; and a second right end cover unit including a second part of the second main body binding point.

[0084] Aspect 13: An IC according to Aspect 11 or 12, wherein the first row of cells includes a third diffusion region, and the IC also includes: a third row of cells, the third row of cells including a third group of one or more signal processing CMOS cells including a fourth diffusion region; a third body binding point, the third body binding point electrically coupling a second voltage rail to the third diffusion region and the fourth diffusion region; and a fourth body binding point, the fourth body binding point electrically coupling the second voltage rail to the third diffusion region and the fourth diffusion region.

[0085] Aspect 14: An IC according to Aspect 13, wherein: the first left end cover unit includes a first part of the third main body binding point; the third row unit includes a third left end cover unit including a second part of the third main body binding point; the first right end cover unit includes a first part of the fourth main body binding point; and the third row unit includes a third right end cover unit including a second part of the fourth main body binding point.

[0086] Aspect 15: An IC according to aspect 12, wherein the first row unit includes a third diffusion region; wherein the first left end cap unit includes a third body tie point electrically coupling a second voltage rail to the third diffusion region; and wherein the first right end cap unit includes a fourth body tie point electrically coupling the second voltage rail to the third diffusion region.

[0087] Aspect 16: According to the IC of Aspect 15, the IC also includes: a left corner unit, which is located adjacent to the first left end cover unit in the column dimension; and a right corner unit, which is located adjacent to the first right end cover unit in the column dimension.

[0088] Aspect 17: The IC according to aspect 15 or 16, the IC further comprising a fifth body tie point electrically coupling the second voltage rail to the third diffusion region, wherein the third body tie point is located between the first left end cap unit and the first right end cap unit.

[0089] Aspect 18: The IC of aspect 17, wherein the third body attachment point, the fourth body attachment point, and the fifth body attachment point are substantially the same size but smaller than the first body attachment point and the second body attachment point.

[0090] Aspect 19: An IC according to any one of Aspects 1 to 18, wherein the first body binding point includes: a first group of one or more parallel fin structures, the first group of one or more parallel fin structures are located above the first diffusion region and electrically coupled to the first diffusion region, wherein the first group of one or more parallel fin structures extend longitudinally along the row dimension; a second group of one or more parallel fin structures, the second group of one or more parallel fin structures are located above the second diffusion region and electrically coupled to the second diffusion region, wherein the first group of one or more parallel fin structures extend longitudinally along the row dimension; and a group of one or more metal strips, the group of one or more metal strips electrically couples the first group of one or more parallel fin structures to the second group of one or more parallel fin structures, wherein the group of one or more metal strips extend longitudinally along the column dimension, and wherein the group of one or more metal strips are electrically coupled to the first voltage rail.

[0091] Aspect 20: The IC of aspect 19, wherein the first body tie point comprises a set of polysilicon structures extending longitudinally along the column dimension, wherein the set of one or more metal strips are respectively seated between the set of polysilicon structures.

[0092] Aspect 21: A method comprising electrically coupling a first voltage rail to a first diffusion region and a second diffusion region in a first row of integrated circuit (IC) cells and a second row of IC cells, respectively, via a first body bonding point extending across the first row of IC cells and the second row of IC cells; and electrically coupling a second voltage rail to a third diffusion region in the first row of IC cells via a second body bonding point at least partially seated within the first row of IC cells.

[0093] Aspect 22: The method of aspect 21, wherein the second body bond point extends into a third row of IC cells, and the method further comprises electrically coupling the second voltage rail to a fourth diffusion region in the third row of IC cells via the second body bond point.

[0094] Aspect 23: A method according to aspect 21 or 22, wherein the first row of IC units includes a first end cap unit, wherein the first body attachment point is partially located within the first end cap unit, and wherein the second body attachment point is at least partially located within the first end cap unit.

[0095] Aspect 24: The method of aspect 23, wherein the second row of IC units comprises a second end cap unit, wherein the first body tie point is partially located within the second end cap unit.

[0096] Aspect 25: The method according to any one of aspects 21 to 24, the method further comprising electrically coupling the first voltage rail to the first diffusion region and the second diffusion region via a third body tie point extending across the first row of IC cells and the second row of IC cells, respectively.

[0097] Aspect 26: A method according to aspect 25, wherein the first row of IC units includes a first left end cap unit and a first right end cap unit, wherein the first body binding point is partially located within the first left end cap unit, and wherein the third body binding point is partially located within the first right end cap unit.

[0098] Aspect 27: A method according to aspect 26, wherein the second row of IC units includes a second left end cover unit and a second right end cover unit, wherein the first body binding point is partially located within the second left end cover unit, and wherein the third body binding point is partially located within the second right end cover unit.

[0099] Aspect 28: A device comprising: a first component for electrically coupling a first voltage rail to a first diffusion region and a second diffusion region in a first row of integrated circuit (IC) cells and a second row of IC cells, respectively, the first electrical coupling component extending across the first row of IC cells and the second row of IC cells; and a second component for electrically coupling a second voltage rail to a third diffusion region in the first row of IC cells, the second electrical coupling component being at least partially seated within the first row of IC cells.

[0100] Aspect 29: The apparatus of aspect 28, wherein the second electrical coupling component extends into a third row of IC cells, and wherein the second electrical coupling component couples the second voltage rail to a fourth diffusion region in the third row of IC cells.

[0101] Aspect 30: A wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver, the transceiver coupled to the at least one antenna; and an integrated circuit (IC), the integrated circuit (IC) comprising one or more signal processing cores coupled to the transceiver, wherein the one or more signal processing cores include: a first row of cells, the first row of cells comprising a first group of one or more signal processing complementary metal oxide semiconductor (CMOS) cells including a first diffusion region; a second row of cells, the second row of cells comprising a second group of one or more signal processing CMOS cells including a second diffusion region; and a first body binding point, the first body binding point electrically coupling a first voltage rail to the first diffusion region and the second diffusion region.

[0102] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but should be granted the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC), comprising: a first row of cells comprising a first set of one or more signal processing complementary metal oxide semiconductor (CMOS) cells including a first diffusion region; a second row of cells comprising a second set of one or more signal processing CMOS cells including a second diffusion region; as well as A first body tie point electrically couples a first voltage rail to the first diffusion region and the second diffusion region.

2. The IC of claim 1, wherein: The first row unit includes a first end cap unit including a first portion of the first body tie point; and The second row unit includes a second end cap unit including a second portion of the first body tie point.

3. The IC of claim 1 , wherein the first row of cells comprises a third diffusion region, and the IC further comprises: a third row of cells, the third row of cells comprising a third group of one or more signal processing CMOS cells including a fourth diffusion region; as well as A second body tie point electrically couples a second voltage rail to the third diffusion region and the fourth diffusion region.

4. The IC of claim 3, wherein: The first row unit includes a first end cap unit including a first portion of the first body tie point and a first portion of the second body tie point; the second row unit comprising a second end cap unit including a second portion of the first body tie point; and The third row of units includes a third end cap unit including a second portion of the second body tie point.

5. The IC of claim 3, wherein: The first body binding point includes an n body binding point, the first voltage rail includes a lower voltage rail, and the first diffusion region and the second diffusion region include p+ diffusion regions, and the second body binding point includes a p body binding point, the second voltage rail includes an upper voltage rail, and the third diffusion region and the fourth diffusion region include n+ diffusion regions.

6. The IC of claim 3, wherein: The first body binding point comprises a p body binding point, the first voltage rail comprises an upper voltage rail, and the first diffusion region and the second diffusion region comprise n+ diffusion regions, and the second body binding point comprises an n body binding point, the second voltage rail comprises a lower voltage rail, and the third diffusion region and the fourth diffusion region comprise p+ diffusion regions.

7. The IC of claim 1, wherein the first row of cells includes a third diffusion region, and the IC further includes a second body tie point electrically coupling a second voltage rail to the third diffusion region.

8. The IC of claim 7, further comprising a corner cell sitting adjacent to the first row cell in a column dimension.

9. The IC of claim 7, further comprising a third body tie point electrically coupling the second voltage rail to the third diffusion region, wherein the third body tie point is located between two signal processing CMOS cells of the first group.

10. The IC of claim 9, wherein the second body attachment point and the third body attachment point are substantially the same size but smaller than the first body attachment point.

11. The IC of claim 1 , further comprising a second body tie point electrically coupling the first voltage rail to the first diffusion region and the second diffusion region.

12. The IC of claim 11, wherein: The first row of units comprises: a first left end cap unit comprising a first portion of the first body tie point; and a first right end cap unit comprising a first portion of said second body tie point; and The second row of units comprises: a second left end cap unit comprising a second portion of said first body tie point; and A second right end cap unit includes a second portion of the second body tie point.

13. The IC of claim 12, wherein the first row of cells comprises a third diffusion region, and the IC further comprises: a third row of cells, the third row of cells comprising a third group of one or more signal processing CMOS cells including a fourth diffusion region; a third body tie point electrically coupling a second voltage rail to the third diffusion region and the fourth diffusion region; as well as A fourth body bonding point electrically couples the second voltage rail to the third diffusion region and the fourth diffusion region.

14. The IC of claim 13, wherein: The first left end cap unit includes a first portion of the third body tie point; The third row unit includes a third left end cap unit including a second portion of the third body tie point; The first right end cap unit includes a first portion of the fourth body tie point; and The third row unit includes a third right end cap unit including a second portion of the fourth body tie point.

15. The IC of claim 12, wherein: The first row of cells includes a third diffusion region; wherein the first left end cap unit comprises a third body tie point electrically coupling a second voltage rail to the third diffusion region; and The first right end cap unit includes a fourth body tie point electrically coupling the second voltage rail to the third diffusion region.

16. The IC of claim 15, further comprising: a left corner unit, the left corner unit being located adjacent to the first left end cap unit in a column dimension; as well as A right corner unit is positioned adjacent to the first right end cap unit in the column dimension.

17. The IC of claim 15, further comprising a fifth body tie point electrically coupling the second voltage rail to the third diffusion region, wherein the third body tie point is seated between the first left end cap unit and the first right end cap unit.

18. The IC of claim 17, wherein the third, fourth, and fifth body attachment points are substantially the same size but smaller than the first and second body attachment points.

19. The IC of claim 1, wherein the first body tie point comprises: a first set of one or more parallel fin structures, the first set of one or more parallel fin structures sitting over and electrically coupled to the first diffusion region, wherein the first set of one or more parallel fin structures extend longitudinally along a row dimension; a second set of one or more parallel fin structures, the second set of one or more parallel fin structures sitting over and electrically coupled to the second diffusion region, wherein the first set of one or more parallel fin structures extend longitudinally along the row dimension; as well as A set of one or more metal strips electrically couples the first set of one or more parallel fin structures to the second set of one or more parallel fin structures, wherein the set of one or more metal strips extends longitudinally along a column dimension, and wherein the set of one or more metal strips is electrically coupled to the first voltage rail.

20. The IC of claim 19, wherein the first body tie point comprises a set of polysilicon structures extending longitudinally along the column dimension, wherein the set of one or more metal strips are respectively seated between the set of polysilicon structures.

21. A method comprising: electrically coupling a first voltage rail to first and second diffusion regions in a first row of integrated circuit (IC) cells and a second row of IC cells, respectively, via a first body tie point extending across the first and second rows of IC cells; as well as A second voltage rail is electrically coupled to a third diffusion region in the first row of IC cells via a second body tie point at least partially seated within the first row of IC cells.

22. The method of claim 21, wherein the second body bond extends into a third row of IC cells, and the method further comprises electrically coupling the second voltage rail to a fourth diffusion region in the third row of IC cells via the second body bond.

23. The method of claim 21, wherein the first row of IC units includes a first end cap unit, wherein the first body tie point is partially located within the first end cap unit, and wherein the second body tie point is at least partially located within the first end cap unit.

24. The method of claim 23, wherein the second row of IC units includes a second end cap unit, wherein the first body tie point is partially located within the second end cap unit.

25. The method of claim 21, further comprising electrically coupling the first voltage rail to the first diffusion region and the second diffusion region via a third body tie extending across the first row of IC cells and the second row of IC cells, respectively.

26. The method of claim 25, wherein the first row of IC units comprises a first left end cap unit and a first right end cap unit, wherein the first body tie point is partially located within the first left end cap unit, and wherein the third body tie point is partially located within the first right end cap unit.

27. The method of claim 26, wherein the second row of IC units comprises a second left end cap unit and a second right end cap unit, wherein the first body tie point is partially located within the second left end cap unit, and wherein the third body tie point is partially located within the second right end cap unit.

28. An apparatus, comprising: a first means for electrically coupling a first voltage rail to first and second diffusion regions in a first and second rows of integrated circuit (IC) cells, respectively, the first electrical coupling means extending across the first and second rows of IC cells; as well as A second means for electrically coupling a second voltage rail to a third diffusion region in the first row of IC cells, the second electrical coupling means being at least partially seated within the first row of IC cells.

29. The apparatus of claim 28, wherein the second electrical coupling component extends into a third row of IC cells, and wherein the second electrical coupling component couples the second voltage rail to a fourth diffusion region in the third row of IC cells.

30. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; as well as An integrated circuit (IC) comprising one or more signal processing cores coupled to the transceiver, wherein the one or more signal processing cores include: a first row of cells comprising a first set of one or more signal processing complementary metal oxide semiconductor (CMOS) cells including a first diffusion region; a second row of cells comprising a second set of one or more signal processing CMOS cells including a second diffusion region; and A first body tie point electrically couples a first voltage rail to the first diffusion region and the second diffusion region.

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