Battery pack information collection method, device, equipment and storage medium

Abstract

The present application relates to a method, device, equipment and storage medium for collecting information from a battery pack. The main technical scheme includes: determining the total number of cells in a battery pack; determining the total number of collection channels connected to the cells based on the total number of cells, wherein each cell is connected to a corresponding collection channel; determining at least one target chip with the highest collection channel utilization connected to the battery pack, wherein each target chip has multiple collection channels, and the collection channel utilization represents the ratio of the total number of collection channels connected to the cells to the total number of collection channels on all target chips; connecting the collection channels on the at least one target chip to the cells respectively, and collecting cell information. The present application can improve the chip collection channel utilization, save design space, and reduce costs.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a method, device, equipment and storage medium for collecting battery pack information. Background Art

[0002] Currently, new energy vehicles use a combination of MCU (Microcontroller Unit) and AFE (Analog Front End) chips to manage the battery system. The AFE chip collects and monitors the voltage of each cell in the battery pack.

[0003] However, due to different vehicle model requirements, different battery pack voltages and installation spaces, there are differences in the number of parallel and string batteries, such as 6 parallel and 20 strings, 4 parallel and 26 strings, 8 parallel and 16 strings, etc., and the number of parallel and single parallel strings is diverse. At the same time, there are fewer types of AFE chip voltage acquisition channels on the market, such as 18 channels, 24 channels, etc. In the prior art, a single AFE chip is usually used to collect the voltage of the cells in the same number of strings on the battery pack, which will lead to waste of AFE chip acquisition channels, resulting in high product costs. For example, in the past, each of the 6 parallel and 20 strings of total cells used the same AFE acquisition chip and an AFE chip, and a 24 acquisition channel chip was used as an example. That is, a battery pack with 6 parallel and 20 strings requires 6 AFE chips with 24 acquisition channels. The design solution is that 120 cells require a total of 144 AFE acquisition channels, and the channel utilization rate is 83%. The low utilization rate of the acquisition channels causes waste. Therefore, there is an urgent need for a method to solve the above problems. Summary of the invention

[0004] Based on this, the present application provides a battery pack information collection method, device, equipment and storage medium to solve the problems existing in the prior art.

[0005] In a first aspect, a method for collecting battery pack information is provided, the method comprising:

[0006] Determine the total number of cells in the battery pack;

[0007] Determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel;

[0008] Determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips;

[0009] The collection channels on the at least one target chip are connected to the battery cells respectively, and the battery cell information is collected.

[0010] According to an achievable method in the embodiment of the present application, determining at least one target chip with the highest acquisition channel utilization rate connected to the battery pack includes:

[0011] At least one target chip connected to the battery pack with a collection channel utilization rate of 100% is determined, wherein the collection channel utilization rate of 100% indicates that the total number of collection channels connected to the battery cell is equal to the total number of collection channels on all target chips.

[0012] According to an achievable method in the embodiment of the present application, determining at least one target chip with the highest acquisition channel utilization rate connected to the battery pack includes:

[0013] The number of information acquisition channels provided on each type of chip is obtained respectively, wherein the number of information acquisition channels provided on different types of chips is different;

[0014] At least one target chip combination of the same type or multiple target chip combinations of different types having the highest utilization rate of the acquisition channels connected to the battery pack is determined.

[0015] According to an achievable method in an embodiment of the present application, determining the total number of cells in the battery pack includes:

[0016] Obtain the number of battery modules connected in parallel and / or in series in the battery pack, wherein each battery module includes a plurality of battery cells connected in series;

[0017] Get the number of cells connected in series in each battery module;

[0018] The total number of battery cells in the battery pack is determined by multiplying the number of battery modules by the number of battery cells connected in series.

[0019] According to an achievable method in an embodiment of the present application, connecting the acquisition channels on the multiple target chips to the battery cells respectively includes:

[0020] Determine at least one acquisition board according to the battery pack space;

[0021] Evenly arranging the target chips on the at least one acquisition board;

[0022] The acquisition channels of the target chip on the at least one acquisition board are connected to the battery cells respectively.

[0023] According to an achievable method in an embodiment of the present application, the target chips are evenly arranged on the at least one acquisition board, including:

[0024] Provide a first acquisition board, and evenly arrange all target chips on the first acquisition board; or,

[0025] A plurality of identical second acquisition boards are provided, all target chips are evenly arranged on the plurality of second acquisition boards, and part of the target chips are arranged on each of the second acquisition boards.

[0026] According to an achievable method in an embodiment of the present application, the method of setting a plurality of identical second acquisition boards and setting a part of the target chip on each of the second acquisition boards includes:

[0027] Obtaining the total number of cells in the battery pack as a first number;

[0028] Determine that the number of the second acquisition boards is a second number;

[0029] Calculating a ratio of the first quantity to the second quantity to obtain a third quantity;

[0030] A part of the target chips provided on the second acquisition board is determined, wherein the number of acquisition channels contained in the part of the target chips is equal to the third number.

[0031] In a second aspect, a battery pack information collection device is provided, the device comprising:

[0032] Acquisition module: used to determine the total number of cells in the battery pack;

[0033] A determination module: used to determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel;

[0034] Combination module: used to determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips;

[0035] Acquisition module: used to connect the acquisition channels on the at least one target chip to the battery cells respectively and collect battery cell information.

[0036] In a third aspect, a computer device is provided, comprising:

[0037] at least one processor; and

[0038] a memory communicatively connected to the at least one processor; wherein,

[0039] The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method involved in the first aspect above.

[0040] In a fourth aspect, a computer-readable storage medium is provided, on which computer instructions are stored, characterized in that the computer instructions are used to enable a computer to execute the method involved in the first aspect above.

[0041] According to the technical content provided in the embodiments of the present application, the embodiments of the present application determine the total number of collection channels connected to the battery cells through the total number of battery cells, determine at least one target chip with the highest utilization rate of the collection channels connected to the battery pack based on the total number of collection channels connected to the battery cells, and connect the collection channels on the target chip to each battery cell respectively, which can improve the utilization rate of the chip's collection channels, save design space, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a flowchart of a method for collecting battery pack information in one embodiment;

[0043] Figure 2 This is one of the collection schematic diagrams of a battery pack information collection method in one embodiment;

[0044] Figure 3 This is a second collection schematic diagram of a battery pack information collection method in an embodiment;

[0045] Figure 4 is a structural block diagram of a battery pack information collection device in one embodiment;

[0046] Figure 5 FIG. 4 is a schematic structural diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0047] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] Figure 1 A flowchart of a battery pack information collection method provided in an embodiment of the present application, such as Figure 1 As shown, the method may include the following steps:

[0049] Step 101: Determine the total number of cells in the battery pack.

[0050] Specifically, the total number of cells in the battery pack is determined by calculating the product of the number of series and the number of parallels. The number of parallels refers to the number of first cells connected in parallel in the battery pack, which determines the capacity of the battery pack; the number of series refers to the number of second cells in series contained in each first cell in parallel, which determines the voltage of the battery pack. For example, the total number of cells in the battery pack is determined to be X.

[0051] Step 102: Determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel.

[0052] Specifically, when collecting battery pack information, each battery cell corresponds to a collection channel, and each battery cell is connected to the corresponding collection channel. The total number of collection channels connected to the battery cells is determined according to the total number of battery cells. When the total number of battery cells in the battery pack is X, the total number of collection channels connected to the battery cells is also X.

[0053] Step 103: Determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips.

[0054] Specifically, the target chip is an AFE chip, and each AFE chip has multiple acquisition channels. The number of acquisition channels on different types of AFE chips is different, for example, the number of acquisition channels is 18, 24, etc. According to the total number of acquisition channels X connected to the battery cell, determine the target chip combination with the highest utilization of the acquisition channels connected to the battery pack, for example, target chip one with 18 acquisition channels and target chip two with 24 acquisition channels. The acquisition channel utilization represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips. For example, the total number of acquisition channels connected to the battery cell is X, the total number of acquisition channels on all target chips is Z, and the acquisition channel utilization is X / Z. Moreover, when the total number of acquisition channels X connected to the battery cell is equal to the total number of acquisition channels Z on all target chips, the acquisition channel utilization is the highest, and at this time, the acquisition channel utilization is 100%.

[0055] Step 104: Connect the collection channels on at least one target chip to the battery cells respectively, and collect the battery cell information.

[0056] Specifically, the acquisition channel on the target chip determined in step 103, ie, the AFE chip, is connected to each battery cell respectively, and all the battery cells, a number X of which are in the battery pack, are connected to one acquisition channel respectively to acquire information of each battery cell.

[0057] It can be seen that the embodiment of the present application determines the total number of collection channels connected to the battery cells according to the total number of battery cells, determines at least one target chip with the highest collection channel utilization connected to the battery pack according to the total number of collection channels connected to the battery cells, and connects the collection channels on the target chip to each battery cell respectively, which can improve the chip's collection channel utilization, save design space, and reduce costs.

[0058] In one embodiment of the present application, determining the total number of battery cells in a battery pack includes: obtaining the number of battery modules connected in parallel and / or in series in the battery pack, wherein each battery module includes a plurality of battery cells connected in series; obtaining the number of battery cells connected in series in each battery module; and multiplying the number of battery modules by the number of battery cells connected in series to determine the total number of battery cells in the battery pack.

[0059] Specifically, the total number of cells in a battery pack is determined by calculating the product of the number of series and the number of parallels. The number of parallels is the number of battery modules connected in parallel and / or in series in a battery pack, wherein each battery module includes a plurality of cells connected in series; the number of series is the number of cells connected in series in each battery module. The total number of cells in a battery pack can be determined by multiplying the number of battery modules connected in parallel by the number of cells connected in series.

[0060] In one embodiment of the present application, determining at least one target chip with the highest collection channel utilization connected to a battery pack includes: determining at least one target chip with a collection channel utilization connected to the battery pack of 100%, wherein the collection channel utilization of 100% indicates that the total number of collection channels connected to the battery cell is equal to the total number of collection channels on all target chips.

[0061] Specifically, each target chip has multiple acquisition channels, and the number of acquisition channels on different types of target chips is different. For example, the number of acquisition channels is 18, 20, 24, etc. Determine at least one target chip whose acquisition channel utilization connected to the battery pack is 100%. Among them, the acquisition channel utilization represents the ratio of the total number of acquisition channels connected to the battery cells to the total number of acquisition channels on all target chips. The acquisition channel utilization of 100% represents that the total number of acquisition channels connected to the battery cells is equal to the total number of acquisition channels on all target chips. For example, a battery pack with 120 battery cells in series can use all 24-channel AFE acquisition chips, and the number is 120 / 24=5, that is, the target chips are 5 chips with 24 channels, and the acquisition channel utilization is At this time, the total number of acquisition channels on all target chips is , which is equal to the total number of cells in the battery pack.

[0062] In one embodiment of the present application, determining at least one target chip with the highest utilization rate of the acquisition channel connected to the battery pack includes: respectively obtaining the number of information acquisition channels provided on each type of chip, wherein the number of information acquisition channels provided on different types of chips is different; and determining a combination of multiple target chips of the same type or a combination of multiple target chips of different types with the highest utilization rate of the acquisition channels connected to the battery pack.

[0063] Specifically, different types of chips have different numbers of information acquisition channels. For example, the number of acquisition channels is 18, 20, 24, and so on. Determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack. The target chip can be a combination of multiple target chips of the same type, or a combination of multiple target chips of different types. Different types of AFE chips can be freely matched to improve the utilization rate of the acquisition channels, thereby reducing costs. For example, a battery pack with 120 cells in series can use all 24-channel AFE acquisition chips, and the number is 120 / 24=5, that is, the target chip is 5 chips with 24 channels, and the acquisition channel utilization rate is ; You can also mix and match 4 18-channel AFE acquisition chips with 2 24-channel AFE chips to maximize the utilization of acquisition channels. , that is, the target chips are 4 18-channel chips and 2 24-channel chips. In both cases, the acquisition channel utilization rate can reach 100%.

[0064] In one embodiment of the present application, the acquisition channels on multiple target chips are connected to the battery cells respectively, including: determining at least one acquisition board according to the battery pack space; evenly arranging the target chips on the at least one acquisition board; and connecting the acquisition channels of the target chips on the at least one acquisition board to the battery cells respectively.

[0065] Specifically, Figure 2 As shown, at least one acquisition board is determined according to the battery pack space, and target chips are evenly arranged on the at least one acquisition board, for example Figure 2 Chips 1 to 6 are evenly arranged on the acquisition board 1, and the acquisition channels of chips 1 to 6 on the acquisition board 1 are connected to each battery cell respectively. It should be noted that: Figure 2 Only the specific connection method between chip 1 to chip 3 and the battery cell is drawn. The specific connection method between chip 4 to chip 5 and the battery cell is exactly the same as that between chip 1 to chip 3, so it is not drawn in the figure. Those skilled in the art can directly derive the connection method between chip 4 and chip 5 based on the connection method between chip 1 to chip 3.

[0066] In one embodiment of the present application, target chips are evenly arranged on at least one acquisition board, including: providing a first acquisition board, and evenly arranging all target chips on the first acquisition board; or, providing multiple identical second acquisition boards, and evenly arranging all target chips on multiple second acquisition boards and arranging some target chips on each second acquisition board.

[0067] Specifically, Figure 2 As shown, combined with Figure 3 , evenly arranging the target chips on at least one acquisition board, including arranging a first acquisition board, and evenly arranging all the target chips on the first acquisition board. For example, Figure 2The acquisition board 1 in the figure is the first acquisition board, and all target chips, i.e., chips 1 to 6, are evenly arranged on the acquisition board 1. Alternatively, multiple identical second acquisition boards are arranged, and all target chips are evenly arranged on the multiple second acquisition boards, and part of the target chips are arranged on each second acquisition board. Figure 3 As shown, multiple identical second acquisition boards, namely, acquisition board 1 and acquisition board 2, are identical, and both contain half of all target chips, namely, chips 1 to 3. It should be noted that, Figure 3 Only the specific connection method between chip 1 to chip 3 and the battery cell on acquisition board 1 is drawn. The specific connection method between chip 1 and chip 3 on acquisition board 2 is exactly the same as that of acquisition board 1, so it is not drawn in the figure. Those skilled in the art can directly derive the connection method of acquisition board 2 based on acquisition board 1.

[0068] In the embodiments of the present application, a first acquisition board can be set up, and all target chips can be evenly arranged on the first acquisition board, or multiple identical second acquisition boards can be set up, and all target chips can be evenly arranged on multiple second acquisition boards and some target chips can be arranged on each second acquisition board. The number of acquisition boards can be flexibly divided according to the battery pack space, and the same design of the acquisition boards can be reused to reduce development investment. Multiple acquisition boards can use the same design reuse method to reduce development and product BOM costs.

[0069] In one embodiment of the present application, a plurality of identical second acquisition boards are provided, and a part of the target chips are provided on each second acquisition board, including: obtaining the total number of cells in the battery pack as a first number; determining the number of second acquisition boards as a second number; calculating the ratio of the first number to the second number to obtain a third number; determining a part of the target chips provided on the second acquisition board, and the number of acquisition channels contained in the part of the target chips is equal to the third number.

[0070] Specifically, the total number of battery cells in the battery pack is obtained as a first number, i.e., X, and the number of second acquisition boards is determined to be a second number, for example, the second number is Y, which represents Y acquisition boards; the ratio of the first number to the second number is calculated to obtain a third number X / Y, i.e., it is determined that the total number of acquisition channels contained in the target chip set on each second acquisition board is equal to the third number X / Y.

[0071] For example, the calculation method for selecting the target chip may include the following steps:

[0072] (1) Calculate the total number of battery pack cell strings. For example, the number of parallel strings of a battery pack with single and parallel cells b1 is a1, the number of parallel strings of a battery pack with single and parallel cells b2 is a2, and so on. The total number of battery pack cell strings is

[0073] (2) The number of acquisition channels of the existing AFE acquisition chip is obtained as follows:

[0074] (3) Determine the target chip combination and select the AFE chip combination as follows: c1 n1 channel chip + d1 n2 channel chip + e1 n3 channel chip + f1 n4 channel chip, etc., and ;

[0075] (4) According to the formula , Y is a positive integer;

[0076] Set up Y acquisition boards, each of which uses c1 n1 channel chips + d1 n2 channel chips + e1 n3 channel chips + f1 n4 channel chips...

[0077] It can be seen that the embodiment of the present application can flexibly adjust the configuration of the target chip and its acquisition channel on each acquisition board by calculating the total number of battery cells in the battery pack and determining the number of acquisition boards. This design enables the system to adapt to battery packs of different sizes and configurations, improving the scalability and adaptability of the system. By accurately calculating the type and number of target chips required on each acquisition board (such as C1 N1 channel chips, D1 N2 channel chips, etc.), it is possible to ensure the effective use of resources and avoid unnecessary waste. This refined management helps to reduce costs and improve the economy of the system.

[0078] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in the present application, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in FIG. 1 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0079] Figure 4 A schematic diagram of the structure of a battery pack information collection device provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the device may include:

[0080] Acquisition module 401: used to determine the total number of cells in the battery pack;

[0081] Determining module 402: used to determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel;

[0082] Combining module 403: used to determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips;

[0083] The acquisition module 404 is used to connect the acquisition channels on the at least one target chip to the battery cells respectively, and to acquire the battery cell information.

[0084] In one embodiment of the present application, the combination module 403 is also used to determine multiple target chips whose collection channel utilization rate connected to the battery pack is 100%, wherein the collection channel utilization rate of 100% indicates that the total number of collection channels connected to the battery cell is equal to the total number of collection channels on all target chips.

[0085] In one embodiment of the present application, the combination module 403 is also used to respectively obtain the number of information acquisition channels provided on each type of chip, wherein the number of information acquisition channels provided on different types of chips is different; and determine a combination of multiple target chips of the same type or a combination of multiple target chips of different types having the highest utilization rate of the acquisition channels connected to the battery pack.

[0086] In one embodiment of the present application, the acquisition module 401 is also used to obtain the number of battery modules connected in parallel in the battery pack, wherein each battery module includes a plurality of battery cells connected in series; obtain the number of battery cells connected in series in each battery module; and multiply the number of battery modules by the number of battery cells connected in series to determine the total number of battery cells in the battery pack.

[0087] In one embodiment of the present application, the acquisition module 404 is also used to determine at least one acquisition board according to the battery pack space; evenly arrange the target chip on the at least one acquisition board; and connect the acquisition channels of the target chip on the at least one acquisition board to the battery cells respectively.

[0088] In one embodiment of the present application, the acquisition module 404 is also used to set a first acquisition board, and evenly set all target chips on the first acquisition board; or, set multiple identical second acquisition boards, and evenly set all target chips on multiple second acquisition boards and set some target chips on each of the second acquisition boards.

[0089] In one embodiment of the present application, the acquisition module 404: is also used to obtain the total number of battery cells in the battery pack as a first number; determine the number of the second acquisition boards as a second number; calculate the ratio of the first number to the second number to obtain a third number; determine some target chips set on the second acquisition board, and the number of acquisition channels contained in the some target chips is equal to the third number.

[0090] According to the specific embodiments provided in this application, the technical solution provided in this application can have the following advantages:

[0091] Determine the total number of acquisition channels connected to the battery cells by the total number of battery cells, determine at least one target chip with the highest utilization rate of acquisition channels connected to the battery pack according to the total number of acquisition channels connected to the battery cells, and connect the acquisition channels on the target chip to each battery cell respectively, so as to improve the utilization rate of chip acquisition channels, save design space, and reduce costs;

[0092] By calculating the total number of battery cells in the battery pack and determining the number of acquisition boards, the configuration of the target chip and its acquisition channel on each acquisition board can be flexibly adjusted. This design enables the system to adapt to battery packs of different sizes and configurations, improving the scalability and adaptability of the system. By accurately calculating the type and number of target chips required on each acquisition board (such as C1 N1 channel chips, D1 N2 channel chips, etc.), it is possible to ensure the effective use of resources and avoid unnecessary waste. This refined management helps reduce costs and improve the economy of the system.

[0093] It is understood that the implementation of any method or product of the present application does not necessarily require all of the advantages described above to be achieved at the same time.

[0094] The same or similar parts between the above embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0095] It should be noted that the embodiments of the present application may involve the use of user data. In actual applications, user-specific personal data can be used in the scheme described in this article within the scope permitted by applicable laws and regulations, subject to the requirements of applicable laws and regulations of the country where the user is located (for example, explicit consent from the user, effective notification to the user, explicit authorization from the user, etc.).

[0096] According to an embodiment of the present application, the present application also provides a computer device and a computer-readable storage medium.

[0097] like Figure 5 , is a block diagram of a computer device according to an embodiment of the present application. The computer device is intended to represent various forms of digital computers or mobile devices. The digital computer may include a desktop computer, a portable computer, a workbench, a personal digital assistant, a server, a mainframe computer, and other suitable computers. The mobile device may include a tablet computer, a smart phone, a wearable device, etc.

[0098] like Figure 5 As shown, the device 500 includes a computing unit 501, a ROM 502, a RAM 503, a bus 504, and an input / output (I / O) interface 505. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other through the bus 504. The input / output (I / O) interface 505 is also connected to the bus 504.

[0099] The computing unit 501 may perform various processes in the method embodiments of the present application according to computer instructions stored in a read-only memory (ROM) 502 or computer instructions loaded from a storage unit 508 into a random access memory (RAM) 503. The computing unit 501 may be various general and / or special processing components with processing and computing capabilities. The computing unit 501 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. In some embodiments, the method provided in the embodiments of the present application may be implemented as a computer software program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 508.

[0100] RAM 503 may also store various programs and data required for the operation of device 500. Part or all of the computer program may be loaded and / or installed on device 500 via ROM 802 and / or communication unit 509.

[0101] The input unit 506, output unit 507, storage unit 508 and communication unit 509 in the device 500 can be connected to the I / O interface 505. The input unit 506 can be, for example, a keyboard, a mouse, a touch screen, a microphone, etc. The output unit 507 can be, for example, a display, a speaker, an indicator light, etc. The device 500 can exchange information, data, etc. with other devices through the communication unit 509.

[0102] It should be noted that the device may also include other components necessary for normal operation, or may only include components necessary for implementing the solution of the present application, rather than all the components shown in the figure.

[0103] Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations of them.

[0104] The computer instructions for implementing the method of the present application can be written in any combination of one or more programming languages. These computer instructions can be provided to the computing unit 501, so that when the computer instructions are executed by the computing unit 501 such as a processor, the steps involved in the method embodiment of the present application are executed.

[0105] The computer-readable storage medium provided in the present application may be a tangible medium that may contain or store computer instructions for executing the steps involved in the method embodiments of the present application. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, and other forms of storage media.

[0106] The above specific implementations do not constitute a limitation on the protection scope of this application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this application should be included in the protection scope of this application.

Claims

1. A battery pack information collection method, characterized in that: The method includes: Determine the total number of cells in the battery pack; Determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel; Determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips; The collection channels on the at least one target chip are connected to the battery cells respectively, and the battery cell information is collected.

2. The battery pack information collection method according to claim 1, characterized in that: The step of determining at least one target chip with the highest acquisition channel utilization rate connected to the battery pack comprises: At least one target chip connected to the battery pack with a collection channel utilization rate of 100% is determined, wherein the collection channel utilization rate of 100% indicates that the total number of collection channels connected to the battery cell is equal to the total number of collection channels on all target chips.

3. The battery pack information collection method according to claim 1 or 2, characterized in that: The step of determining at least one target chip with the highest acquisition channel utilization rate connected to the battery pack comprises: The number of information acquisition channels provided on each type of chip is obtained respectively, wherein the number of information acquisition channels provided on different types of chips is different; At least one target chip combination of the same type or multiple target chip combinations of different types having the highest utilization rate of the acquisition channels connected to the battery pack is determined.

4. The battery pack information collection method according to claim 1 or 2, characterized in that: Determining the total number of cells in the battery pack includes: Obtain the number of battery modules connected in parallel and / or in series in the battery pack, wherein each battery module includes a plurality of battery cells connected in series; Get the number of cells connected in series in each battery module; The total number of battery cells in the battery pack is determined by multiplying the number of battery modules by the number of battery cells connected in series.

5. The battery pack information collection method according to claim 1, characterized in that: The step of connecting the collection channels on the at least one target chip to the battery cells respectively includes: Determine at least one acquisition board according to the battery pack space; Evenly arranging the target chips on the at least one acquisition board; The acquisition channels of the target chip on the at least one acquisition board are connected to the battery cells respectively.

6. The battery pack information collection method according to claim 5, characterized in that: The target chips are evenly arranged on the at least one acquisition board, comprising: Provide a first acquisition board, and evenly arrange all target chips on the first acquisition board; or, A plurality of identical second acquisition boards are provided, all target chips are evenly arranged on the plurality of second acquisition boards, and part of the target chips are arranged on each of the second acquisition boards.

7. The battery pack information collection method according to claim 6, characterized in that: The method of setting a plurality of identical second acquisition boards and setting a part of the target chip on each of the second acquisition boards comprises: Obtaining the total number of cells in the battery pack as a first number; Determine that the number of the second acquisition boards is a second number; Calculating a ratio of the first quantity to the second quantity to obtain a third quantity; A part of the target chips provided on the second acquisition board is determined, wherein the number of acquisition channels contained in the part of the target chips is equal to the third number.

8. A battery pack information collection device, characterized in that: The device includes: Acquisition module: used to determine the total number of cells in the battery pack; A determination module: used to determine the total number of collection channels connected to the battery cells according to the total number of battery cells, wherein each battery cell is connected to a corresponding collection channel; Combination module: used to determine at least one target chip with the highest acquisition channel utilization rate connected to the battery pack, wherein each target chip has multiple acquisition channels, and the acquisition channel utilization rate represents the ratio of the total number of acquisition channels connected to the battery cell to the total number of acquisition channels on all target chips; Acquisition module: used to connect the acquisition channels on the at least one target chip to the battery cells respectively and collect battery cell information.

9. A computer device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores computer instructions that can be executed by the at least one processor, and the computer instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that: The computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 7.

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