Method and device for ISA simulation

Abstract

The invention relates to a method and device for ISA simulation. The method comprises the following steps of: detecting illegal instruction abnormity triggered by an illegal instruction in a user mode of a CPU (Central Processing Unit); in response to the illegal instruction exception, calling a user mode illegal instruction exception handling program configured in the first CSR; in response to operation of the exception handling program, acquiring runtime data associated with the thread from the second CSR and acquiring an instruction address of an illegal instruction from the third CSR; based on the acquired runtime data and the instruction address of the illegal instruction, performing ISA simulation on one or more instructions in a user mode; and in a case where the ISA emulation of the one or more instructions has been completed, restoring from the exception handler to a normal instruction execution stream of the application in response to execution of the first instruction.

Description

Technical Field

[0001] The present disclosure relates to the field of computers, and more particularly, to a method and apparatus for instruction set architecture (ISA) simulation. Background Art

[0002] Binary Translation (BT) is a technology that directly translates executable binary programs. It can translate binary programs on one processor to execute on another processor, making it easy to port binary programs between different processors, thereby expanding the applicability of hardware and software.

[0003] Existing ISA emulation solutions use BT technology to emulate unsupported instructions when an illegal instruction exception is triggered. In existing solutions, each exception handling involves at least two context switches between the kernel and user space, which introduces huge context switching overhead and has a great impact on BT performance. Summary of the invention

[0004] According to an embodiment of the present disclosure, a method for ISA emulation is provided, comprising: detecting an illegal instruction exception triggered by an illegal instruction in a user mode of a CPU; in response to detecting the illegal instruction exception, calling a user mode illegal instruction exception handler configured in a first control status register (CSR); in response to the execution of the user mode illegal instruction exception handler, acquiring runtime data associated with a thread including the illegal instruction from a second CSR and acquiring an instruction address of the illegal instruction from a third CSR; based on the acquired runtime data and the instruction address of the illegal instruction, performing ISA emulation in user mode on one or more instructions associated with the thread including the illegal instruction; and in response to the execution of a first instruction, restoring from the user mode illegal instruction exception handler to a normal instruction execution flow of an application program when the ISA emulation of the one or more instructions has been completed.

[0005] According to an embodiment of the present disclosure, a device for ISA simulation is provided, wherein the device includes a processor circuit, and the processor circuit is configured to execute the above method for ISA simulation.

[0006] According to an embodiment of the present disclosure, a computer-readable storage medium is provided, on which instructions are stored, wherein when the instructions are executed by a processor, the processor executes the above-mentioned method for ISA simulation.

[0007] According to an embodiment of the present disclosure, a computer program product is provided, comprising instructions, wherein when the instructions are executed by a processor, the processor performs the above-mentioned method for ISA emulation.

[0008] The present disclosure constructs an optimized user space exception handling mechanism by introducing new CSR support and new instructions. With this exception handling mechanism, the corresponding hardware logic can directly perform BT context switching, thereby eliminating the overhead of context switching between the kernel and the user space in the previous solution, and improving the performance of the processor when processing BT tasks. The mechanism can achieve application-agnostic and low-overhead ISA conversion, provide backward software compatibility for handling obsolete and outdated instructions, and provide forward software compatibility for supporting new user mode instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present disclosure will be described by way of example and not limitation with reference to the figures of the accompanying drawings in which like reference numerals refer to like elements and in which: Figure 1 Illustrated is a block diagram of an example processor and / or SoC 100 that may have one or more cores and with an integrated memory controller.

[0010] Figure 2 A flowchart of a method for ISA simulation according to an embodiment of the present disclosure is shown.

[0011] Figure 3 An example configuration of a utvec CSR according to an embodiment of the present disclosure is shown.

[0012] Figure 4 An example configuration of a UEBP CSR according to an embodiment of the present disclosure is shown.

[0013] Figure 5 An example configuration of a uepc CSR according to an embodiment of the present disclosure is shown.

[0014] Figure 6 A schematic diagram of a workflow for illegal instruction exception handling according to an embodiment of the present disclosure is shown.

[0015] Figure 7 A schematic diagram of a per-vCPU context stack and software-emulated registers according to an embodiment of the present disclosure is shown.

[0016] Figure 8 A schematic diagram of the initialization process of UEBP CSR according to an embodiment of the present disclosure is shown.

[0017] Fig. 9A flowchart of BT context switching in ISA emulation according to an embodiment of the present disclosure is shown.

[0018] Fig.10 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (eg, a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. DETAILED DESCRIPTION

[0019] The features and exemplary embodiments of various aspects of the application will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the application. However, it is obvious to those skilled in the art that the application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the application by illustrating the example of the application. The application is by no means limited to any specific configuration proposed below, but covers any modification, replacement and improvement of elements, parts and algorithms without departing from the spirit of the application. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid causing unnecessary ambiguity to the application.

[0020] Furthermore, various operations will be described as multiple discrete operations in a manner that is most helpful for understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations do not need to be performed in the order presented.

[0021] The phrases "in an embodiment," "in one embodiment," and "in some embodiments" are used repeatedly herein. The phrase generally does not refer to the same embodiment; however, it may. The terms "comprising," "having," and "including" are synonymous unless the context dictates otherwise. The phrases "A or B" and "A / B" mean "(A), (B) or (A and B)."

[0022] Figure 1 A block diagram of an example processor and / or SoC 100 is illustrated, which may have one or more cores and have an integrated memory controller. The processor 100 illustrated by the solid line box has a single core 102(A), a system agent unit circuit 110, and a set of one or more interface controller unit circuits 116, while the optionally added dashed line box illustrates an alternative processor 100 as having multiple cores 102(A)-(N), a set of one or more integrated memory control unit circuits 114 in the system agent unit circuit 110, dedicated logic 108, and a set of one or more interface controller unit circuits 116.

[0023] Different implementations of processor 100 may include: 1) a CPU, where dedicated logic 108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 102 (A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, where cores 102 (A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 102 (A)-(N) are a large number of general-purpose in-order cores. Thus, processor 100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-in-one (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. Processor 100 may be part of and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0024] The memory hierarchy includes one or more levels of cache unit circuits 104(A)-(N) within the cores 102(A)-(N), a set of one or more shared cache unit circuits 106, and external memory (not shown) coupled to the set of integrated memory controller unit circuits 114. The set of one or more shared cache unit circuits 106 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as last level cache (LLC), and / or combinations thereof. While in some examples an interface network circuit 112 (e.g., a ring interconnect) provides an interface to the dedicated logic 108 (e.g., integrated graphics logic), the set of shared cache unit circuits 106, and the system agent unit circuit 110, alternative examples use any number of well-known techniques to provide interfaces to these units. In some examples, coherency is maintained between one or more circuits in the shared cache unit circuits 106 and the cores 102(A)-(N). In some examples, interface controller unit circuitry 116 couples the cores to one or more other devices 118 , such as one or more I / O devices, storage, one or more communication devices (eg, wireless network, wired network, etc.), and the like.

[0025] In some examples, one or more of the cores 102(A)-(N) have multi-threading capabilities. The system agent unit circuit 110 includes those components that coordinate and operate the cores 102(A)-(N). The system agent unit circuit 110 may include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU may be (or may include) logic and components required to adjust the power state of the cores 102(A)-(N) and / or the dedicated logic 108 (e.g., integrated graphics logic). The display unit circuit is used to drive one or more externally connected displays.

[0026] The cores 102(A)-(N) may be homogeneous with respect to instruction set architecture (ISA). Alternatively, the cores 102(A)-(N) may be heterogeneous with respect to ISA; that is, a subset of the cores 102(A)-(N) may be capable of executing one ISA, while other cores may be capable of executing only a subset of the ISA or may be capable of executing another ISA. In one embodiment, the processor cores 102(A)-(N) may employ, in whole or in part, a fifth generation reduced instruction set computer (RISC-V) instruction set architecture. In another embodiment, the processor cores 102(A)-(N) may employ various other instruction set architectures, such as x86, ARM, MIPS, etc.

[0027] The high customizability of RISC-V and the rapid evolution of its ISA extensions have led to the problem of ISA fragmentation in the RISC-V chip ecosystem, which ultimately leads to huge software compatibility challenges. Software applications that run well on a chip from one vendor are likely to fail with illegal instruction exceptions on another vendor's chip due to lack of support for certain ISA extensions. In addition, for heterogeneous ISA architectures (for example, the Sophgo platform with small cores that support vector ISA and large cores that do not support vectors), binary translation (BT) technology is needed to migrate threads between large and small core architectures.

[0028] The existing solution is to use BT technology to emulate unsupported instructions when an illegal instruction exception is triggered. In the existing solution, each exception handling involves at least two context switches between the kernel and the user space, which introduces a huge context switch overhead and has a great impact on the performance of BT.

[0029] In view of this, the present disclosure constructs an optimized user space exception handling mechanism by introducing support for new control status registers (CSRs) and new instructions. With this exception handling mechanism, the corresponding hardware logic can directly perform BT context switching, thereby eliminating the overhead of context switching between the kernel and user space in previous solutions, and improving the performance of the processor when processing BT tasks. This mechanism can achieve application-agnostic and low-overhead ISA conversion, provide backward software compatibility for handling obsolete and outdated instructions, and provide forward software compatibility for supporting new user mode (U-mode) instructions.

[0030] The following discusses the user space exception handling mechanism disclosed in the present application by taking three CSRs and a new instruction as examples, but it should be understood that the function of each CSR or each instruction disclosed in the present application can be implemented by using more CSRs or more instructions, and the present disclosure does not limit the specific number of CSRs and instructions. On the contrary, the present invention is intended to cover all possible changes and modifications as long as they fall within the technical scope claimed by the present invention.

[0031] Figure 2 A flow chart of a method for ISA simulation according to an embodiment of the present disclosure is shown. In one embodiment, method 200 may be performed by a RISC-V processor. In another embodiment, method 200 may be performed by a processor based on any other instruction set architecture, such as x86, ARM, MIPS, etc. Method 200 may include steps S202, S204, S206, S208, and S210. However, in some embodiments, method 200 may include more or less different steps, which is not limited by the present disclosure.

[0032] In step S202, an illegal instruction exception triggered by an illegal instruction is detected in the user mode of the CPU; In step S204, in response to detecting an illegal instruction exception, calling a user mode illegal instruction exception handler configured in the first CSR; At step S206, in response to the execution of the user mode illegal instruction exception handler, the runtime data associated with the thread including the illegal instruction is obtained from the second CSR and the instruction address of the illegal instruction is obtained from the third CSR; At step S208, based on the acquired runtime data and the instruction address of the illegal instruction, ISA emulation is performed in user mode on one or more instructions associated with the thread including the illegal instruction; and At step S210 , when ISA emulation of one or more instructions has been completed, a normal instruction execution flow of the application is restored from the user mode illegal instruction exception handler in response to execution of a first instruction.

[0033] In an embodiment of the present disclosure, the user mode of the CPU may include a user trap mode, and the user mode illegal instruction exception handler may run in the user trap mode. In one embodiment, if an illegal instruction is detected in the user trap mode, an illegal instruction exception is triggered to the corresponding privileged mode.

[0034] In an embodiment of the present disclosure, the first CSR is a user-mode trap vector (utvec) CSR, which is configured to delegate an illegal instruction exception detected in the user mode to a user-mode illegal instruction exception handler configured in the utvec CSR.

[0035] In an embodiment of the present disclosure, a user mode illegal instruction exception handler can be registered in the utvec CSR using a programming interface (API) of the kernel of the operating system. When an undefined or illegal instruction is detected and an exception is triggered, the CPU can directly call the exception handler of the BT module in the user space to perform ISA emulation. When the ISA emulation is completed, the exception handler restores the register state of the CPU from the runtime data of the BT and executes the first instruction to restore the next instruction to be processed in the application execution flow stored in the third CSR.

[0036] In an embodiment of the present disclosure, the utvec CSR is used to store an entry pointer to a user-mode illegal instruction exception handler. In one embodiment, the utvec CSR is accessible only in a privileged mode, for example, only in a supervisor mode (S-mode).

[0037] Figure 3 An example configuration of the utvec CSR according to an embodiment of the present disclosure is shown. Figure 3 As shown, the utvec CSR can be a read / write register with a user-mode extended length (UXLEN) bit width, which includes a vector base address (BASE) field and a vector mode (MODE) field, wherein the BASE field can be used to store a user-mode address associated with a user-mode illegal instruction exception handler, and the MODE field can be used to indicate whether the illegal instruction exception delegation function is enabled.

[0038] In one embodiment, the BASE field of the utvec CSR is used to store an entry pointer to the entry point of the user-mode illegal instruction exception handler. In one embodiment, the BASE field is a WARL (Write Any Read Legal) field, for example, including UXLEN-2 bits. In one embodiment, the user-mode address stored in BASE must meet the following alignment constraints: the address must be aligned to 4 bytes, that is, the lowest 2 bits are both 0.

[0039] In one embodiment, the MODE field of the utvec CSR may include 2 bits. Table 1 shows the encoding format of the MODE field.

[0040] Table 1

[0041] As shown in Table 1, when MODE = 0, the illegal instruction exception delegation function is disabled. When MODE = 1, if an illegal instruction exception occurs and the current operating mode is user mode, the CPU sets the PC register to the address stored in the BASE field.

[0042] In an embodiment of the present disclosure, the second CSR is a user mode exception base data pointer (UEBP) CSR, which is configured to store the storage address of per-thread runtime data for the user mode exception handler. In one embodiment, the UEBP CSR is accessible in both user mode and privileged mode. In one embodiment, the UEBP CSR is accessible only in user trap mode and privileged mode.

[0043] In an embodiment of the present disclosure, when the emulator finds that the uebp CSR is not initialized, a dedicated vCPU can be allocated to the current application thread and the vCPU context can be kept active throughout the process life cycle. When context switching is performed between the application and the emulator, the vCPU registers and the physical CPU registers can be synchronized to ensure that the application can jump in / out of its code block without restriction.

[0044] Figure 4 An example configuration of the UEBP CSR according to an embodiment of the present disclosure is shown. Figure 4 As shown, the uebp CSR may have a UXLEN bit width. In an embodiment of the present disclosure, the uebp CSR may be used to store a pointer to runtime data of a user ISA emulator that tracks the CPU registers of the corresponding software emulation. In one embodiment, the uebp CSR has a default value after being reset, and all bits of the default value are set to 1.

[0045] In an embodiment of the present disclosure, the third CSR is a user exception program counter (UEPC) CSR, which is used to save the address of the illegal instruction that triggers the exception when an illegal instruction exception is triggered, and after the exception handling is completed, for example, by saving the address of the to-be-processed instruction after the simulated one or more instructions in the corresponding thread in the uepc CSR to restore the program counter (PC) register, thereby ensuring that the processor can continue to execute the instructions of the corresponding thread from the correct position after the exception handling is completed.

[0046] In one embodiment, uepc CSR is accessible in both user mode and privileged mode. In one embodiment, uepc CSR is accessible only in user trap mode and privileged mode.

[0047] Figure 5 An example configuration of the uepc CSR according to an embodiment of the present disclosure is shown. Figure 5 As shown, the uepc CSR may have a UXLEN bit width. In one embodiment, the uepc CSR is a WARL register that may be used to store all valid user mode addresses. Specifically, when an illegal instruction exception occurs in user mode, the uepc CSR is written to the address of the illegal instruction that caused the exception, and when the illegal instruction simulation is completed, the uepc CSR is written to the address of the next instruction to be processed in the corresponding thread. Except for the case where it is automatically written when handling an exception, the uepc CSR is generally not directly written by the processor's hardware implementation, although software may explicitly write to the uepc CSR through specific instructions.

[0048] In an embodiment of the present disclosure, the first instruction is a user mode trap return (uret) instruction. In one embodiment, the uret instruction can be used to return the CPU from the user trap mode to the normal user mode. In one embodiment, the uret instruction is used to set the PC register to the instruction address stored in the uepc CSR (i.e., the address of the next instruction to be processed in the thread) after the simulation ends, so that when the user mode illegal instruction exception handler completes its task, the processor can return to the normal execution flow of the corresponding thread by executing the uret instruction. By using the uret instruction to directly set the value of the PC register, additional context switching overhead is avoided.

[0049] In one embodiment, the uret instruction can only be executed in user trap mode, and no privilege level or stack change occurs during execution. In one embodiment, if the uret instruction is detected in a privileged mode (such as kernel mode or supervisor mode) or in normal user mode (non-trap mode), an illegal instruction exception is triggered to the corresponding privileged mode.

[0050] Figure 6 FIG. 1 is a schematic diagram showing a workflow for handling illegal instruction exceptions according to an embodiment of the present disclosure. Figure 6As shown, the exception management of user mode and ISA emulation are divided into two parts running in different CPU modes. The user mode illegal instruction exception handler is managed by utvec CSR, which can only be accessed in privileged mode (e.g., supervisory mode s-mode). When utvec CSR is correctly configured, the illegal instruction exception in the user space will be captured and redirected to the ISA emulation part running in user mode. The ISA emulator can, for example, only run in user mode to avoid the simulated application code from illegally accessing the system memory or the memory of other processes. The ISA emulator uses uebp CSR and uepc CSR to obtain the previously saved BT runtime data and the instructions to be simulated, respectively. When the ISA emulation is completed, the exception handler will restore the CPU registers from the BT runtime data and execute the uret instruction to restore the next instruction to be processed in the application execution flow stored in uepcCSR. In an embodiment of the present disclosure, the exception handler of the emulator can be mapped to the same process address space as the application process, that is, the emulator and the application can share the memory address space, just like loading a dynamic library, so that the emulator can seamlessly access the runtime context of the application (e.g., runtime stack, memory space and CPU registers). When the thread scheduler of the operating system kernel performs thread switching, it saves the data in the current utvec CSR, uebp CSR, and uepc CSR to the CPU context of the thread management metadata corresponding to the current thread in the kernel, and loads the corresponding data from the CPU context of the thread management metadata of the next thread to be run into utvec CSR, uebp CSR, and uepc CSR, thereby completing the relevant thread context switching.

[0051] In an embodiment of the present disclosure, when switching the CPU context to enter / exit a user mode illegal instruction exception handler, a per-virtual CPU (vCPU) context stack (emu_stack) can be used to save / restore the values ​​of the physical CPU registers, and the context stack can also be used to store the runtime function stack of the ISA emulator itself. Figure 7 FIG. 4 shows a schematic diagram of a per-vCPU context stack and software-emulated registers according to an embodiment of the present disclosure. Figure 7As shown, the user space ISA emulator emulates all registers (X0-Xn) that need to be supported, and maintains a runtime data area (vmarea0-vmareaX) for each vCPU (vCPU0-vCPUx), which saves the register values ​​of these software emulations throughout the life cycle of the process. When entering or exiting the emulation code, the corresponding runtime data can be restored from the uebp CSR / the pointer to the corresponding runtime data can be saved to the uebp CSR.

[0052] In an embodiment of the present disclosure, the runtime data associated with the corresponding thread can be obtained from the uebp CSR to first determine the initialization of the uebp CSR. When the uebp CSR is not initialized, a per-vCPU runtime data area can be allocated for the current application thread to initialize the runtime environment of each vCPU. When the initialization of the uebp CSR is completed, the uebp CSR is set to a pointer to the per-virtual CPU runtime data area associated with the current thread.

[0053] Figure 8 A schematic diagram of the initialization process of UEBP CSR according to an embodiment of the present disclosure is shown. Figure 8 As shown, the initialization process of UEBP CSR may include the following steps: At step 810, it is determined whether the uebp CSR has been initialized; At step 820, if the uebp CSR is not initialized, a per-vCPU runtime data area associated with the current thread of the application is allocated to initialize the per-vCPU runtime environment (e.g., stack and vCPU state); At step 830, after initialization is complete, the uebp CSR is set to a pointer to the per-virtual CPU runtime data; At step 840, based on the pointer stored in the uebp CSR, the stack is switched to the emu_stack in the corresponding runtime data, that is, the physical stack pointer register (SP) of the CPU is set to the stack top address of emu_stack; if it is determined at 810 that the uebp CSR has been initialized, steps 820 and 830 are skipped and the process proceeds directly to step 840; In step 850, ISA emulation is performed using the corresponding runtime data. When the ISA emulation ends, the emulator may execute a uret instruction to return to the normal instruction execution flow of the application program.

[0054] In an embodiment of the present disclosure, ISA emulation of one or more instructions associated with the thread where the illegal instruction is located, including the illegal instruction, in user mode based on the acquired runtime data and the instruction address of the illegal instruction may also include: saving the data in the physical hardware register of the CPU associated with the thread to the virtual register of the vCPU; and setting the value of the virtual program counter (vPC) register of the vCPU to the instruction address of the illegal instruction stored in the uepc CSR. In an embodiment of the present disclosure, when the ISA emulation of one or more instructions has been completed, the data of the vCPU virtual register associated with the thread where the illegal instruction is located may be saved to the physical hardware register of the CPU, and the value of the vPC register of the vCPU may be saved to the uepc CSR.

[0055] Fig. 9 FIG. 4 is a flow chart showing a BT context switch in ISA simulation according to an embodiment of the present disclosure. Fig. 9 As shown, when it is detected in user mode that the instruction executed by the application is an illegal instruction, an illegal instruction exception will be triggered, and the emulator is configured to execute the user mode illegal instruction exception handler specified by the utvec CSR in response to the illegal instruction exception, and perform the following operations: At step 910, the runtime data of the vCPU is obtained through the pointer stored in the uebp CSR; At step 920, the value of the physical hardware register of the CPU is saved to the virtual register of the vCPU; At step 930, the value stored in the uepc CSR (i.e., the instruction address of the illegal instruction) is written into the vPC register of the vCPU; At step 940, ISA emulation is performed on one or more instructions including illegal instructions according to the BT policy; At step 950, after the ISA emulation is completed, the value of the virtual register of the vCPU is saved to the physical hardware register of the CPU; At step 960, the uepc CSR is updated using the value of the vPC register of the vCPU (i.e., the address of the next instruction to be executed in the simulation environment); At step 970, the uret instruction is executed to set the PC to the value of the uepc CSR, thereby restoring the application execution flow before the emulation.

[0056] In the embodiments of the present disclosure, all existing dynamic binary emulation (DBT) technologies can be applied to the user space ISA emulator to reduce repeated instruction emulation and share the overall BT context switching overhead, such as hot code identification, adjustable emulation block size, emulation code cache, etc.

[0057] The present disclosure provides a hardware / software co-design, which aims to eliminate the binary emulation context switching overhead between user space and kernel space in the ISA emulation solution. Compared with the Soft-ISA emulation solution implemented purely by software in the prior art, the performance analysis data measured by the performance benchmark test shows that: in the worst case of Soft-ISA performance, that is, each instruction triggers an illegal instruction processing, the kernel-user space BT switch accounts for 75% of the context switching overhead, while the performance will be improved by nearly 4 times by using the solution of the present disclosure; according to the benchmark test results, when the step size is 8 (that is, the BT module simulates 8 instructions at a time), the performance improvement of BT is expected to reach 15% by using the solution of the present disclosure.

[0058] The newly configured utvec CSR, uebp CSR and uepc CSR and uret instruction of the present disclosure together constitute an optimized user space exception handling mechanism, and the corresponding hardware logic can directly perform BT context switching, thereby eliminating the overhead of context switching between the kernel and the user space in the existing solution, and improving the performance of the processor when processing BT tasks. The mechanism can realize application-agnostic and low-overhead ISA conversion, provide backward software compatibility for handling obsolete and outdated instructions, and provide forward software compatibility for supporting new user mode instructions.

[0059] Fig.10 is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Specifically, Fig.10 A schematic diagram of hardware resources 1000 is shown, which includes one or more processors (or processor cores) 1010, one or more memory / storage devices 1020, and one or more communication resources 1030, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via a bus 1040 or other interface circuits. For embodiments utilizing node virtualization (e.g., network function virtualization (NFV)), a hypervisor 1002 can be executed to provide an execution environment for one or more network slices / sub-slices to utilize hardware resources 1000.

[0060] Processor 1010 may include, for example, processor 1012 and processor 1014. Processor 1010 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0061] The memory / storage device 1020 may include a main memory, a disk storage device, or any suitable combination thereof. The memory / storage device 920 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0062] The communication resources 1030 may include interconnect or network interface controllers, components, or other suitable devices to communicate with one or more peripheral devices 1004 or one or more databases 1006 or other network elements via the network 1008. For example, the communication resources 1030 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® low energy) components, Wi-Fi® components, and other communication components.

[0063] The instructions 1050 may include software, a program, an application, an applet, an application, or other executable code for causing at least any one of the processors 1010 to perform any one or more of the methods discussed herein. The instructions 1050 may reside in whole or in part in at least one of the processor 1010 (e.g., in a cache of the processor), the memory / storage device 1020, or any suitable combination thereof. In addition, any portion of the instructions 1050 may be transmitted to the hardware resource 1000 from any combination of the peripheral device 1004 or the database 1006. Therefore, the memory of the processor 1010, the memory / storage device 1020, the peripheral device 1004, and the database 1006 are examples of computer-readable and machine-readable media.

[0064] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium to store logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and the like. In some examples, logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, APIs, instruction sets, computing codes, computer codes, code segments, computer code segments, words, values, symbols, or any combination of these.

[0065] According to some examples, a computer-readable medium may include a non-transitory storage medium to store or maintain instructions that, when executed by a machine, a computing device, or a system, cause the machine, the computing device, or the system to perform methods and / or operations according to the described examples. The instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, a computing device, or a system to perform a specific function. The instructions may be implemented using any appropriate high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0066] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium representing various logic within the processor, which when read by a machine, computing device or system causes the machine, computing device or system to fabricate logic to perform the techniques described herein. Such representations, known as "IP cores", may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to load into fabrication machines that actually fabricate the logic or processor.

[0067] The appearance of the phrase "an example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with respect to the same figure or element. The division, omission or inclusion of block functions depicted in the figures does not infer that the hardware components, circuits, software and / or elements used to implement these functions will necessarily be divided, omitted or included in the embodiments.

[0068] Some examples may be described using the expressions "coupled" and "connected," and their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also refer to two or more elements that are not in direct contact with each other, but still cooperate or interact with each other.

[0069] The terms "first", "second" and the like do not represent any order, quantity or importance in this article, but are used to distinguish one element from another element. The term "one" herein does not represent a limitation on quantity, but rather represents the presence of at least one item mentioned. The term "assertion" used when referring to a signal herein refers to a state of the signal, in which the signal is valid, and the state can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal. The term "subsequently" or "afterwards" may refer to immediately following or following some or some other event. According to alternative embodiments, other step sequences may also be performed. In addition, depending on the specific application, additional steps may be added or removed. Any combination of variations may be used, and those of ordinary skill in the art who benefit from the present disclosure will understand its many variations, modifications and alternative embodiments.

[0070] Unless specifically stated otherwise, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood within the context to be generally used to state that an item, term, etc. can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended to, and should not, imply that certain embodiments require the presence of each of at least one X, at least one Y, or at least one Z. Furthermore, unless specifically stated otherwise, conjunctive language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z."

Claims

1. A method for ISA simulation, comprising: Detect illegal instruction exceptions triggered by illegal instructions in the user mode of the CPU; In response to detecting the illegal instruction exception, calling a user mode illegal instruction exception handler configured in a first control status register CSR; In response to the execution of the user mode illegal instruction exception handler, obtaining runtime data associated with the thread including the illegal instruction from a second CSR and obtaining an instruction address of the illegal instruction from a third CSR; Based on the acquired runtime data and the instruction address of the illegal instruction, perform ISA emulation in user mode on one or more instructions associated with the thread including the illegal instruction; as well as In a case where ISA emulation of the one or more instructions has been completed, normal instruction execution flow of the application is restored from the user mode illegal instruction exception handler in response to execution of the first instruction.

2. The method according to claim 1, wherein: The first CSR is used to store an entry pointer pointing to an entry point of the user mode illegal instruction exception handler.

3. The method according to claim 1, wherein: In the case where ISA emulation of the one or more instructions has been completed, resuming normal instruction execution flow of the application from the user mode illegal instruction exception handler in response to execution of the first instruction comprises: updating the value of the third CSR to the instruction address of the next instruction to be processed after the one or more instructions; and In response to execution of the first instruction, the value of the program counter is set to the updated value in the third CSR.

4. The method according to any one of claims 1 to 3, wherein: In response to execution of the user mode illegal instruction exception handler, obtaining runtime data associated with the thread including the illegal instruction from the second CSR, including: determining whether the second CSR is initialized; In response to the second CSR being uninitialized, allocating a per-vCPU runtime data area associated with the thread to initialize a per-vCPU runtime environment; and In response to initialization of the second CSR being completed, the second CSR is set to a pointer to a per-virtual-CPU runtime data area associated with the thread.

5. The method according to any one of claims 1 to 3, wherein: Performing ISA emulation on one or more instructions associated with the thread including the illegal instruction in user mode based on the acquired runtime data and the instruction address of the illegal instruction includes: Saving data in a physical hardware register of a CPU associated with the thread to a virtual register of a vCPU; Set the physical stack pointer register of the CPU to the dedicated stack address in the acquired runtime data area; Setting the value of the virtual program counter register of the vCPU to the instruction address of the illegal instruction stored in the third CSR; and The user mode ISA emulator emulates execution of one or more instructions associated with the thread, including the illegal instruction, based on the vCPU virtual register data.

6. The method according to claim 5, further comprising: When ISA emulation of the one or more instructions is completed, saving data of the vCPU virtual register associated with the thread to a physical hardware register of the CPU; and The value of the virtual program counter register of the vCPU is saved to the third CSR.

7. The method according to any one of claims 1 to 3, further comprising: The user mode illegal instruction exception handler is registered in the first CSR by using the programming interface of the kernel of the operating system.

8. The method according to any one of claims 1 to 3, wherein: The first CSR is accessible only in privileged mode.

9. The method according to any one of claims 1 to 3, wherein: The second and third CSRs are accessible in both user mode and privileged mode.

10. The method according to any one of claims 1 to 3, wherein: The second and third CSRs are accessible only in user trap mode and privileged mode.

11. The method according to any one of claims 1 to 3, wherein: The first CSR includes a vector base address field and a vector mode field, wherein the vector base address field is used to store a user mode address associated with the user mode illegal instruction exception handler, and the mode field is used to indicate whether an illegal instruction exception delegation function is enabled.

12. The method according to claim 11, further comprising: In response to the mode field in the first CSR indicating that the illegal instruction exception delegation function is enabled, when the illegal instruction exception is detected and the current operating mode is user mode, the program counter register is set to the address in the vector base address field.

13. The method according to any one of claims 1 to 3, wherein: The user mode of the CPU includes a user trap mode, and the user mode illegal instruction exception handler runs in the user trap mode.

14. The method according to claim 13, wherein if an illegal instruction is detected in the user trap mode, an illegal instruction exception is triggered to the corresponding privileged mode.

15. The method according to any one of claims 1 to 3, wherein: The ISA emulation is RISC-VISA emulation, x86ISA emulation, ARMISA emulation or MIPSISA emulation.

16. A device for ISA simulation, wherein: The apparatus comprises a processor circuit configured to perform the method of any one of claims 1-15.

17. A computer-readable storage medium having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-15.

18. A computer program product comprising instructions, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 15.

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