Power chip computing power resource scheduling method, system, equipment and medium

Abstract

The invention relates to the technical field of intelligent power grids, in particular to a power chip computing power resource scheduling method, system and device and a medium, and the method comprises the steps: obtaining original computing power resource data needed by a power chip to execute a computing task from a power system in real time, and preprocessing the original computing power resource data to obtain to-be-processed computing power resource data; according to the to-be-processed computing power resource data, obtaining the total load capacity of service computing data; in response to the chip computing power distribution instruction, determining a fitness function according to the total load of service computing data, and obtaining an optimal computing power resource scheduling strategy by using a firefly algorithm according to the fitness function; and dynamically scheduling the computing power resources on the power chip according to the optimal computing power resource scheduling strategy, and allocating the computing power resources to different computing tasks. According to the method, the calculation power resource of the power chip is optimized and dispatched by adopting the firefly algorithm, so that the resource utilization rate is improved, and the adaptability and reliability of the power chip in a complex power grid environment are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of smart grid technology, and in particular to a method, system, device and medium for scheduling computing power resources of power chips. Background Art

[0002] In the process of modernization of the power system, smart grid, as a core component of the new power system, is facing unprecedented challenges. With the continuous increase in the proportion of renewable energy and the widespread access to distributed energy systems, the complexity and dynamics of the power grid have increased significantly. This change not only requires smart grids to be able to process massive amounts of power grid data in real time, but also requires accurate prediction and analysis capabilities to ensure the stability and reliability of power grid operation. However, existing smart grids are often limited by computing power bottlenecks when dealing with these complex tasks, and it is difficult to meet the needs of efficient and real-time data processing.

[0003] Especially in the context of the continuous expansion of the scale and increasing complexity of the power grid, the amount of data that needs to be processed has increased dramatically, which has put forward higher requirements on the computing power of the smart grid. The traditional computing architecture is not only inefficient but also consumes a lot of energy when processing such a large amount of data. It cannot meet the real-time and high efficiency requirements of the smart grid, which seriously restricts the development of the smart grid. Therefore, how to improve the energy efficiency of the power system has become a key issue that needs to be solved urgently. However, most of the existing computing power configuration methods are based on a fixed computing architecture, which is difficult to flexibly adjust according to the actual grid data processing needs. This method not only fails to make full use of computing power resources, but also leads to waste of energy. Especially when faced with grid data with strong random volatility and high real-time requirements, traditional computing power configuration methods often perform poorly.

[0004] In summary, the existing computing power configuration methods have obvious limitations in the field of smart grids and cannot meet the needs of new power systems for efficient, real-time and reliable data processing. Therefore, there is an urgent need for an adaptive computing power configuration method that can flexibly respond to dynamic changes in power grid data and automatically optimize the configuration of computing power resources, improve the computing energy efficiency of smart grids, and ensure the stable operation of the power grid. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a method, system, device and medium for scheduling power chip computing resources.

[0006] In a first aspect, the present invention provides a method for scheduling power chip computing resources, the method comprising the following steps:

[0007] Acquire the original computing power resource data required for the power chip to perform computing tasks in real time from the power system, and pre-process the original computing power resource data to obtain the computing power resource data to be processed;

[0008] Cache the computing power resource data to be processed in an on-chip cache area, and obtain the total load of business computing data according to the computing power resource data to be processed;

[0009] In response to the chip computing power allocation instruction, a fitness function is determined according to the total load of the business computing data, and according to the fitness function, an optimal computing power resource scheduling strategy is obtained by using a firefly algorithm based on an elite retention strategy;

[0010] The computing resources on the power chip are dynamically scheduled according to the optimal computing resource scheduling strategy, and the computing resources are allocated to different computing tasks.

[0011] In a further implementation scheme, the step of preprocessing the original computing power resource data to obtain the computing power resource data to be processed includes:

[0012] The original computing power resource data is divided into a plurality of computing power resource slice data according to the timestamp, and the maximum and minimum values ​​of each computing power resource slice data are counted;

[0013] According to the maximum and minimum values ​​of each computing resource shard data, each computing resource shard data is normalized to obtain normalized resource shard data;

[0014] Anomaly detection is performed on the normalized resource shard data, and the normalized resource shard data after anomaly detection is integrated to form computing power resource data to be processed.

[0015] In a further embodiment, the step of determining the fitness function according to the total load of the business calculation data includes:

[0016] Dividing the total load of the business calculation data into several equal parts to obtain the business data load split amount;

[0017] According to the business data load segmentation amount and the bus bandwidth capacity, the task data upload delay and the execution result return delay of each computing task to be executed are obtained;

[0018] Obtaining a total processing delay according to the task data upload delay and the execution result return delay, and obtaining a normalized time resource factor according to the total processing delay;

[0019] Obtain a total power consumption requirement based on the task calculation power consumption requirement and the GPU basic power consumption, and obtain a normalized calculation energy consumption factor based on the total power consumption requirement;

[0020] The normalized time resource factor and the normalized computing energy consumption factor are weighted by using the hierarchical analysis method to obtain a fitness function.

[0021] In a further embodiment, the step of obtaining the total processing delay according to the task data upload delay and the execution result return delay comprises:

[0022] Determine the load throughput according to the total load of the business computing data, and obtain the actual active time of the GPU according to the ratio between the load throughput and the business data load segmentation amount;

[0023] Calculate the task execution delay time required for each to-be-executed computing task to be executed on different graphics processing units according to the actual active time of the GPU, the actual operating frequency of the power chip, and the ideal computing frequency of the power chip;

[0024] The total processing delay is obtained according to the task execution delay time, the task data upload delay and the execution result return delay.

[0025] In a further implementation scheme, the step of obtaining the task data upload delay and the execution result return delay of each computing task to be executed according to the business data load segmentation amount and the bus bandwidth capacity includes:

[0026] According to the business data load segmentation amount, the amount of computing task data to be executed and the bus bandwidth capacity, the task data upload delay required for each computing task to be uploaded from the central processing unit to the graphics processing unit is obtained;

[0027] According to the business data load segmentation amount, the execution result data amount and the bus bandwidth capacity, the execution result return delay required for transmitting the execution result of each computing task from the graphics processing unit back to the central processing unit is obtained.

[0028] In a further embodiment, the step of obtaining the optimal computing resource scheduling strategy using the firefly algorithm according to the fitness function includes:

[0029] Determine the multidimensional solution space and randomly initialize the firefly population in the multidimensional solution space; each firefly position represents a computing resource configuration;

[0030] The distance between two fireflies is calculated using the Euclidean distance method, and the relative fluorescence brightness between the two fireflies is obtained based on the distance between the two fireflies.

[0031] Calculate the attraction between individual fireflies according to the relative fluorescence brightness, determine the maximum number of iterations, and calculate the adaptive step size according to the maximum number of iterations and the current number of iterations;

[0032] According to the attraction between individual fireflies and the adaptive step size, the fitness function is used to iteratively update the position of each firefly, and during the position update process, the elite retention strategy is used to retain the position of the best firefly individual in the current population until the maximum number of iterations is reached, and the optimal computing resource scheduling strategy is output.

[0033] In a further embodiment, the calculation formula of the adaptive step size is:

[0034]

[0035] In the formula, S K is the adaptive step size; S max is the maximum step length; K is the current number of iterations; K max is the maximum number of iterations; S min is the minimum step length.

[0036] In a second aspect, the present invention provides a power chip computing resource scheduling system, the system comprising:

[0037] A data acquisition module is used to acquire the original computing power resource data required by the power chip to perform computing tasks from the power system in real time, and pre-process the original computing power resource data to obtain the computing power resource data to be processed;

[0038] A data cache module, used to cache the computing power resource data to be processed into an on-chip cache area, and obtain a total load of business computing data according to the computing power resource data to be processed;

[0039] A scheduling optimization module, for responding to a chip computing power allocation instruction, determining a fitness function according to the total load of the business computing data, and obtaining an optimal computing power resource scheduling strategy using a firefly algorithm based on an elite retention strategy according to the fitness function;

[0040] The resource scheduling module is used to dynamically schedule the computing resources on the power chip according to the optimal computing resource scheduling strategy and allocate the computing resources to different computing tasks.

[0041] In a third aspect, the present invention further provides a computer device, comprising a processor and a memory, wherein the processor is connected to the memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory so that the computer device performs the steps of implementing the above method.

[0042] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0043] The present invention provides a method, system, device and medium for scheduling computing power resources of power chips. The method obtains the original computing power resource data required for the power chip to perform computing tasks in real time from the power system, and pre-processes the original computing power resource data to obtain the computing power resource data to be processed; caches the computing power resource data to be processed in an on-chip cache area, and obtains the total load of business computing data according to the computing power resource data to be processed; responds to the chip computing power allocation instruction, determines the fitness function according to the total load of business computing data, and obtains the optimal computing power resource scheduling strategy based on the fitness function using the firefly algorithm based on the elite retention strategy; dynamically schedules the computing power resources on the power chip according to the optimal computing power resource scheduling strategy, and allocates the computing power resources to different computing tasks. Compared with the prior art, the method uses the firefly algorithm based on the elite retention strategy to perform efficient global optimization scheduling of the computing power resources of the power chip, realizes the fine control and efficient utilization of computing power resources, improves the utilization rate of resources, reduces energy consumption, and enhances the adaptability and reliability of the power chip in a complex power grid environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the flow chart of the power chip computing power resource scheduling method provided by an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of a power chip architecture provided by an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of a data compression process provided by an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of the firefly algorithm flow provided by an embodiment of the present invention;

[0048] Figure 5 It is a block diagram of a power chip computing power resource scheduling system provided by an embodiment of the present invention;

[0049] Figure 6 It is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following specifically illustrates the implementation mode of the present invention in conjunction with the accompanying drawings. The embodiments are provided for illustrative purposes only and cannot be understood as limiting the present invention. The accompanying drawings are provided for reference and illustration only and do not constitute a limitation on the scope of patent protection of the present invention, because many changes can be made to the present invention without departing from the spirit and scope of the present invention.

[0051] refer to Figure 1 , an embodiment of the present invention provides a method for scheduling computing power resources of a power chip, such as Figure 1 As shown, the method comprises the following steps:

[0052] S1. Acquire the original computing power resource data required for the power chip to perform computing tasks from the power system in real time, and pre-process the original computing power resource data to obtain the computing power resource data to be processed.

[0053] In this embodiment, the step of preprocessing the original computing power resource data to obtain the computing power resource data to be processed includes:

[0054] The original computing power resource data is divided into a plurality of computing power resource slice data according to the timestamp, and the maximum and minimum values ​​of each computing power resource slice data are counted;

[0055] According to the maximum and minimum values ​​of each computing resource shard data, each computing resource shard data is normalized to obtain normalized resource shard data;

[0056] Anomaly detection is performed on the normalized resource shard data, and the normalized resource shard data after anomaly detection is integrated to form computing power resource data to be processed.

[0057] Specifically, Figure 2 As shown in FIG. 1 , the power chip architecture includes an embedded CPU, an internal memory, an embedded GPU, an improved firefly algorithm module, a power communication module, a dedicated power data processing module, and a power management module connected by a high-speed bus. The embedded CPU is the central processing unit (Central Processing Unit) in the chip. The power chip is mainly responsible for processing the complex calculation and control logic related to the power system. The internal memory is used to store the data and instructions required for the operation of the chip. In the power chip, the internal memory stores the power system status, control parameters and algorithm data. The embedded GPU is a graphics processing unit (Graphics Processing Unit), which is used to process graphics-related computing tasks. In the power chip, the embedded GPU is used to accelerate tasks such as graphics rendering and data visualization in the power system. The power communication module is responsible for the communication between the chip and the external power system. It realizes data exchange and transmission of control instructions between the chip and other parts of the power system through communication protocols and interfaces. The dedicated power data processing module is responsible for processing real-time data, fault data, etc. in the power system, and provides corresponding processing results. The power management module is responsible for the power management of the chip, including voltage regulation, power consumption control, etc. In the power chip, the power management module needs to ensure that the chip operates stably in a complex power system environment.

[0058] In this embodiment, the original computing resource data is divided into a plurality of computing resource slice data according to the timestamp, and the computing resource slices are mapped in parallel to the task monitoring nodes in the distributed cluster by using the Map task of the distributed cluster, so as to facilitate the distributed processing process. Each task monitoring node is responsible for processing one or more computing resource slices. At the same time, the task monitoring node performs statistical analysis on each computing resource slice to obtain the maximum and minimum values ​​of each computing resource slice data. After the task monitoring node completes the data statistics, Figure 3 As shown, in this embodiment, the data processed by each node can be output to the cluster in the form of a data stream for compression processing. The compression algorithm can select a compression algorithm such as Huffman coding to reduce the storage space of the data and improve the transmission efficiency.

[0059] Due to the different dimensions of power data, this embodiment needs to standardize these data after data compression, and use the maximum and minimum values ​​to normalize the computing power resource slice data to the interval [0, 1] to obtain normalized resource slice data; for the normalized resource slice data, this embodiment needs to detect and eliminate abnormal data points. Assume that this embodiment collects three data points A, B, and C. When A is an abnormal data point, its abnormal degree is calculated according to the weighted cosine formula. After obtaining the weighted cosine value, the abnormal score is calculated through the eigenvalue of the abnormal data covariance matrix and the reconstructed data set, and the abnormal data is eliminated according to the abnormal score. The normalized resource slice data after abnormal detection is integrated to form the computing power resource data to be processed.

[0060] S2. Cache the computing power resource data to be processed into an on-chip cache area, and obtain the total load of business computing data based on the computing power resource data to be processed.

[0061] This embodiment caches the computing power resource data to be processed after eliminating abnormal data into the on-chip cache (On-ChipCache) for use by subsequent computing tasks. When the power chip needs to execute a total of i businesses, this embodiment can determine the number of businesses i of the computing tasks to be executed according to business needs, forming a computing load set I, and at the same time determine the number of GPU resources j available for allocation on the chip to form a GPU set J. The scheduler will allocate appropriate GPU resources to the kernel function based on the current resource usage and task queue. At the same time, this embodiment determines the total load of business computing data, that is, the amount of data that needs to be allocated computing power, based on the amount of data in the cache and the needs of the computing tasks.

[0062] S3. In response to the chip computing power allocation instruction, determine the fitness function according to the total load of the business computing data, and according to the fitness function, use the firefly algorithm based on the elite retention strategy to obtain the optimal computing power resource scheduling strategy.

[0063] In this embodiment, the step of determining the fitness function according to the total load of the business calculation data includes:

[0064] Dividing the total load of the business calculation data into several equal parts to obtain the business data load split amount;

[0065] According to the business data load split amount and the bus bandwidth capacity, the task data upload delay and the execution result return delay of each to-be-executed computing task are obtained; wherein, according to the business data load split amount and the bus bandwidth capacity, the step of obtaining the task data upload delay and the execution result return delay of each to-be-executed computing task comprises: according to the business data load split amount, the amount of computing task data to be executed and the bus bandwidth capacity, obtaining the task data upload delay required for each computing task to be uploaded from the central processing unit to the graphics processing unit; according to the business data load split amount, the amount of execution result data and the bus bandwidth capacity, obtaining the execution result return delay required for the execution result of each computing task to be transmitted from the graphics processing unit back to the central processing unit;

[0066] Obtaining a total processing delay according to the task data upload delay and the execution result return delay, and obtaining a normalized time resource factor according to the total processing delay;

[0067] Obtain a total power consumption requirement based on the task calculation power consumption requirement and the GPU basic power consumption, and obtain a normalized calculation energy consumption factor based on the total power consumption requirement;

[0068] The normalized time resource factor and the normalized computing energy consumption factor are weighted by using the hierarchical analysis method to obtain a fitness function.

[0069] The step of obtaining the total processing delay according to the task data upload delay and the execution result return delay comprises:

[0070] Determine the load throughput according to the total load of the business computing data, and obtain the actual active time of the GPU according to the ratio between the load throughput and the business data load segmentation amount;

[0071] Calculate the task execution delay time required for each to-be-executed computing task to be executed on different graphics processing units according to the actual active time of the GPU, the actual operating frequency of the power chip, and the ideal computing frequency of the power chip;

[0072] The total processing delay is obtained according to the task execution delay time, the task data upload delay and the execution result return delay.

[0073] Specifically, in this embodiment, the total business computing data load is divided into several parts to obtain the business data load segmentation amount. For example, if the total business computing data load is 10GB, it can be divided into 10 1GB data blocks, and each business data load segmentation amount is managed to achieve more accurate resource scheduling. This block processing method helps to improve resource utilization and ensure that each computing task can obtain appropriate resource allocation. Then, for each business data load segmentation amount, the task data upload delay of each computing task to be executed is calculated according to the business data load segmentation amount, the data volume of the computing task to be executed and the bus bandwidth capacity. The specific calculation formula of the task data upload delay is:

[0074]

[0075] In the formula, Delay for uploading mission data; is the amount of computing task data to be executed; α is the amount of business data load segmentation; b i is the bus bandwidth capacity, which represents the available bus bandwidth; N is the number of equal parts of the total business computing data load into which the business data load is divided.

[0076] At the same time, this embodiment obtains the execution result return delay required for the execution result of each computing task to be transmitted from the graphics processing unit to the central processing unit according to the business data load segmentation amount, the execution result data amount and the bus bandwidth capacity, wherein the specific calculation formula for the execution result return delay is:

[0077]

[0078] In the formula, Delay in returning the execution result; The amount of execution result data.

[0079] This embodiment can predict and optimize the task execution process by calculating the task data upload delay and the execution result return delay of each computing task to be executed, which helps to reduce the waiting time of the task during the data transmission process, thereby reducing the overall delay. Next, this embodiment can determine the system load throughput by dividing the total load of business computing data by the number of tasks per unit time. The throughput reflects the amount of data that the system can process per unit time. The actual time required for the GPU to process each data block is calculated based on the load throughput and the business data load segmentation amount to obtain the GPU actual active time. The specific calculation formula for the GPU actual active time is:

[0080]

[0081] In the formula, is the actual active time of the GPU; h ij is the load throughput.

[0082] When executing a computing task on the GPU, it is first necessary to wait for the GPU scheduler to allocate the kernel function and start running it. This process introduces a kernel function scheduling delay. This delay and the GPU active time together constitute the complete computing delay. When the operating frequency of the computing load decreases, which is specifically manifested as a decrease in the GPU clock frequency, this change will simultaneously affect the operating frequency of the GPU kernel function scheduler and the computing frequency of the GPU execution unit. As a result, the computing delay will be proportionally reduced accordingly. Therefore, this embodiment can divide the task execution delay on the GPU into two parts: kernel function scheduling delay and GPU active time, and comprehensively consider the impact of the delay on the operating frequency reduction. Therefore, this embodiment is based on According to the actual active time of the GPU, the actual working frequency of the power chip and the ideal computing frequency of the power chip, the task execution delay time required for each to-be-executed computing task to be executed on different graphics processing units (GPUs) is calculated. This embodiment can reduce unnecessary energy consumption by accurately controlling the working frequency and computing frequency of the power chip, especially in the calculation of the actual active time of the GPU, it can avoid excessive power consumption and realize the reasonable allocation and use of energy. Specifically, this embodiment calculates the execution efficiency according to the working frequency and the ideal computing frequency, and calculates the task execution delay time of each task on different GPUs according to the actual active time and execution efficiency of the GPU. The specific calculation formula for the task execution delay time is:

[0083]

[0084] In the formula, Delay time for task execution; It is the actual active time of GPU; is the kernel function scheduling delay, which and the task execution delay are both ideal computing performances without considering GPU frequency reduction; f j is the actual operating frequency of the power chip; F is the ideal calculation frequency of the power chip.

[0085] When the GPU operating frequency is affected by power reduction, it can be expressed as follows:

[0086]

[0087] In the formula, a f This is the factor that affects the GPU operating frequency when the GPU's theoretical power requirement exceeds the GPU power upper limit. Calculate the power consumption requirement for the task, that is, the theoretical total power requirement of all computational loads run by the GPU; P is the power ceiling of the GPU.

[0088] For each task, this embodiment adds up its task execution delay time, task data upload delay and execution result return delay, accumulates the total processing delay of all tasks, and obtains the total processing delay of the entire computing task. The total processing delay refers to the total time required to complete a computing task, including data transmission time, computing processing time and result return time, so as to ensure that the performance of each computing task to be executed on different graphics processing units can be accurately evaluated, and provide a reliable basis for subsequent computing resource scheduling; it should be noted that the process of executing computing tasks on the GPU mainly includes the following three main stages: first, the data is loaded onto the GPU device; then, the GPU executes a specific computing task; finally, the computing result is returned to the CPU. In addition, when the GPU performs calculations, its basic execution unit is the kernel function, and the entire execution process can be further divided into two stages: kernel function scheduling and kernel function execution. In this process, the built-in scheduler of the GPU serves as the core of managing GPU resources. It reasonably allocates the required resources to each kernel function based on the current resource occupancy status and the arrangement of the task queue. Therefore, this embodiment divides the total processing delay into the sum of the time consumed in these three stages.

[0089] After the total processing delay is calculated, this embodiment obtains a normalized time resource factor according to the ratio of the total processing delay to the maximum and minimum tolerable delays, wherein the maximum and minimum tolerable delays are tolerable delay thresholds set according to system requirements or task requirements. The specific calculation formula of the normalized time resource factor is:

[0090]

[0091] Where Tm′ is the normalized time resource factor; is the total processing delay; is the minimum tolerable delay; is the maximum tolerable delay.

[0092] The total power consumption requirement is obtained according to the task computing power consumption requirement and the GPU basic power consumption, wherein the task computing power consumption requirement refers to the power required to complete a computing task, which is usually related to factors such as the computing complexity and data volume of the task; the GPU basic power consumption refers to the power consumed by the GPU in an idle state (i.e., when no computing tasks are performed), which can be obtained by measuring the power consumption of the GPU when it is idle. According to the total power consumption requirement and the maximum and minimum power consumption capacity, the normalized computing energy consumption factor is obtained. The maximum and minimum power consumption capacity refers to the maximum and minimum power consumption that the system or device can withstand. The specific calculation formula of the normalized computing energy consumption factor is:

[0093]

[0094] Among them, as the number of computing workloads increases, the power of the GPU shows a linear growth trend, which means that the theoretical total power requirement on the GPU device is the sum of the power required by all computing loads deployed on the GPU. In addition, this embodiment also needs to take into account that the GPU will consume a certain amount of power in the idle standby state. Therefore, the total power consumption requirement calculation formula of the GPU is:

[0095]

[0096] Where En′ is the normalized calculation energy consumption factor; is the total power consumption requirement; is the minimum power consumption capacity; is the maximum power consumption capacity; p idle is the GPU basic power consumption, that is, the GPU idle power consumption; p i Calculate the power consumption requirement for the task, that is, calculate the power requirement of the load independently; ij When computation load i runs on GPU device j, its value is 1, otherwise its value is 0.

[0097] This embodiment uses the hierarchical analysis method to determine the weights of the normalized time resource factor and the normalized computing energy consumption factor, takes the decision goal (such as computing power resource scheduling optimization) as the highest layer, and takes the normalized time resource factor and the normalized computing energy consumption factor as the decision criteria of the middle layer. Through expert scoring or experience judgment, the importance between the normalized time resource factor and the normalized computing energy consumption factor is compared, and a judgment matrix is ​​constructed. The weight vector of the judgment matrix is ​​calculated using the sum-product method, etc., to obtain the weights of the normalized time resource factor and the normalized computing energy consumption factor. According to the obtained weights, a fitness function is constructed to achieve effective scheduling and optimization of computing power resources, wherein the calculation formula of the fitness function is:

[0098] f=g*Tm′+z*En′

[0099] Where f is the fitness function; g is the time resource weight; z is the energy consumption weight.

[0100] In this embodiment, the step of obtaining the optimal computing resource scheduling strategy using the firefly algorithm according to the fitness function includes:

[0101] Determine the multidimensional solution space and randomly initialize the firefly population in the multidimensional solution space; each firefly position represents a computing resource configuration;

[0102] The distance between two fireflies is calculated using the Euclidean distance method, and the relative fluorescence brightness between the two fireflies is obtained based on the distance between the two fireflies.

[0103] Calculate the attraction between individual fireflies according to the relative fluorescence brightness, determine the maximum number of iterations, and calculate the adaptive step size according to the maximum number of iterations and the current number of iterations;

[0104] According to the attraction between individual fireflies and the adaptive step size, the fitness function is used to iteratively update the position of each firefly, and during the position update process, the elite retention strategy is used to retain the position of the best firefly individual in the current population until the maximum number of iterations is reached, and the optimal computing resource scheduling strategy is output.

[0105] Specifically, Figure 4 As shown, this embodiment determines an m-dimensional solution space, where m represents the number of parameters in the GPU computing power configuration, such as core frequency, voltage level, memory bandwidth, etc., and randomly initializes the position of each firefly in the m-dimensional solution space to form a firefly population. The position of each firefly represents a GPU computing power configuration, sets key parameters such as the firefly's own brightness, light absorption coefficient, and initial attraction, and determines the maximum number of iterations, the maximum step size, and the minimum step size. In the current iteration process, the Euclidean distance method is used to calculate the distance between two firefly individuals in the Kth iteration process. According to the calculated distance between the two fireflies, the relative fluorescence brightness between the two fireflies is calculated, and the attraction between the fireflies is calculated according to the relative fluorescence brightness. The specific calculation formula for the attraction between the fireflies is:

[0106]

[0107] In the formula, I bp,K (r bp,K ) is the firefly x at the Kth iteration b To Firefly x p The relative fluorescence brightness between b For Firefly x b The absolute brightness; γ is the light absorption coefficient; μ bp,K is the distance between two fireflies in the Kth iteration; β bp,K (r bp,K ) is the attraction between fireflies; β0 is the firefly x b The attractiveness of the initial position.

[0108] In each iteration, in order to prevent the best individual of each iteration from being destroyed or lost, this embodiment adopts the elite retention strategy to improve the position update formula, and strengthen the traction effect of the best firefly individual in the current population on other individuals. The position update formula is specifically:

[0109] x p,K+1 =x b,K +β bp,K (μ bp,K)(x b,K -x p,K )+s1(rand-0.5)(x g,K -x p,K )

[0110] In the formula, x p,K+1 The updated position of each firefly; x b,K is the firefly x in the Kth iteration b The position of x p,K is the firefly x in the Kth iteration p The position of x g,K is the optimal position of the firefly population individual in the Kth iteration; rand is a random number in the interval [0, 1] that follows a uniform distribution; s1 is the step size, s1∈[0, 1].

[0111] The position of the best firefly individual in the current population is recorded as the elite individual to ensure that the position of the best individual is not destroyed or lost during the position update process to retain the optimal solution. This embodiment uses an improved position update formula and an adaptive step length to update the position of each firefly, wherein the adaptive step length is calculated based on the current number of iterations K, the maximum number of iterations, the maximum step length, and the minimum step length, which can prevent the firefly from missing the position of the optimal value due to an excessively large step length and causing oscillation. In this embodiment, the calculation formula for the adaptive step length is:

[0112]

[0113] In the formula, S K is the adaptive step size; S max is the maximum step length; K is the current number of iterations; K max is the maximum number of iterations; S min is the minimum step length.

[0114] Repeat the above steps until the maximum number of iterations is reached. After each iteration, calculate the value of the objective function, find the minimum objective function value and the corresponding individual position of the firefly, and compare them with the result of the previous iteration. If the difference between the two meets the accuracy requirement and the number of iterations has reached the maximum number of iterations, the algorithm is considered to have converged, and the optimal solution set of the converged fitness function is output to the CPU. The CPU optimizes the scheduling of GPU computing resources according to the optimal solution set to achieve the purpose of optimal chip energy efficiency. This embodiment simulates the natural behavior of fireflies and combines the elite retention strategy to effectively search for the global optimal solution in the solution space. The firefly algorithm itself has parallelism and randomness, which can avoid falling into the local optimum, and the elite retention strategy ensures that the optimal solution will not be lost during the iteration process. The elite retention strategy and adaptive step size design enhance the robustness and convergence of the algorithm, thereby improving the global optimization capability.

[0115] This embodiment optimizes the scheduling of computing power resources for power chips. By accurately calculating the relative fluorescence brightness and attractiveness of each firefly individual and using an improved position update formula and adaptive step size, it achieves fine control and efficient utilization of computing power resources. By optimizing the configuration and utilization of computing power resources and reducing energy consumption, it can adapt to computing power resource scheduling problems of power chips of different scales and complexities.

[0116] S4. Dynamically schedule the computing resources on the power chip according to the optimal computing resource scheduling strategy, and allocate the computing resources to different computing tasks.

[0117] This embodiment adopts the firefly algorithm based on the elite retention strategy. By simulating the natural behavior of fireflies and combining the elite retention strategy, the global optimal scheduling of computing resources is realized. This method not only improves the chip energy efficiency, but also has strong robustness and convergence. It can be applied to power chip computing resource scheduling problems of different scales and complexities.

[0118] The embodiment of the present invention provides a method for scheduling computing power resources of power chips, which obtains the original computing power resource data required for the power chip to perform computing tasks in real time from the power system, and pre-processes the original computing power resource data to obtain the computing power resource data to be processed; caches the computing power resource data to be processed in an on-chip cache area, and obtains the total load of business computing data according to the computing power resource data to be processed; responds to the chip computing power allocation instruction, determines the fitness function according to the total load of business computing data, and obtains the optimal computing power resource scheduling strategy using the firefly algorithm according to the fitness function; dynamically schedules the computing power resources on the power chip according to the optimal computing power resource scheduling strategy, and allocates the computing power resources to different computing tasks. Compared with the prior art, the method adopts the firefly algorithm based on the elite retention strategy to dynamically adjust the computing power configuration, realizes the efficient global optimization scheduling of the computing power resources of the power chip, can adapt to the computing power resource scheduling problems of power chips of different scales and complexities, improves the utilization rate of computing power resources, reduces energy consumption, and enhances the adaptability and reliability of power chips in complex power grid environments.

[0119] It should be noted that the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0120] In one embodiment, Figure 5 As shown, an embodiment of the present invention provides a power chip computing resource scheduling system, the system comprising:

[0121] The data acquisition module 101 is used to acquire the original computing power resource data required by the power chip to perform computing tasks in real time from the power system, and pre-process the original computing power resource data to obtain the computing power resource data to be processed;

[0122] The data cache module 102 is used to cache the computing power resource data to be processed into an on-chip cache area, and obtain the total load of business computing data according to the computing power resource data to be processed;

[0123] The scheduling optimization module 103 is used to respond to the chip computing power allocation instruction, determine the fitness function according to the total load of the business computing data, and obtain the optimal computing power resource scheduling strategy based on the firefly algorithm based on the elite retention strategy according to the fitness function;

[0124] The resource scheduling module 104 is used to dynamically schedule the computing resources on the power chip according to the optimal computing resource scheduling strategy and allocate the computing resources to different computing tasks.

[0125] For the specific definition of a power chip computing power resource scheduling system, please refer to the above-mentioned definition of a power chip computing power resource scheduling method, which will not be repeated here. A person of ordinary skill in the art can appreciate that the various modules and steps described in conjunction with the embodiments disclosed in this application can be implemented in hardware, software, or a combination of both. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0126] The embodiment of the present invention provides a power chip computing power resource scheduling system, wherein the system acquires the original computing power resource data required for the power chip to perform computing tasks from the power system in real time through a data acquisition module, and pre-processes the original computing power resource data to obtain the computing power resource data to be processed; the data cache module caches the computing power resource data to be processed to an on-chip cache area, and obtains the total load of business computing data according to the computing power resource data to be processed; the scheduling optimization module responds to the chip computing power allocation instruction, determines the fitness function according to the total load of business computing data, and obtains the optimal computing power resource scheduling strategy using the firefly algorithm according to the fitness function; the resource scheduling module dynamically schedules the computing power resources on the power chip according to the optimal computing power resource scheduling strategy, and allocates the computing power resources to different computing tasks. Compared with the prior art, the system adopts the firefly algorithm based on the elite retention strategy to dynamically adjust the computing power configuration, realizes the efficient global optimization scheduling of the computing power resources of the power chip, can adapt to the computing power resource scheduling problems of power chips of different scales and complexities, improves the utilization rate of computing power resources, reduces energy consumption, and enhances the adaptability and reliability of the power chip in a complex power grid environment.

[0127] Figure 6 A computer device provided by an embodiment of the present invention includes a memory, a processor and a transceiver, which are connected via a bus; the memory is used to store a set of computer program instructions and data, and can transmit the stored data to the processor, and the processor can execute the program instructions stored in the memory to perform the steps of the above method.

[0128] The memory may include a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories; the processor may be a central processing unit, a microprocessor, an application-specific integrated circuit, a programmable logic device, or a combination thereof. By way of example but not limitation, the programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0129] Additionally, the memory may be a physically separate unit or may be integrated with the processor.

[0130] It can be understood by those skilled in the art that Figure 6 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have the same component arrangement.

[0131] In one embodiment, the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0132] An embodiment of the present invention provides a method, system, device and medium for scheduling computing power resources of a power chip. The method for scheduling computing power resources of a power chip adopts a firefly algorithm to dynamically adjust the computing power configuration, thereby improving resource utilization and enhancing the adaptability and reliability of the power chip in a complex power grid environment.

[0133] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., an SSD), etc.

[0134] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods.

[0135] The above-mentioned embodiments only express several preferred implementation modes of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in the technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be regarded as the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be based on the protection scope of the claims.

Claims

1. A method for scheduling power chip computing resources, characterized in that: The following steps are involved: Acquire the original computing power resource data required for the power chip to perform computing tasks in real time from the power system, and pre-process the original computing power resource data to obtain the computing power resource data to be processed; Cache the computing power resource data to be processed into an on-chip cache area, and obtain the total load of business computing data according to the computing power resource data to be processed; In response to the chip computing power allocation instruction, a fitness function is determined according to the total load of the business computing data, and according to the fitness function, an optimal computing power resource scheduling strategy is obtained by using a firefly algorithm based on an elite retention strategy; The computing resources on the power chip are dynamically scheduled according to the optimal computing resource scheduling strategy, and the computing resources are allocated to different computing tasks.

2. A method for scheduling power chip computing resources according to claim 1, characterized in that: The step of preprocessing the original computing power resource data to obtain the computing power resource data to be processed includes: The original computing power resource data is divided into a plurality of computing power resource slice data according to the timestamp, and the maximum and minimum values ​​of each computing power resource slice data are counted; According to the maximum and minimum values ​​of each computing resource shard data, each computing resource shard data is normalized to obtain normalized resource shard data; Anomaly detection is performed on the normalized resource shard data, and the normalized resource shard data after anomaly detection is integrated to form computing power resource data to be processed.

3. A method for scheduling power chip computing resources according to claim 1, characterized in that: The step of determining the fitness function according to the total load of the business calculation data comprises: Dividing the total load of the business calculation data into several equal parts to obtain the business data load split amount; According to the business data load segmentation amount and the bus bandwidth capacity, the task data upload delay and the execution result return delay of each computing task to be executed are obtained; Obtaining a total processing delay according to the task data upload delay and the execution result return delay, and obtaining a normalized time resource factor according to the total processing delay; Obtain a total power consumption requirement based on the task calculation power consumption requirement and the GPU basic power consumption, and obtain a normalized calculation energy consumption factor based on the total power consumption requirement; The normalized time resource factor and the normalized computing energy consumption factor are weighted by using the hierarchical analysis method to obtain a fitness function.

4. A method for scheduling power chip computing resources as claimed in claim 3, characterized in that: The step of obtaining the total processing delay according to the task data upload delay and the execution result return delay comprises: Determine the load throughput according to the total load of the business computing data, and obtain the actual active time of the GPU according to the ratio between the load throughput and the business data load segmentation amount; Calculate the task execution delay time required for each to-be-executed computing task to be executed on different graphics processing units according to the actual active time of the GPU, the actual operating frequency of the power chip, and the ideal computing frequency of the power chip; The total processing delay is obtained according to the task execution delay time, the task data upload delay and the execution result return delay.

5. A method for scheduling power chip computing resources as claimed in claim 3, characterized in that: The step of obtaining the task data upload delay and the execution result return delay of each to-be-executed computing task according to the business data load segmentation amount and the bus bandwidth capacity comprises: Obtaining a task data upload delay required for each computing task to be uploaded from the central processing unit to the graphics processing unit according to the business data load segmentation amount, the amount of computing task data to be executed, and the bus bandwidth capacity; According to the business data load segmentation amount, the execution result data amount and the bus bandwidth capacity, the execution result return delay required for transmitting the execution result of each computing task from the graphics processing unit back to the central processing unit is obtained.

6. A method for scheduling power chip computing resources according to claim 1, characterized in that: The step of obtaining the optimal computing resource scheduling strategy using the firefly algorithm according to the fitness function includes: Determine the multidimensional solution space and randomly initialize the firefly population in the multidimensional solution space; each firefly position represents a computing resource configuration; The distance between two fireflies is calculated using the Euclidean distance method, and the relative fluorescence brightness between the two fireflies is obtained based on the distance between the two fireflies. Calculate the attraction between individual fireflies according to the relative fluorescence brightness, determine the maximum number of iterations, and calculate the adaptive step size according to the maximum number of iterations and the current number of iterations; According to the attraction between individual fireflies and the adaptive step size, the fitness function is used to iteratively update the position of each firefly, and during the position update process, the elite retention strategy is used to retain the position of the best firefly individual in the current population until the maximum number of iterations is reached, and the optimal computing resource scheduling strategy is output.

7. A method for scheduling power chip computing resources as claimed in claim 6, characterized in that: The calculation formula of the adaptive step size is: In the formula, S K is the adaptive step size; S max is the maximum step length; K is the current number of iterations; K max is the maximum number of iterations; S min is the minimum step length.

8. A power chip computing resource scheduling system, characterized in that: The system comprises: A data acquisition module is used to acquire the original computing power resource data required by the power chip to perform computing tasks from the power system in real time, and pre-process the original computing power resource data to obtain the computing power resource data to be processed; A data cache module, used to cache the computing power resource data to be processed into an on-chip cache area, and obtain a total load of business computing data according to the computing power resource data to be processed; A scheduling optimization module, for responding to a chip computing power allocation instruction, determining a fitness function according to the total load of the business computing data, and obtaining an optimal computing power resource scheduling strategy using a firefly algorithm based on an elite retention strategy according to the fitness function; The resource scheduling module is used to dynamically schedule the computing resources on the power chip according to the optimal computing resource scheduling strategy and allocate the computing resources to different computing tasks.

9. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein the processor is connected to the memory, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory, so that the computer device executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the method according to any one of claims 1 to 7 is implemented.

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