Computing core module, multi-core communication system, multi-core communication method and vehicle

Abstract

The invention discloses a computing core module, a multi-core communication system, a multi-core communication method and a vehicle. The calculation core module comprises a processor unit and an interrupt generation unit; the processor unit comprises a storage unit, at least one storage subunit is pre-divided in the storage unit, and one storage subunit is used for independently storing data written into the module by other computing core modules; the address range of each storage subunit is pre-stored in the interrupt generation unit; the interrupt generation unit is used for generating a target interrupt signal aiming at the target storage subunit when the data written into the target storage subunit is detected to meet a reading condition at the data control interface of the processor unit, and sending the target interrupt signal to the interrupt control unit; and the interrupt control unit is arranged in the processor unit and is used for controlling the processor unit to read data from the target storage subunit for processing according to the target interrupt signal. According to the embodiment of the invention, efficient inter-core communication is realized in a mode that hardware automatically generates interruption.

Description

Technical Field

[0001] The present invention relates to the field of computer hardware technology, and in particular to a computing core module, a multi-core communication system, a multi-core communication method and a vehicle. Background Art

[0002] As the number of computing cores (processors) in MCU (Microcontroller Unit) increases, the amount of communication data of intelligent vehicles is also increasing. As the complexity of electronic control units increases, the application of multi-core heterogeneous processors is becoming more and more common. At this time, the performance of inter-core communication plays a decisive role in the performance release of the entire processor.

[0003] In the prior art, inter-core communication technology is mainly implemented by using a shared cache space or mailbox hardware. In these implementations, the source computing core writes the communication data into a shared cache or mailbox, and then the source computing core sends an interrupt notification to the destination computing core. After receiving the interrupt, the destination computing core moves the communication data from the corresponding storage space.

[0004] However, the existing inter-core communication method will generate large delays in the entire communication process and increase the computing load of the computing core, which has a certain impact on the performance of the computing core and the real-time nature of communication. As a result, it cannot effectively cope with application scenarios where inter-core communication is frequent and the amount of communication data is large. Summary of the invention

[0005] Embodiments of the present invention provide a computing core module, a multi-core communication system, a multi-core communication method and a vehicle, which realize efficient inter-core communication by automatically generating interrupts through hardware.

[0006] According to one aspect of an embodiment of the present invention, there is provided a computing core module, comprising: processor units and interrupt generation units connected in pairs;

[0007] The processor unit includes a storage unit, in which at least one storage sub-unit is pre-divided, and one storage sub-unit is used to independently store data written to this module by another computing core module; in the interrupt generation unit, the address range of each storage sub-unit is pre-stored;

[0008] An interrupt generation unit, configured to generate a target interrupt signal for the target storage subunit when detecting at the data control interface of the processor unit that the data written to the target storage subunit meets the read condition, and send the target interrupt signal to the interrupt control unit;

[0009] The interrupt control unit is arranged inside the processing unit, and is used to control the processor unit to read data from the target storage subunit for processing according to the target interrupt signal.

[0010] Furthermore, the interrupt generation unit is specifically used for:

[0011] When it is detected at the data control interface of the processor unit that data is written to the termination address of the target storage subunit, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit.

[0012] Furthermore, the interrupt generation unit is specifically used for:

[0013] When it is detected at the data control interface of the processor unit that the amount of data written to the target storage subunit exceeds a preset data amount threshold, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit.

[0014] Furthermore, the interrupt generation unit is specifically used for:

[0015] When it is detected at the data control interface of the processor unit that the writing of the entire data to the target storage sub-unit has been completed and the preset waiting time has passed since the writing completion time point, a target interrupt signal for the target storage sub-unit is generated and sent to the interrupt control unit.

[0016] Further, the storage unit is a storage space divided in a tightly coupled memory inside the processor unit;

[0017] The processor unit includes a central processing unit, a graphics processing unit or a neural network processor.

[0018] According to another aspect of an embodiment of the present invention, a multi-core communication system is provided, comprising a plurality of computing core modules as described in any one of the embodiments of the present invention;

[0019] Among them, the computing core modules establish communication connections through a bus, and the number of storage sub-units contained in the storage unit of each computing core module is the total number of computing core modules contained in the multi-core communication system minus one.

[0020] Furthermore, the processor units included in each computing core module are homogeneous or heterogeneous processor units.

[0021] According to another aspect of an embodiment of the present invention, a multi-core communication method is provided, which is applied to a multi-core communication system as described in any one of the embodiments of the present invention, and the method includes:

[0022] The first computing core module sends a single first data to at least one second computing core module via a bus, where each data item in the first data includes a data write address;

[0023] The processor unit in each second computing core module stores each data item in the first data obtained from the data control interface into a first storage subunit matching the first computing core module in the internal storage unit according to the data write address;

[0024] The interrupt generation unit in each second computing core module generates a first interrupt signal for the first storage subunit when detecting at the data control interface of the module that each data item written to the first storage subunit meets the read condition, and sends the first interrupt signal to the interrupt control unit of the module;

[0025] The interrupt control unit in each second computing core module controls the processor unit of the module to read each data item from the internal first storage subunit for processing according to the first interrupt signal. According to another aspect of an embodiment of the present invention, a multi-core communication method is further provided, which is applied to the multi-core communication system as described in any one of the embodiments of the present invention, and the method includes:

[0026] The plurality of third computing core modules respectively send second data to the data control interface of the fourth computing core module through the bus, wherein each data item in the second data includes a data write address;

[0027] The processor unit in the fourth computing core module stores each data item in the second data sent by each third computing core module obtained from the data control interface into a second storage sub-unit respectively matched with each third computing core module in the internal storage unit according to the data write address;

[0028] The interrupt generation unit in the fourth computing core module generates a second interrupt signal for the target second computing core module whenever it is detected at the data control interface of the module that each data item written to the target second storage sub-unit meets the read condition, and sends the second interrupt signal to the interrupt control unit of the module;

[0029] The interrupt control unit in the fourth computing core module controls the processor unit of this module to read each data item from the internal target second storage subunit for processing according to the second interrupt signal.

[0030] According to another aspect of an embodiment of the present invention, a vehicle is provided, comprising the multi-core communication system as described in any one of the embodiments of the present invention.

[0031] The technical solution of the embodiment of the present invention is to set an interrupt generation unit and a storage subunit that independently stores data written to this module by other computing core modules in the computing core module. When the interrupt generation unit detects at the data control interface in the computing core module that the data written to the target storage subunit meets the read condition, it automatically generates a target interrupt signal for the target storage subunit to control the processor unit to read data from the target storage subunit for processing. A multi-core communication method implemented by automatic hardware interrupt generation is creatively proposed, which effectively reduces the number of information exchanges in the multi-core communication process. In particular, in application scenarios where inter-core communication is frequent and real-time requirements are high, the multi-core communication method of the embodiment of the present invention can reduce the load of the computing core module and significantly improve the efficiency of inter-core communication.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a structural schematic diagram of a computing core module provided according to an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of the structure of a multi-core communication system provided according to an embodiment of the present invention;

[0036] Figure 3 is a structural diagram of a multi-core communication system consisting of four isomorphic computing core modules applicable to an embodiment of the present invention;

[0037] Figure 4 is a flow chart of an implementation of a multi-core communication method provided according to an embodiment of the present invention;

[0038] Figure 5 This is a data flow diagram of a one-to-one inter-core communication applicable to an embodiment of the present invention;

[0039] Figure 6 This is another data flow diagram of one-to-one inter-core communication applicable to the embodiment of the present invention;

[0040] Figure 7This is a data flow diagram of a one-to-many core communication applicable to an embodiment of the present invention;

[0041] Figure 8 is a flowchart of another multi-core communication method provided according to an embodiment of the present invention;

[0042] Fig. 9 This is a data flow diagram of a many-to-one inter-core communication applicable to an embodiment of the present invention;

[0043] Fig.10 This is a data flow diagram of a multi-to-multi-core communication applicable to an embodiment of the present invention;

[0044] Fig.11 A schematic structural diagram of a vehicle provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 A structural schematic diagram of a computing core module provided for an embodiment of the present invention. This embodiment can be applied to the situation where when other computing core modules send communication data to the storage unit of this computing core module, with the cooperation of various hardware units in this computing core module, an interrupt signal is automatically generated when it is detected that the conditions are met to automatically obtain the communication data in the storage unit.

[0048] Correspondingly, such as Figure 1As shown, the computing core module specifically includes: processor units 110 and interrupt generation units 120 connected in pairs. .

[0049] The processor unit 110 includes a storage unit 140, in which at least one storage subunit 150 (ie, Figure 1 In the storage subunit 1, storage subunit 2, ..., storage subunit N), a storage subunit 150 is used to independently store data written to the current computing core module by another computing core module; in the interrupt generation unit 120, the address range of each storage subunit 150 is pre-stored.

[0050] Specifically, the processor unit 110 can be understood as an execution unit for realizing a computing or control function. According to the functions realized, the processor unit 110 can be specifically a CPU (Central Processing Unit), a GPU (graphics processing unit) or an NPU (Neural Processing Unit), etc., and this embodiment does not limit this.

[0051] In this embodiment, it is necessary to allocate an independent storage space for storing inter-core communication data in the processor unit 110, that is, the storage unit 140, for caching the communication data sent (or written) to the computing core module by other computing core modules. Considering that a computing core module may need to communicate with one or more other computing core modules respectively, it is necessary to allocate an independent storage space (that is, the storage subunit 150) in the storage unit 140 of the computing core module for the other computing core modules that communicate with it, so as to store the communication data between the computing core modules separately.

[0052] In an optional implementation of this embodiment, the storage unit 140 may be a storage space divided out of a tightly coupled memory (TCM) inside the processor unit.

[0053] In a specific example, it is assumed that computing core module A can perform inter-core communication with computing core module B and computing core module C respectively, and then, the storage unit of the processor unit of computing core module A can be further divided into storage subunit 1 and storage subunit 2. At the same time, the communication data sent from computing core module B to computing core module A is cached in storage subunit 1, and the communication data sent from computing core module C to computing core module A is cached in storage subunit 2.

[0054] That is, when the computing core module expects to communicate with N other computing core modules, N storage sub-units can be divided in the storage unit of the computing core module. Then, each storage sub-unit caches the communication data sent to the computing core module by other computing core modules. At the same time, each independent storage sub-unit has an independent and non-overlapping cache address range.

[0055] Correspondingly, when computing core module B has a communication need to write data to computing core module A, since the storage subunit 1 allocated to computing core module B in computing core module A is known, and storage subunit 1 has a known address range, when computing core module B sends a communication data, the write address of each data item in the communication data is also known.

[0056] Specifically, the computing core module can receive communication data sent by other computing core modules through the bus through its own data control interface 160. The data control interface 160 can be a slave interface in the processor unit 110.

[0057] The interrupt generation unit 120 is used to generate a target interrupt signal for the target storage subunit when it is detected at the data control interface 160 of the processor unit 110 that the data written to the target storage subunit meets the read condition, and send the target interrupt signal to the interrupt control unit 130.

[0058] In this embodiment, the address range of each storage sub-unit 150 is pre-stored in the interrupt generation unit 120. Further, when the interrupt generation unit 120 detects communication data written by other computing core modules at the data control interface 160 of the processor unit 110, by comparing the write address of the identified communication data with the pre-stored address range of each storage sub-unit 150, it is possible to determine into which storage sub-unit the currently written communication data is specifically written, and also to clarify the specific location in the storage sub-unit where the communication data is written.

[0059] In a specific example, if the address range of the storage sub-unit 1 in the storage unit 140 is 0xOO~0xFF, when it is detected that the storage address of the communication data 1 currently written by other computing core modules is 0xFE, it can be known that the communication data 1 is the data that needs to be written to the second-to-last storage space in the storage sub-unit 1, or, when it is detected that the storage address of the communication data 1 currently written by other computing core modules is 0xFF, it can be known that the communication data 1 is the data that needs to be written to the last storage space in the storage sub-unit 1.

[0060] Accordingly, the judgment logic may be pre-configured in the interrupt generation unit 120. For example, when any storage subunit stores data to the storage address of the last storage space of the storage unit, it is determined that the data for the storage unit meets the read condition. At this time, the hardware of the interrupt generation unit 120 will correspondingly generate an interrupt signal (i.e., a hard interrupt) for the storage unit (i.e., the target storage unit), and the interrupt signal is used to indicate that the processor unit 110 can start reading all the communication data currently cached in the storage subunit.

[0061] Different from the existing technology, every time the source computing core completely writes a data to the set shared cache or mailbox hardware, the source computing core generates a soft interrupt signal to notify the target computing core that needs to receive the data, and the target computing core reads the data from the shared cache or mailbox hardware after receiving the soft interrupt signal, this optional implementation method can allow the target computing core module itself to determine the appropriate time to read the data sent by the source computing core module from the internal storage space of the local machine, and read the cached data accordingly. This greatly improves the efficiency of inter-core communication and effectively reduces the computing load of each computing core module during the inter-core communication process.

[0062] Based on the above embodiments, the interrupt generation unit 120 can be specifically used for:

[0063] When the data control interface 160 of the processor unit 110 detects that data is written to the end address of the target storage subunit, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit 130 .

[0064] In this optional embodiment, when the interrupt generation unit 120 detects that the current write data points to the last address of a storage subunit (i.e., the target storage subunit) in combination with the pre-stored address range of each storage subunit, it can determine that the processor unit 110 needs to read the data in the target storage subunit to avoid data loss or inability to continue caching. At this time, a target interrupt signal for the target storage subunit can be generated accordingly.

[0065] Based on the above embodiments, the interrupt generation unit 120 may be further used for:

[0066] When the data control interface 160 of the processor unit 110 detects that the amount of data written to the target storage subunit exceeds a preset data amount threshold, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit 130 .

[0067] In this embodiment, the inventor further considers that the amount of a single communication data sent by other computing core modules to this computing core module may not fill the entire storage subunit. That is, a single communication data cannot be stored to the last storage address of the storage subunit. At this time, the interrupt signal generation logic of the processor unit 110 can be flexibly set according to the actual communication scenario.

[0068] Specifically, in an actual communication scenario, the average data volume of a single communication can be obtained, and a data volume threshold can be set based on the average data volume. Furthermore, when the processor unit 110 detects that the amount of data currently written to a storage subunit (i.e., a target storage subunit) exceeds a preset data volume threshold (e.g., more than 60% or more than 100B, etc.) in combination with the pre-stored address range of each storage subunit, it determines that the processor unit 110 needs to read the data in the target storage subunit, and at this time, a target interrupt signal for the target storage subunit can be generated accordingly.

[0069] Based on the above embodiments, the interrupt generation unit may also be used for:

[0070] When it is detected at the data control interface 160 of the processor unit 110 that the writing of the entire data to the target storage subunit has been completed and the preset waiting time has passed since the writing completion time point, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit 130.

[0071] In this embodiment, the size of each cache space can be set to be larger than the amount of any single communication data, and then, each single communication data sent by other computing core modules can be completely stored in a storage sub-unit of this computing core module. Furthermore, the processor unit 110 can detect that a communication data currently continuously written to a certain storage sub-unit (that is, the target storage sub-unit) has been written in combination with the address range of each storage sub-unit stored in advance, and when a set time has passed since the last write time, for example, 3 clock cycles or 5 clock cycles, etc., it is determined that the processor unit 110 needs to read the data in the target storage sub-unit. At this time, a target interrupt signal for the target storage sub-unit can be generated accordingly.

[0072] Through the above settings, a computing core module can adaptively determine the optimal hard interrupt generation logic according to actual conditions to adapt to flexible and changeable multi-core communication scenarios.

[0073] The interrupt control unit 130 is disposed inside the processor unit 110 and is used to control the processor unit 110 to read data from the target storage subunit for processing according to the target interrupt signal.

[0074] In actual application scenarios, such as Figure 1 As shown, most types of processor units have an interrupt control unit inside, while some types of processor units may not have an interrupt control unit themselves. Furthermore, the interrupt control unit 130 can be configured inside the processor unit 110, and in rare cases, it is set outside to respond to interrupt signals (not shown in the figure).

[0075] Specifically, after the interrupt control unit 130 receives a target interrupt signal for the target storage sub-unit, it can instruct the processor unit 110 to read all the data currently cached in the target storage sub-unit starting from the first address of the target storage sub-unit for processing, and correspondingly clear the target storage sub-unit so that other computing core modules that are compatible with the target storage sub-unit can continue to write new communication data to the target storage sub-unit.

[0076] The technical solution of the embodiment of the present invention is to set an interrupt generation unit and a storage subunit that independently stores data written to this module by other computing core modules in the computing core module. When the interrupt generation unit detects at the data control interface in the computing core module that the data written to the target storage subunit meets the read condition, it automatically generates a target interrupt signal for the target storage subunit to control the processor unit to read data from the target storage subunit for processing. A multi-core communication method implemented by automatic hardware interrupt generation is creatively proposed, which effectively reduces the number of information exchanges in the multi-core communication process. In particular, in application scenarios where inter-core communication is frequent and real-time requirements are high, the multi-core communication method of the embodiment of the present invention can reduce the load of the computing core module and significantly improve the efficiency of inter-core communication.

[0077] Figure 2 A structural diagram of a multi-core communication system provided by an embodiment of the present invention. Specifically, Figure 2 As shown, the multi-core communication system specifically includes: a plurality of computing core modules 210 as described in any one of the embodiments of the present invention.

[0078] Among them, each computing core module 210 (that is, Figure 2 A communication connection is established between the computing core modules 1, ..., computing core modules N) through the bus 220, and the number of storage subunits 240 included in the storage unit 230 of each computing core module 210 is the total number of computing core modules 210 included in the multi-core communication system minus one.

[0079] In this embodiment, the multi-core communication system includes a total of N computing core modules 210, and further, the storage unit 230 in each computing core module 210 includes a total of N-1 storage sub-units 240, that is, storage sub-unit 1, storage sub-unit 2, ..., storage sub-unit N-1.

[0080] Taking computing core module 1 as an example, in the storage unit of computing core module 1, storage subunit 1 is used to cache the communication data written to computing core module 1 by computing core module 2, storage subunit 2 is used to cache the communication data written to computing core module 1 by computing core module 3, and so on. Storage subunit N-1 is used to cache the communication data written to computing core module 1 by computing core module N.

[0081] In an optional implementation of this embodiment, the processor units included in each computing core module are homogeneous or heterogeneous processor units. That is, each computing core module of the multi-core communication system may include a CPU unit, or a part of the computing core modules of the multi-core communication system may include a CPU unit, and another computing core module may include an NPU unit, etc.

[0082] In fact, the embodiments of the present invention do not limit the type and performance of the processor units contained in each computing core module in the multi-core communication system, as long as each computing core module can generate a hard interrupt and has an independent storage unit for separately caching communication data between different computing core modules.

[0083] Further, in Figure 3 FIG. 2 shows a structural diagram of a multi-core communication system composed of four isomorphic computing core modules applicable to an embodiment of the present invention. Figure 3 As shown, the multi-core communication system includes four computing core modules, each of which includes a CPU unit (i.e., processor unit), namely CPU0, CPU1, CPU2, and CPU3. In each CPU unit, a slave interface is used as a data control interface, and each slave interface establishes a communication connection through a bus. Inside each CPU unit, there is an EVIC (External Vector Interrupt Controller) for implementing interrupt detection and interrupt processing functions. In addition, an independent storage space is set in the TCM space inside each CPU unit to cache the communication data written by other CPU units.

[0084] Specifically, message_cpu1 in the TCM space of CPU0 is used to cache the communication data written by CPU1 to CPU0, message_cpu2 in the TCM space of CPU0 is used to cache the communication data written by CPU2 to CPU0, message_cpu3 in the TCM space of CPU0 is used to cache the communication data written by CPU3 to CPU0, and so on, which will not be repeated hereafter.

[0085] In addition, in each computing core module, an interrupt generation unit corresponding to the CPU unit is provided, namely, an Intr_gen unit. The Intr_gen unit is respectively connected to the EVIC of the CPU unit and the slave device interface, and is used to generate a target interrupt signal (typically, a pulse interrupt) for the target storage subunit when it is detected at the data control interface of the processor unit that the data written to the target storage subunit meets the read condition, and send the target interrupt signal to the interrupt control unit.

[0086] In actual use, the user can divide the TCM space of each CPU unit into storage unit intervals corresponding to other CPU units (that is, message_cpu0, message_cpu1, message_cpu2 and message_cpu3), and write the end address of each address segment to the inter_gen register exclusive to each CPU unit for interrupt generation judgment.

[0087] Among them, the above-mentioned message_cpu0, message_cpu1, message_cpu2 and message_cpu3 are all storage areas with write-only permissions, which are used to receive communication information sent by other computing core modules. When other computing core modules send messages to write the last address of a message storage space in the current CPU unit, Inter_gen identifies the address and write operation signal written to the TCM space through the slave interface, automatically generates an interrupt in advance, and notifies the current CPU unit through the EVIC interface of the CPU unit. The current CPU unit can quickly respond to the interrupt, read the corresponding TCM area, receive the message, and complete the current communication.

[0088] That is, use the source CPU unit to write communication information to the corresponding memory address of the destination CPU unit. At this time, the Intr_gen unit of the destination CPU unit will automatically generate a pulse interrupt to inform the destination CPU unit. The destination CPU unit goes to the address segment corresponding to the interrupt to obtain data. After taking the data out, it performs subsequent processing to complete the inter-core communication task.

[0089] It can be understood that the solution of the embodiment of the present invention has the characteristics that the storage units are independent of each other and the address range can be freely configured, and the interrupts are automatically generated by hardware. It can be used in multi-core communication scenarios, which helps to improve the efficiency of inter-core communication.

[0090] Figure 4 A flowchart for implementing a multi-core communication method provided in an embodiment of the present invention. This embodiment can be applied to implementing multi-core communication between a single computing core module and one or more computing core modules. The technical solution of this embodiment can be applied to the aforementioned multi-core communication system.

[0091] Correspondingly, such as Figure 4 As shown, the method may specifically include:

[0092] S410. The first computing core module sends a single set of first data to at least one second computing core module through a bus, where each data item in the first data includes a data write address.

[0093] In this embodiment, each computing core module implements a single inter-core communication by sending a piece of data each time, wherein a piece of data can be understood as a continuously sent data stream, and each piece of data includes multiple data items.

[0094] Among them, when the first computing core module sends a single data to only one second computing core module, it is equivalent to realizing one-to-one inter-core communication based on the multi-core communication system; when the first computing core module sends a single data to multiple second computing core modules, it is equivalent to realizing one-to-many inter-core communication based on the multi-core communication system.

[0095] S420. The processor unit in each second computing core module stores each data item in the first data obtained from the data control interface in the first storage sub-unit matching the first computing core module in the internal storage unit according to the data write address.

[0096] It can be understood that when the processor unit in each second computing core module receives each data item in a data sent via the bus from the data control interface, it can write each data item into the first storage sub-unit pre-divided for the first computing core module based on the data write address contained in each data item.

[0097] S430. The interrupt generation unit in each second computing core module generates a first interrupt signal for the first storage subunit when it detects at the data control interface of this module that each data item written to the first storage subunit meets the read condition, and sends the first interrupt signal to the interrupt control unit of this module.

[0098] Specifically, the interrupt generation unit in each second computing core module can generate a pulse interrupt signal matching the first storage subunit, that is, a first interrupt signal, and send the first interrupt signal to the interrupt control unit of this module when it detects that a data item is written to the termination address of the first storage subunit, the amount of data written to the first storage subunit exceeds a preset data amount threshold, or the entire data has been written to the first storage subunit, and a preset waiting time has passed since the writing completion time point.

[0099] S440. The interrupt control unit in each second computing core module controls the processor unit of the module to read each data item from the internal first storage subunit for processing according to the first interrupt signal.

[0100] In this embodiment, whenever the interrupt control unit in the second computing core module receives a first interrupt signal, it can obtain the currently written data from the address segment of the first storage sub-unit that matches the first interrupt signal, and clear the first storage sub-unit to continue to receive new communication data sent by the first computing core module.

[0101] The technical solution of the embodiment of the present invention can effectively reduce the number of information interactions during multi-core communication. In application scenarios where inter-core communication is frequent and has high real-time requirements, it can effectively reduce the load on the computing core module and significantly improve the efficiency of inter-core communication.

[0102] In normal inter-core communication, each CPU can act as the source CPU unit and the destination CPU unit, and can perform 1-to-1, 1-to-many, many-to-1, and many-to-many communications. In 1-to-many, many-to-1, and many-to-many inter-core communications, all information can be communicated at the same time, and there is no need to wait for one of the CPU units to complete the communication before moving on to the next CPU unit. However, due to the characteristics of the CPU, each piece of information is sent, received, and processed in order.

[0103] Specifically, in Figure 5 FIG. 2 shows a data flow diagram of a one-to-one inter-core communication applicable to an embodiment of the present invention. Figure 5As shown, CPU0, as the source CPU unit, writes the communication information to the destination CPU unit, that is, the message_cpu0 storage subunit in the TCM of CPU1, through the BUS bus. When the communication data is written to the end address of the message_cpu0 storage subunit, the Intr_gen unit adapted to CPU1 will generate a hardware interrupt, and inform CPU1 through the EVIC of the destination CPU1. After receiving this hardware interrupt, CPU1 will go to the message_cpu0 storage subunit in the storage address segment corresponding to CPU0 in CPU1 to read the data written by CPU0 and perform data processing. The single inter-core communication is completed.

[0104] In another example, Figure 6 FIG. 2 shows another data flow diagram of one-to-one inter-core communication applicable to an embodiment of the present invention. Figure 6 As shown in the figure, when CPU1 is used as the source CPU unit for inter-core communication and CPU0 is used as the destination CPU unit for inter-core communication, the data processing process is the same as Figure 5 The processes shown are consistent. CPU1 writes the communication information to the message_cpu1 storage subunit in the TCM of CPU0 through the BUS bus. When the communication data is written to the end address of the message_cpu1 storage subunit, the Intr_gen unit adapted to CPU0 generates a hardware interrupt and informs CPU0 through the EVIC of CPU0. After receiving the hardware interrupt, CPU0 goes to the message_cpu1 storage subunit in the storage address segment corresponding to CPU1 in CPU0 to read the data written by CPU1 and process the data. The single inter-core communication is completed.

[0105] Further, in Figure 7 FIG. 2 shows a schematic diagram of data flow for one-to-many core communication applicable to an embodiment of the present invention. Specifically, Figure 7As shown, CPU0, as the source CPU unit, writes the communication information to the destination CPU unit, that is, the message_cpu0 storage subunit in the TCM of CPU1, CPU2, and CPU3 in sequence through the BUS bus. When the communication data is written to the end address of each message_cpu0 storage subunit, the Intr_gen unit of each destination CPU unit (CPU1, CPU2, and CPU3) will generate a hardware interrupt, and the interrupt signal will inform the destination CPU unit (CPU1, CPU2, and CPU3) through the EVIC of the destination CPU unit (CPU1, CPU2, and CPU3). After receiving the interrupt, the destination CPU unit (CPU1, CPU2, and CPU3) will go to the storage address segment message_cpu0 storage subunit corresponding to CPU0 in the destination CPU unit to read the data written by CPU0 and perform data processing, and a single inter-core communication is completed.

[0106] Figure 8 A flowchart for implementing another multi-core communication method provided in an embodiment of the present invention. This embodiment can be applied to the situation where multi-core communication is implemented between multiple computing core modules and one or more computing core modules. The technical solution of this embodiment can be applied to the aforementioned multi-core communication system.

[0107] Correspondingly, such as Figure 8 As shown, the method may specifically include:

[0108] S810. Multiple third computing core modules respectively send second data to a data control interface of at least one fourth computing core module through a bus, where each data item in the second data includes a data write address.

[0109] Among them, when multiple third computing core modules send a single data to only one fourth computing core module, it is equivalent to realizing many-to-1 inter-core communication based on the multi-core communication system; when multiple third computing core modules send a single data to multiple fourth computing core modules, it is equivalent to realizing many-to-many inter-core communication based on the multi-core communication system.

[0110] S820. The processor unit in each fourth computing core module stores each data item in the second data sent by each third computing core module obtained from the data control interface in a second storage sub-unit in the internal storage unit that matches each third computing core module respectively according to the data write address.

[0111] It can be understood that when the processor unit in each fourth computing core module receives each data item in a data sent via the bus from the data control interface, it can write each data item into the second storage sub-unit pre-allocated for each third computing core module based on the data write address contained in each data item.

[0112] It can be understood that when the number of the third computing core modules is multiple, the number of the second storage sub-units is also multiple.

[0113] S830. The interrupt generation unit in each fourth computing core module generates a second interrupt signal for the target second storage subunit whenever it is detected at the data control interface of this module that each data item written to the target second storage subunit meets the read condition, and sends the second interrupt signal to the interrupt control unit of this module.

[0114] Specifically, the interrupt generation unit in each fourth computing core module can generate a pulse interrupt signal matching the target second storage subunit, that is, a second interrupt signal, and send the second interrupt signal to the interrupt control unit of this module when it detects that a data item is written to the termination address of the target second storage subunit, the amount of data written to the target second storage subunit exceeds a preset data amount threshold, or the entire data has been written to the target second storage subunit, and a preset waiting time has passed since the writing completion time point.

[0115] S840. The interrupt control unit in each fourth computing core module controls the processor unit of the module to read each data item from the internal target second storage sub-unit for processing according to the second interrupt signal.

[0116] In this embodiment, whenever the interrupt control unit in the fourth computing core module receives a second interrupt signal, it can obtain the currently written data from the address segment of the target second storage sub-unit that matches the second interrupt signal, and clear the target second storage sub-unit to continue to receive new communication data sent by the third computing core module that matches the target second storage sub-unit.

[0117] The technical solution of the embodiment of the present invention can effectively reduce the number of information interactions during multi-core communication. In application scenarios where inter-core communication is frequent and has high real-time requirements, it can effectively reduce the load on the computing core module and significantly improve the efficiency of inter-core communication.

[0118] Fig. 9 Schematic diagram of data flow of a multi-to-one inter-core communication applicable to an embodiment of the present invention. Fig. 9As shown, CPU1, CPU2 and CPU3 are all source CPU units, and write communication information to the destination CPU unit, that is, the matching storage subunit in the TCM of CPU0, through the BUS bus. Specifically, CPU1 writes communication data to the message_cpu1 storage subunit in the TCM of CPU0, CPU2 writes communication data to the message_cpu2 storage subunit in the TCM cache of CPU0, and CPU3 writes communication data to the message_cpu3 storage subunit in the TCM cache of CPU0. When the communication data of each source CPU unit (CPU1, CPU2 and CPU3) is written to the termination address in the matching storage sub-unit, the Intr_gen unit of CPU0 will generate a corresponding hardware interrupt (that is, there are 3 interrupts for 3 source CPU units). The interrupt signal notifies CPU0 through the EVIC module of CPU0. After receiving the interrupt, CPU0 goes to the cache address segment corresponding to the source CPU unit (CPU1, CPU2 and CPU3) in CPU0 to read the data written by the source CPU unit (CPU1, CPU2 and CPU3) and perform data processing. Then, a single inter-core communication is completed.

[0119] Further, in Fig.10 FIG. 2 shows a data flow diagram of a multi-to-multi-core communication applicable to an embodiment of the present invention. Fig.10 As shown, a single source CPU unit, i.e., CPU0, initiates inter-core communication to the destination CPU units, i.e., CPU1, CPU2, and CPU3. The communication process is similar to that shown in FIG. Figure 7 At the same time, there is another communication, multiple source CPU units, namely CPU0, CPU2 and CPU3, initiate inter-core communication to the destination unit, namely CPU1. The communication process is similar to Fig. 9 The communication process shown is similar. That is, in a many-to-many inter-core communication scenario, any two CPU units can communicate with each other at any time, and the communication time is not prioritized.

[0120] exist Fig.11 FIG. 1 shows a schematic diagram of a vehicle structure to which an embodiment of the present invention is applicable. Fig.11 As shown, the vehicle includes: a multi-core communication system 1101 as described in any one of the embodiments of the present invention.

[0121] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0122] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A computing core module, characterized in that: include: Processor units and interrupt generation units connected in pairs; wherein the processor unit includes a storage unit, in which at least one storage sub-unit is pre-divided, and one storage sub-unit is used to independently store data written to this module by another computing core module; In the interrupt generation unit, the address range of each storage sub-unit is pre-stored; An interrupt generation unit, configured to generate a target interrupt signal for the target storage subunit when detecting at the data control interface of the processor unit that the data written to the target storage subunit meets the read condition, and send the target interrupt signal to the interrupt control unit; The interrupt control unit is arranged inside the processing unit, and is used to control the processor unit to read data from the target storage subunit for processing according to the target interrupt signal.

2. The computing core module according to claim 1, characterized in that: The interrupt generation unit is specifically used for: When it is detected at the data control interface of the processor unit that data is written to the termination address of the target storage subunit, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit.

3. The computing core module according to claim 1, characterized in that: The interrupt generation unit is specifically used for: When it is detected at the data control interface of the processor unit that the amount of data written to the target storage subunit exceeds a preset data amount threshold, a target interrupt signal for the target storage subunit is generated and sent to the interrupt control unit.

4. The computing core module according to claim 1, characterized in that: The interrupt generation unit is specifically used for: When it is detected at the data control interface of the processor unit that the writing of the entire data to the target storage sub-unit has been completed and the preset waiting time has passed since the writing completion time point, a target interrupt signal for the target storage sub-unit is generated and sent to the interrupt control unit.

5. The computing core module according to claim 1, characterized in that: The storage unit is a storage space divided in the tightly coupled memory inside the processor unit; The processor unit includes a central processing unit, a graphics processing unit or a neural network processor.

6. A multi-core communication system, characterized in that: comprising a plurality of computing core modules as described in any one of claims 1 to 5; Among them, the computing core modules establish communication connections through a bus, and the number of storage sub-units contained in the storage unit of each computing core module is the total number of computing core modules contained in the multi-core communication system minus one.

7. The multi-core communication system according to claim 6, characterized in that: The processor units included in each computing core module are homogeneous or heterogeneous processor units.

8. A multi-core communication method, characterized in that: Applied in the multi-core communication system as claimed in claim 6 or 7, the method comprises: The first computing core module sends a single first data to at least one second computing core module via a bus, where each data item in the first data includes a data write address; The processor unit in each second computing core module stores each data item in the first data obtained from the data control interface into a first storage subunit matching the first computing core module in the internal storage unit according to the data write address; The interrupt generation unit in each second computing core module generates a first interrupt signal for the first storage subunit when detecting at the data control interface of the module that each data item written to the first storage subunit meets the read condition, and sends the first interrupt signal to the interrupt control unit of the module; The interrupt control unit in each second computing core module controls the processor unit of this module to read each data item from the internal first storage subunit for processing according to the first interrupt signal.

9. A multi-core communication method, characterized in that: Applied in the multi-core communication system as claimed in claim 4 or 5, the method comprises: The plurality of third computing core modules respectively send second data to the data control interface of at least one fourth computing core module through the bus, wherein each data item in the second data includes a data write address; The processor unit in each fourth computing core module stores each data item in the second data sent by each third computing core module obtained from the data control interface into a second storage sub-unit in the internal storage unit that matches each third computing core module respectively according to the data write address; The interrupt generation unit in each fourth computing core module generates a second interrupt signal for the target second storage subunit whenever it is detected at the data control interface of the module that each data item written to the target second storage subunit meets the read condition, and sends the second interrupt signal to the interrupt control unit of the module; The interrupt control unit in each fourth computing core module controls the processor unit of this module to read each data item from the internal target second storage subunit for processing according to the second interrupt signal.

10. A vehicle, characterized in that: Comprising a multi-core communication system as claimed in claim 6 or 7.

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