Service life evaluation method and equipment for satellite-borne SIP device

Abstract

The invention provides a method and equipment for evaluating the service life of a satellite-borne SIP device. The method comprises the following steps: determining each key structure for evaluating the service life in the satellite-borne SIP device; based on the use environment stress and failure mechanism of each key structure, establishing a failure physical model corresponding to each key structure; based on a Monte Carlo method, sampling the geometric dimension parameters of the key structures to obtain parameter samples of the key structures; substituting each parameter sample into a corresponding failure physical model to obtain life data corresponding to each key structure; based on each piece of life data, fitting to obtain a life probability density function of each key structure; obtaining the service life of each key structure based on each service life probability density function; and evaluating the service life of the satellite-borne SIP device based on the service life of each key structure, thereby realizing the reliability evaluation of the satellite-borne SIP device based on the competition failure theory.

Description

Technical Field

[0001] The present invention relates to the technical field of satellite-borne SIP devices, and in particular to a life assessment method and device for satellite-borne SIP devices. Background Art

[0002] At present, System In a Package (SIP) devices are increasingly used in aerospace electronic products. However, it is difficult to evaluate the reliability of SIP devices due to their complex structure, the large number of failure mechanisms and failure modes involved, and their customization, small batch size, and special structure.

[0003] At present, in order to evaluate the reliability of SIP devices, the patent "CN108460209A" discloses a FMEA analysis method and system for aerospace SiP devices. According to the composition structure of aerospace SiP devices, the method hierarchically defines each module of aerospace SiP devices, analyzes the potential failure mode of each module of aerospace SiP devices, analyzes the failure cause and mechanism of each potential failure mode, and obtains the first analysis result; analyzes the failure impact and severity of each potential failure mode to obtain the second analysis result; outputs the FMEA analysis result table according to the first analysis result and the second analysis result. However, the failure of a complex system is not the result of a single failure mode. The occurrence of any failure mode will lead to system failure. This method does not take into account the life evaluation of SIP devices.

[0004] Patent "CN112016227A" discloses a reliability analysis method and process for a high-reliability SiP. According to the design rules, a finite element analysis model is established. According to the first test condition, a simulation link is built, reasonable boundary conditions are set, test loads are applied, calculations are solved, and the results are analyzed according to the failure criteria. The simulation link is built, and simulation calculations of all test items are performed in sequence and the results are analyzed according to the failure criteria; weak links are found according to the analysis results. However, this method also does not take into account the life evaluation of SIP devices and does not quantify the results.

[0005] Patent "CN110222428A" discloses a reliability analysis system and method for system-level package (SIP) devices. This method uses real test data to continuously compare, verify and correct finite element simulation data. Through the simulation sampling of the simulation system with real experimental data, the data is closer to the standard value, and the calculation cycle and test cost are greatly shortened. However, this method requires certain real test data. However, satellite-borne SIP devices have the characteristics of customization, small batches, special structures, etc., which make it difficult to use this method for comparison, verification and correction.

[0006] In summary, there is currently a lack of effective solutions for evaluating the reliability of space-borne SIP devices. Summary of the invention

[0007] The present invention provides a life assessment method and device for a satellite-borne SIP device, which solves the technical problem in the prior art that the reliability of the satellite-borne SIP device cannot be effectively assessed.

[0008] In one aspect, the present invention provides a method for evaluating the life of a satellite-borne SIP device, comprising:

[0009] Identify the key structures in spaceborne SIP devices for lifetime assessment;

[0010] Based on the use environment stress and failure mechanism of each of the key structures, a failure physical model corresponding to each of the key structures is established;

[0011] Based on the Monte Carlo method, sampling the geometrical dimension parameters of each of the key structures is performed to obtain parameter samples of each of the key structures;

[0012] Substituting each of the parameter samples into a corresponding failure physical model to obtain life data corresponding to each of the key structures;

[0013] Based on the lifetime data, a lifetime probability density function of each of the key structures is obtained by fitting;

[0014] Based on the lifetime probability density functions, the lifetime of each of the key structures is obtained;

[0015] The life of the onboard SIP device is evaluated based on the life of each of the key structures.

[0016] On the other hand, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a life assessment method for a satellite-borne SIP device as described above is implemented.

[0017] The life evaluation method and device of a satellite-borne SIP device provided by the present invention determine each key structure used for life evaluation in the satellite-borne SIP device; establish a failure physical model corresponding to each key structure based on the use environment stress and failure mechanism of each key structure; sample the geometric size parameters of each key structure based on the Monte Carlo method to obtain parameter samples of each key structure; substitute each parameter sample into the corresponding failure physical model to obtain life data corresponding to each key structure; obtain the life probability density function of each key structure based on each life data; obtain the life of each key structure based on each life probability density function; evaluate the life of the satellite-borne SIP device based on the life of each key structure, and realize the reliability evaluation of the satellite-borne SIP device based on the competitive failure theory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of a life assessment method of a satellite-borne SIP device provided by an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a satellite-borne SIP device provided in an embodiment of the present invention;

[0021] Figure 3 Schematic diagram of the probability density function of electromigration life of a satellite-borne SIP device chip provided by an embodiment of the present invention;

[0022] Figure 4 Schematic diagram of a probability density function of the breakdown lifetime of a gate oxide layer of a satellite-borne SIP device chip according to an embodiment of the present invention;

[0023] Figure 5 Schematic diagram of the probability density function of the via life of a satellite-borne SIP device provided by an embodiment of the present invention;

[0024] Figure 6 Schematic diagram of the probability density function of shear fatigue failure life of the pad of a satellite-borne SIP device provided by an embodiment of the present invention;

[0025] Figure 7 Schematic diagram of the probability density function of bending fatigue life of bonding wires of a satellite-borne SIP device provided by an embodiment of the present invention;

[0026] Figure 8 Schematic diagram of the probability density of shear fatigue life of bonding wires of a satellite-borne SIP device provided by an embodiment of the present invention;

[0027] Fig. 9 Schematic diagram of the probability density function of thermal fatigue life of micro-bumps of a satellite-borne SIP device provided by an embodiment of the present invention;

[0028] Fig.10 Schematic diagram of a probability density function of fatigue life of an adhesive layer of a satellite-borne SIP device provided by an embodiment of the present invention;

[0029] Fig.11 is a schematic diagram of a probability density function of random vibration life of a satellite-borne SIP device package provided by an embodiment of the present invention;

[0030] Fig.12 is a schematic diagram of a probability density function of thermal fatigue life of a satellite-borne SIP device package provided by an embodiment of the present invention;

[0031] Fig.13 is a schematic diagram of the proportion of device failure caused by various failure mechanisms provided in an embodiment of the present invention;

[0032] Fig.14 It is a schematic diagram of a multi-failure mechanism competition failure model of a satellite-borne SIP device provided by an embodiment of the present invention;

[0033] Fig.15 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Figure 1 It is a flow chart of a life assessment method for a satellite-borne SIP device provided in an embodiment of the present invention. Figure 2 It is a schematic diagram of the structure of a satellite-borne SIP device provided in an embodiment of the present invention. Figure 2 The satellite-borne SIP device may include a housing 1, external leads 2, chip lead bonding 3, active device assembly 4, active devices 5, passive device assembly 6, passive devices 7, flip-chip soldering process 8, flip-chip 9, through silicon via (TSV) silicon transfer substrate 10, low temperature co-fired ceramic (LTCC) substrate 11, external lead bonding 12, sealing cap 13, seam welding ring 14 and other components. Figure 1 The life assessment method of a satellite-borne SIP device may include the following steps 101 to 107.

[0036] 101. Identify the key structures in the onboard SIP device for evaluating its lifespan.

[0037] In this step, the key structure may include at least one of a chip structure, a substrate structure, a bonding wire structure, a flip-chip structure, a through silicon via structure, a welding layer, a tube shell package, a potting plastic, and a lead-out structure. The structures that affect the life can be obtained as key structures based on the failure history data of the satellite-borne SIP device, or based on the experience of the technicians, the structures that affect the life can be obtained as key structures.

[0038] 102. Based on the operating environment stress and failure mechanism of each key structure, establish the corresponding failure physical model of each key structure.

[0039] In this step, the use environment stress may refer to various stresses that the key structure is subjected to in a specific use environment, such as temperature, humidity, vibration, thermal cycle and space radiation, etc. These stresses will accelerate the exposure of potential defects of the product and help discover bad parts and process defects. The failure mechanism may refer to the specific physical, chemical or electrical process that causes the failure of the key structure. Different failure modes may have different failure mechanisms. For example, mechanical fracture may be caused by material fatigue, while short circuit of electronic equipment may be due to circuit design defects. The stress type conditions that the onboard SIP device may be subjected to in the use environment can be analyzed, and the main failure modes and failure mechanisms of each key structure of the SIP device in the use environment can be sorted out. The failure physics model is used to evaluate the life data of the corresponding key structure. Life data can also be understood as failure time. The earlier the failure time, or the smaller the failure time, the shorter the life.

[0040] The failure mechanism of the chip structure may include chip electromigration failure and chip gate oxide layer failure. The failure mechanism of the substrate structure may include thermal fatigue failure of the substrate electroplated through hole. The failure mechanism of the welding layer may include pad shear fatigue. The failure mechanism of the bonding wire structure may include bonding wire bending fatigue failure and bonding wire shear fatigue failure. The failure mechanism of the flip-chip structure may include micro-bump thermal fatigue failure. The failure mechanism of the through-silicon via structure may include adhesive layer fatigue fracture failure. The failure mechanism of the shell and tube package may include random vibration failure of the package body and thermal fatigue failure of the package body. It is also possible to establish a failure physical model corresponding to each key structure based on the use environment stress or failure mechanism of each key structure.

[0041] It can be understood that when introducing each model, the parameters described in the model are the parameters of the key structure corresponding to the model. For example, based on the use environment stress and failure mechanism of each key structure, the failure physical model corresponding to each key structure is established, which may include:

[0042] The chip electromigration failure model of the chip structure can be established by the following formula, as shown in formula (1).

[0043]

[0044] Wherein, W is the width of the chip metallization layer (the width here can also be understood as the length, and the specific width direction can be defined according to the actual situation, and is not specifically limited here); d is the thickness of the chip metallization layer; T is the temperature of the chip; C" is the constant of the diffusion activation energy of the metal film structure of the chip; j is the current density of the metallization layer of the chip; k is the Boltzmann constant of the chip; E ais the activation energy of the metallization material of the chip; MTTF is the mean time to failure of the chip, in hours. The Ea parameter selection table is shown in Table 1.

[0045] Table 1

[0046]

[0047] 103. Based on the Monte Carlo method, the geometric size parameters of each key structure are sampled to obtain the parameter samples of each key structure.

[0048] In this step, it is assumed that the chip metallization layer width of the satellite-borne SIP device is 0.0015mm, the chip metallization layer thickness is 0.0005mm, the temperature is 300K, and the metallization layer current density is 100000A / mm 2 , the activation energy of the metallization material is 0.6eV.

[0049] 104. Substitute each parameter sample into the corresponding failure physical model to obtain the life data corresponding to each key structure.

[0050] 105. Based on the life data, the life probability density function of each key structure is fitted.

[0051] In this step, for example, a total of 5000 Monte Carlo simulations are performed, and the probability density function image (unit: h) of the chip life before electromigration failure is obtained as follows: Figure 3 shown.

[0052] 106. Based on the probability density functions of each life span, the life span of each key structure is obtained.

[0053] In this step, based on Figure 3 The probability density function image of the chip life before electromigration failure is shown. The average and median values ​​of the electromigration life of the satellite-borne SIP device chip are both 2472h.

[0054] 107. Evaluate the life of the onboard SIP device based on the life of each key structure.

[0055] In this embodiment, each key structure in the onboard SIP device for evaluating the life is determined; based on the use environment stress and failure mechanism of each key structure, a failure physical model corresponding to each key structure is established; based on the Monte Carlo method, the geometric size parameters of each key structure are sampled to obtain parameter samples of each key structure; each parameter sample is substituted into the corresponding failure physical model to obtain the life data corresponding to each key structure; based on each life data, the life probability density function of each key structure is fitted; based on each life probability density function, the life of each key structure is obtained; based on the life probability density function, the life of each key structure is evaluated based on the life of each key structure, and the reliability evaluation of the onboard SIP device based on the competitive failure theory is realized.

[0056] In one embodiment of the present specification, the failure mechanism of the chip structure includes the failure of the chip gate oxide layer; based on the use environment stress and failure mechanism of each key structure, a failure physical model corresponding to each key structure is established, which may include:

[0057] When the electric field strength of the chip structure environment is greater than the preset electric field threshold, the chip gate oxide failure model of the chip structure is established by the following formula, which is also called the hole breakdown model, and is based on the Fowler-Nordheim tunneling current, as shown in the following formula (2). The preset electric field threshold can be 5MV / cm, or can be adjusted according to actual needs.

[0058] MTTF = τexp(G / E OX )exp(E a / kT)(2).

[0059] Among them, E in formula (2) ox =E / L, τ is the proportional constant determined by the material and process of the chip gate oxide layer; G is the electric field acceleration factor of the chip gate oxide layer; L is the effective oxide layer thickness of the chip gate oxide layer, in mm; E is the gate voltage of the chip, in V; Ea is the activation energy of the chip dielectric layer material, in eV; E OX is the external electric field on the chip gate oxide layer, in V / mm; T is the temperature of the chip, in K; k is the Boltzmann constant of the chip, usually 1.381×10 -23 J / K. The meanings of other parameters can refer to the above.

[0060] When the electric field strength of the chip structure is less than or equal to the preset electric field threshold, the chip gate oxide failure model of the chip structure is established by the following formula. This model is also called the thermochemical breakdown model (also called the E model), which is a molecular model based on the breaking of covalent bonds, as shown in the following formula (3):

[0061] MTTF = b1 × τexp(-γE OX )exp(E a / kT) (3).

[0062] Among them, b1 is the model breakdown coefficient, with a value range of (0 to 1); γ is the electric field acceleration factor, with the unit of mm / V. The meanings of the remaining parameters can be referred to above. The failure time distribution of this failure physics evaluation is a Weibull distribution, and the specific parameters can be obtained from the statistical results.

[0063] In this embodiment, for example, the chip gate voltage of the satellite SIP is 5V, the effective oxide thickness of the chip is 0.00001mm, the temperature is 300K, the activation energy of the metallization material is 0.75eV, and the remaining parameters are taken according to the model constants. For example, a total of 5000 Monte Carlo simulations were performed, and the probability density function image (unit: h) of the chip gate oxide layer life before breakdown failure is shown as follows: Figure 4 As shown, the calculated average time-dependent breakdown lifetime of the gate oxide layer of the satellite-borne SIP device chip is 7604h, and the median is 7477h.

[0064] In one embodiment of the present specification, the critical structure may include a substrate structure, and the failure mechanism of the substrate structure may include thermal fatigue failure of a substrate plated through hole;

[0065] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0066] The fatigue failure model of the plated through hole of the substrate structure is established by the following formula, as shown in the following formula (4).

[0067]

[0068] Among them, Δε is the total strain amplitude; σ f is fatigue strength; f is the fatigue ductility coefficient; b2 is the fatigue strength index; c is the fatigue ductility index; σ0 is the average stress; E1 is the elastic modulus; N f1 is the number of cycles before failure.

[0069] In this embodiment, for example, the ceramic substrate of the satellite-borne SIP device is a HTCC ceramic substrate, the through hole diameter on the substrate is 75 μm, the maximum through hole depth is 3.25 mm, and the through hole diameter is 75 μm and the depth is 3.25 mm. Based on this, ansys simulation is performed to fit the relationship between the through hole average stress σ0, the total strain amplitude Δε and the through hole diameter d, as shown in the following formulas (5) and (6):

[0070] σ0=-199.4d+128.89(5);

[0071] Δε=-3.65×10 -4 d+2.1641×10 -3 (6).

[0072] For example, a total of 5000 Monte Carlo simulations were performed to obtain the number of cycles before through-hole failure N f The probability density function image of (unit: 1) is as follows Figure 5 As shown, the median and average values ​​of the through-hole life of the satellite-borne SIP device (model 6117SRSC) are calculated to be 2444 cycles.

[0073] In one embodiment of the present specification, the critical structure may include a welding layer, and the failure mechanism of the welding layer may include pad shear fatigue;

[0074] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0075] The failure model of pad shear fatigue of the welding layer is established by the following formula, as shown in the following formula (7).

[0076]

[0077] Among them, C p’ is the shear fatigue coefficient of the pad material; m p’ is the shear fatigue index of the pad material; G p is the shear elastic modulus of the pad material; b p is the pad thickness; b s is the substrate thickness; r is the cross-sectional radius of the lead; E s is the elastic modulus of the substrate material; E w is the elastic modulus of the lead material; E p is the elastic modulus of the pad material, in Pa; α s is the thermal expansion coefficient of the substrate material; α w is the thermal expansion coefficient of the lead material; α p W is the thermal expansion coefficient of the pad material; p W is the pad width; s is the substrate width; v s is the Poisson's ratio of the substrate material; ΔT is the temperature change amplitude; N f2 is the number of cycles before failure.

[0078] In this embodiment, for example, the pad thickness of the satellite-borne SIP device is 0.5 mm, the pad width is 2 mm, and 5000 Monte Carlo simulations are performed. The probability density function image of the number of cycles before the pad shear fatigue failure (unit: 1) is as follows: Figure 6As shown in the figure, the average and median values ​​of the shear fatigue failure life of the pad of the space-borne SIP device are both 731 cycles.

[0079] In one embodiment of the present specification, the key structure may include a bonding wire structure, and the failure mechanism of the bonding wire structure may include bonding wire bending fatigue failure and bonding wire shear fatigue failure;

[0080] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0081] The fatigue failure model of the bonding wire bending fatigue failure of the bonding wire structure is established by the following formula, as shown in the following formula (8):

[0082]

[0083] Among them, C w is the tensile fatigue coefficient of the lead material; m w E is the tensile fatigue index of the lead material; w is the elastic modulus of the lead material; r is the cross-sectional radius of the lead; D is half of the bond wire span; L1 is half of the bond wire length; α s is the thermal expansion coefficient of the substrate material; α w is the thermal expansion coefficient of the lead material; ΔT1 is the temperature variation range; N f3 is the number of cycles before failure.

[0084] In this embodiment, the satellite-borne SIP device uses wire bonding (gold wire ball bonding) to achieve chip interconnection. The cross-sectional diameter of the gold wire is 20 μm, that is, the cross-sectional radius is 0.01 mm, the bonding wire span is 1.51 mm, and the length is 3.44 mm. Among them, the elastic modulus of the gold wire material is 7×10 10 Pa, thermal expansion coefficient is 14.2×10 -6 K -1 The substrate is HTCC high temperature co-fired ceramic material with a thermal expansion coefficient of 7.1×10 -6 K -1 For example, after 5000 Monte Carlo simulations, the probability density function of the number of cycles before the bending fatigue failure of the bonding wire (unit: 1) is as follows Figure 7 As shown in the figure, the average bending fatigue life of the bonding wire of the satellite-borne SIP device is 17628 cycles, and the median is 17829 cycles.

[0085] In one embodiment of the present specification, based on the use environment stress and failure mechanism of each key structure, a failure physical model corresponding to each key structure is established, which may also include:

[0086] The fatigue failure model of the bonding wire shear fatigue failure of the bonding wire structure is established by the following formula, as shown in the following formula (9):

[0087] in,

[0088]

[0089] In the above formula, C w’ is the shear fatigue coefficient of the lead material; m w’ G is the shear fatigue index of the lead material; p is the shear elastic modulus of the pad material; b p is the pad thickness; r is the cross-sectional radius of the lead; l w Half of the wire bonding length; E s is the elastic modulus of the substrate material; E w is the elastic modulus of the lead material; E p is the elastic modulus of the pad material; α s is the thermal expansion coefficient of the substrate material; α w is the thermal expansion coefficient of the lead material; α p W is the thermal expansion coefficient of the pad material; p is the pad width; v s is the Poisson's ratio of the substrate material; ΔT1 is the temperature change amplitude; A s A is the effective cross-sectional area of ​​the substrate s =b s (W p +W s ) / 2; b s is the substrate thickness; A w A is the lead cross-sectional area w =πr 2 ; A p A is the pad cross-sectional area p =W p b p ; N f3 is the number of cycles before failure.

[0090] In this embodiment, the satellite-borne SIP device uses wire bonding (gold wire ball bonding) to achieve interconnection between chips. The cross-sectional diameter of the gold wire is 20 μm, that is, the cross-sectional radius is 0.01 mm. The substrate is HTCC high-temperature co-fired ceramic material with a size of 32 mm × 32 mm × 3.25 mm. The pad material on the substrate is mainly Cu, and the pad size is 0.051 mm × 0.051 mm × 0.01 mm. Among them, the elastic modulus of the gold wire material is 7×10 10 Pa, thermal expansion coefficient is 14.2×10 -6 K -1 ; The elastic modulus of the substrate material is 7.1×1011 Pa, thermal expansion coefficient is 7.1×10 -6 K -1 , Poisson's ratio is 0.3; the shear modulus of the pad material is 47.27×10 9 Pa, elastic modulus is 7.2×10 10 Pa, thermal expansion coefficient is 24×10 -6 K -1 For example, after 5000 Monte Carlo simulations, the probability density function of the number of cycles before shear fatigue failure of the bonding wire (unit: 1) is shown as follows Figure 8 As shown in the figure, the average shear fatigue life of the bonding wire of the satellite-borne SIP device is 14354 cycles, and the median is 14598 cycles.

[0091] In one embodiment of the present specification, the key structure may include a flip-chip structure, and the failure mechanism of the flip-chip structure may include micro-bump thermal fatigue failure;

[0092] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0093] The fatigue failure model of thermal fatigue failure of micro-bumps in the flip-chip structure is established by the following formula, as shown in the following formula (14).

[0094] in;

[0095]

[0096] TTF=24×N f4 (17).

[0097] Among them, Δγ p is the plastic shear strain caused by thermal mismatch; ε f is the fatigue ductility coefficient; c is the fatigue ductility index; F is the empirical correction factor considering the idealized assumption; ΔT2 is the difference between the highest temperature and the lowest temperature; T sj is the average temperature of the package; t D L is the half-cycle temperature dwell time; D is the distance from the micro-bump to the center point; △a is the difference in expansion coefficient between the substrate and the chip; N f4 is the number of cycles within the period; TTF is the cycle time to thermal fatigue failure.

[0098] In this embodiment, for example, the micro-bump length of the satellite-borne SIP device is 0.02 mm, the micro-bump width is 0.02 mm, the micro-bump height is 0.001 mm, and the temperature of the device is 300 K. For example, a total of 5000 Monte Carlo simulations are performed, and the probability density function image (unit: h) of the life before thermal fatigue failure of the micro-bump is as follows: Fig. 9 As shown in the figure, the calculated average and median values ​​of thermal fatigue life of micro-bumps of SIP devices are both 3615h. The stress state (stress and strain) is related to the geometry and material parameters of the package, interconnection and substrate, as well as the temperature parameters. The main influence on the fatigue failure of the bonding wire may be the stress caused by the mismatch of the expansion coefficients of the chip and the substrate due to temperature changes.

[0099] In one embodiment of the present specification, the key structure may include a through silicon via structure, and the failure mechanism of the through silicon via structure may include fatigue fracture failure of the bonding layer;

[0100] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0101] The fatigue failure model of the bonding layer fatigue fracture failure of the through silicon via structure is established by the following formula, as shown in the following formula (18):

[0102]

[0103] Among them, Δσ=E1×ΔCTE×ΔT3, Δσ is the stress difference of the chip interconnect structure, in Pa, E1 is the elastic modulus, in Pa; ΔT3 is the temperature cycle range, in K; ΔCTE is the difference between the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the chip material, in K -1 , ΔCTE=CTE s -CTE c , CTE s is the thermal expansion coefficient of the substrate material, in K -1 ;CTE c is the thermal expansion coefficient of the chip material, in K -1 , N f5 is the number of cycles in the period, C is a material constant related to temperature, da is the differential with respect to a, a is the crack depth, and the formula here is equivalent to integrating from the initial crack depth to the final crack depth.

[0104] In this embodiment, for example, the chip material of the satellite-borne SIP device (6117SRSC) is Si, and the thermal expansion coefficient is 2.52×10 -6 K -1 The substrate is HTCC high temperature co-fired ceramic material with a thermal expansion coefficient of 7.1×10 -6 K -1The chip and substrate are connected by low-temperature conductive adhesive 84-1LMISR4, whose elastic modulus is 3.5×10 10 For example, after 5000 Monte Carlo simulations, the probability density function of the number of cycles before fatigue failure of the bonding layer (unit: 1) is shown in Fig.10 As shown in the figure, the calculated average and median values ​​of the fatigue life of the bonding layer of the space-borne SIP device are both 1199 cycles.

[0105] In one embodiment of the present specification, the key structure may include a tube shell package, and the failure mechanism of the tube shell package may include random vibration failure of the package body and thermal fatigue failure of the package body;

[0106] Based on the environmental stress and failure mechanism of each key structure, the corresponding failure physical model of each key structure is established, which may include:

[0107] The fatigue failure model of random vibration failure of the package body of the tube shell package is established by the following formula. This failure physical model is used to describe the interconnection failure of the package body caused by random vibration, as shown in the following formula (19).

[0108]

[0109] Among them, the input parameters of the model are: N1 is the life of the Steinberg equation, and the logarithm of N1 has a linear relationship with the logarithm of b3;

[0110] Z1 is the displacement of the Steinberg equation, in units of in, and is calculated as shown in (20):

[0111]

[0112] c1 is the device constant for different package types. For standard DIP package c is 1.0, for DIP solder lead package c is 1.26, for four-row pin PGA package c is 1.0, for LCC package c is 2.25, for QFP package c is 1.128. Other cases are similar. t is the thickness of the PCB layer, in inches; L1 is the length of the package device, in inches.

[0113] Z2 is the maximum allowable displacement, in units of in, and is calculated using the following formula (21):

[0114]

[0115] B is the length of the PCB layer parallel to the device, in inches;

[0116] b3 is the vibration fatigue correction factor, which is related to the fatigue life of the structure. For an electronic box structure or the PCB inside the box, the vibration fatigue correction factor is generally around 2.0.

[0117] PSD max is the specified maximum power spectral density in g 2 / Hz;

[0118] R xy is the device curvature relative to the board layer;

[0119] f n is the natural frequency of the packaged device, in Hz;

[0120] Among them, the output parameters of the model are:

[0121] The number of vibration cycles when N2 fails, in units of 1.

[0122] In this embodiment, the Steinberg equation is aimed at the interconnect reliability of the SIP device installed on the PCB during use when subjected to random vibration stress. The length of the SIP6117SRSC package is 32mm. Considering that it is installed in the center of the 320mm×320mm×5mm PCB, it will produce the largest deformation during the vibration process. For example, a total of 5000 Monte Carlo simulations were performed, and the probability density function image (unit: h) of the life before random vibration failure of the package is as follows Fig.11 As shown in the figure, the calculated average random vibration fatigue life of the SIP6117SRSC package is 1870h and the median is 1922h.

[0123] In one embodiment of the present specification, based on the use environment stress and failure mechanism of each key structure, a failure physical model corresponding to each key structure is established, which may include:

[0124] The fatigue failure model of thermal fatigue failure of the package body of the tube shell package is established by the following formula, as shown in the following formula (22).

[0125]

[0126] in

[0127] Where F3 is the correction factor defined by the user; K D3 is the bending stiffness of the free component pin based on the Kotlowitz equation; A is the effective soldering area; h is the soldering height; L3 is 1 / 2 of the maximum pin spacing; Δα is the difference in thermal expansion coefficient between the packaged device and the substrate; ΔT c ,ΔT s are the thermal cycle temperature ranges of the onboard SIP device and substrate respectively; t D3 T is the time spent in the high temperature section during a temperature cycle; sjis the average temperature of the package; c3 is the material parameter; ε f3 is the material constant; N f6 is the number of cycles before failure, Δγ p3 is the inelastic strain range.

[0128] Thermomechanical fatigue failure of the packaging part is mainly due to the inconsistency of thermal expansion coefficients between the packaging material and the substrate, and is mainly concentrated in the internal interconnection, solder layer, substrate, etc.

[0129] In this embodiment, the package form of the satellite SIP is CQFP240, and the electrical connection with other devices is achieved through the external pins soldered on the PCB. The Engelmaier model is applicable to the thermal fatigue life calculation of the package body of this type of package. The bending stiffness of the SIP package pin is 42.2MPa, and the effective soldering area of ​​the pin on the PCB is 5×10 -8 m 2 , welding height is 1×10 -4 m, and the distance between the two pins is 0.5 mm. The SIP device package uses HTCC high temperature co-fired ceramic as the shell material and is welded on the PCB substrate. The thermal expansion coefficients of the two are 7.1×10 -6 K -1 and 17.6×10 -6 K -1 For example, a total of 5000 Monte Carlo simulations were performed, and the probability density function image of the package life before thermal fatigue failure (unit: h) is as follows Fig.12 As shown in the figure, the calculated average thermal fatigue life of the external pins of the SIP6117SRSC package is 2312h, and the median is 2276h.

[0130] In one embodiment of the present specification, evaluating the life of a satellite-borne SIP device based on the life of each key structure may include:

[0131] Monte Carlo sampling is used to sample the life of each key structure to obtain the life sample of each key structure;

[0132] Screen the minimum value in the life samples of each key structure to obtain the minimum sample;

[0133] Repeat the steps of sampling the life of each key structure using Monte Carlo sampling n times to obtain the life sample of each key structure and screening the minimum value among the life samples of each key structure to obtain the minimum sample, and obtain n minimum samples;

[0134] The lifetime of the onboard SIP device is evaluated based on the minimum value among n minimum samples.

[0135] In this embodiment, the results of evaluating the life of the onboard SIP device based on the life of each key structure can be seen in Fig.13 , Fig.13 In the figure, the failure rate of each failure mechanism is shown, with chip electromigration accounting for 20.8%, pad shear fatigue accounting for 6.8%, adhesive layer fatigue fracture accounting for 1.0%, and package thermal fatigue failure accounting for 71.4%. For example, see Fig.14 , the life of each key structure includes k life data such as chip electromigration failure, pad shear fatigue failure, and bonding layer fatigue fracture. The first sampling is performed to obtain sample 1, t11, t21, tk1, and the minimum value (min) is taken to obtain the product failure time tCF1; the second sampling is performed to obtain sample 2, t12, t22, tk2, and the minimum value (min) is taken to obtain the product failure time tCF2; the nth sampling is performed to obtain sample n, t1n, t2n, tkn, and the minimum value (min) is taken to obtain the product failure time tCFn. The minimum value among tCF1, tCF2 and tCFn is taken as the life of the satellite-borne SIP device.

[0136] In order to further deepen the understanding of the present invention, the Monte Carlo method is summarized below. The Monte Carlo method is also called the statistical simulation method and the statistical test method. It is a numerical simulation method that takes probability phenomena as the research object. It is a calculation method that obtains statistical values ​​according to the sampling survey method to infer unknown characteristic quantities. Monte Carlo is a famous casino in Monaco. The method is named to indicate its random sampling nature. Therefore, it is suitable for computational simulation experiments on discrete systems. In computational simulation, by constructing a probability model that is similar to the system performance and conducting random experiments on a digital computer, the random characteristics of the system can be simulated.

[0137] The Monte Carlo method (also known as the statistical experimental method) is a basic method to describe various random phenomena in the process of equipment operation. It is particularly suitable for some problems that are difficult or even impossible to solve by analytical methods. Therefore, it plays an important role in equipment effectiveness evaluation.

[0138] The use of the Monte Carlo method to describe the equipment application process was first proposed by Johnson, an American in 1950. This method can fully reflect the impact and role of random factors on the equipment application process. It more accurately reflects the dynamic process of application activities. In equipment effectiveness evaluation, the Monte Carlo method is often used to determine efficiency indicators containing random factors, such as detection probability, hit probability, average number of damaged targets, etc.; simulate random phenomena in random service systems and calculate their digital characteristics; for some complex equipment application actions, through reasonable decomposition, simplify them into a series of connected events, and then simulate each event using a random sampling method, and finally achieve the purpose of simulating equipment application activities or application processes.

[0139] The basic idea of ​​the Monte Carlo method is: in order to solve a problem, first establish a probability model or a random process so that its parameters or numerical features are equal to the solution of the problem: then calculate these parameters or numerical features through observation or sampling tests of the model or process, and finally give an approximate value of the solution. The accuracy of the solution is expressed by the standard error of the estimated value. The main theoretical basis of the Monte Carlo method is the probability statistics theory, and the main means are random sampling and statistical tests. The basic steps for solving practical problems using the Monte Carlo method are:

[0140] (1) According to the characteristics of the actual problem, a simple and easy-to-implement probability statistical model is constructed so that the solution is exactly the probability distribution or mathematical expectation of the problem;

[0141] (2) Provide sampling methods for various random variables with different distributions in the model;

[0142] (3) Statistically process the simulation results and provide statistical estimates and precision estimates of the solutions to the problem.

[0143] In this study, the fluctuation of process parameters during product production leads to the fluctuation of parameters such as SIP structure size, which ultimately makes the life of SIP structure obey a certain distribution. We cannot conduct a large number of life tests to obtain relevant life data, so we can use the Monte Carlo method to sample random quantities such as product geometric size parameters, and substitute them into the failure physical model to obtain a series of chip electromigration.

[0144] Research on chip structure failure modes and mechanisms

[0145] (1) Chip electromigration

[0146] When microelectronic components are working, a certain amount of current flows through the aluminum strips of the metal interconnects, and metal ions will be transported along the conductors, resulting in the appearance of voids or whiskers in certain parts of the conductors, which is called electromigration. In bulk metals, the current density is low (<104A / cm2), and electromigration only occurs at high temperatures close to the melting point of the material. This is not the case with thin film materials. The aluminum strips deposited on the silicon substrate have a small cross-sectional area and good heat dissipation conditions, and the current density can be as high as 107A / cm2, so electromigration will occur at relatively low temperatures.

[0147] Production Principle

[0148] Electromigration is one of the main failure mechanisms in microelectronic devices. Electromigration can cause open circuits and short circuits in metal wires, increasing device leakage current. Especially after the device develops to submicron and deep submicron, the width of the metal wire continues to decrease, and the current density continues to increase, making it more likely for electromigration to occur and cause device failure. Therefore, with the advancement of technology, reliability prediction of devices based on electromigration has received much attention.

[0149] Metal is a crystal. Metal ions are arranged in sequence inside the crystal. When there is no external electric field, metal ions can change positions through vacancies in the lattice. This movement of metal ions is called self-diffusion. Because any ion close to an adjacent vacancy has the same probability of exchanging positions with the vacancy, self-diffusion does not produce mass transport. When current passes through metal interconnects, metal ions will move in a directional manner. The so-called metal electromigration failure usually refers to the degradation or failure of device or interconnect performance caused by the mass accumulation (Pileup) of metal ions in the local area of ​​the metal layer, or the voids (Voids) due to proton loss. Electromigration is usually caused by high temperature and strong electric field, but the conditions for metallization electromigration are different for different metals.

[0150] 2) Chip gate oxide layer breaks down over time

[0151] In large-scale integrated circuits, the performance of the gate oxide layer inside the chip directly determines the performance, reliability and yield of the integrated circuit, and has always been the key to device reliability. Under certain voltage and temperature conditions, the breakdown phenomenon of the gate oxide dielectric inside the chip over time is called time-dependent dielectric breakdown failure (TDDB, Time Dependent Dielectric Breakdown), that is, the time-dependent breakdown failure of the gate oxide layer. The time-dependent breakdown time of the chip gate oxide layer is an important indicator for evaluating the reliability of the chip gate oxide layer. At present, there are two main physical models of time-dependent dielectric breakdown failure, namely the 1 / E model and the E model. In general, the 1 / E model is applicable to the case of high electric field and high current, while the E model is applicable to the case of low electric field and low current.

[0152] The 1 / E model is also known as the hole breakdown model. It is based on the FN (Fowler-Nordheim) tunneling current and is applicable to silicon devices. Under low voltage, under the action of an external electric field, the accelerated electrons transfer energy to the valence band electrons of the anode Si and excite them to the conduction band (the band gap width of Si is about 1.2eV), generating holes in the valence band, which tunnel back to the oxide layer. Most of the holes are collected by the cathode through the oxide layer only under the action of an external electric field. Some holes may be captured, increasing the electric field and tunneling current at the local defect, forming positive feedback, and finally causing the oxide layer to break down. Therefore, the 1 / E model is also known as the hole breakdown model.

[0153] The 1 / E model is completely based on the FN tunneling current. However, when the external electric field is less than 5MV / cm, the FN tunneling current is very small, and the lifespan extrapolated by the 1 / E model is very different from the actual value. Therefore, when extrapolating the service life of the gate oxide layer, it is necessary to note that its application range cannot be less than 5MV / cm.

[0154] (2)Substrate warpage

[0155] Warping is caused by the mismatch of thermal expansion coefficients between materials, coupled with the limitation of adhesion. Under the influence of external temperature changes, in order to release the internal stress generated by the temperature influence, the packaging materials warp to eliminate the internal stress. The mismatch of thermal expansion coefficients between the substrate and the chip is the main cause of warping, which often occurs in the reflow process with large temperature changes. Warping modes include concave, convex and their combination modes.

[0156] The assembly process of three-dimensional high-density packaging is usually achieved through the reflow process. Generally, the connection with the PCB board is achieved through the reflow process at the same time. The packaging materials include epoxy molding compound (EMC), patch adhesive, silicon wafer, lead-free solder, substrate and PCB material. Due to the mismatch of the thermal expansion coefficient of the packaging materials, the warpage generated during the reflow process has an important impact on the yield of the assembly. First, the warpage of the bottom package is difficult to control. The periphery of the bottom package lacks molding sealing material. Therefore, the periphery is composed of an unsupported packaging substrate. At the same time, in order to reduce the height of the entire stack, the substrate is made as thin as possible. During the reflow process, the substrate will expand due to the increase in temperature during the reflow process, causing the bottom package to have a more serious warpage. In addition, although the top package extends the molding sealing material to the edge of the package, the warpage is usually smaller than the bottom package, but the warpage of the top package must often tolerate the warpage of the bottom package.

[0157] (3) Substrate fracture

[0158] In addition to warping, external stresses such as impact may also cause substrate fracture or surface delamination. A large number of studies have been conducted at home and abroad on the mechanical properties of substrates under impact stresses such as dropping. For example, Jingen Luan studied the effect of dropping on the performance of two-layer PoP devices. The results showed that the solder balls that are most likely to fail are located at the outermost boundary of the bottom package, and the main failure mode is fracture at the interface between the PCB pad and the IMC. Joon-Yeob Lee studied the effect of adding bottom filler on the drop performance of two-layer PoP packages. The study found that filler can effectively improve the drop performance of PoP, and filler with a smaller Young's modulus can absorb the deformation of the drop and improve the drop performance of the device. Vicky Wang, Dan Maslyk and others conducted drop tests on two-layer PoP devices. The results showed that no failure would occur when filler was added to both the top package and the bottom package; only when filler was added to the bottom package, failure would occur, and the failure location was on the top package; at the same time, SAC105 solder balls have better drop performance than SAC305 solder balls. However, with the diversification of chip functions, three-layer and above PoP packages have been increasingly widely used. However, the above research mainly targets two-layer stacked PoP devices, and there is little research on the drop reliability of three-layer and above PoP packages.

[0159] (4) Thermal fatigue failure of plated through holes

[0160] Through-holes in substrates are used to make electrical connections between internal and external circuits, or between the two, by electroplating metal on the walls of the through-holes. As the functionality of electronic packaged chips increases and the feature size decreases, their packaging density increases. In addition, the number of ceramic substrate layers and the number of plated through-holes, blind vias, and buried vias have increased significantly. Therefore, through-hole thermal fatigue failure has gradually become one of the most serious reliability issues for substrates. In order to accommodate these plated through-holes in a smaller area, the diameter of the plated through-holes is reduced, and the ratio of the height of the plated through-hole to its diameter is increased, resulting in a larger aspect ratio. Fatigue failure of the through-hole plating can occur due to the mismatch in the coefficient of thermal expansion (CTE) of the plating material and the substrate material in the thickness direction. This mismatch is mainly in the out-of-plane or thickness direction of the substrate, because the out-of-plane CTE of the board is usually 3 to 4 times larger than the CTE of the plating. Cyclic stress is generated on the through-hole plating due to power cycling and temperature cycling when the temperature changes. Therefore, as the geometry of plated through-holes becomes smaller and smaller, it has become critical to study the reliability of plated through-holes. In ceramic substrates, the in-plane CTE mismatch is usually much lower, but Kevlar and some newer materials may experience more failures.

[0161] (5) Bond wire breakage

[0162] During forward bonding, the first solder joint is placed on the metal pad bonding area of ​​the chip, and the pin is the second solder joint. The more sensitive issue in forward bonding is the crack control of the lead at the heel of the bond and the arc. In the trapezoidal stacked chip structure, the smaller chip is placed on top of the larger chip, and there needs to be enough clearance from the top chip to the edge of the bottom chip, which usually requires a platform mode arc. In the arc close to the second solder joint, a relatively large angle is required because the support point of the arc is the first solder joint, which is much more difficult than making a bend close to the first solder joint. When the bending angle increases, the arc is subject to greater tilting and fracture threats. This problem becomes worse when the bottom chip is much larger than the top chip and the second solder joint lead is very close to the chip edge. Reverse bonding can be used to solve this problem because reverse bonding provides a sharp bend angle and a higher bend height.

[0163] The reverse bonding process is to make the first solder ball in the chip bonding area, and then the lead is used as the first solder joint, and the chip bonding area is used as the second solder joint. Excessive back pulling of the gold wire during the reverse bonding process will cause cracks in the lead heel.

[0164] (6) Bond pad peeling

[0165] Bond pad debonding is often associated with a bond pad debonding. Bond pad debonding occurs when the bond pad or underlying material is mechanically damaged. Bond pad debonding usually manifests itself as a small, irregularly shaped pit where a small amount of silicon has been gouged out, or simply as a disturbance in the silicon single crystal. Occasionally, pits larger than the bond pad size may be seen. When bond pad debonding is present, it can become a source of crack growth during device use, leading to bond pad debonding.

[0166] The different sizes and depths of the exposed bottom surfaces that occur in the silicon chip depend on the type and amount of stress used during bonding.

[0167] (7) Bonding point corrosion

[0168] The corrosion of the metal aluminum pad inside the semiconductor device may result in poor contact at the device's welding point, functional failure or performance degradation; it may also cause the physical isolation between the electrodes of the chip to fail, resulting in leakage current or short circuit, affecting the electrical parameters of the device.

[0169] Metal corrosion refers to the destructive erosion of metals caused by chemical and electrochemical reactions in a specific environment. This type of corrosion is common in the natural environment. According to research over the years, metal corrosion can be divided into two categories: electrochemical corrosion and galvanic corrosion, depending on the different objects involved. Electrochemical corrosion mainly describes the chemical reactions of metals in acidic or alkaline environments, focusing on pH values, the activity of the elements themselves, and the exchange and transmission of electrons. Galvanic corrosion mainly describes the galvanic cell model formed by different metals in an electrolyte solution. The anode metal undergoes an oxidation reaction and is dissolved and generates current, while the cathode metal releases electrons to the anions in the solution to reduce them. Galvanic corrosion focuses on the dissolution potential and redox reactions of metals.

[0170] (8) Overhanging chip breaks during bonding process

[0171] At present, the research and development of overhang chip bonding is being carried out at home and abroad. The application of overhang chip bonding technology will change the development of chip stacking packaging technology, so that the chip stacking structure is no longer bound to a single pyramid stacking structure. Stacking packaging can reasonably arrange the position of stacked chips from the perspective of device function and thermal design. The key to this technology is to solve the feasibility and reliability of overhang chip bonding. The stress during chip bonding causes the overhang chip to break, which is the main problem of this technology.

[0172] Due to the high brittleness of single crystal silicon materials, if an overhang stacking structure is used, the chip will break due to excessive bending stress during chip bonding, which will be greater than the strength limit of the material.

[0173] (9) Large span bonding wire collapse

[0174] In the multi-stack packaging process, each layer of embedded bare chips needs to be connected to the substrate, which often requires forming a wire arc with a longer length and a lower height, and the bonding process conditions become relatively more complicated. In the stacked leads, we often encounter some leads that collapse. Severe "collapse" will cause the lead to short-circuit with the lower layer lead, which is easy to cause a short circuit, causing reliability problems for the product or even overall scrapping, resulting in defective products.

[0175] (10) Micro-bump structure changes

[0176] When the flip chip bumps are in operation, they will experience a thermal stress change process when they are periodically switched on and off or when the ambient temperature changes cyclically, which will then generate periodic thermal stress and act on the bumps to cause displacement changes. As the device works for an extended period of time, the superposition of the bump plastic deformation will cause cracks to initiate and expand in the bumps, eventually causing fatigue failure of the bump structure. Studies have shown that fatigue failure of the bump structure is one of the main reasons for the failure of the flip chip device packaging structure. This is a serious obstacle to the development of flip chip technology.

[0177] (11) Protrusion

[0178] Protrusions, or bumps, usually appear on the TSV surface. Since TSV protrusions can damage the wafer and are a potential risk factor for the reliability of the final 3D stacked device, it is necessary to introduce the protrusions introduced by the TSV process.

[0179] After Cu electroplating, the excess Cu on the wafer surface needs to be removed by chemical mechanical polishing (CMP) and then annealed. Due to the large temperature change before and after annealing, the coefficient of thermal expansion (CTE) between Cu and Si does not match, which causes a lot of thermal stress inside the TSV. In order to release the internal stress, Cu can only expand vertically outward due to the constraints of the surrounding Si substrate, thus forming a bulge. High temperature annealing will also cause the grains to grow coarser and lattice defects to appear.

[0180] The bulge defect is generated in the annealing process. Different annealing conditions have a great influence on the bulge. Studies have shown that annealing temperature is an important factor affecting the bulge. The higher the annealing temperature, the more obvious the bulge. In addition, annealing time and TSV diameter, depth, spacing and other parameters also have a certain effect on the formation of bulge. The bulge is very likely to cause the failure of metal layer interconnection and affect the reliability of the device.

[0181] (12) Filling holes

[0182] Void defects are mainly caused by the filling of TSV through holes. Incomplete filling is the most common problem in the TSV process. In the process of TSV Cu electroplating, the electroplating current density plays a crucial role. The copper filling process is carried out from the side wall to the middle, and the Cu electroplating rate increases with the increase of current density. As the current density continues to increase, the electroplating rate at the through hole mouth increases, so that the copper at the hole mouth is filled earlier than the middle, resulting in the inability to continue to fill the bottom of the hole and produce voids. In addition, the shell effect produced by the etching process causes uneven hole walls and poor wetting, which is another key factor in the formation of TSV filling voids. Uneven seed layer deposition can also form voids.

[0183] Voids in the metal layer may increase the TSV interconnect resistance, change the performance of the device, and even cause open circuit failure. In addition, poor through-hole wettability can also cause serious defects such as truncation of the electroplated metal layer. If the void is located in the insulating layer, such as along the sidewall of the TSV, the result will be a short circuit between the TSV and the substrate, generating leakage current. There are also various TSV filling defects.

[0184] Fig.15 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0185] like Fig.15As shown, the electronic device may include: a processor 1510, a communication interface 1520, a memory 1530 and a communication bus 1540, wherein the processor 1510, the communication interface 1520 and the memory 1530 communicate with each other through the communication bus 1540. The processor 1510 may call the logic instructions in the memory 1530 to execute the life assessment method of the onboard SIP device.

[0186] In addition, the logic instructions in the above-mentioned memory 1530 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0187] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0188] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for evaluating the life of a satellite-borne SIP device, characterized in that: include: Identify the key structures in spaceborne SIP devices for lifetime assessment; Based on the use environment stress and failure mechanism of each of the key structures, a failure physical model corresponding to each of the key structures is established; Based on the Monte Carlo method, sampling the geometrical dimension parameters of each of the key structures is performed to obtain parameter samples of each of the key structures; Substituting each of the parameter samples into a corresponding failure physical model to obtain life data corresponding to each of the key structures; Based on the lifetime data, a lifetime probability density function of each of the key structures is obtained by fitting; Based on the lifetime probability density functions, the lifetime of each of the key structures is obtained; The life of the onboard SIP device is evaluated based on the life of each of the key structures.

2. The life evaluation method of a satellite-borne SIP device according to claim 1, characterized in that: The key structure includes a chip structure, and the failure mechanism of the chip structure includes chip electromigration failure and chip gate oxide layer failure; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The chip electromigration failure model of the chip structure is established by the following formula; Where W is the width of the chip metallization layer; d is the thickness of the chip metallization layer; T is the temperature of the chip; C" is the constant of the diffusion activation energy of the metal film structure of the chip; j is the current density of the metallization layer of the chip; k is the Boltzmann constant of the chip; E a is the activation energy of the metallization material of the chip; MTTF is the mean time to failure of the chip; When the electric field strength of the environment where the chip structure is located is greater than a preset electric field threshold, a chip gate oxide layer failure model of the chip structure is established by the following formula; MTTF = τexp(G / E OX )exp(E a / kT), where τ is the proportional constant determined by the material and process of the chip gate oxide layer; G is the electric field acceleration factor of the chip gate oxide layer; E OX is the external electric field on the chip gate oxide layer; When the electric field strength of the environment where the chip structure is located is less than or equal to the preset electric field threshold, a chip gate oxide layer failure model of the chip structure is established by the following formula; MTTF = b1 × τexp(-γE OX )exp(E a / kT), where b1 is the model breakdown coefficient and -γ is the electric field acceleration factor.

3. The life evaluation method of a satellite-borne SIP device according to claim 2, characterized in that: The key structure includes a substrate structure, and the failure mechanism of the substrate structure includes thermal fatigue failure of substrate plated through holes; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The fatigue failure model of the plated through hole of the substrate structure is established by the following formula; Among them, Δε is the total strain amplitude; σ f is fatigue strength; f is the fatigue ductility coefficient; b2 is the fatigue strength index; c is the fatigue ductility index; σ0 is the average stress; E1 is the elastic modulus; N f1 is the number of cycles before failure.

4. The life evaluation method of a satellite-borne SIP device according to claim 3, characterized in that: The key structure includes a welding layer, and the failure mechanism of the welding layer includes pad shear fatigue; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The failure model of pad shear fatigue of the welding layer is established by the following formula; Among them, C p’ is the shear fatigue coefficient of the pad material; m p’ G is the shear fatigue index of the pad material; p is the shear elastic modulus of the pad material; b p is the pad thickness; b s is the substrate thickness; r is the cross-sectional radius of the lead; E s is the elastic modulus of the substrate material; E w is the elastic modulus of the lead material; E p is the elastic modulus of the pad material, in Pa; α s is the thermal expansion coefficient of the substrate material; α w is the thermal expansion coefficient of the lead material; α p W is the thermal expansion coefficient of the pad material; p W is the pad width; s is the substrate width; v s is the Poisson's ratio of the substrate material; ΔT is the temperature change amplitude; N f2 is the number of cycles before failure.

5. The life evaluation method of a satellite-borne SIP device according to claim 4, characterized in that: The key structure includes a bonding wire structure, and the failure mechanism of the bonding wire structure includes bonding wire bending fatigue failure and bonding wire shear fatigue failure; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: A fatigue failure model of bonding wire bending fatigue failure of the bonding wire structure is established by the following formula; Among them, C w is the tensile fatigue coefficient of the lead material; m w E is the tensile fatigue index of the lead material; w is the elastic modulus of the lead material; r is the cross-sectional radius of the lead; D is half of the bond wire span; L1 is half of the bond wire length; α s is the thermal expansion coefficient of the substrate material; α w is the thermal expansion coefficient of the lead material; ΔT1 is the temperature variation range; N f3 is the number of cycles before failure.

6. The life evaluation method of a satellite-borne SIP device according to claim 5, characterized in that: The key structure includes an inverted structure, and the failure mechanism of the inverted structure includes thermal fatigue failure of micro-bumps; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The fatigue failure model of thermal fatigue failure of micro-bumps of the flip-chip structure is established by the following formula; in; TTF=24×N f4 ; Among them, Δγ p is the plastic shear strain caused by thermal mismatch; ε f is the fatigue ductility coefficient; c is the fatigue ductility index; F is the empirical correction factor; ΔT2 is the difference between the highest temperature and the lowest temperature; T sj is the average temperature of the package; t D is the half-cycle temperature dwell time; L D is the distance from the micro-bump to the center point; △a is the difference in expansion coefficient between the substrate and the chip; N f4 is the number of cycles within the period; TTF is the cycle time to thermal fatigue failure.

7. The life evaluation method of a satellite-borne SIP device according to claim 6, characterized in that: The key structure includes a through silicon via structure, and the failure mechanism of the through silicon via structure includes fatigue fracture failure of the bonding layer; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The fatigue failure model of fatigue fracture failure of the bonding layer of the through silicon via structure is established by the following formula; Where Δσ is the stress difference of the chip interconnect structure; ΔT is the temperature cycle range, in K; a f is the final crack depth; a0 is the initial crack depth; C is the material constant related to temperature; m is the fatigue index; N f5 is the number of cycles under stress before failure, da is the differential of a, and a is the crack depth.

8. The life evaluation method of a satellite-borne SIP device according to claim 7, characterized in that: The key structure includes a tube-shell package, and the failure mechanism of the tube-shell package includes random vibration failure of the package body and thermal fatigue failure of the package body; The failure physical model corresponding to each of the key structures is established based on the use environment stress and failure mechanism of each of the key structures, including: The fatigue failure model of random vibration failure of the package body of the tube shell package is established by the following formula; Where N1 is the life of the Steinberg equation; Z1 is the displacement of the Steinberg equation; Z2 is the maximum allowable displacement; b3 is the vibration fatigue correction factor, the number of vibration cycles when N2 fails; The fatigue failure model of thermal fatigue failure of the package body of the tube shell package is established by the following formula; Among them, N f6 is the number of cycles before failure, Δγ p3 is the inelastic strain range, ε f3 is the material constant and c3 is the material parameter.

9. The life evaluation method of a satellite-borne SIP device according to claim 1, characterized in that: The evaluating the life of the onboard SIP device based on the life of each of the key structures includes: The life of each of the key structures is sampled by Monte Carlo sampling to obtain a life sample of each of the key structures; Screening the minimum value among the life samples of each of the key structures to obtain a minimum sample; Repeating n times the steps of sampling the life of each of the key structures using Monte Carlo sampling to obtain a life sample of each of the key structures and the steps of screening the minimum value among the life samples of each of the key structures to obtain a minimum sample, to obtain n minimum samples; The life of the onboard SIP device is evaluated based on a minimum value among n minimum samples.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the life assessment method of the satellite-borne SIP device as described in any one of claims 1 to 8 is implemented.

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