Display panel, driving method and display device

Abstract

The embodiment of the invention discloses a display panel, a driving method and a display device. The display panel comprises a pixel circuit and a light-emitting element. The pixel circuit comprises a data write-in module, a driving module and a compensation module, the compensation module is configured to be controlled by a first scanning signal, the data write-in module is configured to be controlled by a second scanning signal, V11 is smaller than V11 ', or V11 is smaller than V12; wherein V11 is the high-level voltage of the first scanning signal in the refresh frame, V11'is the high-level voltage of the first scanning signal in the holding frame, and V12 is the high-level voltage of the second scanning signal in the refresh frame. According to the embodiment of the invention, the compensation module can be prevented from generating leakage current in the light-emitting stage of the refresh frame, or the compensation module can be prevented from being turned off in the bias adjustment stage of the holding frame, so that the voltage of the grid of the driving transistor is stabilized, deviation between the light-emitting brightness of the light-emitting element and the target brightness is prevented, and flicker and abnormal splash screen phenomena of the display panel are avoided.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel, a driving method, and a display device. Background Art

[0002] With the continuous development of display technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work.

[0003] Electronic products will use different refresh rates for display in different application scenarios. For example, a higher refresh rate driving method is used to drive the display of dynamic images (such as game scenes) to ensure the smoothness of the displayed images; a lower refresh rate driving method is used to drive the display of slow-motion images or static images to reduce power consumption.

[0004] However, current display devices may experience flickering or even abnormal screen flashing when using different refresh modes, especially low-frequency refresh, which will seriously affect the display effect. Summary of the invention

[0005] The present invention provides a display panel, a driving method and a display device to avoid flickering or even abnormal screen flickering of the display panel and improve the display quality.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including a pixel circuit and a light-emitting element;

[0007] The pixel circuit includes a data writing module, a driving module and a compensation module;

[0008] The driving module includes a driving transistor;

[0009] The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor;

[0010] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0011] Wherein, the picture display process of the display panel includes display frames, and the display frames include refresh frames and hold frames;

[0012] The compensation module is configured to be controlled by a first scanning signal; the first scanning signal satisfies: V11<V11'; wherein V11 is a high level voltage of the first scanning signal in the refresh frame, and V11' is a high level voltage of the first scanning signal in the hold frame.

[0013] In a second aspect, an embodiment of the present invention further provides a display panel, including a pixel circuit and a light-emitting element;

[0014] The pixel circuit includes a data writing module, a driving module and a compensation module;

[0015] The driving module includes a driving transistor;

[0016] The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor;

[0017] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0018] Wherein, the picture display process of the display panel includes display frames, and the display frames include refresh frames;

[0019] The compensation module is configured to be controlled by a first scanning signal; the data writing module is configured to be controlled by a second scanning signal;

[0020] The first scanning signal and the second scanning signal satisfy: V11<V12;

[0021] Among them, V11 is the high level voltage of the first scanning signal in the refresh frame, and V12 is the high level voltage of the second scanning signal in the refresh frame.

[0022] In a third aspect, an embodiment of the present invention further provides a method for driving a display panel, wherein the display panel includes a pixel circuit and a light-emitting element;

[0023] The pixel circuit includes a data writing module, a driving module and a compensation module;

[0024] The driving module includes a driving transistor;

[0025] The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor;

[0026] The compensation module is connected between the gate and the second electrode of the driving transistor;

[0027] Wherein, the picture display process of the display panel includes a plurality of display frames, and the plurality of display frames include a refresh frame and a hold frame;

[0028] The driving method of the display panel includes:

[0029] The compensation module is controlled by using a first scanning signal, wherein the first scanning signal satisfies: V11<V11'; wherein V11 is a high level voltage of the first scanning signal in the refresh frame, and V11' is a high level voltage of the first scanning signal in the hold frame.

[0030] In a fourth aspect, an embodiment of the present invention further provides a display device, comprising any display panel provided by an embodiment of the present invention.

[0031] In the technical solution of the embodiment of the present invention, the compensation module is configured to be controlled by the first scanning signal, and the data writing module is configured to be controlled by the second scanning signal. The first scanning signal and the second scanning signal satisfy: V11<V11', or, V11<V12; wherein V11 is the high-level voltage of the first scanning signal in the refresh frame, V11' is the high-level voltage of the first scanning signal in the holding frame, and V12 is the high-level voltage of the second scanning signal in the refresh frame. On the one hand, the coupling effect of the gate on the middle node of the two transistors can be reduced in the light-emitting stage of the refresh frame, so as to avoid the voltage of the middle node being raised by the capacitive coupling to generate leakage current, and prevent the gate voltage of the driving transistor from affecting the luminous brightness of the light-emitting element due to the leakage current of the transistor in the compensation module; on the other hand, in the bias adjustment stage of the holding frame, it can avoid the situation that the transistor in the compensation module cannot be turned off due to the high-level bias adjustment signal written by the driving transistor, which also affects the gate voltage of the driving transistor, and prevent the abnormal screen flickering phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0033] Figure 2 yes Figure 1 A circuit structure diagram of a pixel circuit and a light-emitting element in the display panel shown;

[0034] Figure 3 It is a pixel circuit driving timing diagram in the related art;

[0035] Figure 4 is a pixel circuit driving timing diagram provided by an embodiment of the present invention;

[0036] Figure 5 is a comparison diagram of display brightness of a display panel under two first scanning signals provided by an embodiment of the present invention;

[0037] Figure 6 is a curve diagram of the high-level voltage of the first scanning signal and the flickering condition of the display panel in a refresh frame provided by an embodiment of the present invention;

[0038] Figure 7 is a curve diagram of the high level voltage of the first scanning signal in the holding frame and the flickering condition of the display panel provided by an embodiment of the present invention;

[0039] Figure 8 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0040] Fig. 9 is another pixel circuit driving timing diagram provided by an embodiment of the present invention;

[0041] Fig.10 is another pixel circuit driving timing diagram provided by an embodiment of the present invention;

[0042] Fig.11 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0043] Fig.12 yes Fig.11 The timing diagrams of some signals in different partitions of the display panel are shown;

[0044] Fig.13 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0045] Fig.14 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0046] Fig.15 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0047] Fig.16 is another pixel circuit driving timing diagram provided by an embodiment of the present invention;

[0048] Fig.17 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0050] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", "right" and the like described in the embodiments of the present invention are described at the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be directly formed "on" or "under" another element, but also indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not represent any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific circumstances.

[0051] The term “including” and its variations used in the present invention are open inclusions, that is, “including but not limited to.” The term “based on” means “based at least in part on.” The term “one embodiment” means “at least one embodiment.”

[0052] It should be noted that the concepts such as "first" and "second" mentioned in the present invention are only used to distinguish the corresponding contents, and are not used to limit the order or interdependence.

[0053] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0054] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 yes Figure 1 The circuit structure diagram of the pixel circuit and the light-emitting element in the display panel shown in FIG. Figure 1 and Figure 2 The display panel includes a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a data writing module 11, a driving module 12 and a compensation module 13; the driving module 12 includes a driving transistor M2; the data writing module 11 is connected between the data signal input terminal Vdata and the first electrode of the driving transistor M2; the compensation module 13 is connected between the gate and the second electrode of the driving transistor M2.

[0055] In addition, the pixel circuit further includes a gate reset module 14, an anode reset module 15, a light emitting control module 16 and a storage capacitor Cst; the gate reset module 14 is connected to the gate reset signal terminal Vref1 and the gate of the driving transistor M2. The anode reset module 15 is connected between the anode reset signal terminal Vref2 and the anode of the light emitting element 20. The light emitting control module 16 includes a first light emitting control unit 161 and a second light emitting control unit 162; the first light emitting control unit 161, the driving module 12, the second light emitting control unit 162, and the light emitting element 20 are sequentially connected in series between the first power signal terminal PVDD and the second power signal terminal PVEE.

[0056] Figure 3 This is a pixel circuit driving timing diagram in the related art, refer to Figure 1-Figure 3 First, the driving process and driving principle of the display panel are briefly introduced. Specifically, the driving process of the pixel circuit 10 may include multiple display frames T, which can be divided into a high refresh mode and a low refresh mode according to the refresh frequency. In the high refresh mode, the multiple display frames T are refresh frames Trefresh; in the low refresh mode, the multiple display frames T may include a refresh frame Trefresh and a hold frame Thold. The refresh frame Trefresh may include a gate reset phase ta, a data writing phase tb and a light emitting phase tc, and the hold frame Thold may include a light emitting phase tc.

[0057] In the gate reset phase ta, the gate reset control signal S1N received by the gate reset module 14 is at a low level, which is an enable signal. The gate reset module 14 is turned on, and the gate reset signal Vref1 is input to the gate of the driving transistor M2 to reset the gate of the driving transistor M2.

[0058] In the data writing phase tb, the data writing control signal SP received by the data writing module 11 is at a low level at this time, which is an enable signal, and the data writing module 11 is turned on; at the same time, the threshold compensation control signal S2N received by the compensation module 13 is at a low level at this time, which is an enable signal, and the compensation module 13 is turned on. The data signal Vdata is input to the gate of the driving transistor M2 through the data writing module 11, the driving module 12, and the compensation module 13, and is stored by the storage capacitor Cst.

[0059] In the light-emitting stage tc, the light-emitting control signal Emit received by the first light-emitting control unit 161 and the second light-emitting control unit 162 is at a low level at this time, which is an enable signal. The first light-emitting control unit 161 and the second light-emitting control unit 162 are turned on, the first power signal terminal PVDD and the second power signal terminal PVEE are turned on, and the on-current is controlled by the driving transistor M2, and the on-current of the driving transistor M2 is related to its gate-source voltage difference. Specifically, the driving transistor M2 forms a certain gate-source voltage difference with the first power signal terminal PVDD according to the data signal Vdata stored in the gate, thereby realizing the control of the on-current of the driving transistor M2, that is, the corresponding driving current can be provided to the light-emitting element 20, so that the light-emitting element 20 emits light at the target brightness.

[0060] However, in the light-emitting stage tc, the transistors in the compensation module 13 are normally in the off state under the control of the threshold compensation control signal S2N, but because they are generally set as P-type dual-gate transistors, that is, including the first transistor M31 and the second transistor M32, the node connected between the two transistors will be capacitively coupled with the gate, and the threshold compensation control signal S2N received by the gate is a high-level signal at this time, which will raise the voltage of the middle node, so that the gate-source voltage difference of the first transistor M31 is reduced, causing the first transistor M31 to generate leakage, and the gate of the driving transistor M2, that is, the potential of the first node N1, continues to increase during the one-frame light-emitting time, causing the light-emitting brightness of the light-emitting element 20 to gradually decrease during the light-emitting stage tc. When the display panel is driven at a low frequency and the one-frame light-emitting time is long, the brightness decreases significantly, and there will be obvious changes in brightness between different display frames. The human eye perceives the changes in brightness and darkness, that is, flickering.

[0061] In addition, considering that the driving transistor M2 is in a forward bias state during the light-emitting stage tc of each display frame, that is, the voltage of the second node N2 is greater than the voltage of the third node N3, a long-term forward bias will cause the electrical characteristic curve of the driving transistor M2 to drift, affecting the accuracy of the light-emitting brightness. Figure 3, the related technology will perform bias adjustment on the driving transistor M2, and will set a bias adjustment stage td in the holding frame Thold, and write the bias adjustment signal VGMP to the driving transistor M2 through the data writing transistor M1, so that the voltage of the third node N3 of the driving transistor M2 is greater than or equal to the second node N2, and is in a reverse bias state, thereby compensating for the forward bias state of the driving transistor M2 in the light-emitting stage tc, stabilizing the electrical characteristics of the driving transistor M2, and ensuring the accuracy of the light-emitting brightness. However, since the third node N3 is written with a high-level bias adjustment signal VGMP in the bias adjustment stage td, for the compensation module 13 that should be turned off, the gate-source voltage difference of the transistors therein, especially the second transistor M32, is reduced, which will cause it to be unable to be completely turned off, and will also affect the gate voltage of the driving transistor M2, so that the brightness of the light-emitting element in the display frame is abnormal, and an abnormal screen flickering phenomenon occurs.

[0062] Figure 4 is a pixel circuit driving timing diagram provided by an embodiment of the present invention, referring to Figure 1 , Figure 2 and Figure 4 In view of the above technical problems, in an embodiment of the present invention, the compensation module 13 is configured to be controlled by the first scanning signal S2N; the first scanning signal S2N satisfies: V11<V11'; wherein V11 is the high level voltage of the first scanning signal S2N in the refresh frame Trefresh, and V11' is the high level voltage of the first scanning signal S2N in the hold frame Thold.

[0063] Specifically, the compensation module 13 includes a first transistor M31 and a second transistor M32, which are sequentially connected in series between the gate and the second electrode of the driving transistor M2, and the first transistor M31 and the second transistor M32 can be set as P-type channel transistors, and their gates receive the first scanning signal S2N. As described above, when the first scanning signal S2N is in a low-level voltage state, the first transistor M31 and the second transistor M32 are turned on, and the pixel circuit 10 enters the data writing stage tb. When the first scanning signal S2N is in a high-level voltage state, the first transistor M31 and the second transistor M32 are turned off, and the pixel circuit 10 can be in the gate reset stage ta of the refresh frame Trefres, the light-emitting stage tc, and the bias adjustment stage td and the light-emitting stage tc of the hold frame Thold. In the embodiment of the present invention, the high level voltage of the first scanning signal S2N in the refresh frame Trefresh and the holding frame Thold is set differently, that is, the high level voltage of the first scanning signal S2N in the refresh frame Trefresh (example is 7.8V) is set lower than the high level voltage of the first scanning signal S2N in the holding frame Thold (example is 8V). On the one hand, the first scanning signal S2N can control the first transistor M31 and the second transistor M32 to turn off at the light emitting stage tc of the refresh frame Trefresh with a relatively low high level voltage, thereby reducing the influence of the gate on the intermediate node of the two transistors. On the other hand, the first scanning signal S2N can be controlled to turn off the first transistor M31 and the second transistor M32 at a relatively high high-level voltage during the bias adjustment stage td of the holding frame Thold, thereby avoiding the situation where the first transistor M31 and the second transistor M32 cannot be turned off due to the high-level bias adjustment signal VGMP written into the third node N3, thereby preventing the abnormal screen flickering phenomenon.In other words, if the first scanning signal S2N uses the same high-level voltage in the refresh frame Trefresh and the holding frame Thold, for example, both use a high-level voltage of 7.8V, and if the bias adjustment signal VGMP is written through the data writing module 11 in the holding frame Thold, the bias adjustment signal VGMP is lower than the high-level voltage of the first scanning signal S2N, and the example bias adjustment signal VGMP is 7V. At this time, the third node N3 where the bias adjustment signal VGMP is written is substantially raised, that is, the voltage of the source of the transistor in the compensation module 13 is increased, and the gate voltage of 7.8V and the source voltage of 7V cannot produce a sufficient gate-source voltage difference, which will cause the transistor of the compensation module 13 to be unable to be turned off in the holding frame Thold, which will cause the voltage of the gate of the driving transistor M2 to change more significantly, and the luminous brightness of the light-emitting element 20 will be more significantly different from the target brightness, resulting in an abnormal screen flickering phenomenon.

[0064] In order to intuitively demonstrate the display effect and internal principle of the display panel in the embodiment of the present invention, the embodiment of the present invention has also carried out corresponding experimental verification.

[0065] first, Figure 5 is a comparison diagram of display panel display brightness under two first scanning signals provided by an embodiment of the present invention, such as Figure 5 As shown, the curve of the frame brightness of the display panel changing with time when two first scanning signals of 6V high level voltage and 8V high level voltage are used to control the shutdown of the compensation module in the pixel circuit of the display panel, and the base frequency of the display panel is 120HZ. The example in the figure is a 30HZ low-frequency driving state, that is, three holding frames Thold are set after each refresh frame Trefresh in the example in the figure, so as to more clearly reflect the degree of change of the frame brightness. Reference Figure 2 and Figure 5 It can be seen that in each display frame, the frame brightness will decrease to varying degrees due to the leakage problem of the compensation module 13. Specifically, when the pixel circuit 10 is driven by the first scanning signal S2N with a high level voltage of 8V and the compensation module 13 is turned off, the frame brightness of the display panel will decrease more significantly, and the decrease will be larger. The display panel will show obvious changes in light and dark, that is, obvious flickering; however, when the pixel circuit 10 is driven by the first scanning signal S2N with a high level voltage of 6V and the compensation module 13 is turned off, the decrease in the frame brightness of the display panel will be slowed down to a certain extent, that is, the degree of brightness decrease is no longer obvious, and the flickering phenomenon of the display panel is improved to a certain extent. The experimental verification results can also prove that by appropriately reducing the high level voltage of the first scanning signal S2N in the refresh frame Trefresh, the leakage problem of the compensation module 13 can be reduced, thereby reducing the influence of the leakage on the gate voltage of the driving transistor M2, reducing the brightness change of the light-emitting element in each display frame, and improving the flickering phenomenon of the display panel.

[0066] Figure 6 is a curve diagram of the high level voltage of the first scanning signal and the flickering condition of the display panel in the refresh frame provided by an embodiment of the present invention, such as Figure 6 As shown, first, the vertical coordinate flicker value represents the brightness ratio when light and dark change, and the horizontal coordinate is the different high-level voltage values ​​of the first scanning signal S2N. Figure 6 It can be seen that within an appropriate range, or it can be understood that the pixel circuit compensation module can be turned off, the higher the high-level voltage of the first scanning signal S2N in the refresh frame Trefresh, the larger its flicker value, indicating that the light-dark change is more obvious, and the flicker phenomenon is easier to be detected by the human eye; conversely, the lower the high-level voltage of the first scanning signal S2N in the refresh frame Trefresh, the smaller its flcker value, that is, the less obvious the light-dark change is, and the flicker phenomenon is less likely to be detected by the human eye. It can be seen that in the embodiment of the present invention, by appropriately reducing the high-level voltage of the first scanning signal S2N in the refresh frame Trefresh, the leakage current of the transistor in the compensation module 13 can be reduced to avoid affecting the voltage of the gate of the driving transistor M2, thereby preventing the luminous brightness from being significantly different from the target brightness, and improving the flicker phenomenon of the display panel.

[0067] Figure 7 1 is a graph of the first scanning signal high level voltage and the display panel flickering condition in the holding frame provided by an embodiment of the present invention. It should be noted that in the holding frame Thold, in the pixel circuit of the display panel, the bias adjustment signal VGMP is written to the driving transistor M2 through the data writing module 11 for bias adjustment. Figure 7 It can be seen that, contrary to the rule of the refresh frame Trefresh, within an appropriate range, the lower the high-level voltage of the first scanning signal S2N in the holding frame Thold, the larger its flicker value, indicating that the bright and dark changes are more obvious, and the flicker phenomenon is easier to be noticed by the human eye; conversely, the higher the high-level voltage of the first scanning signal S2N in the holding frame Thold, the smaller its flicker value, indicating that the bright and dark changes are less obvious, and the flicker phenomenon is less likely to be noticed by the human eye. It can be seen that in the embodiment of the present invention, by appropriately raising the high-level voltage of the first scanning signal S2N in the holding frame Thold, the gate and source of the transistor in the compensation module can generate a sufficient gate-source voltage difference to ensure that it can be effectively turned off, thereby avoiding the abnormal screen flickering phenomenon caused by the inability to turn off the compensation module.

[0068] The embodiment of the present invention also provides a method for driving a display panel. Figure 8 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention, with reference to Figure 4 and Figure 8Based on the above display panel, the driving method of the present invention may include:

[0069] S110, using the first scanning signal to control the compensation module; wherein the first scanning signal satisfies: V11<V11'; wherein V11 is the high level voltage of the first scanning signal in the refresh frame, and V11' is the high level voltage of the first scanning signal in the hold frame.

[0070] The driving method is essentially to control the compensation module 13, specifically to control the off state of the compensation module 13, by using the first scanning signal S2N that undergoes a high-level voltage change in the refresh frame Trefresh and the hold frame Thold. As mentioned above, setting the high-level voltage of the first scanning signal S2N in the refresh frame Trefresh to be lower than the high-level voltage of the first scanning signal S2N in the hold frame Thold can not only prevent the voltage of the middle node of the dual-gate transistor in the compensation module 13 from being raised by capacitive coupling and causing leakage during the light-emitting phase tc of the refresh frame Trefresh, and prevent the gate voltage of the driving transistor M2 from affecting the light-emitting brightness of the light-emitting element 20 due to leakage of the first transistor M31; it can also prevent the first transistor M31 and the second transistor M32 from being unable to be turned off due to the high-level bias adjustment signal VGMP written into the third node N3 during the bias adjustment phase td of the hold frame Thold, and prevent the abnormal screen flickering phenomenon.

[0071] Continue to refer Figure 1 For the compensation module in the pixel circuit, the display panel in the embodiment of the present invention may be provided with a first shift register circuit 31 and a first high-level voltage signal line 41, the first shift register circuit 31 is electrically connected to the first high-level voltage signal line 41; the first high-level voltage signal line 41 is configured to provide a first high-level voltage signal VGH1 to the first shift register circuit 31; the voltage of the first high-level voltage signal VGH1 in the refresh frame Trefresh is less than the voltage in the hold frame Thold. The first shift register circuit 31 is electrically connected to the compensation module 13 to provide the first scanning signal S2N to the compensation module 13.

[0072] Specifically, those skilled in the art will know that the scanning signal received by the pixel circuit of the display panel is actually provided by the shift register circuit, and each level of shift register unit provides a scanning signal to each row of pixel circuits, thereby realizing a row-by-row scanning process and completing the display of a display frame. Based on this, in the embodiment of the present invention, the first scanning signal S2N provided to the compensation module 13 needs to switch the high-level voltage in the refresh frame Trefresh and the hold frame Thold. The driving chip can provide a changing high-level voltage signal to the shift register circuit, that is, through the first high-level voltage signal line 41, the first shift register circuit 31 is provided with a changing high-level voltage signal, that is, the first high-level voltage signal VGH1 provided by the first high-level voltage signal line 41 has a voltage in the refresh frame Trefresh that is less than the voltage in the hold frame Thold. In other words, when the driving chip provides the first high-level voltage signal VGH1 to the first shift register circuit 31 through the first high-level voltage signal line 41, it can be designed to output different high-level voltage signals in the refresh frame Trefresh and the hold frame Thold, thereby causing the first shift register circuit 31 to generate a change in the high-level voltage signal when the refresh frame Trefresh and the hold frame Thold generate the first scanning signal S2N.

[0073] Fig. 9 is another pixel circuit driving timing diagram provided by an embodiment of the present invention, referring to Figure 4 and Fig. 9 Furthermore, in the embodiment of the present invention, the data writing module 11 may be configured to be controlled by the second scanning signal SP, and the first scanning signal S2N and the second scanning signal SP satisfy: V11 = V12 (such as Figure 4 As shown), or, V11<V12 (as shown Fig. 9 Wherein, V12 is a high level voltage of the second scan signal SP in the refresh frame Trefresh.

[0074] The data writing module 11 includes a third transistor M1, the two electrodes of the third transistor M1 are respectively connected between the data signal input terminal Vdata and the first electrode of the driving transistor M2, and the gate of the third transistor M1 receives the second scanning signal SP; the third transistor M1 can also be set as a P-channel transistor.

[0075] exist Figure 4In the illustrated embodiment, the high level voltage V11 of the refresh frame Trefresh of the first scanning signal S2N and the high level voltage V12 of the refresh frame Trefresh of the second scanning signal SP are equal, and both are exemplified as 7.8V, which means that the compensation module 13 and the data writing module 11 use the same high level voltage for shutdown control in the refresh frame Trefresh, and no differentiated processing is performed. Instead, priority is given to the problem that the compensation module 13 may not be able to shut down in the holding frame Thold, and the high level voltage V11' of the first scanning signal S2N in the holding frame Thold is set higher, and is exemplified as 8V, so that the transistors in the compensation module 13, especially the second transistor M32, can still have a sufficient gate-source voltage difference based on the high level voltage signal VGMP written to the source in the bias adjustment stage td, so that the P-type second transistor M32 can be effectively turned off to avoid the problem of abnormal screen flashing in the holding frame Thold.

[0076] exist Fig. 9 In the illustrated embodiment, the high-level voltage V11 (6V in the example) of the refresh frame Trefresh of the first scan signal S2N is less than the high-level voltage V12 (7.8V in the example) of the refresh frame Trefresh of the second scan signal SP, which means that the problem of leakage current in the compensation module 13 in the refresh frame Trefresh can be given priority consideration, and the high-level voltage V11 of the first scan signal S2N in the refresh frame Trefresh is set to be lower than the high-level voltage of the second scan signal SP in the refresh frame Trefresh, that is, on the basis of using a relatively lower high-level voltage to turn off the compensation module 13, it is avoided that the transistor in the compensation module 13 raises the potential of the middle node of the dual-gate transistor due to capacitive coupling, thereby causing leakage current.

[0077] Based on the data writing module being configured to be controlled by the second scanning signal SP, the process of writing the data signal or the bias signal is continued with reference to Figure 8 In the driving method of the embodiment of the present invention, the following steps may be further added:

[0078] S120, using the second scanning signal to control the data writing module; wherein the first scanning signal and the second scanning signal satisfy: V11 = V12, or V11 < V12; wherein V12 is the high level voltage of the second scanning signal in the refresh frame.

[0079] Fig.10 is another pixel circuit driving timing diagram provided by an embodiment of the present invention, referring to Fig.10 , further optionally, the first scanning signal S2N and the second scanning signal SP satisfy: V11'>V12.

[0080] Among them, V11 is 6V, V11' is 8V, and V12 is 7.8V. This embodiment not only considers the problem that the compensation module 13 may not be turned off in the holding frame Thold, and sets the high level voltage V11' of the first scanning signal S2N in the holding frame Thold to be higher, but also considers the problem that the compensation module 13 is prone to leakage in the refresh frame Trefresh, and sets the high level voltage V11 of the first scanning signal S2N in the refresh frame Trefresh to be lower than the high level voltage of the second scanning signal SP in the refresh frame Trefresh, that is, to avoid leakage of the transistor in the compensation module 13.

[0081] Therefore, in this embodiment, the leakage current of the compensation module 13 can be controlled in the refresh frame Trefresh, and the abnormal opening of the compensation module 13 can be effectively avoided in the holding frame Thold, thereby stabilizing the gate potential of the driving transistor M2 in each display frame, avoiding changes in the gate potential of the driving transistor M2 and affecting the deviation of the luminous brightness of the light-emitting element 20 from the target luminous brightness, avoiding flickering or abnormal screen flashing, and ensuring the accuracy and uniformity of the display.

[0082] Continue to refer Figure 4 , Fig. 9 and Fig.10 In an embodiment of the present invention, the refresh frame Trefresh may include a data writing phase ta, and the hold frame Thold may include a bias adjustment phase td; the data writing module 11 is configured to be controlled by the second scanning signal SP, and provide a data signal Vdata to the driving transistor M2 in the data writing phase ta, and provide a bias adjustment signal VGMP to the driving transistor M2 in the bias adjustment phase td, wherein VGMP≥Vdata.

[0083] As described above, the data writing module 11 is multiplexed as a bias adjustment module in the holding frame Thold, and the bias adjustment signal VGMP is written to the data signal input terminal Vdata in the holding frame Thold, so as to make the driving transistor M2 in a reverse bias state, thereby compensating for being in a forward bias state for a long time. In the embodiment of the present invention, the bias adjustment signal VGMP is set to be not lower than the data signal Vdata normally written in the refresh frame Trefresh, and a high-level voltage signal can be written to the third node N3 so that the voltage of the third node N3 is greater than the voltage of the second node N2, and the degree of reverse bias of the driving transistor M2 can be adjusted by a higher bias adjustment signal VGMP, thereby effectively adjusting the bias state of the driving transistor M2.

[0084] Continue to refer Figure 4 and Fig.10Furthermore, the data writing module 11 is configured to write a driving signal to the first electrode of the driving transistor M2, and the maximum value of the driving signal is VGMP; wherein V12>VGMP+1V.

[0085] It can be understood that the third transistor M1 in the data writing module 11 is a P-type transistor, and the high-level voltage of the second scanning signal SP in the refresh frame Trefresh is responsible for controlling the data writing module 11 to turn off. Considering that the data writing module 11 needs to be multiplexed as a bias adjustment module in the holding frame Thold, a high-level bias adjustment signal VGMP is provided to the driving transistor M2, that is, the driving signal written by the data signal input terminal Vdata of the data writing module 11 is not used for data writing all the time, and it will be converted into a bias adjustment signal VGMP with a larger voltage in the bias adjustment stage td. Based on this, when the data writing module 11 is turned off, the high-level voltage written to its gate needs to consider the signal written to the source. Specifically, V12>VGMP+1V is set, which means that the difference between the high-level voltage that controls the data writing module 11 to turn off and the highest voltage signal VGMP written to the data signal input terminal is more than 1V, thereby ensuring that there is a sufficiently large gate-source voltage difference to turn off the P-type third transistor M1. On this basis, the high-level voltage V11' of the first scanning signal S2N in the holding frame Thold is set to be greater than V12, which can ensure that the transistors in the compensation module 13, especially the gate of the second transistor M32, have a sufficiently large high-level voltage. Even if the bias adjustment signal VGMP is written to the third node N3 to reverse bias the driving transistor M2, the gate-source voltage difference of the second transistor M32 can be above 1V, which is greater than its threshold voltage, thereby ensuring that the P-type second transistor M32 is effectively turned off.

[0086] Continue to refer Figure 4 , Fig. 9 and Fig.10 Optionally, the second scanning signal SP also satisfies: V12=V12'; wherein V12' is the high level voltage of the second scanning signal SP in the holding frame Thold. This means that the high level voltage of the second scanning signal SP in the refresh frame and the holding frame does not need to be set differently, and for the third transistor M1 in the data writing module 11, the same high level voltage can be used to effectively shut down in the refresh frame Trefresh and the holding frame Thold.

[0087] Regarding the voltages of the scan signals of the conduction compensation module and the data writing module, in an embodiment of the present invention, the first scan signal S2N and the second scan signal SP may optionally also satisfy: V22≤V21; wherein V21 is the low level voltage of the first scan signal S2N, and V22 is the low level voltage of the second scan signal SP.

[0088] By setting the low level voltage of the first scanning signal S2N not higher than the low level voltage of the second scanning signal SP, it can be ensured that the transistors in the compensation module 13 can have an equal or relatively lower gate-source voltage difference, thereby controlling the P-type first transistor M31 and the second transistor M32 to be fully turned on, and effectively writing the data signal to the gate of the driving transistor M2.

[0089] Similarly, for the data writing module, the display panel in the embodiment of the present invention may further be provided with a second shift register circuit 32 and a second high level voltage signal line 42, the second shift register circuit 32 is electrically connected to the second high level voltage signal line 42; the second high level voltage signal line 42 is configured to provide a second high level voltage signal VGH2 to the second shift register circuit 32; the voltages of the first high level voltage signal VGH1 and the second high level voltage signal VGH2 are different at least part of the time. The second shift register circuit 32 is electrically connected to the data writing module 11 to provide the second scanning signal SP to the data writing module 11.

[0090] Specifically, the voltages of the first high-level voltage signal VGH1 and the second high-level voltage signal VGH2 are different at least in part of the time, which means that the voltages are different in the refresh frame Trefresh and / or the hold frame Thold. Specifically, in the embodiment of the present invention, the second scanning signal SP provided to the data writing module 11 can be set differently from the first scanning signal S2N provided to the compensation module 13, such as Figure 4 , Fig. 9 and Fig.10 In the illustrated embodiment, the high level voltage of the first scanning signal S2N in the holding frame Thold is set higher than the second scanning signal SP, and / or the high level voltage in the refresh frame Trefresh is set lower, thereby forming a difference with the second scanning signal SP. When the differentiated design is specifically implemented, the driver chip can provide the second high level voltage signal VGH2 to the second shift register circuit 32 through the second high level voltage signal line 42, and it is designed to output the same high level voltage signal in the refresh frame Trefresh and the holding frame Thold, and a high level voltage signal different from the first high level voltage signal VGH1 in the refresh frame Trefresh and / or the holding frame Thold, thereby causing the second shift register circuit 32 to generate the second scanning signal SP in the refresh frame Trefresh and the holding frame Thold.

[0091] It should be noted that the second high level voltage signal line 42 and the first high level voltage signal line 41 here are responsible for providing different high level voltage signals to different shift register circuits 32, and the different high level voltage signals can be specifically provided by the driving chip. It can be seen that the second high level voltage signal line 42 and the first high level voltage signal line 41 can be connected to different high level voltage signal output pins of the driving chip to obtain different high level voltage signals.

[0092] In addition, if Figure 1 As shown, the first shift register circuit 31 and the second shift register circuit 32 are respectively arranged on two opposite sides of the display area AA of the display panel. The first shift register circuit 31 or the second shift register circuit 32 is only arranged on the same side of the display area AA. This is only an example of the present invention. Those skilled in the art can arrange the first shift register circuit 31 on both sides of the display area AA at the same time, or arrange the second shift register circuit 32 on both sides of the display area AA at the same time, or arrange the first shift register circuit 31 and the second shift register circuit 32 on the same side of the display area AA according to actual needs. There is no limitation here.

[0093] Fig.11 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig.12 yes Fig.11 The following are some signal timing diagrams of different partitions in the display panel, refer to Fig.11 and Fig.12 In an optional embodiment, the display panel may include a first partition AA1 and a second partition AA2; within the same display time, the proportion of refresh frames Trefresh during the operation of the pixel circuit of the first partition AA1 is higher than the proportion of refresh frames Trefresh during the operation of the pixel circuit of the second partition AA2; the first scan signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first partition AA1 and the second partition AA2 satisfies: V11_1>V11_2; wherein V11_1 is a high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first partition AA1 in the refresh frame Trefresh, and V11_2 is a high-level voltage of the first scan signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second partition AA2 in the refresh frame Trefresh.

[0094] As mentioned above, the display panel can set a high refresh mode and a low refresh mode according to the refresh frequency, and based on the same principle, different areas of the display panel can be further controlled to achieve different refresh frequencies, that is, to achieve a partitioned frequency division function. In an embodiment of the present invention, the display panel is divided into a first partition AA1 and a second partition AA2. In the same time, the different proportions of the refresh frame Trefresh indicate that the two partitions use different refresh frequencies. The proportion of the refresh frame Trefresh in the first partition AA1 is higher, which means that the first partition AA1 is a high refresh area, and the second partition AA2 is a low refresh area. For low-frequency areas with a low refresh frequency and a long time in which the brightness of the refresh frame Trefresh is maintained, when leakage occurs in the compensation module 13 and the brightness changes slightly, it will also accumulate due to the long maintenance time, making it easier for the human eye to perceive. Based on this, in the present embodiment, the high-level voltage V11_2 of the first scanning signal S2N of the second partition AA2 in the refresh frame Trefresh is lower than the high-level voltage V11_1 of the first scanning signal S2N of the first partition AA1 in the refresh frame Trefresh, so that the transistor gate in its compensation module 13 receives a relatively lower high-level voltage for shutdown control, thereby controlling the compensation module 13 in the low-frequency zone to relatively more effectively reduce leakage current, thereby preventing the human eye from perceiving brightness changes caused by leakage current problems.

[0095] For driving other modules in the pixel circuit, the embodiment of the present invention also provides a specific implementation method, which will be referred to below. Figure 2 , Figure 4 , Fig. 9 and Fig.10 , to introduce this.

[0096] Optionally, the gate reset module 14 is configured to be controlled by the third scan signal S1N; the first scan signal S2N and the third scan signal S1N satisfy: V11=V13, and / or, V21=V23; wherein, V11 is a high-level voltage of the first scan signal S2N in the refresh frame Trefresh, V13 is a high-level voltage of the third scan signal S1N in the refresh frame Trefresh, V21 is a low-level voltage of the first scan signal S2N in the refresh frame Trefresh, and V23 is a low-level voltage of the third scan signal S1N in the refresh frame Trefresh.

[0097] Specifically, the gate reset module 14 may include a fourth transistor M41 and a fifth transistor M42; the fourth transistor M41 and the fifth transistor M42 are sequentially connected in series between the gate of the driving transistor M2 and the gate reset signal input terminal Vref1, and the gates of the fourth transistor M41 and the fifth transistor M42 receive the third scanning signal S1N; the fourth transistor M41 and the fifth transistor M42 are P-channel transistors.

[0098] This embodiment means that the first scanning signal S2N of the driving compensation module 13 and the third scanning signal S1N of the driving gate reset module 14 substantially have the same high-level voltage state in the refresh frame Trefresh, that is, they have the same high-level voltage in the refresh frame Trefresh and lower than the high-level voltage in the hold frame Thold, thereby avoiding the gate reset module 14 from generating leakage current in the refresh frame Trefresh due to capacitive coupling, and avoiding the problem of abnormal light emission of the light-emitting element 20 due to the leakage current of the gate reset module 14.

[0099] Furthermore, the first scanning signal and the third scanning signal also satisfy: V11'=V13'; wherein V13' is the high level voltage of the third scanning signal in the holding frame.

[0100] Similarly, this embodiment means that the first scanning signal S2N of the driving compensation module 11 and the third scanning signal S1N of the driving gate reset module 14 substantially have the same high-level voltage state in the holding frame Thold, that is, they have the same high-level voltage in the holding frame Thold and are higher than the refresh frame Trefresh, so that the gate reset module 14 can be effectively turned off in the holding frame Thold.

[0101] In addition, it should be added that in order to avoid the influence of the leakage current of the gate reset module 14 on the luminous brightness, the gate reset module can also be selected as a single transistor design, that is, the dual-gate transistor design is not adopted. Therefore, when holding the frame Thold, even if the third scanning signal S1N is a relatively high high-level voltage, the middle node voltage will not be raised due to the capacitive coupling between the gate and the middle node of the dual-gate transistor, which can prevent the leakage current problem of the gate reset module 14 when holding the frame Thold.

[0102] Fig.13 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.13 For the above-mentioned gate reset module, since the first scanning signal S2N of the driving compensation module 13 and the third scanning signal S1N of the driving gate reset module 14 can have the same high-level voltage state in the refresh frame Trefresh and the hold frame Thold, the first shift register circuit 31 in the display panel can also be set to be electrically connected to the gate reset module 14 to provide the third scanning signal S1N to the gate reset module 14.

[0103] In this embodiment, the first scanning signal S2N of the driving compensation module 13 and the third scanning signal S1N of the driving gate reset module 14 are set to have the same high-level voltage state in the refresh frame Trefresh and the hold frame Thold, so the same shift register circuit, i.e., the first shift register circuit 31, can be used to simultaneously provide the first scanning signal S2N and the third scanning signal S1N. It can be understood that since each level of shift register unit can output multiple levels of first scanning signals S2N with a fixed delay amount, the first scanning signal S2N of other rows can be multiplexed as the third scanning signal S1N of the row according to the delay amounts of the first scanning signal S2N and the third scanning signal S1N required in the same row of pixel circuits 1, so as to control the gate reset module 14 of the row, thereby eliminating the need to separately set a shift register circuit for the gate reset module 14, greatly reducing the number of shift register circuits, reducing the area of ​​the non-display area where the shift register circuit is located, and helping to achieve a narrow frame design.

[0104] Optionally, the anode reset module 15 is configured to be controlled by the second scan signal SP.

[0105] Specifically, the anode reset module 15 may include a sixth transistor M5, the two electrodes of the sixth transistor M5 are connected between the anode reset signal terminal Vref2 and the anode of the light emitting element 20, and the gate of the sixth transistor M5 receives the second scanning signal SP; the sixth transistor M5 is a P-channel transistor.

[0106] It can be understood that the anode reset module 15 has the function of resetting the anode of the light-emitting element 20. Before the light-emitting stage tc of each display frame, by resetting the anode of the light-emitting element 20, that is, writing a fixed anode reset signal to the anode of the light-emitting element 20, it is possible to avoid the anode of the light-emitting element 20 maintaining the voltage state of the previous display frame, thereby preventing the light-emitting brightness of the light-emitting element 20 in the current display frame from being affected by the previous display frame.

[0107] In this embodiment, the anode reset module 15 is configured to be controlled by the second scanning signal SP, which means that both the data writing module 11 and the anode reset module 15 use the second scanning signal SP to control the switch. It can also be understood that in the data writing stage tb, when the data writing module 11 is turned on to write the data signal, the anode reset module 15 is also turned on to reset the anode of the light-emitting element 20. The data writing stage tb is also the anode reset stage.

[0108] For the above-mentioned anode reset module, since the data writing module 11 and the anode reset module 15 can control the switch through the second scanning signal SP, the display panel can also set a second shift register circuit 32 and a second high-level voltage signal line 42 for the anode reset module 15, and the second shift register circuit 32 is electrically connected to the second high-level voltage signal line 42; the second high-level voltage signal line 42 is configured to provide the second high-level voltage signal VGH2 to the second shift register circuit 32; the voltage of the first high-level voltage signal VGH1 and the second high-level voltage signal VGH2 are different at least part of the time. Among them, the second shift register circuit 32 is electrically connected to the data writing module 11 and the anode reset module 15 at the same time to provide the second scanning signal SP to the data writing module 11 and the anode reset module 15. Therefore, it is also no longer necessary to set a shift register circuit separately for the anode reset module 15, which greatly reduces the number of shift register circuits and the area of ​​the non-display area where the shift register circuit is located, which helps to achieve a narrow frame design.

[0109] Optionally, the first light-emitting control unit 161 and the second light-emitting control unit 162 are configured to be controlled by the first light-emitting control signal Emit; the second scanning signal SP and the first light-emitting control signal Emit satisfy: V12=V14, and / or, V22=V24; wherein V14 is a high-level voltage of the first light-emitting control signal Emit, V22 is a high-level voltage of the second scanning signal SP in the refresh frame, and V24 is a low-level voltage of the first light-emitting control signal Emit.

[0110] Specifically, the first light-emitting control unit 161 includes a seventh transistor M61, and the second light-emitting control unit 162 includes an eighth transistor M62; the two electrodes of the seventh transistor M61 are connected between the first power signal terminal PVDD and the first electrode of the driving transistor M2; the two electrodes of the eighth transistor M62 are connected between the second electrode of the driving transistor M2 and the anode of the light-emitting element 20; the gates of the seventh transistor M61 and the eighth transistor M62 receive the first light-emitting control signal Emit; the seventh transistor M61 and the eighth transistor M62 are P-channel transistors.

[0111] This embodiment means that the first light control signal Emit driving the light control module and the second scanning signal SP driving the data writing module 11 have the same level state, which can control the turning off and on of the corresponding transistors according to normal high level voltage and low level voltage.

[0112] For the above-mentioned anode reset module, Fig.14 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.14In an embodiment of the present invention, the display panel may further include a third shift register circuit 33 and a third high-level voltage signal line 43, the light-emitting control module 16 is connected to the third shift register circuit 33; the third shift register circuit 33 is electrically connected to the third high-level voltage signal line 43; the second high-level voltage signal line 42 is electrically connected to the third high-level voltage signal line 43.

[0113] Since the first light control signal Emit for driving the light control module and the second scanning signal SP for driving the data writing module 11 can have the same level state, the shift register circuits respectively set for the light control module 16 and the data writing module 11 of the display panel can adopt the same high level voltage, that is, the third high level voltage signal line 43 corresponding to the third shift register circuit 33 connected to the light control module 16 can be electrically connected to the second high level voltage signal line 42 corresponding to the second shift register circuit 32 connected to the data writing module 11, so as to receive the same high level voltage signal VGH2.

[0114] In other embodiments of the present invention, an independent shift register circuit may be optionally provided for the gate reset module to improve the driving capability. Fig.15 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, referring to Fig.15 A fourth shift register circuit 34 and a fourth high level voltage signal line 44 may also be provided in the display panel, the fourth shift register circuit 34 is electrically connected to the gate reset module 14, the fourth shift register circuit 34 is electrically connected to the fourth high level voltage signal line 44, and the first high level voltage signal line 41 is electrically connected to the fourth high level voltage signal line 44.

[0115] As can be seen from the foregoing, since the first scanning signal S2N driving the compensation module 13 and the third scanning signal S1N driving the gate reset module 14 can be set to have the same high-level voltage state in the refresh frame Trefresh and the hold frame Thold, the shift register circuits respectively set for the compensation module 13 and the gate reset module 14 can use the same high-level voltage, that is, the fourth high-level voltage signal line 44 corresponding to the fourth shift register circuit 34 connected to the gate reset module 14 can be electrically connected to the first high-level voltage signal line 41 corresponding to the first shift register circuit 31 connected to the compensation module 13, so as to receive the same high-level voltage signal VGH1.

[0116] Fig.16 This is another pixel circuit driving timing diagram provided by an embodiment of the present invention. Figure 2 , Fig. 9 , Fig.10 and Fig.16In another embodiment of the present invention, the compensation module 13 may be configured to be controlled by the first scanning signal S2N; the data writing module 11 may be configured to be controlled by the second scanning signal SP; the first scanning signal S2N and the second scanning signal SP satisfy: V11<V12; wherein V11 is the high level voltage of the first scanning signal S2N in the refresh frame Trefresh, and V12 is the high level voltage of the second scanning signal SP in the refresh frame Trefresh.

[0117] Similarly, it can be seen from the foregoing that the high-level voltage V11 (6V in the example) of the refresh frame Trefresh of the first scanning signal S2N is smaller than the high-level voltage V12 (7.8V in the example) of the refresh frame Trefresh of the second scanning signal SP, which means that the problem of leakage current easily occurring in the refresh frame Trefresh of the compensation module 13 can be given priority consideration, and the high-level voltage V11 of the first scanning signal S2N in the refresh frame Trefresh is set to be lower than the high-level voltage of the second scanning signal SP in the refresh frame Trefresh, that is, on the basis of using a relatively lower high-level voltage to turn off the compensation module 13, it is avoided that the transistor in the compensation module 13 raises the potential of the middle node of the dual-gate transistor due to capacitive coupling, thereby causing leakage current.

[0118] It should be noted that if Fig. 9 , Fig.10 and Fig.16 In the embodiment, the gate reset module 14 is controlled by the third scan signal S1N, and the third scan signal S1N may have the same high level voltage state as the first scan signal S2N, that is, Fig. 9 and Fig.10 The embodiment shown can also be reasonably designed according to the influence of the gate reset module 14 on the gate of the driving transistor M2, for example Fig.16 The embodiments shown are not limited here.

[0119] Continue to refer Fig. 9 and Fig.10 Alternatively, V11<V11' can be set, where V11' can be 7.8V or 8V. Fig.10 As shown, when V11'>V12, that is, the high-level voltage V11 of the first scanning signal S2N in the refresh frame Trefresh is set lower than the high-level voltage of the second scanning signal SP in the refresh frame Trefresh, which solves the problem that the compensation module 13 is prone to leakage in the refresh frame Trefresh. At the same time, the high-level voltage V11' of the first scanning signal S2N in the holding frame Thold is set higher, avoiding the problem that the compensation module 13 may not be able to be turned off in the holding frame Thold.

[0120] Continue to refer Fig.11 and Fig.12 ,based on Fig. 9 , Fig.10 or Fig.16 According to the driving timing scheme shown, in the display panel of the embodiment of the present invention, the first scanning signal S2N corresponding to the compensation module 13 of the pixel circuit 10 of the first partition AA1 and the second partition AA2 can also be set to satisfy: V11_1>V11_2; wherein V11_1 is the high-level voltage of the first scanning signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the first partition AA1 in the refresh frame Trefresh, and V11_2 is the high-level voltage of the first scanning signal S2N corresponding to the compensation module 13 in the pixel circuit 10 of the second partition AA2 in the refresh frame Trefresh.

[0121] In this embodiment, the first scanning signal S2N of the second partition AA2 is set to be lower than the high-level voltage V11_2 of the refresh frame Trefresh, so that the transistor gate in its compensation module 13 receives a relatively lower high-level voltage for shutdown control, thereby controlling the compensation module 13 in the low-frequency zone to relatively more effectively reduce leakage current, thereby preventing the human eye from perceiving brightness changes caused by leakage current problems.

[0122] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Fig.17 A schematic diagram of a display device according to an embodiment of the present invention is provided. Fig.17 , the display device includes the display panel 1 provided by any embodiment of the present invention, therefore, the display device provided by the embodiment of the present invention has the corresponding beneficial effects of the display panel provided by the embodiment of the present invention, which will not be repeated here. Exemplarily, the display device can be an electronic device such as a mobile phone, a computer, a smart wearable device (for example, a smart watch), and a vehicle-mounted display device, which is not limited by the embodiment of the present invention.

[0123] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: including a pixel circuit and a light emitting element; The pixel circuit includes a data writing module, a driving module and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; Wherein, the picture display process of the display panel includes display frames, and the display frames include refresh frames and hold frames; The compensation module is configured to be controlled by a first scanning signal; the first scanning signal satisfies: V11<V11'; wherein V11 is a high level voltage of the first scanning signal in the refresh frame, and V11' is a high level voltage of the first scanning signal in the hold frame.

2. The display panel according to claim 1, characterized in that: The data writing module is configured to be controlled by a second scanning signal, and the first scanning signal and the second scanning signal satisfy: V11=V12, or V11<V12; wherein V12 is a high level voltage of the second scanning signal in the refresh frame.

3. The display panel according to claim 2, characterized in that: The first scanning signal and the second scanning signal satisfy: V11'>V12.

4. The display panel according to claim 2, characterized in that: The data writing module is configured to write a driving signal to the first electrode of the driving transistor, and the maximum value of the driving signal is VGMP; Among them, V12>VGMP+1V.

5. The display panel according to claim 1, characterized in that: The display panel includes a first partition and a second partition; in the same time, the proportion of the refresh frame in the operation process of the pixel circuit of the first partition is higher than the proportion of the refresh frame in the operation process of the pixel circuit of the second partition; The first scanning signals corresponding to the compensation modules of the pixel circuits of the first partition and the second partition satisfy: V11_1>V11_2; Among them, V11_1 is the high level voltage of the first scanning signal corresponding to the compensation module in the pixel circuit of the first partition in the refresh frame, and V11_2 is the high level voltage of the first scanning signal corresponding to the compensation module in the pixel circuit of the second partition in the refresh frame.

6. The display panel according to claim 2, characterized in that: The second scanning signal also satisfies: V12=V12′; wherein V12′ is a high level voltage of the second scanning signal in the holding frame.

7. The display panel according to claim 2, characterized in that: The first scanning signal and the second scanning signal also satisfy: V22≤V21; Among them, V21 is the low level voltage of the first scanning signal, and V22 is the low level voltage of the second scanning signal.

8. The display panel according to claim 2, characterized in that: The compensation module comprises a first transistor and a second transistor, wherein the first transistor and the second transistor are sequentially connected in series between the gate electrode and the second electrode of the driving transistor, and the gate electrodes of the first transistor and the second transistor receive the first scanning signal; The data writing module comprises a third transistor, two electrodes of the third transistor are respectively connected between the data signal input terminal and the first electrode of the driving transistor, and the gate of the third transistor receives the second scanning signal; The first transistor, the second transistor and the third transistor are all P-channel transistors.

9. The display panel according to claim 1, characterized in that: The pixel circuit further comprises a gate reset module; the gate reset module is connected to the gate reset signal terminal and the gate of the driving transistor; The gate reset module is configured to be controlled by a third scanning signal; The first scanning signal and the third scanning signal satisfy: V11=V13, and / or, V21=V23; Among them, V11 is the high level voltage of the first scan signal in the refresh frame, V13 is the high level voltage of the third scan signal in the refresh frame, V21 is the low level voltage of the first scan signal in the refresh frame, and V23 is the low level voltage of the third scan signal in the refresh frame.

10. The display panel according to claim 9, characterized in that: The first scanning signal and the third scanning signal also satisfy: V11'=V13'; Wherein, V13' is the high level voltage of the third scanning signal in the holding frame.

11. The display panel according to claim 9, characterized in that: The gate reset module includes a fourth transistor and a fifth transistor; The fourth transistor and the fifth transistor are sequentially connected in series between the gate of the driving transistor and the gate reset signal input terminal, and the gates of the fourth transistor and the fifth transistor receive the third scanning signal; The fourth transistor and the fifth transistor are P-channel transistors.

12. The display panel according to claim 2, characterized in that: The pixel circuit further includes an anode reset module, wherein the anode reset module is connected between the anode reset signal terminal and the anode of the light emitting element; The anode reset module is configured to be controlled by the second scanning signal.

13. The display panel according to claim 12, characterized in that: The anode reset module comprises a sixth transistor, the two electrodes of the sixth transistor are connected between the anode reset signal terminal and the anode of the light emitting element, and the gate of the sixth transistor receives the second scanning signal; The sixth transistor is a P-channel transistor.

14. The display panel according to claim 2 or 3, characterized in that: The pixel circuit further includes a light emitting control module; the light emitting control module includes a first light emitting control unit and a second light emitting control unit; the first light emitting control unit, the driving module, the second light emitting control unit, and the light emitting element are sequentially connected in series between the first power signal terminal and the second power signal terminal; The first light emitting control unit and the second light emitting control unit are configured to be controlled by a first light emitting control signal; The second scanning signal and the first light emitting control signal satisfy: V12=V14, and / or, V22=V24; Among them, V14 is the high level voltage of the first light-emitting control signal, V22 is the high level voltage of the second scanning signal in the refresh frame, and V24 is the low level voltage of the first light-emitting control signal.

15. The display panel according to claim 14, characterized in that: The first light emitting control unit includes a seventh transistor, and the second light emitting control unit includes an eighth transistor; The two electrodes of the seventh transistor are connected between the first power signal terminal and the first electrode of the driving transistor; the two electrodes of the eighth transistor are connected between the second electrode of the driving transistor and the anode of the light emitting element; The gates of the seventh transistor and the eighth transistor receive the first light emitting control signal; The seventh transistor and the eighth transistor are P-channel transistors.

16. The display panel according to claim 1, characterized in that: The refresh frame includes a data writing phase, and the hold frame includes a bias adjustment phase; The data writing module is configured to be controlled by a second scanning signal, provide a data signal Vdata to the driving transistor in the data writing phase, and provide a bias adjustment signal VGMP to the driving transistor in the bias adjustment phase, wherein VGMP≥Vdata.

17. The display panel according to claim 1, characterized in that: The display panel further includes a first shift register circuit and a first high-level voltage signal line, wherein the first shift register circuit is electrically connected to the first high-level voltage signal line; The first high level voltage signal line is configured to provide a first high level voltage signal to the first shift register circuit; The voltage of the first high-level voltage signal in the refresh frame is lower than the voltage in the hold frame; and the first shift register circuit is electrically connected to the compensation module.

18. The display panel according to claim 17, characterized in that: Also includes a second shift register circuit and a second high level voltage signal line, wherein the second shift register circuit is electrically connected to the second high level voltage signal line; The second high level voltage signal line is configured to provide a second high level voltage signal to the second shift register circuit; the voltages of the first high level voltage signal and the second high level voltage signal are different at least part of the time; and the second shift register circuit is electrically connected to the data writing module.

19. The display panel according to claim 18, characterized in that: The pixel circuit also includes a gate reset module, an anode reset module and a light emitting control module; The gate reset module is electrically connected to the first shift register circuit, and the anode reset module is electrically connected to the second shift register circuit; The display panel further includes a third shift register circuit and a third high-level voltage signal line, and the light emitting control module is connected to the third shift register circuit; The third shift register circuit is electrically connected to the third high level voltage signal line; and the second high level voltage signal line is electrically connected to the third high level voltage signal line.

20. The display panel according to claim 18, characterized in that: The pixel circuit also includes a gate reset module, an anode reset module and a light emitting control module; The display panel further includes a third shift register circuit, a fourth shift register circuit, a third high-level voltage signal line and a fourth high-level voltage signal line, the anode reset module is electrically connected to the second shift register circuit, the third shift register circuit is electrically connected to the light emitting control module; the fourth shift register circuit is electrically connected to the gate reset module; The third shift register circuit is electrically connected to the third high level voltage signal line, and the second high level voltage signal line is electrically connected to the third high level voltage signal line; The fourth shift register circuit is electrically connected to the fourth high-level voltage signal line, and the first high-level voltage signal line is electrically connected to the fourth high-level voltage signal line.

21. A display panel, characterized in that: including a pixel circuit and a light emitting element; The pixel circuit includes a data writing module, a driving module and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; Wherein, the picture display process of the display panel includes display frames, and the display frames include refresh frames; The compensation module is configured to be controlled by a first scanning signal; the data writing module is configured to be controlled by a second scanning signal; The first scanning signal and the second scanning signal satisfy: V11<V12; Among them, V11 is the high level voltage of the first scanning signal in the refresh frame, and V12 is the high level voltage of the second scanning signal in the refresh frame.

22. The display panel according to claim 21, characterized in that: The display frame also includes a holding frame; The first scanning signal also satisfies: V11<V11′; wherein V11′ is a high level voltage of the first scanning signal in the holding frame.

23. The display panel according to claim 21, characterized in that: The display panel includes a first partition and a second partition; in the same time, the proportion of the refresh frame in the operation process of the pixel circuit of the first partition is higher than the proportion of the refresh frame in the operation process of the pixel circuit of the second partition; The first scanning signals corresponding to the compensation modules of the pixel circuits of the first partition and the second partition satisfy: V11_1>V11_2; Among them, V11_1 is the high level voltage of the first scanning signal corresponding to the compensation module in the pixel circuit of the first partition in the refresh frame, and V11_2 is the high level voltage of the first scanning signal corresponding to the compensation module in the pixel circuit of the second partition in the refresh frame.

24. A method for driving a display panel, characterized in that: The display panel includes a pixel circuit and a light-emitting element; The pixel circuit includes a data writing module, a driving module and a compensation module; The driving module includes a driving transistor; The data writing module is connected between the data signal input terminal and the first electrode of the driving transistor; The compensation module is connected between the gate and the second electrode of the driving transistor; Wherein, the picture display process of the display panel includes a plurality of display frames, and the plurality of display frames include a refresh frame and a hold frame; The driving method of the display panel includes: The compensation module is controlled by using a first scanning signal, wherein the first scanning signal satisfies: V11<V11'; wherein V11 is a high level voltage of the first scanning signal in the refresh frame, and V11' is a high level voltage of the first scanning signal in the hold frame.

25. The driving method according to claim 24, characterized in that: The display panel driving method further includes: The data writing module is controlled by using a second scanning signal; wherein the first scanning signal and the second scanning signal satisfy: V11=V12, or V11<V12; wherein V12 is a high level voltage of the second scanning signal in the refresh frame.

26. The driving method according to claim 25, characterized in that: The first scanning signal and the second scanning signal also satisfy: V11'>V12.

27. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-23.

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