Electrical conversion structure and manufacturing method thereof, and wafer interconnection structure and manufacturing method thereof

Abstract

The invention discloses an electrical conversion structure and a manufacturing method thereof, and a wafer interconnection structure and a manufacturing method thereof, which are characterized in that electrical interconnection in the horizontal direction is realized by utilizing an epitaxial low-resistance layer, and a low-resistance region is formed to be communicated with the low-resistance layer and electrical interconnection in the vertical direction is realized by adopting thermal diffusion or ion implantation of a local selection region on high-resistance layers on two sides of the low-resistance layer. According to the electrical conversion structure and the manufacturing method thereof as well as the wafer interconnection structure and the manufacturing method thereof, on the basis of the existing semiconductor equipment and technology, the interconnection area is defined by utilizing the photoetching technology, high-density interconnection with hundred-nanometer intervals is realized, wet chemical links such as electroplating and chemical mechanical polishing are not needed, and the production cost is reduced. The technical difficulty of large-area high-density electric interconnection is reduced, and meanwhile the yield is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an electrical conversion structure and a manufacturing method thereof, a wafer interconnection structure and a manufacturing method thereof. Background Art

[0002] Through-silicon via (TSV) and through-glass via (TGV) technologies for advanced semiconductor packaging achieve vertical electrical interconnection of chips through through-holes on silicon wafers and glass substrates and filling the holes with metal or other conductive materials. Compared with bump connections, through-hole technology has higher integration and better high-speed performance.

[0003] Through-hole technology includes multiple key processes such as hole formation, insulation, seed layer, hole filling, planarization and thinning, and requires special equipment to cooperate. For example, the deposition of the seed layer requires physical vapor deposition equipment with good coverage of deep holes. The unevenness of the seed layer deposition will be transmitted to the electroplating hole filling link, causing uneven or incomplete electroplating hole filling, resulting in failure and reduced yield, and it is difficult to compensate or repair later.

[0004] In addition, as a supplement to vertical interconnection, horizontal electrical interconnection needs to be achieved through the redistribution layer (RDL) layer. Through holes together with redistribution technology form a functionally complete high-performance package.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide an electrical conversion structure and a manufacturing method thereof, a wafer interconnection structure and a manufacturing method thereof, which can achieve high-density interconnection with a spacing of hundreds of nanometers based on existing semiconductor equipment and technology, and do not require the use of wet chemical steps such as electroplating and chemical mechanical polishing, thereby reducing the technical difficulty of large-area high-density electrical interconnection and improving the yield.

[0007] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A method for manufacturing an electrical conversion structure, wherein the electrical conversion structure is used to realize electrical interconnection of multiple wafers to be integrated, comprising:

[0009] Providing a substrate, and sequentially forming a first high-resistance layer, a low-resistance layer, and a second high-resistance layer on the surface of the substrate;

[0010] forming a first low resistance region on the second high resistance layer, wherein the first low resistance region is in contact with and electrically connected to the low resistance layer, and the first low resistance region is used to electrically connect one or more wafers to be integrated;

[0011] retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer;

[0012] Retaining the area on the low-resistance layer corresponding to the first low-resistance region and the wiring area, and removing other areas;

[0013] The substrate is removed, and a second low resistance region is formed on the first high resistance layer, wherein the second low resistance region is in contact with and electrically connected to the low resistance layer, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated.

[0014] In one or more embodiments of the present invention, before the step of sequentially forming a first high resistance layer, a low resistance layer, and a second high resistance layer on the surface of the substrate, the method further comprises:

[0015] A step of forming a sacrificial layer on the surface of the substrate;

[0016] The first high resistance layer, the low resistance layer and the second high resistance layer are sequentially formed on the surface of the sacrificial layer.

[0017] In one or more embodiments of the present invention, a first low resistance region is formed on the second high resistance layer by thermal diffusion or ion implantation; and / or,

[0018] The doping type of the first low resistance region is the same as that of the low resistance layer; and / or,

[0019] The doping concentration of the first low resistance region is higher than 5E18cm -3 and / or,

[0020] forming a second low resistance region on the first high resistance layer by thermal diffusion or ion implantation; and / or,

[0021] The doping type of the second low resistance region is the same as that of the low resistance layer; and / or,

[0022] The doping concentration of the second low resistance region is higher than 5E18cm -3 .

[0023] In one or more embodiments of the present invention, the resistivity of the first high resistance layer is greater than 1000Ω / sq; and / or,

[0024] The thickness of the first high resistance layer is in the range of 100 nm to 5000 nm; and / or,

[0025] The resistivity of the second high resistance layer is greater than 1000Ω / sq; and / or,

[0026] The thickness of the second high resistance layer is in the range of 100 nm to 5000 nm; and / or,

[0027] The resistivity of the low-resistance layer is less than 100Ω / sq; and / or,

[0028] The thickness of the low resistance layer is in the range of 20nm-1000nm.

[0029] An electrical conversion structure for realizing electrical interconnection of multiple wafers to be integrated, comprising:

[0030] The low-resistance layer has a first surface and a second surface that are oppositely disposed;

[0031] A first low-resistance structure is formed on a first surface of the low-resistance layer and is electrically connected to the low-resistance layer, wherein the first low-resistance structure is used to electrically connect one or more wafers to be integrated;

[0032] A first high resistance layer is formed on the second surface of the low resistance layer, a second low resistance region is formed in the first high resistance layer, the second low resistance region is in contact with the low resistance layer and is electrically connected, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated;

[0033] The first low-resistance structure, the low-resistance layer and the second low-resistance region form a conductive channel.

[0034] A method for manufacturing a wafer interconnect structure, comprising:

[0035] Providing a first wafer and a second wafer, wherein the first wafer has a first electrical contact area, and the second wafer has a second electrical contact area;

[0036] Providing a substrate, and sequentially forming a first high-resistance layer, a low-resistance layer, and a second high-resistance layer on the surface of the substrate;

[0037] According to the first electrical contact area on the first wafer, a first low resistance area corresponding to the first electrical contact area is formed on the second high resistance layer, wherein the first low resistance area is in contact with the low resistance layer and is electrically connected;

[0038] retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer;

[0039] Retaining the area on the low-resistance layer corresponding to the first low-resistance region and the wiring area, and removing other areas;

[0040] bonding a first electrical contact region of the first wafer to the first low resistance region;

[0041] removing the substrate;

[0042] According to the second electrical contact area on the second wafer, a second low resistance area is formed on the first high resistance layer, wherein the second low resistance area is in contact with the low resistance layer and is electrically connected;

[0043] The second electrical contact region of the second wafer is bonded to the second low resistance region.

[0044] In one or more embodiments of the present invention, when bonding the first electrical contact region of the first wafer to the first low-resistance region, the bonding vacuum is better than 0.1 Pa, the bonding temperature is lower than 400° C., and the bonding pressure is less than 10 kN; and / or,

[0045] When the second electrical contact area of ​​the second wafer is bonded to the second low-resistance area, the bonding vacuum is better than 0.1 Pa, the bonding temperature is lower than 400° C., and the bonding pressure is less than 10 kN.

[0046] In one or more embodiments of the present invention, before bonding the first electrical contact region of the first wafer to the first low resistance region, the method further includes:

[0047] Performing activation treatment on the surface of the first low-resistance region and the surface of the first wafer under vacuum conditions;

[0048] and / or,

[0049] Before bonding the second electrical contact region of the second wafer to the second low resistance region, the method further includes:

[0050] The surface of the first high-resistance layer, the surface of the second low-resistance region and the surface of the second wafer are activated under vacuum conditions.

[0051] In one or more embodiments of the present invention, according to the first electrical contact area on the first wafer, forming a first low resistance area corresponding thereto on the second high resistance layer includes:

[0052] According to the relative position and lateral shape of the first electrical contact area on the first wafer, a pattern with the same position and shape is defined by photolithography in the second high resistance layer, and the photolithography pattern is regionally doped by thermal diffusion or ion implantation to form a first low resistance area;

[0053] and / or,

[0054] According to the second electrical contact area on the second wafer, a second low resistance area is formed on the first high resistance layer, comprising:

[0055] According to the relative position and lateral shape of the second electrical contact area on the second wafer, a pattern with the same position and shape is defined by photolithography in the first high resistance layer, and the photolithography pattern is regionally doped by thermal diffusion or ion implantation to form a second low resistance area.

[0056] In one or more embodiments of the present invention, the doping type of the first low resistance region is the same as that of the low resistance layer; and / or,

[0057] The doping concentration of the first low resistance region is higher than 5E18cm-3 and / or,

[0058] The doping type of the second low resistance region is the same as that of the low resistance layer; and / or,

[0059] The doping concentration of the second low resistance region is higher than 5E18cm -3 and / or,

[0060] The resistivity of the first high resistance layer is greater than 1000Ω / sq; and / or,

[0061] The thickness of the first high resistance layer is in the range of 100 nm to 5000 nm; and / or,

[0062] The resistivity of the second high resistance layer is greater than 1000Ω / sq; and / or,

[0063] The thickness of the second high resistance layer is in the range of 100 nm to 5000 nm; and / or,

[0064] The resistivity of the low-resistance layer is less than 100Ω / sq; and / or,

[0065] The thickness of the low resistance layer is in the range of 20nm-1000nm.

[0066] A wafer interconnect structure, comprising:

[0067] An electrical conversion structure, comprising a low resistance layer, a first low resistance structure and a first high resistance layer, wherein the low resistance layer has a first surface and a second surface arranged opposite to each other; the first low resistance structure is formed on the first surface of the low resistance layer and is electrically connected to the low resistance layer; the first high resistance layer is formed on the second surface of the low resistance layer, a second low resistance region is formed in the first high resistance layer, and the second low resistance region is in contact with the low resistance layer and is electrically connected; wherein the first low resistance structure, the low resistance layer and the second low resistance region form a conductive path;

[0068] A first wafer having a first electrical contact region, wherein the first electrical contact region is in contact with and electrically connected to a first low-resistance structure of the electrical conversion structure;

[0069] The second wafer has a second electrical contact region, wherein the second electrical contact region is in contact with and electrically connected to the second low-resistance region of the electrical conversion structure.

[0070] Compared with the prior art, the electrical conversion structure and its manufacturing method, the wafer interconnection structure and its manufacturing method of the present invention utilize an epitaxial low-resistance layer to achieve electrical interconnection in the horizontal (lateral) direction, and form a low-resistance area to connect the low-resistance layer by locally selective thermal diffusion or ion implantation of the high-resistance layer on both sides of the low-resistance layer, thereby achieving electrical interconnection in the vertical (vertical) direction.

[0071] The electrical conversion structure and its manufacturing method, the wafer interconnection structure and its manufacturing method of the present invention are based on existing semiconductor equipment and technology, use photolithography technology to define the interconnection area, and realize high-density interconnection with a spacing of hundreds of nanometers. There is no need to use wet chemical steps such as electroplating and chemical mechanical polishing, which reduces the technical difficulty of large-area high-density electrical interconnection and improves the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0073] Figure 1 is a flow chart of a method for manufacturing an electrical conversion structure in one embodiment of the present invention;

[0074] Figure 2 is a flow chart of a method for manufacturing a wafer interconnect structure in one embodiment of the present invention;

[0075] Figure 3a-3g 1 is a structural diagram of the steps of a method for manufacturing a wafer interconnect structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0076] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0077] As mentioned in the background technology, the existing method of vertical electrical interconnection of chips through silicon via (TSV) and through glass via (TGV) technology requires special equipment, is costly, and may result in low yield, which is difficult to compensate or repair later. At the same time, an auxiliary redistribution (RDL) layer is required for horizontal electrical interconnection to achieve complete high-performance packaging.

[0078] Based on this, the present invention proposes an electrical conversion structure and a manufacturing method thereof, a wafer interconnection structure and a manufacturing method thereof, which utilize an epitaxial low-resistance layer to realize electrical interconnection in the horizontal (lateral) direction, and form a low-resistance region to connect the low-resistance layer by using local selective thermal diffusion or ion implantation on the high-resistance layer on both sides of the low-resistance layer, thereby realizing electrical interconnection in the vertical (vertical) direction. The electrical conversion structure and a manufacturing method thereof, a wafer interconnection structure and a manufacturing method thereof of the present invention are based on existing semiconductor equipment and technology, and utilize photolithography technology to define the interconnection region to realize high-density interconnection with a spacing of hundreds of nanometers, and do not require the use of wet chemical steps such as electroplating and chemical mechanical polishing, thereby reducing the technical difficulty of large-area high-density electrical interconnection and improving the yield rate.

[0079] like Figure 1 As shown, a method for manufacturing an electrical conversion structure in an embodiment of the present invention includes the following specific steps:

[0080] S1, providing a substrate, and sequentially forming a first high resistance layer, a low resistance layer and a second high resistance layer on the surface of the substrate.

[0081] The substrate may be a single crystal substrate or a single crystal-oxide composite substrate. A composite layer structure containing a sacrificial layer, a first high resistance layer, a low resistance layer and a second high resistance layer is formed by sequential epitaxial growth or ion implantation on the substrate. Among them, the resistivity of the first high resistance layer is greater than 1000Ω / sq (ohms per square); the thickness of the first high resistance layer ranges from 100nm to 5000nm; the resistivity of the second high resistance layer is greater than 1000Ω / sq; the thickness of the second high resistance layer ranges from 100nm to 5000nm; the resistivity of the low resistance layer is less than 100Ω / sq; the thickness of the low resistance layer ranges from 20nm to 1000nm. The provision of the sacrificial layer can facilitate the subsequent removal of the substrate.

[0082] S2, forming a first low resistance region on the second high resistance layer, the first low resistance region is in contact with the low resistance layer and is electrically connected, and the first low resistance region is used to electrically connect one or more wafers to be integrated.

[0083] According to the relative position and lateral shape of the area or array that needs to be electrically interconnected on the wafer to be integrated, such as the electrode, a pattern with the same position and shape can be defined in the second high resistance layer by photolithography, and then the pattern is regionally doped by thermal diffusion or ion implantation to form a first low resistance region. The doping polarity of the first low resistance region is the same as that of the low resistance layer, and the doping concentration of the first low resistance region is higher than 5E18cm -3 , the first low resistance region is in full contact with the low resistance layer and is electrically conductive.

[0084] S3, retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer.

[0085] On the composite layer structure, the first low resistance region is retained and the region outside the first low resistance region in the second high resistance layer is removed by dry or wet etching.

[0086] S4, retaining the area on the low resistance layer corresponding to the first low resistance region and the wiring area, and removing other areas.

[0087] In the composite layer structure, in the low-resistance layer, the area corresponding to the first low-resistance area and the area requiring lateral wiring are retained, and other areas in the low-resistance layer are removed by dry or wet etching. Among them, the area corresponding to the first low-resistance area in the low-resistance layer can be understood as the area covered by the vertical projection of the first low-resistance area in the thickness direction of the composite layer structure. The area requiring lateral wiring is the connection area required when different areas corresponding to different first low-resistance areas need to be horizontally connected (horizontally).

[0088] S5, removing the substrate, forming a second low resistance region on the first high resistance layer, the second low resistance region is in contact with the low resistance layer and is electrically connected, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated.

[0089] The substrate is completely removed by using a sacrificial layer using mechanical and chemical methods to expose the first high-resistance layer close to one side of the substrate.

[0090] According to the relative position and lateral shape of the areas or arrays that need to be electrically interconnected on other wafers to be integrated, such as electrodes, a pattern with the same position and shape can be defined in the first high-resistance layer by photolithography, and then the pattern is regionally doped by thermal diffusion or ion implantation to form a second low-resistance region. The doping polarity of the second low-resistance region is the same as that of the low-resistance layer, and the doping concentration of the second low-resistance region is higher than 5E18cm -3 , the second low resistance region is in full contact with the low resistance layer and is electrically conductive.

[0091] Finally, the first low-resistance region, the low-resistance layer and the second low-resistance region form a conductive channel, and a plurality of wafers to be integrated are electrically interconnected in a vertical direction through the conductive channel.

[0092] The present invention also provides an electrical conversion structure for realizing electrical interconnection of multiple wafers to be integrated, the electrical conversion structure comprising a low resistance layer, a first low resistance structure and a first high resistance layer, wherein the first resistance structure is the first resistance region.

[0093] The low-resistance layer has a first surface and a second surface which are arranged opposite to each other. The resistivity of the low-resistance layer is less than 100Ω / sq; and the thickness of the low-resistance layer ranges from 20nm to 1000nm.

[0094] The first low-resistance structure is formed on the first surface of the low-resistance layer and is electrically connected to the low-resistance layer. The first low-resistance structure is used to electrically connect one or more wafers to be integrated. The doping polarity of the first low-resistance region is the same as that of the low-resistance layer, and the doping concentration of the first low-resistance region is higher than 5E18cm -3 .

[0095] The first high resistance layer is formed on the second surface of the low resistance layer. The resistivity of the second high resistance layer is greater than 1000Ω / sq; the thickness of the second high resistance layer ranges from 100nm to 5000nm. A second low resistance region is formed in the first high resistance layer, the second low resistance region is in contact with the low resistance layer and is electrically conductive, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated. The doping polarity of the second low resistance region is the same as that of the low resistance layer, and the doping concentration of the second low resistance region is higher than 5E18cm -3 .

[0096] The first low-resistance structure, the low-resistance layer and the second low-resistance region form a conductive channel.

[0097] The electrical conversion structure of the present invention can be manufactured by the above-mentioned method for manufacturing the electrical conversion structure.

[0098] like Figure 2 As shown, a method for manufacturing a wafer interconnect structure in an embodiment of the present invention includes the following specific steps:

[0099] S10, providing a first wafer and a second wafer, wherein the first wafer has a first electrical contact region, and the second wafer has a second electrical contact region. The first electrical contact region and the second electrical contact region may be a single region or a plurality of array regions.

[0100] S20, providing a substrate, and sequentially forming a first high resistance layer, a low resistance layer, and a second high resistance layer on a surface of the substrate.

[0101] refer to Figure 3a As shown, the substrate 10 can be a single crystal substrate or a single crystal-oxide composite substrate. A composite layer structure including a sacrificial layer 21, a first high resistance layer 22, a low resistance layer 23 and a second high resistance layer 24 is formed by sequential epitaxial growth or ion implantation on the substrate 10. Among them, the resistivity of the first high resistance layer 22 is greater than 1000Ω / sq; the thickness of the first high resistance layer 22 is in the range of 100nm-5000nm; the resistivity of the second high resistance layer 24 is greater than 1000Ω / sq; the thickness of the second high resistance layer 24 is in the range of 100nm-5000nm; the resistivity of the low resistance layer 23 is less than 100Ω / sq; the thickness of the low resistance layer 23 is in the range of 20nm-1000nm. The provision of the sacrificial layer 21 can facilitate the subsequent removal of the substrate 10.

[0102] S30 , forming a first low resistance region corresponding to the first electrical contact region on the first wafer on the second high resistance layer, wherein the first low resistance region contacts the low resistance layer and is electrically connected.

[0103] refer to Figure 3b As shown, according to the relative position and lateral shape of the area or array A1 that needs to be electrically interconnected on the first wafer A to be connected, such as an electrode, a pattern with the same position and shape can be photolithographically defined in the second high resistance layer 24, and then the pattern is regionally doped by thermal diffusion or ion implantation to form a first low resistance region 241. The doping polarity of the first low resistance region 241 is the same as that of the low resistance layer 23, and the doping concentration of the first low resistance region 241 is higher than 5E18cm -3 , the first low resistance region 241 is in full contact with the low resistance layer 23 and is electrically conductive.

[0104] S40, retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer.

[0105] refer to Figure 3c As shown, on the composite layer structure, the first low resistance region 241 is retained and the area outside the first low resistance region 241 in the second high resistance layer 24 is removed by dry or wet etching.

[0106] S50, retaining the area on the low-resistance layer corresponding to the first low-resistance region and the wiring area, and removing other areas.

[0107] refer to Figure 3c As shown, in the composite layer structure, in the low-resistance layer 23, the area corresponding to the first low-resistance region 241 and the area requiring horizontal wiring are retained, and other areas in the low-resistance layer 23 are removed by dry or wet etching. Among them, the area corresponding to the first low-resistance region 241 in the low-resistance layer 23 can be understood as the area covered by the vertical projection of the first low-resistance region in the thickness direction of the composite layer structure. The area requiring horizontal wiring is the connection area required when different areas corresponding to different first low-resistance regions need to be horizontally connected (horizontally).

[0108] S60 , bonding the first electrical contact region of the first wafer to the first low resistance region.

[0109] refer to Figure 3d As shown, the first low resistance area 241 is aligned with the area or array A1 of the first wafer A that needs to be electrically interconnected, and after the surface of the first low resistance area 241 and the surface of the first wafer A are activated under vacuum conditions, wafer-level low-temperature bonding is performed, the bonding vacuum degree is better than 0.1 Pa, the bonding temperature is lower than 400°C, and the bonding pressure is less than 10kN.

[0110] S70, removing the substrate.

[0111] refer to Figure 3eAs shown, the substrate 10 is completely removed by using the sacrificial layer 21 by mechanical and chemical methods, exposing the first high resistance layer 22 close to one side of the substrate 10 .

[0112] S80 , forming a second low resistance region on the first high resistance layer according to the second electrical contact region on the second wafer, wherein the second low resistance region contacts the low resistance layer and is electrically connected.

[0113] refer to Figure 3f As shown, according to the relative position and lateral shape of the area or array B1 that needs to be electrically interconnected on the second wafer B to be connected, such as an electrode, a pattern with the same position and shape can be photolithographically defined in the first high resistance layer 22, and then the pattern is regionally doped by thermal diffusion or ion implantation to form a second low resistance region 221. The doping polarity of the second low resistance region 221 is the same as that of the low resistance layer 23, and the doping concentration of the second low resistance region 221 is higher than 5E18cm -3 , the second low resistance region 221 is in full contact with the low resistance layer 23 and is electrically conductive.

[0114] S90 , bonding the second electrical contact region of the second wafer to the second low resistance region.

[0115] refer to Figure 3g As shown, the second low resistance area 221 is aligned with the area or array B1 of the second wafer B that needs to be electrically interconnected, and after the surface of the second low resistance area 221 and the surface of the second wafer B are activated under vacuum conditions, a second wafer-level low-temperature bonding is performed, the bonding vacuum degree is better than 0.1 Pa, the bonding temperature is lower than 400°C, and the bonding pressure is less than 10kN.

[0116] After bonding, the first wafer A and the second wafer B are electrically interconnected in the vertical and horizontal directions through the longitudinal selective doping and low resistance layer of the first high resistance region and the second high resistance region.

[0117] The present invention also provides a wafer interconnection structure, comprising:

[0118] The electrical conversion structure includes a low resistance layer, a first low resistance structure and a first high resistance layer.

[0119] The low-resistance layer has a first surface and a second surface which are arranged opposite to each other. The resistivity of the low-resistance layer is less than 100Ω / sq; and the thickness of the low-resistance layer ranges from 20nm to 1000nm.

[0120] The first low-resistance structure is formed on the first surface of the low-resistance layer and is electrically connected to the low-resistance layer. The doping polarity of the first low-resistance structure is the same as that of the low-resistance layer, and the doping concentration of the first low-resistance structure is higher than 5E18cm -3 .

[0121] The first high resistance layer is formed on the second surface of the low resistance layer. The resistivity of the second high resistance layer is greater than 1000Ω / sq; the thickness of the second high resistance layer ranges from 100nm to 5000nm. A second low resistance region is formed in the first high resistance layer, and the second low resistance region is in contact with the low resistance layer and electrically conductive. The doping polarity of the second low resistance region is the same as that of the low resistance layer, and the doping concentration of the second low resistance region is higher than 5E18cm -3 .

[0122] Wherein, the first low-resistance structure, the low-resistance layer and the second low-resistance region form a conductive channel;

[0123] A first wafer having a first electrical contact region, the first electrical contact region being in contact with and electrically connected to a first low-resistance structure of the electrical conversion structure;

[0124] The second wafer has a second electrical contact region, and the second electrical contact region is in contact with and electrically connected to the second low-resistance region of the electrical conversion structure.

[0125] The wafer interconnection structure of the present invention can be manufactured by the above-mentioned method for manufacturing a wafer interconnection structure.

[0126] Compared with the prior art, the electrical conversion structure and its manufacturing method, the wafer interconnection structure and its manufacturing method of the present invention utilize an epitaxial low-resistance layer to achieve electrical interconnection in the horizontal (lateral) direction, and form a low-resistance area to connect the low-resistance layer by locally selective thermal diffusion or ion implantation of the high-resistance layer on both sides of the low-resistance layer, thereby achieving electrical interconnection in the vertical (vertical) direction.

[0127] The electrical conversion structure and its manufacturing method, the wafer interconnection structure and its manufacturing method of the present invention are based on existing semiconductor equipment and technology, use photolithography technology to define the interconnection area, and realize high-density interconnection with a spacing of hundreds of nanometers. There is no need to use wet chemical steps such as electroplating and chemical mechanical polishing, which reduces the technical difficulty of large-area high-density electrical interconnection and improves the yield.

[0128] Embodiment 1:

[0129] Using molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD), a 100nm thick InGaP sacrificial layer, an 800nm ​​thick undoped AlGaAs layer (first high resistance layer), a 500nm thick P-type doped InGaAsN layer (low resistance layer) and a 3000nm thick undoped GaAs layer (second high resistance layer) are epitaxially grown in sequence on a 6-inch semi-insulating GaAs substrate.

[0130] The sheet resistance of the InGaAsN layer is 80Ω / sq, the sheet resistance of the AlGaAs layer is 5000Ω / sq, and the sheet resistance of the GaAs layer is 7000Ω / sq.

[0131] According to the shape and size of the electrode of wafer No. 1 to be integrated, a 500nm thick SiO2 mask is deposited on the GaAs layer and photolithography is performed for the first time, and the mask opening is etched into a non-periodic pattern of 20μm-200μm.

[0132] The wafer #1 with mask is placed in a diffusion furnace for Zn diffusion. The diffusion depth is 3000nm and the surface Zn concentration is 1E19cm -3 , remove the SiO2 mask layer.

[0133] A second photolithography is performed according to the requirements of lateral wiring, and then dry etching is used to remove the non-diffused GaAs layer and the InGaAsN layer that does not require lateral wiring is etched away.

[0134] In a 1E-3Pa vacuum environment, the surfaces of the two wafers to be bonded are treated with N2 plasma, and pattern alignment and the first wafer-level bonding are performed under 300°C and 1kN conditions.

[0135] Combine mechanical thinning and polishing with sulfuric acid-hydrogen peroxide mixed solution to remove the GaAs substrate and InGaP sacrificial layer. According to the shape and size of the electrode of the 2# wafer to be integrated, a 300nm thick SiN is deposited on the AlGaAs layer. X Mask and perform photolithography for the third time, etching the mask opening into a periodic pattern of 500nm.

[0136] The masked wafer #2 was implanted with Zn ions, with an implantation depth of 800nm ​​and a surface Zn concentration of 1E20cm -3 , remove SiN X Mask layer.

[0137] In a 1E-3Pa vacuum environment, N2 plasma was used to treat the surfaces of the two wafers to be bonded, and pattern alignment and a second wafer-level bonding were performed under 300°C and 1kN conditions. The vertical and lateral electrical interconnection between wafer #1 and wafer #2 was achieved through selectively doped IIIV multilayer epitaxial wafers.

[0138] Embodiment 2:

[0139] A 12-inch silicon on insulating substrate (SOI) substrate is used, the substrate device layer is 2000nm thick non-doped Si, and the square resistance is 2000Ω / sq. N-type ion implantation is used on the substrate to form a 300nm thick low-resistance layer below the surface 1000nm, and the square resistance is 30Ω / sq.

[0140] According to the shape and size of the electrode of wafer No. 1 to be integrated, a 500nm thick SiO2 mask is deposited on the upper Si layer and photolithography is performed for the first time, and the mask opening is etched into a non-periodic pattern of 20μm-200μm.

[0141] The masked wafer #1 is placed in a diffusion furnace for P diffusion. The diffusion depth is 1000nm and the surface P concentration is 1E18cm -3 , remove the SiO2 mask layer.

[0142] A second photolithography is performed according to the requirements of lateral wiring, and then dry etching is used to remove the non-diffused upper Si layer and the low-resistance layer that does not require lateral wiring is etched away.

[0143] In a 1E-3Pa vacuum environment, the surfaces of the two wafers to be bonded are treated with N2 plasma, and pattern alignment and the first wafer-level bonding are performed under 300°C and 1kN conditions.

[0144] Combine mechanical thinning and polishing with hydrofluoric acid solution to remove the Si substrate and buried SiO2 sacrificial layer. According to the shape and size of the electrode of the 2# wafer to be integrated, a 300nm thick SiN is deposited on the lower Si layer. X Mask and perform photolithography for the third time, etching the mask opening into a periodic pattern of 500nm.

[0145] The masked wafer #2 was implanted with Sb ions, with an implantation depth of 700nm and a surface Sb concentration of 1E20cm -3 , remove SiN X Mask layer.

[0146] In a 1E-3Pa vacuum environment, N2 plasma was used to treat the surfaces of the two wafers to be bonded, and pattern alignment and a second wafer-level bonding were performed at 300°C and 1kN. The vertical and lateral electrical interconnection between wafer #1 and wafer #2 was achieved through selectively doped Si multilayer epitaxial wafers.

[0147] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0148] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing an electrical conversion structure, wherein the electrical conversion structure is used to realize electrical interconnection of multiple wafers to be integrated, characterized in that: include: Providing a substrate, and sequentially forming a first high-resistance layer, a low-resistance layer, and a second high-resistance layer on the surface of the substrate; forming a first low resistance region on the second high resistance layer, wherein the first low resistance region is in contact with and electrically connected to the low resistance layer, and the first low resistance region is used to electrically connect one or more wafers to be integrated; retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer; Retaining the area on the low-resistance layer corresponding to the first low-resistance region and the wiring area, and removing other areas; The substrate is removed, and a second low resistance region is formed on the first high resistance layer, wherein the second low resistance region is in contact with and electrically connected to the low resistance layer, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated.

2. The method for manufacturing an electrical conversion structure according to claim 1, characterized in that: Before the step of sequentially forming a first high resistance layer, a low resistance layer and a second high resistance layer on the surface of the substrate, the method further comprises: A step of forming a sacrificial layer on the surface of the substrate; The first high resistance layer, the low resistance layer and the second high resistance layer are sequentially formed on the surface of the sacrificial layer.

3. The method for manufacturing an electrical conversion structure according to claim 1, characterized in that: forming a first low resistance region on the second high resistance layer by thermal diffusion or ion implantation; and / or, The doping type of the first low resistance region is the same as that of the low resistance layer; and / or, The doping concentration of the first low resistance region is higher than 5E18cm -3 and / or, forming a second low resistance region on the first high resistance layer by thermal diffusion or ion implantation; and / or, The doping type of the second low resistance region is the same as that of the low resistance layer; and / or, The doping concentration of the second low resistance region is higher than 5E18cm -3 .

4. The method for manufacturing an electrical conversion structure according to claim 1, characterized in that: The resistivity of the first high resistance layer is greater than 1000Ω / sq; and / or, The thickness of the first high resistance layer is in the range of 100 nm to 5000 nm; and / or, The resistivity of the second high resistance layer is greater than 1000Ω / sq; and / or, The thickness of the second high resistance layer is in the range of 100 nm to 5000 nm; and / or, The resistivity of the low-resistance layer is less than 100Ω / sq; and / or, The thickness of the low resistance layer is in the range of 20nm-1000nm.

5. An electrical conversion structure for realizing electrical interconnection of multiple wafers to be integrated, characterized in that: include: The low-resistance layer has a first surface and a second surface that are oppositely disposed; A first low-resistance structure is formed on a first surface of the low-resistance layer and is electrically connected to the low-resistance layer, wherein the first low-resistance structure is used to electrically connect one or more wafers to be integrated; A first high resistance layer is formed on the second surface of the low resistance layer, a second low resistance region is formed in the first high resistance layer, the second low resistance region is in contact with the low resistance layer and is electrically connected, and the second low resistance region is used to electrically connect the remaining one or more wafers to be integrated; The first low-resistance structure, the low-resistance layer and the second low-resistance region form a conductive channel.

6. A method for manufacturing a wafer interconnect structure, characterized in that: include: Providing a first wafer and a second wafer, wherein the first wafer has a first electrical contact area, and the second wafer has a second electrical contact area; Providing a substrate, and sequentially forming a first high-resistance layer, a low-resistance layer, and a second high-resistance layer on the surface of the substrate; According to the first electrical contact area on the first wafer, a first low resistance area corresponding to the first electrical contact area is formed on the second high resistance layer, wherein the first low resistance area is in contact with the low resistance layer and is electrically connected; retaining the first low resistance region on the second high resistance layer, and removing other regions on the second high resistance layer; Retaining the area on the low-resistance layer corresponding to the first low-resistance region and the wiring area, and removing other areas; bonding a first electrical contact region of the first wafer to the first low resistance region; removing the substrate; According to the second electrical contact area on the second wafer, a second low resistance area is formed on the first high resistance layer, wherein the second low resistance area is in contact with the low resistance layer and is electrically connected; A second electrical contact region of the second wafer is bonded to the second low resistance region.

7. The method for manufacturing a wafer interconnect structure according to claim 6, characterized in that: When bonding the first electrical contact region of the first wafer to the first low-resistance region, the bonding vacuum is better than 0.1 Pa, the bonding temperature is lower than 400° C., and the bonding pressure is less than 10 kN; and / or, When the second electrical contact area of ​​the second wafer is bonded to the second low-resistance area, the bonding vacuum is better than 0.1 Pa, the bonding temperature is lower than 400° C., and the bonding pressure is less than 10 kN.

8. The method for manufacturing a wafer interconnect structure according to claim 6, characterized in that: Before bonding the first electrical contact region of the first wafer to the first low resistance region, the method further includes: Performing activation treatment on the surface of the first low-resistance region and the surface of the first wafer under vacuum conditions; and / or, Before bonding the second electrical contact region of the second wafer to the second low resistance region, the method further includes: The surface of the first high-resistance layer, the surface of the second low-resistance region and the surface of the second wafer are activated under vacuum conditions.

9. The method for manufacturing a wafer interconnect structure according to claim 6, characterized in that: According to the first electrical contact area on the first wafer, a first low resistance area corresponding to the first electrical contact area is formed on the second high resistance layer, comprising: According to the relative position and lateral shape of the first electrical contact area on the first wafer, a pattern with the same position and shape is defined by photolithography in the second high resistance layer, and the photolithography pattern is regionally doped by thermal diffusion or ion implantation to form a first low resistance area; and / or, According to the second electrical contact area on the second wafer, a second low resistance area is formed on the first high resistance layer, comprising: According to the relative position and lateral shape of the second electrical contact area on the second wafer, a pattern with the same position and shape is defined by photolithography in the first high resistance layer, and the photolithography pattern is regionally doped by thermal diffusion or ion implantation to form a second low resistance area.

10. The method for manufacturing a wafer interconnect structure according to claim 6, characterized in that: The doping type of the first low resistance region is the same as that of the low resistance layer; and / or, The doping concentration of the first low resistance region is higher than 5E18cm -3 and / or, The doping type of the second low resistance region is the same as that of the low resistance layer; and / or, The doping concentration of the second low resistance region is higher than 5E18cm -3 and / or, The resistivity of the first high resistance layer is greater than 1000Ω / sq; and / or, The thickness of the first high resistance layer is in the range of 100 nm to 5000 nm; and / or, The resistivity of the second high resistance layer is greater than 1000Ω / sq; and / or, The thickness of the second high resistance layer is in the range of 100 nm to 5000 nm; and / or, The resistivity of the low-resistance layer is less than 100Ω / sq; and / or, The thickness of the low resistance layer is in the range of 20nm-1000nm.

11. A wafer interconnect structure, characterized in that: include: An electrical conversion structure, comprising a low resistance layer, a first low resistance structure and a first high resistance layer, wherein the low resistance layer has a first surface and a second surface arranged opposite to each other; The first low-resistance structure is formed on the first surface of the low-resistance layer and is electrically connected to the low-resistance layer; the first high-resistance layer is formed on the second surface of the low-resistance layer, a second low-resistance region is formed in the first high-resistance layer, and the second low-resistance region is in contact with the low-resistance layer and is electrically connected; wherein the first low-resistance structure, the low-resistance layer and the second low-resistance region form a conductive path; A first wafer having a first electrical contact region, wherein the first electrical contact region is in contact with and electrically connected to a first low-resistance structure of the electrical conversion structure; The second wafer has a second electrical contact region, wherein the second electrical contact region is in contact with and electrically connected to the second low-resistance region of the electrical conversion structure.

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